Communication method and communication device

Abstract

A communication method and a communication device, the communication method is applied to a first host, a plurality of transmission paths for transmitting messages exist between the first host and a second host, and the method comprises the following steps: the first host obtains information of a first resource space in the second host, the information of the first resource space comprises an initial address of the first resource space, length information of the first resource space and order-preserving attribute information corresponding to the first resource space. The first host stores order-preserving attribute information corresponding to the first resource space and first path information, and the first path information is used for indicating a transmission path corresponding to the first access message accessing the first resource space. Therefore, under the condition that the first host sends the access message to the second host to access the first resource space, the order-preserving requirement of the access message can be obtained by the stored information, and order-preserving transmission of the message in a multi-path transmission scene is realized.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to a communication method and a communication device. Background Art

[0002] The Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard used to connect a processor to external devices, which are referred to as PCIe devices or simply devices.

[0003] In the current PCIe system, communication between any two devices can only be single-path communication between two interfaces. If in-order transmission of packets is required between the two communicating devices, an in-order mechanism for point-to-point communication can be used to ensure the order of packets on the transmission path, thereby achieving end-to-end in-order transmission.

[0004] However, the current PCIe system only supports single-path packet in-order transmission. Therefore, how to design a solution that can achieve packet in-order transmission in a multi-path transmission scenario has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a communication method to achieve packet in-order transmission in a multi-path transmission scenario.

[0006] In a first aspect, a communication method is provided, which is applied to a first host. This method can be executed by the first host, or can also be executed by a circuit or chip configured in the first host. This application does not make any limitation in this regard. For the sake of description, hereinafter, it is described by taking the first host as an example.

[0007] The communication method includes: the first host obtains information about a first resource space in a second host, where the information about the first resource space includes the starting address of the first resource space, the length information of the first resource space, and the in-order attribute information corresponding to the first resource space, and the in-order attribute information corresponding to the first resource space is used to indicate the in-order requirement for a first access packet for accessing the first resource space; the first host saves the in-order attribute information corresponding to the first resource space and first path information, where the first path information is used to indicate the transmission path corresponding to the first access packet for accessing the first resource space, and the transmission path indicated by the first path information is one of multiple transmission paths between the first host and the second host.

[0008] Based on the above technical solution, the first host is used as the source device and the second host is used as the target device. In a general bus system, when data packets are transmitted between the source device and the target device, the data packets can be transmitted through multiple transmission paths. Specifically, in this technical solution, the first resource space (such as, memory segment and / or function entity) on the second host can be provided for the first host to use by means of registration. When the first host obtains information related to the first resource space of the second host, in addition to obtaining information such as the size and address of the first resource space (such as, the starting address of the first resource space, the length information of the first resource space), it also obtains the in-sequence delivery attribute information corresponding to the first resource space, and saves the information corresponding to the first resource space (such as, saving the in-sequence delivery attribute information corresponding to the first resource space and the first path information), so that when the first host sends an access data packet to the second host to access the first resource space, it can know the in-sequence delivery requirement of the access data packet accessing the first resource space and the transmission path of the access data packet based on the saved information, that is, access data packets with the same in-sequence delivery requirement can be transmitted through a certain transmission path, while access data packets with different in-sequence delivery requirements are transmitted through different paths, realizing in-sequence delivery of data packets in a multi-path transmission scenario.

[0009] In combination with the first aspect, in some implementation manners of the first aspect, the first host saves the in-sequence delivery attribute information and the first path information corresponding to the first resource space, including: the first host configures the information of the first resource space into a decoder entry, and the decoder entry includes a first entry, and the first entry includes the first path information and the in-sequence delivery attribute information corresponding to the first resource space.

[0010] Based on the above technical solution, the first host can record the information of the first resource space based on the first entry in the decoder entry by configuring the information of the first resource space into the decoder entry, which simplifies the way for the first host to save the information of the first resource space.

[0011] In combination with the first aspect, in some implementation manners of the first aspect, when the first host determines to send a first access data packet to the second host to access the first resource space, the method includes: the first host queries the decoder entry to determine the first path information and the in-sequence delivery requirement corresponding to the first access data packet; the first host determines the output port and the first transmission path corresponding to the first access data packet according to the first path information; where the first transmission path is the transmission path used to transmit the first access data packet among the multiple transmission paths, and the first transmission path is used to transmit access data packets corresponding to the same path information.

[0012] Based on the above technical solution, when the first host determines to send a first access message to access the first resource space, the first host can obtain the sequence attribute information corresponding to the first access message by querying the decoder entry, so as to ensure the transmission of the first access message on the premise of meeting the in-sequence requirement of the first access message.

[0013] Combined with the first aspect, in some implementation manners of the first aspect, the method further includes: the first host generates the first access message according to the first transmission path and the in-sequence requirement corresponding to the first access message, where information indicating the in-sequence requirement corresponding to the first access message is carried in the in-sequence field of the first access message, and information indicating the first transmission path is carried in the load sharing factor field of the first access message.

[0014] Based on the above technical solution, when the first host generates the first access message, according to the sequence attribute information and the first path information corresponding to the first access message obtained by querying the decoder entry, relevant fields of the message are filled, so that the generated first access message carries information indicating the in-sequence attribute and information of the transmission path.

[0015] Combined with the first aspect, in some implementation manners of the first aspect, the routing indication field of the first access message is set to 0, where setting the routing indication field to 0 is used to indicate that the hash routing mechanism is adopted to determine the transmission path of the first access message.

[0016] Combined with the first aspect, in some implementation manners of the first aspect, the first host obtains the in-sequence attribute information corresponding to the first resource space, including: the first host receives the in-sequence attribute information corresponding to the first resource space from the second host; or, the first host determines the in-sequence attribute information corresponding to the resource space according to the use of the first resource space.

[0017] Based on the above technical solution, the way for the first host to obtain the in-sequence attribute information corresponding to the first resource space can be: received from the second host. For example, when the second host provides the first resource space for the first host to use through registration, different in-sequence requirements can be set according to the functions of different resource spaces, and the corresponding in-sequence attribute information is provided to the first host. Or, the first host can determine different in-sequence requirements by itself according to the use of different resource spaces, improving the flexibility of the solution.

[0018] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: the first host obtains information about a second resource space in the second host, where the information about the second resource space includes the starting address of the second resource space, the length information of the second resource space, and the in-order property information corresponding to the second resource space, and the in-order property information corresponding to the second resource space is used to indicate the in-order requirement for a second access message for accessing the second resource space; the first host saves the in-order property information corresponding to the second resource space and second path information, where the second path information is used to indicate the transmission path for the second access message for accessing the second resource space, and where the second path information is different from the first path information, and the in-order property information corresponding to the second resource space is different from the in-order property information corresponding to the first resource space.

[0019] Based on the above technical solution, the first host can obtain information about different resource spaces on the second host. In addition, access messages corresponding to resource spaces with different in-order requirements can be transmitted through different paths, so as to achieve in-order transmission of messages on the premise of ensuring multi-path transmission.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the first host saves the in-order property information corresponding to the second resource space and second path information, including: the first host configures the information about the second resource space into the decoder entry, where the decoder entry includes a second entry, and the second entry includes the second path information and the in-order property information corresponding to the second resource space.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the in-order requirement for the first access message includes any one of the following: strongly ordered (SO), non-ordered (NO), or relaxed ordering (RO). Among them, strongly ordered indicates that the first access message is an in-order message, needs to follow the in-order transmission method, and depends on the transmission results of other messages for transmission. For example, the first access message has an in-order requirement with a previous message marked as RO. Non-ordered indicates that the first access message has no in-order requirement and does not need to depend on the transmission results of other messages for transmission; Relaxed ordering indicates that there is an in-order requirement between the first access message and subsequent messages marked as SO. For example, a message marked as SO cannot be transmitted earlier than a message marked as RO.

[0022] In a second aspect, a communication method is provided, which is applied to a second host. This method can be executed by the second host, or can also be executed by a circuit or chip configured in the second host. This application does not make any limitation in this regard. For the convenience of description, in the following, it is described by taking the execution by the second host as an example.

[0023] The communication method includes: the second host receives a first access message from the first host, where the first access message is used to access a first resource space in the second host. Information indicating the in-sequence requirement corresponding to the first access message is carried in the in-sequence field of the first access message, and information indicating a first transmission path is carried in the load sharing factor field of the access message; the second host determines the in-sequence requirement of the first access message according to the in-sequence field of the first access message; wherein, the physical port for receiving at least one access message transmitted on the first transmission path by the second host is the same, and the first access message is one of the at least one access messages.

[0024] For the technical effects of the method shown in the above second aspect and its possible designs, reference can be made to the technical effects in the first aspect and its possible designs.

[0025] In a third aspect, a communication device is provided. The device includes: a storage module for storing programs; a processing module for executing the programs stored in the storage module. When the programs stored in the storage module are executed, the processing module is used to execute the methods provided in the above aspects.

[0026] In a fourth aspect, a computer-readable storage medium is provided. The computer-readable medium stores program codes for a device to execute, and the program codes include the methods provided in the above aspects.

[0027] In a fifth aspect, a computer program product including instructions is provided. When the computer program product runs on a computer, the computer is enabled to execute the methods provided in the above aspects.

[0028] In a sixth aspect, a chip is provided. The chip includes a processing module and a communication interface. The processing module reads instructions stored on a memory through the communication interface and is used to execute the methods provided in the above aspects.

[0029] Optionally, as an implementation, the chip may further include a storage module, and instructions are stored in the storage module. The processing module is used to execute the instructions stored on the storage module. When the instructions are executed, the processing module is used to execute the methods provided in the above aspects.

[0030] In a seventh aspect, a chip is provided. The chip includes a first host for executing the method provided in the first aspect and a second host for executing the method provided in the second aspect.

[0031] In an eighth aspect, a computer system is provided, which includes the chip shown in the seventh aspect.

[0032] In a ninth aspect, a terminal device is provided, which includes the chip shown in the seventh aspect. For example, the terminal device includes, but is not limited to, terminals such as mobile phones and vehicles.

[0033] In a tenth aspect, a communication system is provided, which includes a first host for executing the method provided in the first aspect and a second host for executing the method provided in the second aspect. Description of the Drawings

[0034] Figure 1 It is a schematic structural diagram of the computer device provided by the embodiment of the present application.

[0035] Figure 2 It is a schematic diagram of the data center provided by the embodiment of the present application.

[0036] Figure 3 It is a schematic diagram of a general bus protocol message format provided by the embodiment of the present application.

[0037] Figure 4 It is a schematic diagram of supporting multi-path transmission in a general bus protocol system provided by the embodiment of the present application.

[0038] Figure 5 It is a schematic diagram of the PCIe architecture provided by the embodiment of the present application.

[0039] Figure 6 It is a schematic flowchart of a communication method provided by the present application.

[0040] Figure 7 It is a schematic diagram of a resource registration provided by the present application.

[0041] Figure 8 It is a schematic diagram of determining the order-preserving attribute of the resource space provided by the present application.

[0042] Figure 9 It is a schematic diagram of the data structure of an entry provided by the present application.

[0043] Figure 10 It is a schematic diagram of a message format provided by the present application.

[0044] Figure 11 It shows a schematic structural diagram of a communication device 1100 provided by the embodiment of the present application.

[0045] Figure 12 It shows a schematic structural diagram of a chip system 1200 provided by the embodiment of the present application.

[0046] Figure 13 Schematically shows a conceptual partial view of a computer program product provided by an embodiment of the present application. Detailed implementation manners

[0047] For the convenience of understanding the embodiments of the present application, the following points are explained.

[0048] First, "at least one" shown in the present application means one or more, and "a plurality" means two or more. Additionally, in the embodiments of the present application, "first", "second", and various numerical numbers (e.g., "#1", "#2", etc.) are only for the convenience of description and do not limit the scope of the embodiments of the present application. The magnitudes of the sequence numbers of the following processes do not imply the order of execution. The execution order of each process should be determined by its function and internal logic and should not constitute any limitation to the implementation process of the embodiments of the present application. It should be understood that the described objects can be interchanged under appropriate circumstances so as to be able to describe solutions other than the embodiments of the present application. Furthermore, in the embodiments of the present application, words such as "S610" are only identifiers for the convenience of description and do not limit the order of execution steps.

[0049] Second, in the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, using words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0050] Third, the "storage" involved in the embodiments of the present application may refer to being stored in one or more memories. The one or more memories may be separately provided or integrated in an encoder or decoder, a processor, or a communication device. The one or more memories may also have a part separately provided and a part integrated in a decoder, a processor, or a communication device. The type of the memory may be any form of storage medium, and the present application does not limit this.

[0051] Fourth, when "including" (also known as "includes", "including", "comprises", and / or "comprising") is used in the embodiments of the present application, it specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups.

[0052] Fifth, the "if" involved in the embodiments of the present application may be interpreted to mean "when" (either "when" or "upon") or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined that..." or "if [the stated condition or event] is detected" may be interpreted to mean "when it is determined that..." or "in response to determining..." or "when [the stated condition or event] is detected" or "in response to detecting [the stated condition or event]".

[0053] Sixth, the terms used in the description of the various examples in the embodiments of the present application are only for describing specific examples and are not intended to be limiting. As used in the description of the various examples and the appended claims, the numerical forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0054] Seventh, the term "and / or" herein is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0055] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings.

[0056] The present application involves the configuration space for a processor in a computer system to access an external device. Among them, the computer system can be a server or a terminal. The terminal includes, but is not limited to, user systems such as desktop computers, laptop computers, and smart phones. For ease of understanding, the structure of the computer system will be introduced below.

[0057] See Figure 1 The schematic structural diagram of the computer system shown. The computer system includes a processor 101, an input / output device (I / O device) 102, a memory 103, a cache 104, a memory management unit (MMU) 105, an input / output memory management unit (IOMMU) 106, an external memory 107, and a bus 108.

[0058] Processor 101 includes at least one core. This core is also referred to as a computing engine. Among them, each core can execute tasks independently. When processor 101 includes multiple cores, tasks from an application can be divided so that the application can make full use of multiple cores and execute more tasks within a specific time. In this embodiment, processor 101 can be a main processor, such as a Central Processing Unit (CPU).

[0059] The input / output device 102 refers to a hardware device with the ability to input data and / or output data. The input / output device 102 can be divided into an input device and an output device. Among them, the input device can include devices such as a mouse, a keyboard, a joystick, a stylus, a microphone, etc., and the output device can include devices such as a display, a speaker, etc.

[0060] The memory 103 is also referred to as internal memory or main memory, and is used to temporarily store the operation data in the processor 101. Further, the memory 103 is also used to temporarily store the data exchanged with the external memory 107. The memory 103 can generally be implemented using storage media such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM).

[0061] The cache 104 (in this embodiment, it refers to the processor cache, such as the CPU cache) is a component used to reduce the average time required for the processor 101 to access the memory 103. Refer to Figure 1 , in the pyramid storage system, the cache 104 is located in the second layer from the top down, second only to the register of the processor 101 ( Figure 1 not shown in the figure), and higher than the memory 103 (the memory 103 is located in the third layer from the top down). Generally, the capacity of the cache 104 is much smaller than that of the memory 103, but the access speed can be close to the frequency of the processor 101.

[0062] The Memory Management Unit 105 is a computer hardware used to process data access requests. The Memory Management Unit 105 is specifically used to map the virtual address (VA) in the data access request. Among them, the Memory Management Unit 105 can intercept the data access request sent by the core of the processor 101, and map (or translate) the virtual address in the data access request into a physical address (PA), so as to access the memory 103 according to this physical address.

[0063] The input / output memory management unit 106 is essentially a memory management unit. Similar to the memory management unit 105 that maps virtual addresses visible to the processor 101 to physical addresses, the input / output memory management unit 106 is used to map virtual addresses (which can also be referred to as device addresses or I / O addresses) visible to the input / output device 102 to physical addresses.

[0064] The external memory 107 is also referred to as external storage or auxiliary storage, and is typically used to persistently store data. For example, the external memory 107 can persistently store the operation data in the processor 101. Even if the power supply is abnormal, the data already written to the external memory 107 can still be saved, avoiding data loss. In a specific implementation, the external memory 107 includes at least one non-volatile memory 1071. When the external memory includes multiple non-volatile memories, these multiple non-volatile memories can be of the same type or different types. For example, in Figure 1 the example of, the external memory 107 can include two types of non-volatile memories, such as storage class memory (SCM) and solid state drive (

[0065] The bus 108 is used to connect the various functional components of the computer system. The bus 108 is a common communication trunk for transmitting information between various functional components of the computer system. The bus 108 can be a transmission wire harness formed by wires. According to the different connection objects, the bus 108 can also be divided into an internal bus and an external bus.

[0066] Among them, the internal bus uses an internal bus protocol to transmit information. The internal bus protocol includes a bus protocol for accessing the memory space of the computer system. The external bus uses an external bus protocol to transmit information. The external bus protocol includes a bus protocol for accessing the external memory space of the computer system. Among them, the memory space refers to the address space of the memory, and the external memory space refers to the address space of the external memory.

[0067] In some embodiments, the internal bus protocol includes, but is not limited to, the peripheral component interconnect (PCI) bus, the peripheral component interconnect express (PCIe) protocol, the IntelTM Quick Path Interconnect (QPI) protocol, and the unified bus protocol. The external bus protocol includes, but is not limited to, the small computer system interface (SCSI) protocol or the serial attached SCSI (SAS) protocol.

[0068] It should be noted that Figure 1 the computer system shown is exemplified with the external storage 107 as the remote external storage. As Figure 1 shown, the external storage 107 includes a network card 1072. The network card 1072 can be, for example, a smart NIC network interface card (i.e., a network adapter). The external storage 107 accesses the network through the network card 1072, and then connects to other components of the computer system 101 through the network. The network can be a wired communication network, such as an optical fiber communication network, or a wireless communication network, such as a wireless local area network (WLAN) or the fifth generation (5G) mobile communication network.

[0069] In some possible implementation manners, the external storage 107 of the computer system can also be a local external storage, and other components of the computer system, such as the processor 101, can be connected to the local external storage through the bus 108. In some other possible implementation manners, the computer system can include both a remote external storage and a local external storage. In addition, the embodiments of the present application can be applied to a centralized storage or a distributed storage scenario, and the present embodiment does not limit this.

[0070] Exemplarily, the method for accessing the configuration space register of the access bus device provided in the embodiments of the present application can also be applied to Figure 2 the server cluster for cross-network communication shown, such as Figure 2 the data center shown. Among them, Figure 2 the internal structure of the switch or server shown in Figure 1 is as shown above in

[0071] In addition, the internal bus protocol supported by the computer system involved in the present application includes a general bus protocol, and a transport layer connection can be established between computer systems. Among them, the general bus protocol can also be called the Lingqu bus protocol or the unified bus protocol, which is a bus protocol standard, and the present application does not limit the name of the general bus protocol.

[0072] The universal bus protocol breaks down the existing barriers of various protocols and removes unnecessary conversion overhead in the middle, thereby achieving extremely low latency. The universal bus protocol defines an independent transaction layer (TA) and transport layer (TP). There is a connection between the transport layers, but no connection between the transaction layers. For the host, there is no connection between the transaction layers of the two hosts, but there is a connection between the transport layers. Then all transactions of any of the two hosts are carried on the transport layer for transmission. The universal bus protocol includes the transport layer and the transaction layer. The transport layer is responsible for network packet loss retransmission to ensure reliable transmission, and the transaction layer handles different transactions. The transport layer receives the packet from the network, strips off the transport layer header, and forwards it to the transaction layer.

[0073] The general bus protocol message format is as follows Figure 3 Specifically, the fields in the universal bus protocol message format are defined as shown in Table 1 below:

[0074] Table 1

[0075]

[0076]

[0077] Specifically, the transaction layer of the universal bus protocol and the interactive interface between the application are called Jetty. Application messages can be sent to any destination through a Jetty, and messages from any source can also be received through a Jetty. A Jetty that can only send is defined as (Jetty for send, JFS); a Jetty that can only receive is defined as (Jetty for receive, JFR).

[0078] Figure 4 It is a schematic diagram of supporting multi-path transmission in a universal bus protocol system provided in an embodiment of the present application.

[0079] like Figure 4 As shown, the universal bus protocol system involved in this application supports multiple paths, including source multi-port (such as Figure 4 Port #0 (port #0), port #1, port #2, and port #3) in host A as shown in , the destination multi-port (such as Figure 4 0, Port #1, Port #2, and Port #3 in Host B as shown in ) and network multipathing (such as Figure 4 , path #1, path #2, ..., path #n) shown in FIG. 1 , wherein host A can be understood as a source device, host B can be understood as a destination device, and host A can send a message to host B through multiple paths.

[0080] Optionally, the host A and / or the host B may further include a processing unit (PU) (such as a central processing unit (CPU)), a controller, and a system on chip (NOC), etc. In this application, there are no restrictions on the hardware or software systems included in the host, and reference can be made to the introduction of the host in the current related technologies, which will not be elaborated in this application.

[0081] Exemplarily, in Figure 4 the shown general bus protocol system, messages can be transmitted between two devices through source multi-ports or destination multi-ports, as well as network multi-paths, in order to improve the communication bandwidth.

[0082] In the above text, in combination with Figures 1 to 4 a simple introduction to the scenarios where this application can be applied and the internal logic units of the host involved. For the convenience of understanding the embodiments of this application, some basic concepts involved in this application are briefly described.

[0083] 1. Message in-order delivery: Messages are sent and / or received in a certain order to achieve message in-order delivery. For example, in the current PCIe system, when the CPU accesses the memory with different attributes of peripherals through messages for access (such as store instructions, load instructions, etc.), different in-order delivery methods can be used to achieve message in-order delivery.

[0084] Exemplarily, memory attributes are divided into two categories:

[0085] Device-type memory: The input / output (IO) memory space including device registers.

[0086] Normal-type memory: The memory space including static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0087] When accessing the device-type memory space, message in-order delivery is usually achieved in the endpoint order manner; when accessing the normal-type memory, message in-order delivery is usually achieved in the request order manner. Among them, endpoint order can achieve the order of multiple messages to the same endpoint; request order can achieve the order of multiple messages to the same address.

[0088] For the convenience of understanding, in combination with Figure 5Briefly describe how to achieve packet ordering for communication between two devices in the current PCIe system.

[0089] As Figure 5 shown, the PCIe network forms a tree structure, including a PCIe root complex (RC), a switch device, and a PCIe endpoint (EP) as shown in Figure 5 . Among them, the PCIe RC is responsible for managing the communication between the CPU and other devices. The switch device is used to expand one PCIe interface into multiple PCIe interfaces. The PCIe EP is a device without the function of forwarding data.

[0090] It should be understood that Figure 5 only for example, it does not constitute any limitation to the protection scope of this application, but only illustrates how to achieve packet ordering in the scenario of communication between different devices in the PCIe network. For example, in the scenario shown in Figure 5 , the CPU issues 3 store requests, and there is no ordering relationship between these three store requests. However, after the PCIe RC receives the first store request, it will reply with a Comp response, indicating that the current request has arrived and it is necessary to ensure that the execution order of the commands is the same as the reception order. Therefore, these three packets need to be marked as SO, that is, strong-order execution is required.

[0091] The packet ordering in the current PCIe system has the following characteristics:

[0092] 1) Only supports single path. In the current PCIe system ordering mechanism, through a point-to-point ordering mechanism, it is expected to ensure the order on the entire packet transmission path, and thus achieve end-to-end ordering;

[0093] 2) Even when there are multiple Bar spaces on the PCIe EP side for the PCIe RC to use, the access to the input / output memory map (MMIO) space still follows the same path and obeys the same set of ordering mechanisms;

[0094] 3) In the current PCIe system design, the logical implementation is all in a tightened manner. When the load / store instructions issued by the xPU are connected to the PCIe link, the default order attribute all adopts "SO".

[0095] 2. Ordered Messages: As described above, message ordering targets messages with ordering requirements. In this application, messages with ordering requirements are called ordered messages, and messages without ordering requirements are called unordered messages. Exemplarily, messages with ordering requirements include, but are not limited to: messages sent depending on the reception of other messages. For example, if message #1 can only be sent when message #2 is successfully received, then message #1 is an ordered message. Similarly, messages without ordering requirements include, but are not limited to: messages sent regardless of the reception of other messages.

[0096] 3. Transport Group (TPG): At least one TPG can be established between the initiator device and the target device at the transport layer. Each TPG contains multiple transport ports (TPs). When the initiator device sends a message to the target device, it can perform load balancing among multiple TPs within the TPG, and different messages can be transmitted through different network paths.

[0097] 4. Resource Registration: In a general bus system, memory segments and / or function entities (FEs) on the target device can be provided for use by the initiator device through registration. Among them, memory segments and / or function entities are units for the target device to partition its own resources, representing device resources with a certain degree of isolation. For example, a memory segment is a continuous virtual address (VA) space, and each memory segment corresponds to a physical memory. The target device creates and registers a memory segment, and the initiator device applies to use the memory segment of the target device.

[0098] Exemplarily, after the initiator device obtains the memory segment information, it maps the unified bus address (UBA) of the memory segment to the local process VA space to obtain the mapped VA (mVA).

[0099] It should be understood that the resource registration process of the target device in this application is not limited. For example, the initiator device and the target device can complete resource application registration through an in-band exchange mechanism or an out-of-band exchange mechanism.

[0100] As mentioned above in conjunction with Figure 2 briefly introduced the scenarios applicable to the communication method provided in this application and the basic concepts involved in this application. And in the basic concepts, the method of message ordering in the current PCIe system design was introduced. As described above, the message ordering in the current PCIe system design only supports single-path and does not have multi-path capabilities, and cannot provide a larger interaction bandwidth. That is to say, this method of message ordering is not applicable toFigure 4 In the general bus protocol system shown, because Figure 4 the general bus protocol system shown supports multipath transmission.

[0101] In addition, from the characteristics of message in-order preservation in the PCIe system design shown above, it can be known that Load / store instructions access the network and always perform heat preservation and in-order preservation according to "SO", resulting in low execution efficiency on the receiving side. Moreover, for flows without an order relationship, since the same physical link is used, order association is introduced, leading to a decline in interaction efficiency.

[0102] This application provides a communication method to achieve message in-order preservation in the scenario of multipath transmission. Among them, the scenario of multipath transmission includes but is not limited to Figure 4 the multipath transmission supported by the general bus protocol system shown, or it can also be other supported multipath transmission systems (such as a PCIe system capable of supporting multipath transmission).

[0103] It should be understood that the communication method provided in the embodiments of this application can be applied to a computer system. For example, Figure 2 in the cross-network communication system shown.

[0104] It should also be understood that the embodiments shown below do not particularly limit the specific structure of the execution entity of the method provided in the embodiments of this application. As long as it can run a program recording the code of the method provided in the embodiments of this application to implement the method provided in the embodiments of this application. For example, the execution entity of the method provided in the embodiments of this application can be a device, or a functional module in the device that can call and execute the program.

[0105] Figure 6 is a schematic flowchart of a communication method provided by this application. It is applied to the scenario of communication between a first host and a second host, such as Figure 2 in the scenario shown.

[0106] In Figure 6 the embodiment shown, the first host can be used as the sending end (or called the source device (initiator)), and the second host can be used as the receiving end (or called the target device (target)). For the receiving end, the receiving end is the local device, and the sending end is the remote device. For the sending end, the sending end is the local device, and the receiving end is the remote device.

[0107] Exemplarily, the above-mentioned first host can be a physical machine or a virtual machine. If the first host is a virtual machine, the steps executed by the first host can be executed by the virtual machine; similarly, the second host can be a physical machine or a virtual machine. If the second host is a virtual machine, the steps executed by the second host can be executed by the virtual machine.

[0108] Specifically, Figure 6 The method shown includes the following steps:

[0109] S610, the first host obtains information about the first resource space in the second host.

[0110] In this embodiment, the first host is the sending end that sends a message. For example, the first host is a device that sends load and / or store instructions. The second host is the receiving end that receives a message. For example, the second host is a device that receives load and / or store instructions.

[0111] Exemplarily, in this embodiment, the first host can be understood as a device that uses a resource space, and the second host can be a device that provides a resource space for the first host to use. For example, the first host can be a user host in a general bus system, and the second host can be a home device in the general bus system; also for example, the first host and the second host can be home devices in the general bus system, or the first host and the second host can be user hosts in the general bus system; and for another example, the first host and the second host can be other devices in the general bus system, and this embodiment does not limit this. Among them, the second host can provide its own resources for the first host to use. For example, the second host provides resources at the FE or memory segment level for the first host to use, so that the first host can use resources of other devices in the general bus system.

[0112] For ease of understanding, the following combines Figure 7 to introduce in detail how the second host provides its own resources for the first host to use in this embodiment, and how the first host enables the use of resources of the second host.

[0113] From Figure 7 it can be seen that a general bus system includes a first host (i.e., a user host), a second host (i.e., a home device), and a function management (FM) device. Among them, the first host is a device that uses resources of the second host, the second host is a device that provides available resources for the first host, and the FM device is a device that implements management functions in the system. For example, the FM device can obtain at least one home device in the system by scanning.

[0114] Exemplarily, after the FM device discovers the second host by scanning, it incorporates the second host into management, and the FM device can register resources of the second host (such as FE resources or memory segments, etc.) in the first host. The first host can create a driver (such as Figure 7 the device driver of the first host shown in

[0115] It should be understood that the above Figure 7 way in which the second host shown provides its own resources for the first host to use is only an example and does not impose any limitation on the protection scope of this application. The second host can also register its own resources with the first host in other ways so that the first host can use the resources of the second host, and this is not limited in this embodiment.

[0116] Exemplarily, in this embodiment, the first host can obtain information about the resource space in the second host according to the communication address of the second host and the description information of the second host specified by the FM device.

[0117] Specifically, the information of the first resource space includes the start address of the first resource space, the length information of the first resource space, and the in-sequence property information corresponding to the first resource space. The in-sequence property information corresponding to the first resource space is used to indicate the in-sequence requirement for the first access message for accessing the first resource space.

[0118] It should be understood that the first host can obtain information about at least one resource space in the second host. The above-mentioned first resource space is any one of the at least one resource space. The information of the first resource space includes the start address of the first resource space and the length of the first resource space. The in-sequence requirement corresponding to the first resource space is indicated by the in-sequence property information corresponding to the first resource space. The in-sequence requirement corresponding to the first resource space can be understood as the in-sequence requirement for the access message for accessing the first resource space. For example, the first host can also obtain information about the second resource space in the second host. The information of the second resource space includes the start address of the second resource space, the length information of the second resource space, and the in-sequence property information corresponding to the second resource space. The in-sequence property information corresponding to the second resource space is used to indicate the in-sequence requirement for the second access message for accessing the second resource space.

[0119] As a possible implementation manner, the in-sequence property information corresponding to different resource spaces is provided by the second host. For example, the in-sequence property information corresponding to the resource space included in the information about at least one resource space obtained by the first host.

[0120] In this implementation manner, the in-sequence property information corresponding to different resource spaces is determined by the second host. For example, the second host can determine the in-sequence property information corresponding to the resource space based on the function of the resource space and provide the corresponding in-sequence property information to the first host in the resource space registration process.

[0121] For the sake of easy understanding, in combination with Figure 8 it is described how the second host determines the in-sequence property information of different resource spaces.

[0122] As Figure 8As shown, there are multiple FE resources available on the second host. The resource spaces corresponding to one or more FEs are determined for different uses during functional design. For example, the resource spaces corresponding to some FEs are used for configuration; the resource spaces corresponding to some FEs are used for interrupt information; the resource spaces corresponding to some FEs are used as command queues for issuing commands; the resource spaces corresponding to some FEs are used as doorbells for the command queue; the resource spaces corresponding to some FEs are used for data storage, and so on.

[0123] The resource spaces corresponding to different FEs can have different order attributes. For example, the resource spaces corresponding to the command queue for issuing commands or for data storage can be RO / NO; also, for example, the resource space corresponding to the doorbell can be SO. There may or may not be an order-preserving requirement between the resource spaces corresponding to different FEs. For example, there may be no order requirement between different FE resource spaces.

[0124] As another possible implementation, the order-preserving attribute information corresponding to different resource spaces is determined by the first host.

[0125] In this implementation, when the second host provides different resource spaces for the first host to use, it does not provide the preservation attribute information corresponding to the different resource spaces. The first host can determine the order-preserving attributes of the different resource spaces according to the actual uses of the different resource spaces.

[0126] For example, the second host provides resource space #1 and resource space #2 for the first host. The first host decides that resource space #1 is used for data storage and resource space #2 is used for receiving interrupt instructions. Then the first host determines that the preservation attribute information corresponding to resource space #1 is information indicating that preservation is not required, and the preservation attribute information corresponding to resource space #2 is information indicating that strong preservation is required.

[0127] Furthermore, in this embodiment, after the first host obtains the information of the resource spaces in the second host and determines the order-preserving attribute information corresponding to different resource spaces, it can save the order-preserving attribute information corresponding to the resource spaces and the path information corresponding to the resource spaces. For example, configure the information of different resource spaces into the general bus decoder (UBdecoder) table entries of the first host, and these table entries are used to determine the routing path of the message; also, for example, the order-preserving attribute information corresponding to the resource spaces and the path information corresponding to the resource spaces can be saved in the storage space or recorded by other means, and this embodiment does not make any limitations in this regard.

[0128] For ease of understanding, in this embodiment, the example of configuring the order-preserving attribute information corresponding to the resource storage space and the path information corresponding to the resource space into the general bus decoder (UB decoder) entry is used for illustration. Then Figure 6 The method flow shown also includes:

[0129] S620, the first host configures the decoder entry.

[0130] For ease of description, in the following, the example of the first host configuring the information of the first resource space into the decoder entry is used for illustration. Among them, the first resource space can be any resource space in at least one resource space provided by the second host. The first host configures the information of the first resource space into the decoder entry. The decoder entry includes a first entry, and the first entry includes the path information (which can be simply referred to as the first path information) corresponding to the first access message for indicating access to the first resource space and the order-preserving attribute information corresponding to the first resource space.

[0131] For example, the first host obtains the information of multiple resource spaces in the second host. Among them, the order-preserving attributes corresponding to the multiple resource spaces may be different.

[0132] In this embodiment, the first entry in the table corresponding to the first resource space. Among them, the data structure of an entry in the table is as Figure 9 shown, including UBA, transport group number (TPGNumber), path information or order ID, order-preserving attribute information or order type, destination entity ID (DstEID), TokenID, and TokenValue.

[0133] Exemplarily, the meanings of each field in the entry are shown in Table 2 below:

[0134] Table 2

[0135]

[0136] The stream of the current access address space involved in Table 2 includes at least one message in the current access address space, that is, one or more access messages accessing the same address space are called the "stream of the access address space".

[0137] It should be understood that the main function of the above decoder is to support the first host to query the UBA of the message and the partial field conversion information function of the message according to the physical address (HPA) of the message.

[0138] Exemplarily, the first host query decoder obtains the following information:

[0139] TPG: Indicates the TPG for transmitting the current message. Multiple path-reachable transmission ports / paths between the source end and the destination end are maintained in this TPG.

[0140] Order ID: Used to indicate the flow Order ID for accessing the current address space. The Order ID is used to select a unique outgoing port / path from the multiple path-reachable transmission ports / paths within the TPG, and this Order ID is filled in the message as the load balancing (LB) field. The HASH routing mechanism can be enabled, thereby ensuring that the message reaches the receiving side through a unique path.

[0141] Order Type: Used to indicate the Order type of the flow for accessing the current address space, such as: NO, RO, or SO. This field segment is directly used by the controller to fill the "ODR" field segment in the message.

[0142] It should be understood that the first host can obtain the information of at least one resource space in the second host and configure the information of the at least one resource space into the general bus decoder of the first host. The above-mentioned first resource space is any one of the at least one resource spaces. For example, for the information of the second resource space in the second host obtained by the first host, the first host configures the information of the second resource space into the decoder entry. The decoder entry includes a second entry, and the second entry includes path information corresponding to the second access message for accessing the second resource space and in-order delivery attribute information corresponding to the second resource space.

[0143] As an example rather than a limitation, the path information corresponding to the above-mentioned second access message (which can be simply referred to as the second path information) is different from the path information corresponding to the first access message, and the in-order delivery attribute information corresponding to the second resource space is different from the in-order delivery attribute information corresponding to the first resource space. That is, in this embodiment, access messages with different in-order delivery requirements can be transmitted through different paths, thereby ensuring in-order delivery of messages in a multi-path transmission scenario.

[0144] After the above-mentioned entry configuration is completed, if the first host initiates an access to the second host in order to access the first resource space provided by the second host to the first host, the first host can obtain the in-order delivery requirements that the first access message needs to meet by querying the decoder entry, and generate the first access message based on the information obtained by querying the decoder entry (such as, in-order delivery attribute information, transmission path information, etc.). Then Figure 6 The shown method flow further includes:

[0145] S630, the first host generates a first access message.

[0146] Specifically, when the first host group sends the first access message, according to the retrieved sequence attribute information, relevant fields of the sent data packet are filled, and the selection of the sending path is made.

[0147] Exemplarily, the format of the first access message is as Figure 10 shown, including but not limited to the routing mode (routingmode) field and the LB field. Among them, the meanings of RM and LB are as shown in Table 3 below:

[0148] Table 3

[0149] RM Message Routing Mode Indicator Field LB Load Sharing Factor in the Message, which can participate in the hash calculation during routing multi-path load sharing

[0150] It should be noted that the first access message also includes other information. In this embodiment, it mainly involves the RM field and the LB field in the message. Other fields can refer to the description of the message format in the current general bus protocol, which will not be elaborated here.

[0151] Specifically, the definition of the RM field in the message header can be as shown in Table 4 below:

[0152] Table 4

[0153]

[0154] Optionally, if the RM field indicates that the transmission path selection method of the current first access message is the flow-based Hash method, the first host and the intermediate switch can perform Hash routing based on the tuple. For example, in the flow-based Hash, the first host and the intermediate switch can select one or more fields of the message header for Hash routing, such as the five-tuple {srcIP, dstIP, protocol, transport layer source port, transport layer destination port} in the IP message format; for the compressed message format, {srcCNA, dstCNA, LB} can be used for Hash. Hash routing can also select parameter information of the message in the network device, etc. to participate in the hash calculation (such as the incoming port number of the switch, etc.).

[0155] Furthermore, the TAH of the first access message also includes the ODR field. Among them, the definition of the ODR field can be as shown in Table 5 below:

[0156] Table 5

[0157]

[0158]

[0159] Exemplarily, after the first host group forms the first access message, it can pass through a multi-path network (such as Figure 4If the network shown in Figure 6 The method flow shown also includes:

[0160] S640, the first host sends a first access message to the second host.

[0161] Specifically, the switch determines the path for transmitting the first access message among multiple paths based on the RM field in the first access message. Further, after receiving the first access message, the second host can determine the in-order requirement of the first access message according to the "ODR" field in the first access message.

[0162] Figure 6 In the communication method, through the resource registration phase, it is recognized that there is no in-order requirement between messages accessing certain resource spaces and they can be executed out of order, or it is recognized that there is an in-order requirement for messages accessing certain resource spaces, that is, the in-order requirements between messages accessing different resource spaces can be obtained in advance. Further, the relevant information is configured in the decoder table entry. When the access request is sent, the corresponding in-order attribute can be obtained by querying the relevant information in the decoder table entry, and the relevant fields of the message can be filled according to the in-order attribute. In the in-order scenario, multiple paths can still be utilized.

[0163] For ease of understanding, the following uses a specific example to illustrate Figure 6 In the communication method shown, how to achieve in-order transmission of messages in a multi-path scenario.

[0164] Example 1:

[0165] Step 1: The Load / store operation issued by the xPU of the first host reaches the unified bus controller in the first host via the internal bus;

[0166] Step 2: The unified bus controller determines that this Load / store operation needs to be sent to the second host via the unified bus link;

[0167] Step 3: The unified bus controller sends a table lookup request to the decoder table entry;

[0168] Step 4: Perform an internal table lookup according to the HPA to obtain the corresponding information, which includes information such as UBA, Order ID, and Order Type provided when the second host registers the resource space;

[0169] Step 5: After obtaining the destination communication object information according to the look-up decoder table entry, the general bus controller queries the internal routing table to obtain multiple reachable "out ports / paths". The general bus controller uses the "Order ID" as the routing input for the multiple reachable "out ports / paths", and routes the packets with the same "Order ID" to the same "out port / path".

[0170] Step 6: The general bus controller performs packet assembly, fills the "order type" obtained by querying the decoder table entry into the "ODR" of the packet, fills the "Order ID" into the "LB" of the packet, sets the "bit0 of RM" in the packet to 0, and fills other information (such as, UBA, DstEID, TokenID, …) into the corresponding positions of the packet.

[0171] Step 7: When the packet is transmitted to the switch, the switch detects that the "bit0 of RM" in the packet is set to 0 and adopts the Hash routing mechanism. For the compressed packet format, {srcCNA, dstCNA, LB} can be used for Hash. Therefore, the same {srcCNA, dstCNA, LB} can reach the second host through a determined path.

[0172] Step 8: For the second host, the packets corresponding to the same Order ID of load / store sent from the same source device are received from the same physical port, and the second host performs sequence processing according to the "ODR" in the packet.

[0173] It should be understood that in the embodiments of the present application Figures 5 to 10 The specific examples shown are only to help those skilled in the art better understand the embodiments of the present application, rather than limiting the scope of the embodiments of the present application. It should also be understood that the magnitudes of the sequence numbers of the above processes do not mean the order of execution is prior or subsequent. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0174] It should also be understood that in various embodiments of the present application, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0175] The above mainly introduced the solution provided by the embodiments of the present application from the perspective of methods. To implement the above functions, it includes the corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should easily realize that, combining the units and algorithm steps of each example described in the embodiments disclosed in this article, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0176] The following will Figures 11 to 13 describe in detail the communication device provided by the embodiments of the present application. It should be understood that the description of the device embodiments corresponds to the description of the method embodiments. Therefore, for the content not described in detail, reference can be made to the above method embodiments. For the sake of brevity, some content will not be repeated.

[0177] The embodiments of the present application can divide the functional modules of the first host or the second host according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical functional division, and there can be other division methods in actual implementation. The following will take the example of dividing each functional module corresponding to each function for illustration.

[0178] Figure 11 Fig. shows the structural schematic diagram of a communication device 1000 provided by the embodiments of the present application.

[0179] As an example, the communication device 1100 can be applied to the first host, and the communication device 1000 can be used to execute the above communication method, for example, used to execute Figure 6 the method shown. Specifically, the communication device 1100 can include a transceiver unit 1110 and a processing unit 1120.

[0180] A transceiver unit 1110 is configured to obtain information of a first resource space in a second host. The information of the first resource space includes a start address of the first resource space, length information of the first resource space, and in-sequence property information corresponding to the first resource space. The in-sequence property information corresponding to the first resource space is used to indicate an in-sequence requirement for a first access message for accessing the first resource space. A processing unit 1120 is configured to configure the information of the first resource space into a decoder entry. The decoder entry includes a first entry, and the first entry includes path information corresponding to a first access message for accessing the first resource space and the in-sequence property information corresponding to the first resource space. Among them, there are multiple transmission paths between the first host and the second host.

[0181] As an example, in combination with Figure 6 , the transceiver unit 1010 can be configured to execute S610 and S640, and the processing unit 1020 can be configured to execute S620 and S630.

[0182] It should be noted that Figure 11 the described device can also be used to execute the method steps involved in the deformation of the embodiments shown in the foregoing figures, which will not be elaborated here.

[0183] In another example, a communication device 1100 can be applied to the second host, and the communication device 1100 can be used to execute the above communication method, for example, to execute Figure 5 the method shown.

[0184] A transceiver unit 1010 is configured to receive, for the second host, a first access message from a first host. The first access message is used to access a first resource space in the second host. An in-sequence field of the first access message carries information indicating an in-sequence requirement corresponding to the first access message, and a load sharing factor field of the access message carries information indicating a first transmission path. A processing unit 1120 is configured to determine the in-sequence requirement of the first access message according to the in-sequence field of the first access message. Among them, physical ports for receiving at least one access message transmitted on the first transmission path are the same, and the first access message is one of the at least one access message.

[0185] As an example, in combination with Figure 6 , the transceiver unit 1010 can be configured to execute S610 and S640.

[0186] It should be noted that Figure 11 the described device can also be used to execute the method steps involved in the deformation of the embodiments shown in the foregoing figures, which will not be elaborated here.

[0187] An embodiment of the present application further provides a chip system 1200, asFigure 12 As shown, the chip system 1200 includes at least one processor and at least one interface circuit. As an example, when the chip system 1200 includes one processor and one interface circuit, the one processor can be Figure 12 the processor 1210 shown by the solid line box in Figure 12 (or the processor 1210 shown by the dashed line box), and the one interface circuit can be

[0188] the interface circuit 1220 shown by the solid line box in Figure 12 (or the interface circuit 1220 shown by the dashed line box). There is no limitation on this. The processor 1210 and the interface circuit 1220 can be interconnected by lines. For example, the interface circuit 1220 can be used to receive signals (such as instructions stored in a memory, etc.). Also for example, the interface circuit 1220 can be used to send signals to other devices (such as the processor 1210). Figure 12 When the chip system 1200 includes two processors and two interface circuits, the two processors include

[0189] the processor 1210 shown by the solid line box and the processor 1210 shown by the dashed line box in

[0190] and the two interface circuits include

[0191] Figure 13 the interface circuit 1220 shown by the solid line box and the interface circuit 1220 shown by the dashed line box in

[0192] In one embodiment, the computer program product is provided using the signal-bearing medium 1300. The signal-bearing medium 1300 can include one or more program instructions, which when run by one or more processors can provide the above for Figure 6The described functions or some of the functions. Thus, for example, with reference to Figure 6 one or more features of S610 to S640 may be borne by one or more instructions associated with the signal-bearing medium 1300. In addition, Figure 13 The program instructions in also describe example instructions.

[0193] In some examples, the signal-bearing medium 1300 may include a computer-readable medium 1301, such as but not limited to, a hard disk drive, a compact disc (CD), a digital video disc (DVD), a digital tape, a memory, a read-only memory (ROM), or a random access memory (RAM), and so on.

[0194] In some embodiments, the signal-bearing medium 1300 may include a computer-recordable medium 1302, such as but not limited to, a memory, a read / write (R / W) CD, an R / W DVD, and so on.

[0195] In some embodiments, the signal-bearing medium 1300 may include a communication medium 1303, such as but not limited to, a digital and / or analog communication medium (e.g., an optical fiber cable, a waveguide, a wired communication link, a wireless communication link, and so on). The signal-bearing medium 1300 may be conveyed by a communication medium 1303 in a wireless form. One or more program instructions may be, for example, computer-executable instructions or logic-implemented instructions.

[0196] In some examples, in response to one or more program instructions via the computer-readable medium 1301, the computer-recordable medium 1302, and / or the communication medium 1303, various operations, functions, or actions are provided.

[0197] It should be understood that the arrangements described herein are for illustrative purposes only. Thus, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and groups of functions, etc.) can be used instead, and some elements can be omitted altogether according to the desired results. Additionally, many of the elements described can be implemented as discrete or distributed components, or as functional entities combined with other components in any suitable combination and location.

[0198] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled professionals may use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0199] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0200] In several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0201] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0202] In addition, the functional units in each embodiment of this application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0203] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs that can store program codes.

[0204] As described above, the above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A communication method, characterized in that, the method includes: The first host obtains information of a first resource space in the second host, where the information of the first resource space includes the start address of the first resource space, the length information of the first resource space, and the in-sequence attribute information corresponding to the first resource space, and the in-sequence attribute information corresponding to the first resource space is used to indicate the in-sequence requirement for a first access message for accessing the first resource space; The first host saves the in-sequence attribute information corresponding to the first resource space and first path information, where the first path information is used to indicate the transmission path corresponding to a first access message for accessing the first resource space, wherein the transmission path indicated by the first path information is one of multiple transmission paths between the first host and the second host.

2. The method according to claim 1, characterized in that, the first host saving the in-sequence attribute information corresponding to the first resource space and first path information includes: The first host configures the information of the first resource space into a decoder entry, and the decoder entry includes a first entry, and the first entry includes the first path information and the in-sequence attribute information corresponding to the first resource space.

3. The method according to claim 2, characterized in that, when the first host determines to send a first access message to the second host to access the first resource space, the method includes: The first host queries the decoder entry to determine the first path information and the in-sequence requirement corresponding to the first access message; The first host determines the output port and the first transmission path corresponding to the first access message according to the first path information; wherein the first transmission path is the transmission path for transmitting the first access message among the multiple transmission paths, and the first transmission path is used to transmit access messages corresponding to the same path information.

4. The method according to claim 3, characterized in that, the method further includes: The first host generates the first access message according to the first transmission path and the in-sequence requirement corresponding to the first access message, wherein information indicating the in-sequence requirement corresponding to the first access message is carried in the in-sequence field of the first access message, and information indicating the first transmission path is carried in the load sharing factor field of the first access message.

5. The method according to claim 4, characterized in that, the routing indication field of the first access message is set to 0, wherein setting the routing indication field to 0 is used to indicate that a hash routing mechanism is adopted to determine the transmission path of the first access message.

6. The method according to any one of claims 1 to 5, characterized in that, the first host obtaining the in-sequence attribute information corresponding to the first resource space includes: The first host receives the in-sequence attribute information corresponding to the first resource space from the second host; or, The first host determines the in-sequence attribute information corresponding to the resource space according to the use of the first resource space.

7. The method according to any one of claims 1 to 6, It is characterized in that The method further includes: The first host obtains information of a second resource space in the second host, where the information of the second resource space includes a start address of the second resource space, length information of the second resource space, and order-preserving attribute information corresponding to the second resource space, and the order-preserving attribute information corresponding to the second resource space is used to indicate an order-preserving requirement for a second access message for accessing the second resource space; The first host saves the order-preserving attribute information corresponding to the second resource space and second path information, where the second path information is used to indicate a transmission path corresponding to a second access message for accessing the second resource space, wherein the second path information is different from the first path information, and the order-preserving attribute information corresponding to the second resource space is different from the order-preserving attribute information corresponding to the first resource space.

8. The method according to claim 7, It is characterized in that The first host saving the order-preserving attribute information corresponding to the second resource space and second path information includes: The first host configures the information of the second resource space into an entry in a decoder table, where the entry in the decoder table includes a second entry, and the second entry includes the second path information and the order-preserving attribute information corresponding to the second resource space.

9. The method according to any one of claims 1 to 8, It is characterized in that The order-preserving requirement for the first access message includes any one of the following: Strong order-preserving SO, no order-preserving NO, or flexible order-preserving RO.

10. A communication method, It is characterized in that The method includes: The second host receives a first access message from the first host, where the first access message is used to access a first resource space in the second host, information indicating an order-preserving requirement corresponding to the first access message is carried in an order-preserving field of the first access message, and information indicating a first transmission path is carried in a load sharing factor field of the access message; The second host determines the order-preserving requirement for the first access message according to the order-preserving field of the first access message; wherein the second host receives the first access message on the same physical port as at least one access message transmitted on the first transmission path, and the first access message is one of the at least one access message.

11. A communication method, It is characterized in that It includes: The first host obtains information of a first resource space in the second host, where the information of the first resource space includes a start address of the first resource space, length information of the first resource space, and order-preserving attribute information corresponding to the first resource space, and the order-preserving attribute information corresponding to the first resource space is used to indicate an order-preserving requirement for a first access message for accessing the first resource space; The first host saves the order-preserving attribute information corresponding to the first resource space and first path information, where the first path information is used to indicate a transmission path corresponding to a first access message for accessing the first resource space, The second host receives a first access message from the first host. The first access message is used to access a first resource space in the second host. Information indicating the in-sequence requirement corresponding to the first access message is carried in the in-sequence field of the first access message, and information indicating a first transmission path is carried in the load sharing factor field of the access message; The second host determines the in-sequence requirement of the first access message according to the in-sequence field of the first access message; Wherein, the physical ports for the second host to receive at least one access message transmitted on the first transmission path are the same, and the first access message is one of the at least one access message.

12. A communication system, Characterized in that, It includes a first host and at least one second host, The first host is configured to obtain information about a first resource space in a second host. The information about the first resource space includes the starting address of the first resource space, the length information of the first resource space, and the in-sequence attribute information corresponding to the first resource space. The in-sequence attribute information corresponding to the first resource space is used to indicate the in-sequence requirement corresponding to a first access message for accessing the first resource space; The first host is configured to save the in-sequence attribute information corresponding to the first resource space and first path information. The first path information is used to indicate the transmission path corresponding to a first access message for accessing the first resource space, The second host is configured to receive a first access message from the first host. The first access message is used to access a first resource space in the second host. Information indicating the in-sequence requirement corresponding to the first access message is carried in the in-sequence field of the first access message, and information indicating a first transmission path is carried in the load sharing factor field of the access message; The second host determines the in-sequence requirement of the first access message according to the in-sequence field of the first access message; Wherein, the physical ports for the second host to receive at least one access message transmitted on the first transmission path are the same, and the first access message is one of the at least one access message.

13. A communication device, Characterized in that, It includes: A processor, configured to read instructions stored in a memory. When the processor executes the instructions, the communication device implements the method according to any one of claims 1 to 10; or, the communication device implements the method according to claim 11.

14. A computer program product, Characterized in that, The computer program product includes computer program code. When the computer program code runs on a computer, the method according to any one of claims 1 to 10 is executed; or, when the computer program code runs on a computer, the method according to claim 11 is executed.

15. A computer-readable storage medium, Characterized in that, Comprising a computer program which, when running on a computer system, causes a processing module in the computer system to execute the method according to any one of claims 1 to 10; or which, when running on a computer system, causes a processing module in the computer system to execute the method according to claim 11.

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