High-speed serial communication interface, chip and clock distribution method

Abstract

The application provides a high-speed serial communication interface, a chip and a clock distribution method. The high-speed serial communication interface comprises an internal-external interconnection module, at least one internal reference clock buffer module and an external reference clock buffer module. The external reference clock buffer module is connected with the internal-external interconnection module, and the internal-external interconnection module is connected with the at least one internal reference clock buffer module. The external reference clock buffer module is used for receiving a clock signal of an external clock source and outputting the clock signal to the internal-external interconnection module. The at least one internal reference clock buffer module is used for receiving a clock signal from other high-speed serial communication interfaces and outputting the clock signal to the internal-external interconnection module, or outputting a clock signal received from the internal-external interconnection module to other high-speed serial communication interfaces. The internal-external interconnection module is used for taking the clock signal received from the external reference clock buffer module or the clock signal received from the at least one internal reference clock buffer module as a reference clock of the high-speed serial communication interface.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to a high-speed serial communication interface, a chip and a clock distribution method. BACKGROUND

[0002] High-speed network switching chips play a vital role in modern communication and data centers. These chips usually contain multiple SerDes ports. In large-scale and super-large-scale switching chips, the number of SerDes can reach hundreds, and the number of lanes can reach several hundreds, as shown in FIG. 1. Figure 1

[0003] Each SerDes needs a high-speed differential clock signal to ensure correct output and reception of data. CML (Current Mode Logic) level is a commonly used high-speed differential clock signal level standard. The differential clock of the CML level standard is usually used as the reference clock of the Serdes, and the frequency is usually 100 MHz, 156.25 MHz, etc. SUMMARY

[0004] The application aims to provide a high-speed serial communication interface, a chip and a clock distribution method, and aims to solve the problems of high difficulty and high cost in top-level processing of differential clock networks during chip integration and packaging in the related art.

[0005] According to a first aspect of the application, a high-speed serial communication interface is provided, comprising: an internal-external interconnection module, at least one internal reference clock buffer module and an external reference clock buffer module; the external reference clock buffer module is connected to the internal-external interconnection module, and the internal-external interconnection module is connected to the at least one internal reference clock buffer module;

[0006] The external reference clock buffer module is configured to receive a clock signal of an external clock source and output the clock signal to the internal-external interconnection module.

[0007] The at least one internal reference clock buffer module is configured to receive a clock signal from another high-speed serial communication interface and output the clock signal to the internal-external interconnection module, or output a clock signal received from the internal-external interconnection module to another high-speed serial communication interface.

[0008] The internal-external interconnection module is configured to take the clock signal received from the external reference clock buffer module or the clock signal received from the at least one internal reference clock buffer module as a reference clock of the high-speed serial communication interface.

[0009] In an optional embodiment, the internal-external interconnection module further outputs the received clock signal to one or more of the at least one internal reference clock buffer module. In an optional embodiment, the internal-external interconnection module further outputs the received clock signal to one or more of the at least one internal reference clock buffer module.

[0010] In an optional embodiment, under the control of a first enable signal, the external reference clock buffer module receives a clock signal from an external clock source and outputs to the internal-external interconnection module; under the control of a second enable signal, the at least one internal reference clock buffer module receives a clock signal from other high-speed serial communication interfaces and outputs to the internal-external interconnection module, or outputs the clock signal received from the internal-external interconnection module to other high-speed serial communication interfaces.

[0011] In an optional embodiment, after the high-speed serial communication interface is integrated and packaged in a chip, an external pin electrically connected with the external reference clock buffer module is packaged on the top layer of the chip.

[0012] In an optional embodiment, the internal reference clock buffer module is multiple, and the multiple internal reference clock buffer modules are distributed in different directions on the edge of the high-speed serial communication interface.

[0013] According to a second aspect of the present application, a chip is provided, comprising one or more high-speed serial communication interfaces of the first aspect.

[0014] In an optional embodiment, the high-speed serial communication interface comprises at least one first high-speed serial communication interface and at least one second high-speed serial communication interface; after the first high-speed serial communication interface is packaged in the chip, an external pin is packaged on the top layer of the chip and electrically connected with the first high-speed serial communication interface, and after the second high-speed serial communication interface is packaged in the chip, a clock signal line of the second high-speed serial communication interface is not electrically connected with an external pin packaged on the top layer of the chip.

[0015] In an optional embodiment, at least one internal reference clock buffer module of the first high-speed serial communication interface is connected with at least one second high-speed serial communication interface;

[0016] The external reference clock buffer module of the first high-speed serial communication interface receives a clock signal from the external pin and outputs the clock signal to the internal-external interconnection module;

[0017] The at least one internal reference clock buffer module of the first high-speed serial communication interface receives the clock signal from the internal-external interconnection module and outputs the clock signal to the connected second high-speed serial communication interface.

[0018] In an optional embodiment, the same second high-speed serial communication interface is connected with one of the first high-speed serial communication interfaces or with other second high-speed serial communication interfaces; wherein the second high-speed serial communication interface connected with other second high-speed serial communication interfaces receives a clock signal from the other second high-speed serial communication interfaces.

[0019] In an optional embodiment, further comprising: a control management unit, wherein the control management unit is configured to output a first enable signal and / or a second enable signal to one or more of the high-speed serial communication interfaces;

[0020] The control management unit controls the high-speed serial communication interfaces to receive a clock signal from an external pin through the external reference clock buffer module under the control of the first enable signal or to receive a clock signal from another high-speed serial communication interface through the internal reference clock buffer module under the control of the second enable signal through the first enable signal and the second enable signal, and / or the control management unit controls part of the high-speed serial communication interfaces to output a clock signal to another high-speed serial communication interface through the internal reference clock buffer module through the second enable signal.

[0021] According to a third aspect of the present application, a clock distribution method is provided, which is implemented on a chip as described in the second aspect, comprising:

[0022] outputting a first enable signal and a second enable signal to the high-speed serial communication interfaces on the chip;

[0023] The first enable signal and the second enable signal cooperate to enable the high-speed serial communication interfaces to receive a clock signal from an external pin through the external reference clock buffer module under the control of the first enable signal or to receive a clock signal from another high-speed serial communication interface through the internal reference clock buffer module under the control of the second enable signal, and / or part of the high-speed serial communication interfaces to output a clock signal to another high-speed serial communication interface through the internal reference clock buffer module under the control of the second enable signal.

[0024] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0025] The chip architecture of the present application is more flexible, and the distribution scheme of the clock signal can be easily adjusted. The top-level integration of the chip design is simple, and only the differential clock connection between SerDes needs to be completed and simply controlled. In implementation, the buffer is built-in the SerDes, and the position is determined according to the packaging layout of the SerDes. The top-level routing resources are not occupied, the area is more optimized, and the surrounding layout is not affected. It is especially suitable for top-level routing resource shortage, super-large scale chip, and does not need to handle the differential clock network at the top level, which can reduce the physical implementation difficulty and greatly shorten the development cycle.

[0026] Other features and advantages of the present application will be set forth in the following specification, and in part will be apparent from the description, or can be learned by practice of the application. The objects and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0028] Figure 1 is a chip layout structure diagram of a multi-Serdes interface according to the related art.

[0029] Figure 2 is a centralized clock distribution network structure diagram in a chip of a multi-Serdes interface according to the related art.

[0030] Figure 3 is a distributed clock distribution network structure diagram in a chip of a multi-Serdes interface according to the related art.

[0031] Figure 4 is a structure diagram of a high-speed serial communication interface according to an exemplary embodiment of the present application.

[0032] Figure 5 is a chip structure diagram of a plurality of high-speed serial communication interfaces according to an exemplary embodiment of the present application.

[0033] Figure 6 is a simplified chip structure diagram of a plurality of high-speed serial communication interfaces according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort are within the protection scope of the present application.

[0035] In a multi-port SerDes system, the distribution of high-speed differential clock faces the following problems: clock jitter, complexity of clock distribution, power consumption and area, engineering implementation difficulty, etc. The related differential clock distribution technology mainly has two kinds of centralized and distributed, wherein:

[0036] Centralized: Shared differential clock source, signals are distributed to each SerDes port through a global clock tree network.

[0037] Distributed: Multiple differential clock sources are shared locally by SerDes, reducing the length of the clock tree network.

[0038] For the centralized differential clock distribution network architecture, see [link to architecture]. Figure 2 As shown, it includes: a central clock source, a branch network from the starting point of the clock source to each end SerDes, and differential buffers located at different positions in the network. The advantage of centralized differential clocking is its simple structure, while its disadvantages are reflected in three aspects: clock quality, resource consumption, and complexity. In terms of clock quality, the large length of the clock tree and the number of branch points lead to increased latency and jitter. In terms of resources, more buffers are needed to optimize latency and jitter. In terms of complexity, the clock tree needs to be laid out and routed at the top level of the chip, requiring careful evaluation of the tree structure and the number and location of buffers, which makes physical implementation difficult and the development cycle long.

[0039] See the distributed differential clock distribution network structure. Figure 3 As shown, this includes multiple clock sources, a shared clock source for multiple SerDes within a local area, and differential buffers located within the local network. Compared to centralized clocking, distributed differential clocking divides the clock network into multiple smaller blocks, resulting in a shorter clock tree length and better jitter and latency. The disadvantage of distributed differential clocking lies in its complexity. Since the clock tree still needs to be laid out and routed at the top level of the chip, careful evaluation of the tree structure and the number and location of buffers is required, making physical implementation difficult and time-consuming.

[0040] Regardless of whether it's a centralized or the more common distributed approach, the differential clock network structure still needs to be determined at the top level, and the number and location of buffers need to be planned, which also occupies routing resources. In large-scale and ultra-large-scale switching chips, the number of SerDes can reach tens or hundreds, and the number of channels can reach hundreds, which makes the difficulty and cost of processing the differential clock network at the top level even more prominent.

[0041] To this end, the application proposes a solution that lowers the buffer of CMLCLK to the inside of SerDes as a standard component of SerDes, and realizes clock interconnection in four directions with matching logic, so that SerDes itself can be a transfer node of reference clock, and receive and forward the reference clock. Further, a small amount of configuration signals for serdes reference clock interconnection are added to topCCU to realize the reference clock interconnection configuration of each serdes. In the solution, only the wiring interconnection of reference clock between serdes is needed according to the clock network distribution architecture in the chip top layer integration, which can reduce the difficulty of chip design and physical implementation, optimize resources, and make the architecture more flexible, and can be easily and quickly iterated and adjusted.

[0042] Referring to Figure 4 The application exemplarily proposes a high-speed serial communication interface, which comprises an internal-external interconnection module, at least one internal reference clock buffer module and an external reference clock buffer module; the external reference clock buffer module is connected with the internal-external interconnection module, and the internal-external interconnection module is connected with the at least one internal reference clock buffer module.

[0043] The external reference clock buffer module is configured to receive a clock signal of an external clock source and output the clock signal to the internal-external interconnection module.

[0044] The at least one internal reference clock buffer module is configured to receive a clock signal from other high-speed serial communication interfaces and output the clock signal to the internal-external interconnection module, or output a clock signal received from the internal-external interconnection module to other high-speed serial communication interfaces.

[0045] The internal-external interconnection module is configured to take a clock signal received from the external reference clock buffer module or a clock signal received from the at least one internal reference clock buffer module as a reference clock of the high-speed serial communication interface.

[0046] Exemplarily, the high-speed serial communication interface Serdes can comprise one or more internal reference clock buffer modules B-E that output or receive clock signals in different directions, which can be understood as different wiring directions after the high-speed serial communication interface is laid out on a chip. The internal reference clock buffer module is bidirectional, that is, it can receive clock signals int_ref_clk_* (int_ref_clk_north, int_ref_clk_sorth, int_ref_clk_west, int_ref_clk_east shown in the figure) from other high-speed serial communication interfaces in different wiring directions laid out on a chip, and output clock signals int_ref_clk_* to other high-speed serial communication interfaces in different wiring directions laid out on a chip.

[0047] Exemplarily, the external reference clock buffering module A receives the clock signal Ext_ref_clk from the external clock source, which can be understood as a clock source outside the chip after the high-speed serial communication interface is packaged on the chip. It should be noted that the same high-speed serial communication interface either receives the clock signal of the external clock source through the external reference clock buffering module, or receives the clock signal of other high-speed serial communication interfaces through the internal reference clock buffering module, and in the case of multiple internal reference clock buffering modules, only one of the internal reference clock buffering modules receives the clock signal, and the other internal reference clock buffering modules output or do not output the clock signal to other high-speed serial communication interfaces.

[0048] Exemplarily, the clock signals received by the external reference clock buffering module and the internal reference clock buffering module are both output to the internal-external interconnection module F. If the internal-external interconnection module F receives the clock signal of the external reference clock buffering module, it takes the clock signal as the clock of the high-speed serial communication interface, and also outputs the clock signal to the internal reference clock buffering module. If the internal-external interconnection module F receives the clock signal of the internal reference clock buffering module, it takes the clock signal as the clock of the high-speed serial communication interface, and also outputs the clock signal to the internal reference clock buffering module other than the internal reference clock buffering module receiving the clock signal.

[0049] Exemplarily, the internal-external interconnection module can selectively output the clock signal to part of the internal reference clock buffering modules. The internal-external interconnection module can also output the clock signal to all the internal reference clock buffering modules, and whether the internal reference clock buffering module receives or outputs the clock signal to other high-speed serial communication interfaces can be controlled by a special control management unit.

[0050] In some optional embodiments, the internal-external interconnection module also outputs the received clock signal to one or more of the at least one internal reference clock buffering module.

[0051] Exemplarily, the external reference clock buffer module or the internal reference clock buffer module both output the received clock signal to the internal-external interconnection module, and the internal-external interconnection module outputs the received clock signal to other internal reference clock buffer modules no matter whether the clock signal is received from the external reference clock buffer module or the internal reference clock buffer module. It should be noted that if the clock signal is received from the external reference clock buffer module, the internal-external interconnection module outputs the clock signal to all the internal reference clock buffer modules, and if the clock signal is received from one of the internal reference clock buffer modules, the internal-external interconnection module outputs the clock signal to the remaining internal reference clock buffer modules. It can be understood that the internal-external interconnection module receives the clock signal from either the external reference clock buffer module or one of the internal reference clock buffer modules. Of course, the internal-external interconnection module can also not output the clock signal to any of the internal reference clock buffer modules.

[0052] In some optional embodiments, under the control of a first enable signal, the external reference clock buffer module receives a clock signal from an external clock source and outputs the clock signal to the internal-external interconnection module; and under the control of a second enable signal, at least one internal reference clock buffer module receives a clock signal from another high-speed serial communication interface and outputs the clock signal to the internal-external interconnection module, or outputs the clock signal received from the internal-external interconnection module to the other high-speed serial communication interface.

[0053] Exemplarily, the high-speed serial communication interface can receive a first enable signal aa and at least one second enable signal bb-dd from the external clock source, the second enable signals corresponding to the internal reference clock buffer modules one by one. The first enable signal is used to control whether the external reference clock buffer module receives the clock signal from the external clock source, and if the clock signal is received from the external clock source under the control of the first enable signal, the external reference clock buffer module will output the clock signal received from the external to the internal-external interconnection module. The second enable signal is used to control whether the corresponding internal reference clock buffer module is in communication with other high-speed serial communication interfaces, and in the case of communication with other high-speed serial communication interfaces, the second enable signal is also used to control the signal direction of the corresponding internal reference clock buffer module, that is, whether to output the clock signal to other high-speed serial communication interfaces or receive the clock signal from other high-speed serial communication interfaces. It should be noted that in the case that the high-speed serial communication interface receives the clock signal from the external clock source through the external reference clock buffer module, it no longer receives the clock signal of other high-speed serial communication interfaces from any internal reference clock buffer module; and if the high-speed serial communication interface receives the clock signal through the internal reference clock buffer module, it cannot receive the clock signal of the external clock source through the external reference clock buffer module, and can only receive the clock signal from other high-speed serial communication interfaces by one internal reference clock buffer module, while other internal reference clock buffer modules either output the clock signal to other high-speed serial communication interfaces or neither receive nor output the clock signal.

[0054] In some optional embodiments, after the high-speed serial communication interface is integrated into a chip, external pins electrically connected to the external reference clock buffer module are packaged on the top layer of the chip.

[0055] Exemplarily, when the high-speed serial communication interface is packaged in a chip, external pins electrically connected to the external reference clock buffer module of the high-speed serial communication interface can be packaged on the top layer of the chip during integration. When the chip is used, the external pins can be connected to the external clock source, so that the high-speed serial communication interface can be provided with a clock signal through the external clock source. Of course, it can be understood that the high-speed serial communication interface can also not be packaged with external pins during integration of the chip, but receive the clock signal from other high-speed serial communication interfaces through the internal reference clock buffer module.

[0056] In some optional embodiments, the internal reference clock buffer module is multiple, and the multiple internal reference clock buffer modules are distributed in different directions on the edge of the high-speed serial communication interface.

[0057] Exemplarily, the plurality of internal reference clock buffer modules can be arranged in different wiring directions inside the high-speed serial communication interface. For example, four internal reference clock buffer modules are arranged in the up, down, left and right directions with the high-speed serial communication interface as the reference point. The internal reference clock buffer modules in the four directions can receive or output clock signals from other high-speed serial communication interfaces around the high-speed serial communication interface through wiring design. It should be noted that, in order to simplify chip design and realize logic, the high-speed serial communication interface only outputs clock signals to other high-speed serial communication interfaces adjacent to the layout.

[0058] The above high-speed serial communication interface proposed in the present application internally embeds the CML CLK buffer (external reference clock buffer module) into the high-speed serial communication interface. The reference clock can be directly input into the high-speed serial communication interface from the external bump, or input from other high-speed serial communication interfaces in one of the plurality of directions (up, down, left and right). Meanwhile, in cooperation with the external enable signal, the clock signal can also be output in the up, down, left and right directions.

[0059] Correspondingly, referring to Figure 5 Exemplarily, the present application proposes a chip comprising one or more high-speed serial communication interfaces as described above.

[0060] The details of the high-speed serial communication interface included in the chip can be referred to the description of the high-speed serial communication interface above, and will not be repeated here.

[0061] In some optional embodiments, the high-speed serial communication interface comprises at least one first high-speed serial communication interface and at least one second high-speed serial communication interface; the first high-speed serial communication interface is electrically connected to the external pins packaged on the top layer of the chip after being packaged in the chip, and the clock signal line of the second high-speed serial communication interface is not electrically connected to the external pins packaged on the top layer of the chip after being packaged in the chip.

[0062] Exemplarily, as Figure 6As shown, the high-speed serial communication interface can be divided into two types, one is the high-speed serial communication interface receiving clock signal from external clock source through external reference clock buffer module, for convenience of description, it is called first high-speed serial communication interface in this paper; the other is the module receiving clock signal through internal reference clock buffer module, for convenience of description, it is called second high-speed serial communication interface in this paper. Since the first high-speed serial communication interface needs to receive clock signal from external clock source, therefore, when the chip is integrated and packaged, the external pin bump is packaged on the top layer, so that the external clock source inputs the clock signal to the external reference clock buffer module of the first high-speed serial communication interface through the external pin. The second high-speed serial communication interface receives clock signal from other high-speed serial communication interface (which can be first high-speed serial communication interface or other second high-speed serial communication interface) through internal reference clock buffer module, instead of from external clock source, therefore, the clock signal line of the second high-speed serial communication interface does not need to be packaged as external pin.

[0063] In some optional embodiments, at least one internal reference clock buffer module of the first high-speed serial communication interface is connected with at least one second high-speed serial communication interface;

[0064] The external reference clock buffer module of the first high-speed serial communication interface receives clock signal from external pin, and outputs the clock signal to the internal-external interconnection module;

[0065] At least one internal reference clock buffer module of the first high-speed serial communication interface receives clock signal from the internal-external interconnection module, and outputs the clock signal to the connected second high-speed serial communication interface.

[0066] Exemplarily, the first high-speed serial communication interface can directly receive clock signal from external clock source, which can be provided to surrounding second high-speed serial communication interface through internal reference clock buffer module, in this way, the design and physical implementation difficulty of the chip can be reduced.

[0067] Exemplarily, after the external reference clock buffer module of the first high-speed serial communication interface receives clock signal from external clock source, it takes the clock signal as its own reference clock, and at the same time, outputs the clock signal to the internal-external interconnection module, which in turn provides the clock signal to each internal reference clock buffer module, so that under the control of the enable signal, the clock signal is provided to the surrounding second high-speed serial communication interface by the corresponding internal reference clock buffer module.

[0068] The second high-speed serial communication interface, after receiving the clock signal from the first high-speed serial communication interface of the periphery, can use the clock signal as its reference clock, and further provide the clock signal to other second high-speed serial communication interfaces through the internal reference clock buffer module. It should be noted that the first high-speed serial communication interface only receives the clock signal from the external clock source, and the second high-speed serial communication interface receives the clock signal of other high-speed serial communication interfaces through one of the internal reference clock buffer modules, and the first high-speed serial communication interface or the second high-speed serial communication interface can output the clock signal to one or more other second high-speed serial communication interfaces.

[0069] In some optional embodiments, the same second high-speed serial communication interface is connected to one of the first high-speed serial communication interfaces or to other second high-speed serial communication interfaces; the second high-speed serial communication interface connected to the other second high-speed serial communication interfaces receives the clock signal from the other second high-speed serial communication interfaces.

[0070] For example, the same second high-speed serial communication interface receives the clock signal from one of the first high-speed serial communication interfaces or from one of the second high-speed serial communication interfaces.

[0071] In some optional embodiments, the control management unit is configured to output the first enable signal and / or the second enable signal to one or more of the high-speed serial communication interfaces;

[0072] The control management unit controls the high-speed serial communication interface to receive the clock signal from the external pin through the external reference clock buffer module under the control of the first enable signal or to receive the clock signal from the other high-speed serial communication interface through the internal reference clock buffer module under the control of the second enable signal through the first enable signal and the second enable signal, and / or the control management unit controls part of the high-speed serial communication interface to output the clock signal to the other high-speed serial communication interface through the internal reference clock buffer module through the second enable signal.

[0073] Exemplarily, it can be understood that the clock signal lines of part or all of the high-speed serial communication interfaces on the chip can be packaged into external pins bumps, and whether to receive the clock signal of the external clock source can also be controlled by the control management unit. That is, by configuring the first and second enable signals output by the control management unit, the control is performed on part of the high-speed serial communication interfaces to receive the clock signal from the external clock source through the external reference clock buffer module, and the control is performed on the part of the high-speed serial communication interfaces to transmit the clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module. In addition, the control management unit can also control the part of the high-speed serial communication interfaces that receive the clock signal through the internal reference clock buffer module to further output the clock signal to the high-speed serial communication interfaces that do not receive the clock signal from the external clock source through other internal reference clock buffer modules.

[0074] The high-degree-of-freedom integrated scheme provided in the application can package the external reference clock buffer modules of each SerDes into external pin bumps on the top layer of the chip, and can freely select which external pins of the SerDes as the input of the external clock source at the board level, so that the number of external clock sources can be freely selected, and the clock transmission relationship between the serdes can be freely configured by the control of the control management unit topCCU.

[0075] Exemplarily, referring to Figure 6 A simplified scheme of the application is that part of the serdes are packaged into external pins (Ball type packaging is shown in the figure) on the top layer of the chip, and the remaining part of the serdes are not packaged into external pins on the top layer of the chip, and the serdes are connected through the internal reference clock buffer modules in a fixed direction, and each SerDes only uses the internal reference clock buffer modules in the up-down direction. In this simplified scheme, the enable signals of the control management unit topCCU are not necessary, and the first and second enable signals can be set to fixed values.

[0076] In the above simplified scheme, only the external reference clock buffer modules of part of the SerDes are packaged into external pins on the top layer of the chip, so that the clock signal of the external clock source is input only on the external pins of the fixed SerDes at the board level, and the clock transmission relationship between the SerDes in the chip can also be fixed, as shown in Figure 6 The SerDes that receive the clock signal from the external clock source only output the clock signal to the adjacent SerDes in the up-down direction, so that the SerDes enable signal can also be fixed, and therefore the control management unit can not be used, and the enable signal can be set to a fixed value.

[0077] The application scheme has at least the following advantages over related art:

[0078] The chip architecture of the application scheme is more flexible, and the distribution scheme of the clock signal can be conveniently adjusted. The top layer integration of the chip design is simple, and only the differential clock connection between SerDes needs to be completed and is simply controlled. In the implementation, the buffer is built in the SerDes, and the position is determined according to the packaging layout of the SerDes. The top layer wiring resources are not occupied, the area is more optimized, and the surrounding layout is not affected. It is especially suitable for large-scale chips with tight top layer wiring resources, and does not need to process the differential clock network on the top layer, which can reduce the physical implementation difficulty and greatly shorten the development cycle.

[0079] Correspondingly, the application also exemplarily proposes a clock distribution method, which is implemented on the chip described in the above embodiments, comprising:

[0080] outputting the first enable signal and the second enable signal to the high-speed serial communication interface on the chip;

[0081] The first enable signal and the second enable signal cooperate to enable the high-speed serial communication interface to receive the clock signal from the external pin through the external reference clock buffer module under the control of the first enable signal or to receive the clock signal from other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal, and / or some high-speed serial communication interfaces also output the clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal.

[0082] The above method can be implemented by the chip provided in the above embodiments, and the specific implementation manner can refer to the description of the chip in the above embodiments, which will not be repeated here.

[0083] It can be understood that the circuit structure, name and parameter described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above multiple embodiments according to the use needs, and the concept of the application should not be limited to the specific details of the above examples.

[0084] Although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A high-speed serial communication interface, characterized in that, include: The system includes an internal and external interconnect module, at least one internal reference clock buffer module, and an external reference clock buffer module; the external reference clock buffer module is connected to the internal and external interconnect module, and the internal and external interconnect module is connected to the at least one internal reference clock buffer module. The external reference clock buffer module is used to receive clock signals from an external clock source and output them to the internal and external interconnection module; The at least one internal reference clock buffer module is used to receive clock signals from other high-speed serial communication interfaces and output them to the internal and external interconnection modules, or to output the clock signals received from the internal and external interconnection modules to other high-speed serial communication interfaces. The internal and external interconnection module is used as the reference clock of the high-speed serial communication interface, either by receiving the clock signal from the external reference clock buffer module or by receiving the clock signal from the at least one internal reference clock buffer module. The high-speed serial communication interface is integrated and packaged in a chip, and the top layer of the chip is packaged with external pins that are electrically connected to the external reference clock buffer module. The high-speed serial communication interface includes at least one first high-speed serial communication interface and at least one second high-speed serial communication interface; After the first high-speed serial communication interface is encapsulated in the chip, it is electrically connected to the external pins encapsulated on the top layer of the chip. After the second high-speed serial communication interface is encapsulated in the chip, the clock signal line of the second high-speed serial communication interface is not electrically connected to the external pins encapsulated on the top layer of the chip. At least one internal reference clock buffer module of the first high-speed serial communication interface is connected to at least one of the second high-speed serial communication interfaces. The external reference clock buffer module of the first high-speed serial communication interface receives a clock signal from the external pin and outputs the clock signal to the internal and external interconnection module; The at least one internal reference clock buffer module of the first high-speed serial communication interface receives the clock signal from the internal and external interconnection module and outputs the clock signal to the connected second high-speed serial communication interface.

2. The high-speed serial communication interface according to claim 1, characterized in that, The internal and external interconnection module also outputs the received clock signal to one or more of the at least one internal reference clock buffer module.

3. The high-speed serial communication interface according to claim 1 or 2, characterized in that, Under the control of the first enable signal, the external reference clock buffer module receives a clock signal from an external clock source and outputs it to the internal and external interconnection module; Under the control of the second enable signal, the at least one internal reference clock buffer module receives a clock signal from other high-speed serial communication interfaces and outputs it to the internal and external interconnection modules, or outputs the clock signal received from the internal and external interconnection modules to other high-speed serial communication interfaces.

4. The high-speed serial communication interface according to claim 1 or 2, characterized in that, When there are multiple internal reference clock buffer modules, the multiple internal reference clock buffer modules are distributed in different directions at the edge of the high-speed serial communication interface.

5. A chip, characterized in that, It includes a high-speed serial communication interface as described in any one of claims 1-4, wherein the number of high-speed serial communication interfaces is multiple.

6. The chip according to claim 5, characterized in that, The same second high-speed serial communication interface is connected to one of the first high-speed serial communication interfaces or to other second high-speed serial communication interfaces; wherein, the second high-speed serial communication interface connected to other second high-speed serial communication interfaces receives clock signals from the other second high-speed serial communication interfaces.

7. The chip according to any one of claims 5-6, characterized in that, Also includes: A control management unit; the control management unit is configured to output a first enable signal and / or a second enable signal to one or more of the high-speed serial communication interfaces; The control management unit controls the high-speed serial communication interface to receive clock signals from external pins through the external reference clock buffer module under the control of the first enable signal or to receive clock signals from other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal, and / or the control management unit also controls some of the high-speed serial communication interfaces to output clock signals to other high-speed serial communication interfaces through the internal reference clock buffer module via the second enable signal.

8. A clock allocation method, characterized in that, The method is implemented on the chip according to any one of claims 5-6, comprising: Output a first enable signal and a second enable signal to the high-speed serial communication interface on the chip; Wherein, the first enable signal and the second enable signal cooperate to enable the high-speed serial communication interface to receive clock signals from external pins through the external reference clock buffer module under the control of the first enable signal, or to receive clock signals from other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal, and / or some of the high-speed serial communication interfaces also output clock signals to other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal.

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