Random test vector generation device and method and logic built-in self-test structure and method

Abstract

The invention relates to a random test vector generation device and method and a logic built-in self-test structure and method, and the device comprises a random vector generation module which is used for generating a random vector corresponding to each domain in all domains of an X86 instruction; the random instruction generation module is used for generating a random instruction aiming at the X86 instruction by utilizing the generated random vector aiming at each domain of the X86 instruction; the instruction selection module is used for obtaining the length of a random instruction and selecting target random instructions according to the length of the random instruction and the generated random instruction, the selected multiple target random instructions can be randomly combined into the random test vector, and the random test vector is output to the X86 instruction decoding module. Therefore, logic built-in self-testing can be effectively carried out on the X86 instruction decoding module.

Description

Technical Field

[0001] The present disclosure relates to the field of Design for Testability (DFT), and particularly to an apparatus and method for generating random test vectors, as well as a logic built-in self-test structure and method. Background Art

[0002] In the related art, a logic built-in self-test (LBIST) structure can be used to perform a self-test on a circuit under test. The LBIST structure may include a test vector generator, a counter, a test response compression module, and a test control module. The counter counts the generated random test vectors. When the module under test is in the test mode, the test controller controls the test vector generator to generate random test vectors, and sends the generated random test vectors into the circuit under test. After processing in the circuit under test, the data is sent into the test response compression module. The test response compression module makes a judgment on the correctness of the circuit under test by comparing the returned data with a target value, and sends the final test response data back to the test control module, thereby completing the current LBIST built-in self-test.

[0003] In practical applications, it may be necessary to perform a logic built-in self-test on an X86 instruction decoding module. However, if the existing LBIST structure is used to perform a logic built-in self-test on the X86 instruction decoding module as the circuit under test, it is equivalent to using the original completely random test vectors, and there will be several invalid test data, thus unable to effectively perform a logic built-in self-test on the X86 instruction decoding module. Summary of the Invention

[0004] In view of this, the present disclosure provides an apparatus and method for generating random test vectors, as well as a logic built-in self-test structure and method, so as to be able to effectively perform a logic built-in self-test on an X86 instruction decoding module.

[0005] According to a first aspect of the present disclosure, there is provided an apparatus for generating random test vectors, which is used to generate random test vectors to be used when the circuit under test is an X86 instruction decoding module. The generating apparatus includes: a random vector generating module, which is used to generate random vectors corresponding to each domain in all domains of X86 instructions; a random instruction generating module, which is used to generate random instructions for X86 instructions by using the generated random vectors for each domain of X86 instructions; an instruction selection module, which is used to obtain the random instruction length, and select target random instructions according to the random instruction length and the generated random instructions, wherein a plurality of selected target random instructions can be randomly combined into the random test vectors, and the random test vectors are output to the X86 instruction decoding module.

[0006] In a possible implementation, the random vector generation module includes an 8-bit pseudo-random vector generator, a 16-bit pseudo-random vector generator, a 24-bit pseudo-random vector generator, and a 32-bit pseudo-random vector generator. For each domain in all domains of the X86 instruction, the corresponding bit pseudo-random vector generator included in the random vector generation module is respectively called to generate the random vector corresponding to this domain.

[0007] In a possible implementation, the random instruction generation module is configured to: for the random vector corresponding to each domain of the generated X86 instruction, respectively select the random vector corresponding to each domain according to the situation, and randomly combine the selected random vectors to obtain the random instruction.

[0008] In a possible implementation, the random instruction generation module includes an 18-bit random sequence generator. The 18-bit random sequence generator is divided into six groups of 3 bits each. Each group of the random sequence generator corresponds to a domain of the X86 instruction. Among them, the first bit of each group of the random sequence generator can represent whether the domain corresponding to this group of the random sequence generator exists in the generated random instruction, and the second and third bits of each group of the random sequence generator can represent the length of the domain corresponding to this group of the random sequence generator.

[0009] In a possible implementation, the length of the random instruction generated by the random instruction generation module can be calculated according to whether the corresponding domain of the X86 instruction exists and the length of the corresponding domain that exists.

[0010] In a possible implementation, the instruction selection module includes a 4-bit random sequence generator. The 4-bit random sequence generator obtains the random instruction length and selects a random instruction with the instruction length being the random instruction length from the generated random instructions as the target random instruction.

[0011] In a possible implementation, the selected multiple target random instructions are randomly combined into a 128-bit test vector as the random test vector.

[0012] In a possible implementation, the above-mentioned generation device further includes: a monitoring module, which is used to obtain and store filtering information related to the instruction length and / or instruction type from the X86 instruction decoding module. Among them, when generating a random test vector each time, the redundant random test vectors that have been covered are filtered according to the filtering information.

[0013] In a possible implementation, all fields of the X86 instruction are a prefix field, an opcode field, an address formation specifier field, a scale index byte field, an offset field, and an immediate field. Correspondingly, the random vector generation module obtains a constraint condition for imposing a constraint on at least one of the prefix field, the address formation specifier field, and the scale index byte field according to a test scenario, and generates a random vector corresponding to the corresponding field according to the constraint condition.

[0014] In a possible implementation, the constraint conditions for imposing a constraint on the prefix field include: using a constraint to define a valid value range of a corresponding type of prefix in the prefix field; and / or using a constraint to define that a corresponding field in the prefix field is a non-random value.

[0015] In a possible implementation, the address formation specifier field includes a Mod field, a Reg field, and an R / M field. Correspondingly, the constraint conditions for imposing a constraint on the address formation specifier field include using a constraint to define the value of the R / M field when the Mod field takes a corresponding value.

[0016] In a possible implementation, the constraint conditions for imposing a constraint on the scale index byte field include using a constraint to define that the use of the scale index byte field depends on the value of the Mod field.

[0017] In a possible implementation, the random instruction generation module obtains a constraint condition defined according to the X86 instruction encoding rule, and generates a random instruction for the X86 instruction according to the constraint condition and the generated random vector for each field of the X86 instruction.

[0018] According to a second aspect of the present disclosure, a logic built-in self-test (LBIST) structure is provided, including: the above-mentioned generating device; a test control module for controlling the generating device to generate a random test vector; an X86 instruction decoding module as a circuit under test, and when the X86 instruction decoding module is in a test mode, inputting the random test vector into the X86 instruction decoding module for decoding; and a test response compression module for comparing a decoded value of the X86 instruction decoding module with a target value to determine the correctness of the X86 instruction decoding module.

[0019] According to a third aspect of the present disclosure, a method for generating random test vectors is provided, which is used to generate random test vectors to be used when the circuit under test is an X86 instruction decoding module. The generating method includes: a random vector generating step of generating random vectors corresponding to each field in all fields of the X86 instruction; a random instruction generating step of using the generated random vectors for each field of the X86 instruction to generate a random instruction for the X86 instruction; an instruction selection step of obtaining the random instruction length and selecting a target random instruction according to the random instruction length and the generated random instruction, wherein a plurality of selected target random instructions can be randomly combined into the random test vector, and the random test vector is output to the X86 instruction decoding module.

[0020] In a possible implementation manner, the random vector generating step includes: for each field in all fields of the X86 instruction, respectively calling a pseudo-random vector generator for the corresponding bit to generate a random vector corresponding to the field, wherein the pseudo-random vector generator for the corresponding bit includes an 8-bit pseudo-random vector generator, a 16-bit pseudo-random vector generator, a 24-bit pseudo-random vector generator, and a 32-bit pseudo-random vector generator.

[0021] In a possible implementation manner, the random instruction generating step includes: for the random vectors corresponding to each field of the generated X86 instruction, respectively selecting the random vectors corresponding to each field according to the situation, and randomly combining the selected random vectors to obtain the random instruction.

[0022] In a possible implementation manner, the module for executing the random instruction generating step includes an 18-bit random sequence generator, and the 18-bit random sequence generator is divided into six groups with 3 bits in each group. Each group of random sequence generators corresponds to a field of the X86 instruction, wherein the first bit of each group of random sequence generators can represent whether the field corresponding to the group of random sequence generators exists in the generated random instruction, and the second and third bits of each group of random sequence generators can represent the length of the field corresponding to the group of random sequence generators.

[0023] In a possible implementation manner, the length of the random instruction generated in the random instruction generating step can be calculated according to whether there is a corresponding field of the X86 instruction and the length of the existing corresponding field.

[0024] In a possible implementation manner, the module for executing the instruction selection step includes a 4-bit random sequence generator, and the 4-bit random sequence generator obtains the random instruction length and selects a random instruction with the instruction length being the random instruction length from the generated random instructions as the target random instruction.

[0025] In a possible implementation, the selected multiple target random instructions can be randomly combined into a 128-bit test vector as the random test vector.

[0026] In a possible implementation, the above generation method further includes: a monitoring step of obtaining and storing filtering information related to instruction length and / or instruction type from the X86 instruction decoding module, where, each time a random test vector is generated, the covered redundant random test vectors are filtered according to the filtering information.

[0027] In a possible implementation, all fields of the X86 instruction are a prefix field, an opcode field, an address formation specifier field, a scale index byte field, an offset field, and an immediate field. Correspondingly, in the random vector generation step, constraint conditions for imposing constraints on at least one of the prefix field, the address formation specifier field, and the scale index byte field according to a test scenario are obtained, and random vectors corresponding to the respective fields are generated according to the constraint conditions.

[0028] In a possible implementation, in the random instruction generation step, constraint conditions defined according to the X86 instruction encoding rule are obtained, and a random instruction for the X86 instruction is generated according to the constraint conditions and the random vectors generated for each field of the X86 instruction.

[0029] According to a fourth aspect of the present disclosure, a logic built-in self-test (LBIST) method is provided, including: when the X86 instruction decoding module as a circuit under test is in a test mode, using the above generation method to generate random test vectors; inputting the random test vectors into the X86 instruction decoding module for decoding; comparing the decoded value of the X86 instruction decoding module with a target value to determine the correctness of the X86 instruction decoding module.

[0030] Therefore, the present disclosure proposes a device and method for generating random test vectors for an X86 instruction decoding module, as well as a logic built-in self-test structure and method. By generating random vectors for different fields of the X86 instruction, randomness in length, and randomness in permutation order, random test vectors for the X86 instruction are finally output. Thus, most of the generated random test vectors are meaningful for the X86 instruction decoding module, so that effective random test vectors for the X86 instruction decoding module can be generated, thereby enabling effective logic built-in self-test for the X86 instruction decoding module.

[0031] Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Description of the Drawings

[0032] The accompanying drawings, which are included in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the present disclosure, and are used to explain the principles of the present disclosure together with the specification.

[0033] Figure 1 Shows the X86 instruction encoding format.

[0034] Figure 2 A block diagram showing the LBIST structure in the related art.

[0035] Figure 3 A block diagram showing a generating device for random test vectors according to an embodiment of the present disclosure.

[0036] Figure 4 A block diagram showing a generating device for random test vectors according to an embodiment of the present disclosure.

[0037] Figure 5 A block diagram showing a generating device for random test vectors according to an embodiment of the present disclosure.

[0038] Figure 6 A block diagram showing the LBIST structure according to an embodiment of the present disclosure.

[0039] Figure 7 A flowchart showing a method for generating random test vectors according to an embodiment of the present disclosure.

[0040] Figure 8 A flowchart showing a logic built-in self-test method according to an embodiment of the present disclosure. Detailed Description of the Invention

[0041] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0042] As used herein, the term "exemplary" means "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0043] In addition, for a better understanding of the present disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art should understand that the present disclosure can be practiced without some of these specific details. In some instances, well-known methods, means, elements, and circuits have not been described in detail so as to highlight the gist of the present disclosure.

[0044] For ease of understanding, the X86 instruction encoding format will be described first. As Figure 1As shown, the X86 instruction includes a prefix field, an opcode field, an address formation specifier (ModR / M) field, a scale index byte (SIB) field, a displacement field, and an immediate field.

[0045] There are four types of prefix fields, including: lock and repeat execution prefixes such as the LOCK prefix or the REP prefix, segment prefixes, prefixes for modifying the default operand length, and prefixes for modifying the default address length. These four types of prefixes can be arranged in any order, and their possible bit lengths are 1 byte (8 bits), 2 bytes (16 bits), 3 bytes (24 bits), or 4 bytes (32 bits). It should be understood that at most all four types exist, and in this case, the length of the prefix field is 4 bytes.

[0046] The possible bit lengths of the opcode field are 1 byte (8 bits), 2 bytes (16 bits), and 3 bytes (24 bits). The ModR / M field is used to specify the addressing mode and operands, and it includes a Mod field, a Reg field, and an R / M field. If the ModR / M field exists, it is 1 byte (8 bits). The SIB field is used to calculate the array index offset, and it includes a Scale field, an Index field, and a Base field. If the SIB field exists, it is 1 byte (8 bits); the displacement field is used to store the offset of the operand, and the possible bit lengths of the displacement field are 1 byte (8 bits), 2 bytes (16 bits), and 4 bytes (32 bits); the possible bit lengths of the immediate field are 1 byte (8 bits), 2 bytes (16 bits), and 4 bytes (32 bits).

[0047] Figure 2 The block diagram of the LBIST structure in the related art is shown. As Figure 2 shown, the LBIST structure includes a Linear Feedback Shift Register (LFSR), a counter CNT, a Multiple Input Signature Register (MISR), a selector MUX, and a Design Under Test (DUT). It should be understood that the LBIST structure also includes a test control module (not shown in Figure 2 ). The basic mechanism of LBIST is: use the LFSR to generate the input of the internal scan chain of the device under test, start a functional cycle, use the MISR to capture the response of the device under test, and compress the captured response. The compressed response is called a signature. Any abnormality in the output signature indicates a defect in the device under test.

[0048] The LFSR is used to generate a repeatable pseudo - random sequence. This circuit consists of n - stage flip - flops and some XOR gates. In each clock cycle, a new input value is fed back to the input terminals of each flip - flop inside the LFSR. Part of the input value comes from the output terminal of the LFSR, and the other part is obtained by performing an XOR operation on the output terminals of the LFSR. The initial value of the LFSR is called the seed of the pseudo - random sequence, and the output of its last flip - flop is a periodically repeating pseudo - random sequence. A number of bits of data are taken from predefined tap positions and an XOR operation is performed to calculate a feedback value.

[0049] Through Figure 2 the entire structure within the dashed box sends out the BIST signal. The selector MUX selects whether the DUT is in the test mode or the normal working mode according to the BIST signal. Among them, if the BIST signal is not activated, it is in the normal working mode, and other modules send corresponding data to the DUT for decoding. If the BIST signal is activated, it is in the test mode. The test controller controls the LFSR to generate random test vectors by configuring the seed and taps. The test controller controls the counter CNT by configuring the init_value to determine how many random test vectors the LFSR has generated. The generated random test vectors are sent to the DUT for decoding. After processing in the DUT, the data (response) is sent to the MISR. The MISR makes a judgment on the correctness of the circuit by comparing the decoded value of the DUT with the target value, and sends back the lbist_done signal (a signal indicating the completion of this built - in self - test) and the final MISR data to the test controller, indicating the end of this LBIST built - in self - test.

[0050] Although Figure 2 the LBIST structure shown can make corresponding configurations of the initial LFSR seed according to different circuits under test by changing the test controller, when the circuit under test is an X86 instruction decoding module, there are several invalid test data in the random test vectors generated by the LFSR relative to the X86 instruction decoding module, so that the logic built - in self - test of the X86 instruction decoding module cannot be effectively performed.

[0051] Based on this, the present disclosure considers the X86 instruction decoding module as the circuit under test and improves the LFSR structure to provide an improved generating device for generating random test vectors for the X86 instruction decoding module, so as to be able to generate valid random vectors for the X86 instruction decoding module, and further be able to effectively perform the logic built - in self - test on the X86 instruction decoding module. The following will be described in detail in combination with Figures 3 to 5 to describe the generating device of the present disclosure in detail.

[0052] Figure 3The block diagram of a generating device for random test vectors according to an embodiment of the present disclosure is shown. As Figure 3 shown, the device may include a random vector generating module 310, a random instruction generating module 320, and an instruction selecting module 330. The random vector generating module 310 is configured to generate random vectors corresponding to each domain in all domains of X86 instructions. The random instruction generating module 320 is connected to the random vector generating module 310 and is configured to generate random instructions for X86 instructions by using the generated random vectors for each domain of X86 instructions. The instruction selecting module 330 is connected to the random instruction generating module 320 and is configured to obtain the random instruction length and select target random instructions according to the random instruction length and the generated random instructions. Among them, a plurality of selected target random instructions can be randomly combined into the random test vectors and the random test vectors are output to the X86 instruction decoding module.

[0053] Thus, the random vector generating module 310 generates random vectors for different domains of X86 instructions. The random instruction generating module 320 generates random instructions for X86 instructions with random lengths by using the random vectors generated for different domains of X86 instructions. The instruction selecting module 330 selects target random instructions with random lengths. By arranging and combining the selected target random instructions in a random permutation order, random test vectors with random lengths and random permutation orders generated for different domains of X86 instructions can be obtained. Thus, random test vectors effective for decoding X86 instructions can be generated.

[0054] Therefore, according to this embodiment, a generating device for random test vectors for an X86 instruction decoding module is proposed. By generating random vectors, random lengths, and random permutation orders for different domains of X86 instructions, random test vectors for X86 instructions are finally output. Thus, most of the generated random test vectors are meaningful to the X86 instruction decoding module. Therefore, random test vectors effective for the X86 instruction decoding module can be generated, so that the X86 instruction decoding module can be effectively subjected to logic built-in self-testing.

[0055] In a possible implementation manner, as Figure 4 shown, the random vector generating module 310 may include an 8-bit pseudo-random vector generator (8-bit LFSR), a 16-bit pseudo-random vector generator (16-bit LFSR), a 24-bit pseudo-random vector generator (24-bit LFSR), and a 32-bit pseudo-random vector generator (32-bit LFSR). Among them, for each domain in all domains of X86 instructions, the corresponding bit pseudo-random vector generator included in the random vector generating module is respectively called to generate the random vector corresponding to this domain.

[0056] In this embodiment, according to the X86 instruction format, the maximum number of bits for the 6 fields of the X86 instruction can reach 32 bits. Therefore, pseudo-random vector generators (LFSRs) of 8 bits, 16 bits, 24 bits, and 32 bits are respectively required to generate corresponding random vectors for each field.

[0057] For example, as Figure 4 shown, for the prefix field, 8-bit LFSR, 16-bit LFSR, 24-bit LFSR, and 32-bit LFSR can be called to generate random vectors for the prefix field; for the opcode field, 8-bit LFSR, 16-bit LFSR, and 24-bit LFSR can be called to generate random vectors for the opcode field; for the Mod R / M field, 8-bit LFSR can be called to generate random vectors for the Mod R / M field; for the SIB field, 8-bit LFSR can be called to generate random vectors for the SIB field; for the offset field, 8-bit LFSR, 16-bit LFSR, and 32-bit LFSR can be called to generate random vectors for the offset field; for the immediate field, 8-bit LFSR, 16-bit LFSR, and 32-bit LFSR can be called to generate random vectors for the immediate field.

[0058] Therefore, when generating random vectors corresponding to each field in all fields of the X86 instruction, LFSRs with corresponding lengths among 8-bit LFSR, 16-bit LFSR, 24-bit LFSR, and 32-bit LFSR can be called for each field. Thus, random vectors can be generated for different fields of the X86 instruction.

[0059] In a possible implementation manner, the random instruction generation module 320 is configured to: for the random vectors corresponding to each field of the generated X86 instruction, respectively select the random vectors corresponding to each field according to the situation, and randomly combine the selected random vectors to obtain the random instruction.

[0060] Thus, the random instruction generation module 320 can generate a random instruction with a random length for the X86 instruction by using the random vectors generated for different fields of the X86 instruction.

[0061] In a possible implementation manner, as Figure 4 shown, the random instruction generation module 320 is an 18-bit random sequence generator (18-bit LFSR), and the 18-bit random sequence generator is divided into six groups of 3 bits each. Each group of random sequence generators corresponds to a field of the X86 instruction. Among them, the first bit of each group of random sequence generators can represent whether the field corresponding to the group of random sequence generators exists in the generated random instruction, and the second and third bits of each group of random sequence generators can represent the length of the field corresponding to the group of random sequence generators.

[0062] In this embodiment, an 18-bit random sequence generator (LFSR) is set up to randomly generate a sequence. Every three bits form a group, with a total of 6 groups (3 * 6 = 18 bits). The 6 groups respectively represent 6 fields of the X86 instruction format. Whether a specific instruction has a certain field is indicated by whether the first bit of each group is valid (such as 0 or 1). Exemplarily, the operation field must exist (as one of the constraint conditions), and the remaining two bits of each group, namely the second and third bits, are used to determine the length of the current bit field.

[0063] Exemplarily, taking the prefix field as an example, assume that the value of each group of prefixes is fixed (as one of the constraint conditions), and it is currently determined that the length of the prefix field is 3. Then, the 18-bit LFSR included in the random instruction generation module 320 can randomly select 3 groups from 4 groups of prefix information, and then randomly select a prefix from the 3 groups. Finally, the random vectors corresponding to the selected prefix field are combined in a random order.

[0064] It should be understood that the length of the random instruction generated at this time can be calculated based on whether the field corresponding to each group exists as indicated by the first bit of each group and the length of the existing field as indicated by the second and third bits of each group, so as to be used by the instruction selection module 330 to select the target random instruction.

[0065] In a possible implementation manner, as Figure 4 shown, the instruction selection module 330 may include a 4-bit random sequence generator (LFSR). The 4-bit random sequence generator obtains the random instruction length and selects a random instruction with an instruction length equal to the random instruction length from the generated random instructions as the target random instruction.

[0066] In this embodiment, considering that the maximum valid length of an X86 instruction is 15 bytes, a 4-bit (2 4 = 16) random sequence generator is set up to randomly select instructions of different lengths as the target random instructions according to the random instructions output by the 18-bit LFSR included in the random instruction generation module 320. For example, the 4-bit LFSR included in the instruction selection module 330 can obtain the random instruction length and can calculate the length of the random instructions output by the 18-bit LFSR included in the random instruction generation module 320, so as to select the target random instruction according to the random instruction length and the calculated length.

[0067] Thus, the target random instruction with a random length can be selected through the 4-bit LFSR included in the instruction selection module 330.

[0068] In a possible implementation manner, as Figure 4As shown, a plurality of target random instructions selected by the 4-bit LFSR included in the instruction selection module 330 are randomly combined into a 128-bit test vector as the random test vector.

[0069] In this embodiment, the target random instructions selected by the 4-bit LFSR included in the instruction selection module 330 can be arranged and combined in a random permutation order, and a 128-bit random test vector with a random length and a random permutation order generated for different domains of X86 instructions can be obtained. The 128-bit random test vector is used as an input signal and input into the X86 instruction decoding module.

[0070] In a possible implementation manner, as Figure 5 shown, the generating device 300 may further include: a monitoring module 340, configured to obtain and store filtering information related to the instruction length and / or instruction type from the X86 instruction decoding module. Wherein, each time a random test vector is generated, the redundant random test vectors that have been covered are filtered according to the filtering information.

[0071] In this embodiment, as Figure 5 shown, a monitoring module 340 is added as a feedback structure at the input end of the overall LFSR, some valid information related to the instruction length and / or instruction type is obtained from the X86 instruction decoding module, and these valid information are recorded in the monitoring module 340. Each time a random test vector for the X86 instruction decoding module is generated, for the instruction type information that has been covered, it is masked with a mask (mask) during subsequent generation, that is, the original value is maintained during the next generation. For example, if it is known from the valid information that there are 4 types of prefixes and the arrangement is known, there is no need to call the corresponding LFSR to generate a random vector for the known prefix domain. Only the random vectors of the other 5 domains are called respectively to generate the corresponding random vectors, which reduces the flip rate between adjacent vectors, and thus can reduce the dynamic power consumption of the test circuit.

[0072] Exemplarily, after the X86 instruction decoding module completes decoding, for the instruction types that can be covered by the previous random test vectors, some information can be obtained, such as whether there is a lock prefix, and the operand is 3 bytes. Taking the prefix as an example, if it is determined that the generated random vector contains an instruction with a prefix combination of lock+seg+os+as, a mask is generated, that is, during the generation of the random vector in the next clock cycle, this combination is maintained, and only the other domains are randomly generated. This avoids repeatedly testing the same instruction type, improves the test efficiency, and does not randomize the prefix domain, reducing a part of the flips, thereby reducing the dynamic power consumption.

[0073] Thus, by adding a monitoring module, the test efficiency of LBIST can be improved. The mask structure avoids redundant testing repeatedly and can effectively reduce resource consumption, achieving low power consumption of the LBIST for the test circuit.

[0074] In a possible implementation, the random vector generation module 310 can obtain constraint conditions for imposing constraints on at least one of the prefix domain, the address formation specifier domain, and the scale index byte domain according to the test scenario, and generate random vectors corresponding to the respective domains according to the constraint conditions.

[0075] In this embodiment, considering that different test scenarios may require random test vectors matching the test scenario, some constraint conditions can be added according to the actual test scenario. In this way, when the generation device generates random test vectors, random test vectors matching the current test scenario can be generated. Since the generation device in this embodiment generates random test vectors for the X86 instruction decoding module, some constraint conditions can be added according to the actual test scenario to generate random test vectors that better conform to the semantics of the corresponding fields of the X86 instruction.

[0076] As described above, the random vector generation module 310 can generate corresponding random vectors for the 6 domains of the X86 instruction in blocks, that is, generate random vectors corresponding to each domain completely randomly. In one implementation, the random vector generation module 310 may not generate random vectors for each domain completely randomly. In other words, the random vector generation module 310 can selectively generate vectors completely randomly for some domains and not completely randomly for some domains according to the actual test scenario.

[0077] For example, for the opcode domain, the immediate operand domain, and the displacement domain, the random vector generation module 310 can generate vectors completely randomly, so no constraint conditions adapted to the test scenario need to be added to these domains; for at least one of the prefix domain, the Mod R / M domain, and the SIB domain, the random vector generation module 310 may not generate vectors completely randomly. Exemplarily, constraint conditions can be added to control the values of some reserved fields.

[0078] Therefore, a series of different constraint conditions can be defined to ensure that the generated random test vectors conform to the semantics of the corresponding fields of the X86 instruction. For example, the randomization mechanism of a high-level language can be used to define each part of the instruction, including the prefix domain, and corresponding constraint conditions can be imposed.

[0079] In one implementation, the random vector generation module 310 obtains constraint conditions for imposing constraints on the prefix field according to the test scenario, and generates a random vector corresponding to the prefix field according to the constraint conditions. The constraint conditions may include, but are not limited to: using constraints to define the valid value range of the corresponding type of prefix in the prefix field; and / or using constraints to define that the corresponding field in the prefix field is a non-random value. Exemplarily, the value of the REX prefix is from 40H to 4FH, which is used to access the extended register set (such as R8 to R15), and some constraint conditions are used to define the valid value range of the REX prefix; of course, if necessary, certain fields can be set to non-random values to ensure specific test scenarios, such as OS (66H), AS (67H), etc.

[0080] In one implementation, the random vector generation module 310 obtains constraint conditions for imposing constraints on the address formation specifier field and / or the scale index byte field according to the test scenario, and generates a random vector corresponding to the corresponding field according to the constraint conditions. The constraint conditions may include, but are not limited to: using constraints to define the value of the R / M field when the Mod field takes a corresponding value, and using constraints to define that the use of the scale index byte field depends on the value of the Mod field.

[0081] In this embodiment, considering that there may be mutual constraints between different fields of the same domain and different domains of the X86 instruction, constraint conditions can be defined accordingly to generate targeted and correct random test vectors containing X86 instruction semantics.

[0082] Exemplarily, the following constraint conditions can be defined: for the R / M field, when the Mod field is 00 or 01 or 10, the R / M field can take the following values: 000 to 111 (corresponding to 8 registers: rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi); when the Mod field is 11, this field specifies the operation register. The following constraint conditions can also be defined: when the Mod field is 00 and the R / M field is 100, the SIB byte is introduced to support more complex addressing modes (00h-FFh).

[0083] In one implementation, when the random instruction generation module 320 combines the random vectors corresponding to each field, some constraint conditions can be added according to the encoding rules of the X86 instruction and some operations, and a random instruction for the X86 instruction is generated according to these constraint conditions and the random vectors for each field of the X86 instruction generated. Exemplarily, the constraint conditions may include, but are not limited to: when it is determined that the prefix contains OS / AS, the operand size of the offset field or the immediate number field should be selected according to the specific situation.

[0084] It should be understood that the above constraints can be used to ensure that the generated random test vectors conform to the semantics of the corresponding fields of the X86 instructions. However, the above constraints are only examples of the constraints of the present disclosure and do not limit the present disclosure. Those skilled in the art can define more stringent or broader constraints according to the actual test scenarios and requirements, so as to generate random test vectors that match the test scenarios.

[0085] Figure 6 FIG. shows a block diagram of an LBIST structure according to an embodiment of the present disclosure. By comparing Figure 2 and Figure 6 it can be seen that the difference between the LBIST structure of this embodiment and the existing LBIST structure is that the LFSR in Figure 2 is replaced by the generating device 300. For the description of the generating device 300, reference can be made to the previous description of Figures 3 to 5 For other components of the LBIST structure, reference can be made to the previous description of Figure 2

[0086] Figure 7 FIG. shows a schematic flowchart of a method for generating a random test vector according to an embodiment of the present disclosure. The generating method is used to generate random test vectors to be used when the circuit under test is an X86 instruction decoding module. As Figure 7 shown, the method may include the following steps:

[0087] In step S701 (random vector generation step), random vectors corresponding to each field in all fields of the X86 instruction are generated.

[0088] In step S702 (random instruction generation step), the generated random vectors for each field of the X86 instruction are used to generate a random instruction for the X86 instruction.

[0089] In step S703 (instruction selection step), the random instruction length is obtained, and target random instructions are selected according to the random instruction length and the generated random instruction. Among them, a plurality of selected target random instructions can be randomly combined into the random test vector, and the random test vector is output to the X86 instruction decoding module.

[0090] ​Thus, random vectors are generated for different fields of the X86 instruction through the random vector generation step. Through the random instruction generation step, random instructions with a random length for the X86 instruction are generated by using the random vectors generated for different fields of the X86 instruction. Through the instruction selection step, the target random instruction with a random length is selected. By arranging and combining the selected target random instructions in a random permutation order, random test vectors with a random length and a random permutation order generated for different fields of the X86 instruction can be obtained. Thus, random test vectors effective for X86 instruction decoding can be generated.

[0091] Therefore, according to this embodiment, a method for generating random test vectors for an X86 instruction decoding module is proposed. By generating random vectors, a random length, and a random permutation order for different fields of the X86 instruction, random test vectors for the X86 instruction are finally output. Thus, most of the generated random test vectors are meaningful for the X86 instruction decoding module. Therefore, random test vectors effective for the X86 instruction decoding module can be generated, thereby enabling effective logic built-in self-testing for the X86 instruction decoding module.

[0092] In a possible implementation manner, the random vector generation step includes: for each field in all fields of the X86 instruction, a pseudo-random vector generator corresponding to the corresponding bit is respectively called to generate the random vector corresponding to the field. Among them, the pseudo-random vector generator corresponding to the corresponding bit includes an 8-bit pseudo-random vector generator, a 16-bit pseudo-random vector generator, a 24-bit pseudo-random vector generator, and a 32-bit pseudo-random vector generator.

[0093] In a possible implementation manner, the random instruction generation step includes: for the random vector corresponding to each field of the generated X86 instruction, the random vector corresponding to each field is respectively selected according to the situation, and the selected random vectors are randomly combined to obtain the random instruction.

[0094] In a possible implementation manner, the module for executing the random instruction generation step includes an 18-bit random sequence generator. The 18-bit random sequence generator is divided into six groups of 3 bits each. Each group of random sequence generators corresponds to a field of the X86 instruction. Among them, the first bit of each group of random sequence generators can represent whether the field corresponding to the group of random sequence generators exists in the generated random instruction, and the second and third bits of each group of random sequence generators can represent the length of the field corresponding to the group of random sequence generators.

[0095] In a possible implementation manner, the length of the random instruction generated in the random instruction generation step can be calculated according to whether the corresponding field of the X86 instruction exists and the length of the existing corresponding field.

[0096] In a possible implementation, the module for performing the instruction selection step includes a 4-bit random sequence generator, which obtains the random instruction length and selects a random instruction with an instruction length equal to the random instruction length from the generated random instructions as the target random instruction.

[0097] In a possible implementation, the selected multiple target random instructions can be randomly combined into a 128-bit test vector as the random test vector.

[0098] In a possible implementation, the above generation method may further include a monitoring step of obtaining and storing filtering information related to the instruction length and / or instruction type from the X86 instruction decoding module, where, each time a random test vector is generated, the covered redundant random test vectors are filtered according to the filtering information.

[0099] In a possible implementation, all fields of the X86 instruction are a prefix field, an opcode field, an address formation specifier field, a scale index byte field, an offset field, and an immediate number field. Correspondingly, in the random vector generation step, constraint conditions for imposing constraints on at least one of the prefix field, the address formation specifier field, and the scale index byte field according to the test scenario are obtained, and random vectors corresponding to the corresponding fields are generated according to the constraint conditions.

[0100] In a possible implementation, the constraint conditions for imposing constraints on the prefix field include using constraints to define the valid value range of the corresponding type of prefix in the prefix field; and / or using constraints to define that the corresponding field in the prefix field is a non-random value.

[0101] In a possible implementation, the address formation specifier field includes a Mod field, a Reg field, and an R / M field. Correspondingly, the constraint conditions for imposing constraints on the address formation specifier field include using constraints to define the value of the R / M field when the Mod field takes a corresponding value.

[0102] In a possible implementation, the constraint conditions for imposing constraints on the scale index byte field include using constraints to define that the use of the scale index byte field depends on the value of the Mod field.

[0103] In a possible implementation, in the random instruction generation step, constraint conditions defined according to the X86 instruction encoding rules are obtained, and random instructions for the X86 instruction are generated according to the constraint conditions and the random vectors for each field of the X86 instruction generated.

[0104] Figure 8A flowchart showing a logic built-in self-test method according to an embodiment of the present disclosure, which is used to perform logic built-in self-test on an X86 instruction decoding module. As Figure 8 shown, the method may include the following steps:

[0105] In step S801, it is determined whether the X86 instruction decoding module as the circuit under test is in the test mode. If it is determined that the X86 instruction decoding module is in the test mode, it indicates that logic built-in self-test is to be performed on the X86 instruction decoding module. Therefore, steps S701, S702, and S703 are sequentially executed to generate random test vectors, and then step S802 is executed. If it is determined that the X86 instruction decoding module is in the normal working mode, steps S701, S702, and S703 are not executed. Optionally, corresponding data can be sent by other modules to the X86 instruction decoding module for decoding.

[0106] In step S802, the random test vector is input into the X86 instruction decoding module for decoding.

[0107] In step S803, the decoded value of the X86 instruction decoding module is compared with the target value to judge the correctness of the X86 instruction decoding module.

[0108] In some embodiments, the functions or modules included in the device in the device embodiment provided above in the embodiments of the present disclosure can be used to execute the method described in the method embodiment. Its specific implementation can refer to the description of the device embodiment above. For the sake of brevity, it will not be repeated here.

[0109] In summary, the present disclosure proposes a device and method for generating random test vectors for an X86 instruction decoding module, as well as a logic built-in self-test structure and method. By generating random vectors for different domains of the X86 instruction, randomness in length, and randomness in permutation order, random test vectors for the X86 instruction are finally output. Thus, most of the generated random test vectors are meaningful for the X86 instruction decoding module, so effective random test vectors for the X86 instruction decoding module can be generated, and thus the X86 instruction decoding module can be effectively subjected to logic built-in self-test. Moreover, by adding a monitoring module to store the valid information in the X86 instruction decoding module and feedback the valid information back to the LBIST, redundant vectors can be eliminated, and the test power consumption of the circuit under test can be reduced.

[0110] The embodiments of the present disclosure have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device for generating a random test vector, characterized in that: Used to generate random test vectors to be used when the circuit to be tested is an X86 instruction decoding module, the generating device includes: A random vector generation module, used to generate a random vector corresponding to each domain in all domains of an X86 instruction; A random instruction generation module, for generating random instructions for X86 instructions using the generated random vector for each domain of the X86 instructions; An instruction selection module is used to obtain the random instruction length and select a target random instruction according to the random instruction length and the generated random instruction. Among them, the selected multiple target random instructions can be randomly combined into the random test vector, and the random test vector is output to the X86 instruction decoding module.

2. The generating device according to claim 1, characterized in that The random vector generation module includes an 8-bit pseudo-random vector generator, a 16-bit pseudo-random vector generator, a 24-bit pseudo-random vector generator and a 32-bit pseudo-random vector generator. For each of all the domains of the X86 instruction, the pseudo-random vector generator of the corresponding bit included in the random vector generation module is called to generate a random vector corresponding to the domain.

3. The generating device according to claim 1, characterized in that: The random instruction generation module is configured to: for the random vector corresponding to each domain of the generated X86 instruction, select the random vector corresponding to each domain according to the situation, and randomly combine the selected random vectors to obtain the random instruction.

4. The generating device according to claim 3, characterized in that: The random instruction generation module includes an 18-bit random sequence generator, which is divided into six groups of 3 bits each, each group of random sequence generators corresponding to a domain of the X86 instruction, wherein the first bit of each group of random sequence generators can represent whether the domain corresponding to the group of random sequence generators exists in the generated random instruction, and the second and third bits of each group of random sequence generators can represent the length of the domain corresponding to the group of random sequence generators.

5. The generating device according to claim 4, characterized in that: The length of the random instruction generated by the random instruction generation module can be calculated based on whether there is a corresponding domain of the X86 instruction and the length of the corresponding domain.

6. The generating device according to claim 1, characterized in that: The instruction selection module includes a 4-bit random sequence generator, which obtains the random instruction length and selects a random instruction with an instruction length equal to the random instruction length from the generated random instructions as the target random instruction.

7. The generating device according to claim 1, characterized in that The selected multiple target random instructions are randomly combined into a 128-bit test vector as the random test vector.

8. The generating device according to claim 1, characterized in that Also includes: The monitoring module is used to obtain and store filtering information related to instruction length and / or instruction type from the X86 instruction decoding module, wherein each time a random test vector is generated, the redundant random test vector that has been covered is filtered according to the filtering information.

9. The generating device according to claim 1, characterized in that: All fields of the X86 instruction are prefix field, opcode field, address formation specifier field, telescopic index byte field, offset field, and immediate field. The random vector generation module obtains a constraint condition for applying a constraint to at least one of a prefix field, an address formation specifier field, and a telescoping index byte field according to a test scenario, and generates a random vector corresponding to the corresponding field according to the constraint condition.

10. The generating device according to claim 9, characterized in that The constraint conditions imposed on the prefix domain include: using the constraint to define the valid value range of the prefix of the corresponding type in the prefix domain; and / or using the constraint to define the corresponding field in the prefix domain as a non-random value.

11. The generating device according to claim 10, characterized in that: The address formation specifier field includes a Mod field, a Reg field and an R / M field. Accordingly, the constraint condition imposed on the address formation specifier field includes using the constraint to define the value of the R / M field when the Mod field takes a corresponding value.

12. The generating device according to claim 11, characterized in that The constraint condition for imposing a constraint on the telescopic index byte field includes using the constraint to define that the use of the telescopic index byte field depends on the value of the Mod field.

13. The generating device according to claim 1, characterized in that The random instruction generation module obtains constraints defined according to X86 instruction encoding rules, and generates random instructions for X86 instructions according to the constraints and the generated random vector for each domain of the X86 instruction.

14. A logic built-in self-test (LBIST) structure, characterized in that: include: The generating device according to any one of claims 1 to 13; A test control module, used to control the generating device to generate random test vectors; The circuit to be tested, when the X86 instruction decoding module as the circuit to be tested is in a test mode, inputs the random test vector into the X86 instruction decoding module for decoding; The test response compression module is used to compare the decoding value of the X86 instruction decoding module with the target value to determine the correctness of the X86 instruction decoding module.

15. A method for generating a random test vector, characterized in that: Used to generate random test vectors to be used when the circuit to be tested is an X86 instruction decoding module, the generation method includes: A random vector generation step, generating a random vector corresponding to each field in all fields of the X86 instruction; A random instruction generation step, using the generated random vector for each domain of the X86 instruction to generate a random instruction for the X86 instruction; an instruction selection step, obtaining a random instruction length, and selecting a target random instruction according to the random instruction length and the generated random instruction, The selected multiple target random instructions can be randomly combined into the random test vector, and the random test vector is output to the X86 instruction decoding module.

16. The generation method according to claim 15, characterized in that: The random vector generation step comprises: for each domain in all domains of the X86 instruction, calling the pseudo-random vector generator of the corresponding bit to generate a random vector corresponding to the domain, Among them, the corresponding bit pseudo-random vector generator includes an 8-bit pseudo-random vector generator, a 16-bit pseudo-random vector generator, a 24-bit pseudo-random vector generator and a 32-bit pseudo-random vector generator.

17. The generation method according to claim 15, characterized in that: The random instruction generation step includes: for the random vector corresponding to each domain of the generated X86 instruction, selecting the random vector corresponding to each domain according to the situation, and randomly combining the selected random vectors to obtain the random instruction.

18. The generation method according to claim 17, characterized in that: The module for executing the random instruction generating step includes an 18-bit random sequence generator, which is divided into six groups of 3 bits each, each group of random sequence generators corresponds to a domain of the X86 instruction, wherein the first bit of each group of random sequence generators can characterize whether the domain corresponding to the group of random sequence generators exists in the generated random instruction, and the second and third bits of each group of random sequence generators can characterize the length of the domain corresponding to the group of random sequence generators.

19. The generation method according to claim 18, characterized in that: The length of the random instruction generated in the random instruction generation step can be calculated based on whether a corresponding domain of the X86 instruction exists and the length of the corresponding domain that exists.

20. The generation method according to claim 15, characterized in that: The module for executing the instruction selection step includes a 4-bit random sequence generator, which obtains the random instruction length and selects a random instruction with an instruction length equal to the random instruction length from the generated random instructions as the target random instruction.

21. The generation method according to claim 15, characterized in that: The selected multiple target random instructions can be randomly combined into a 128-bit test vector as the random test vector.

22. The generation method according to claim 15, characterized in that: Also includes: The monitoring step obtains and stores filtering information related to instruction length and / or instruction type from the X86 instruction decoding module, wherein each time a random test vector is generated, the covered redundant random test vector is filtered according to the filtering information.

23. The generation method according to claim 15, characterized in that: All fields of the X86 instruction are prefix field, opcode field, address formation specifier field, telescopic index byte field, offset field, and immediate field. In the random vector generation step, a constraint condition for applying a constraint to at least one of the prefix field, the address formation specifier field and the telescopic index byte field according to a test scenario is obtained, and a random vector corresponding to the corresponding field is generated according to the constraint condition.

24. The generation method according to claim 23, characterized in that: The constraint conditions imposed on the prefix domain include: using the constraint to define the valid value range of the prefix of the corresponding type in the prefix domain; and / or using the constraint to define the corresponding field in the prefix domain as a non-random value.

25. The generation method according to claim 24, characterized in that: The address formation specifier field includes a Mod field, a Reg field and an R / M field. Accordingly, the constraint condition imposed on the address formation specifier field includes using the constraint to define the value of the R / M field when the Mod field takes a corresponding value.

26. The generation method according to claim 25, characterized in that: The constraint condition for imposing a constraint on the telescopic index byte field includes using the constraint to define that the use of the telescopic index byte field depends on the value of the Mod field.

27. The generation method according to claim 15, characterized in that: In the random instruction generation step, constraints defined according to X86 instruction encoding rules are obtained, and random instructions for X86 instructions are generated according to the constraints and the generated random vectors for each domain of the X86 instructions.

28. A logic built-in self-test (LBIST) method, characterized in that: include: When an X86 instruction decoding module as a circuit to be tested is in a test mode, a random test vector is generated using a generation method according to any one of claims 15 to 27; Inputting the random test vector into the X86 instruction decoding module for decoding; The decoded value of the X86 instruction decoding module is compared with the target value to determine the correctness of the X86 instruction decoding module.

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