A method, device, server and storage medium for checking logic code quality

Abstract

The present application provides a logic code quality inspection method, device, server, and storage medium, which are applied to the field of computer technology. After completing the logic synthesis of an integrated circuit, the method extracts the starting registers and end registers of all timing paths in the integrated circuit, counts the number of subsequent fan-out registers and the number of previous fan-in registers for each register, and obtains a register quantity threshold corresponding to the integrated circuit. If the number of previous fan-in registers or the number of subsequent fan-out registers corresponding to any register is greater than the register quantity threshold, the logic code of the integrated circuit is determined to be abnormal. Compared with the prior art method of performing logic code quality inspection after completing layout and routing, the method provided by the present application can perform code quality inspection immediately after logic synthesis is completed, and can complete the logic code quality inspection as early as possible, effectively avoiding the discovery of logic code abnormalities after completing all physical designs, thereby improving design efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, server, and storage medium for checking the quality of logic code. Background Art

[0002] In the existing integrated circuit design process, there is a clear separation between logic design and physical design: the logic design stage mainly focuses on functional implementation, while timing convergence issues often have to wait until the physical design stage (such as after layout and routing) to be exposed through static timing analysis.

[0003] As the amount of logic code data continues to increase, the lag in the design process leads to a significant extension of the design iteration cycle. That is, if logic code quality problems are discovered in the late stage of physical design, it may lead to the readjustment of the logic code, which not only consumes a lot of resources but also may introduce new design risks due to repeated modifications.

[0004] Therefore, how to detect the quality of logic code as early as possible and discover quality problems of logic code has become one of the technical problems that technical personnel in this field urgently need to solve. Summary of the Invention

[0005] In view of this, the present application is committed to providing a logic code quality inspection method, device, server and storage medium to solve the problem in the prior art that it is difficult to inspect the logic code quality as early as possible and the abnormal logic code leads to a long integrated circuit design cycle.

[0006] In a first aspect, the present application provides a method for checking the quality of logic code, comprising:

[0007] After completing the logic synthesis of the integrated circuit, extracting the starting register and the ending register of all timing paths in the integrated circuit;

[0008] Count the number of subsequent fan-out registers and the number of preceding fan-in registers of each register, where the number of subsequent fan-out registers is the total number of the first register connected to the subsequent stage of the register, and the number of preceding fan-in registers is the total number of the first register connected to the preceding stage of the register;

[0009] Obtaining a register quantity threshold corresponding to the integrated circuit;

[0010] If the number of preceding fan-in registers or the number of succeeding fan-out registers corresponding to any register is greater than the register number threshold, it is determined that the logic code of the integrated circuit is abnormal.

[0011] In an optional implementation, extracting the starting register and the ending register of all timing paths in the integrated circuit includes:

[0012] Obtaining a timing constraint file of the integrated circuit and a gate netlist obtained after completing logic synthesis;

[0013] Static timing analysis is performed on the gate netlist based on the timing constraint file, and the starting register and the ending register corresponding to each timing path are identified through the static timing analysis.

[0014] In an optional implementation, obtaining a register quantity threshold corresponding to the integrated circuit includes:

[0015] Acquiring design parameters of the integrated circuit, wherein the design parameters include a target clock frequency, a single-stage delay time, and a target single-stage fan-out value;

[0016] A threshold value of the number of registers corresponding to the integrated circuit is determined according to the target clock frequency, the single-stage delay time, and the target single-stage fan-out value.

[0017] In an optional implementation, determining a threshold value of the number of registers corresponding to the integrated circuit according to the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value includes:

[0018] Determining a maximum allowable number of stages corresponding to the integrated circuit according to the target clock frequency and the single-stage delay duration;

[0019] A threshold value of the number of registers corresponding to the integrated circuit is determined according to the maximum allowed number of stages and the target single-stage fan-out value.

[0020] In an optional implementation, the process of obtaining the single-stage delay duration includes:

[0021] determining a delay time of a logic unit with the shortest inherent time delay in the integrated circuit as a target unit delay;

[0022] Performing segmented statistics on the line delays of all metal lines in the integrated circuit at preset time intervals, and fitting a normal distribution curve based on the statistical results;

[0023] Determine the expected value of line delay calculated based on the normal distribution curve as the target line delay;

[0024] The sum of the target unit delay and the target line delay is determined to be the single-stage delay length.

[0025] In an optional implementation, the process of obtaining the target single-stage fan-out value includes:

[0026] According to different preset single-stage fan-out values, completing the layout and routing of the integrated circuit to obtain corresponding initial design results;

[0027] Performing static timing analysis on each of the initial design results to obtain corresponding timing violation results;

[0028] The preset single-stage fan-out value corresponding to the optimal timing violation result among the preset single-stage fan-out values is used as the target single-stage fan-out value.

[0029] In an optional embodiment, the method provided in the first aspect of the present application further includes:

[0030] The registers whose number of previous-stage fan-in registers or subsequent-stage fan-out registers is greater than the register number threshold are used as target registers;

[0031] Performing logic design optimization or physical design optimization on the target register.

[0032] In an optional implementation, the process of performing logic design optimization on the target register includes:

[0033] Copying the target register to obtain N target registers, where N is greater than or equal to 2;

[0034] Decoupling the target timing path to which the target register belongs into N groups of optimized timing paths;

[0035] Each group of the optimized timing paths is connected to one of the target registers.

[0036] In an optional implementation, the process of performing logic design optimization on the target register includes:

[0037] Starting from the target register, traverse along the subsequent timing path step by step;

[0038] If there is a branch point of logical bifurcation before traversing to the end register, insert a new register at the target branch point so that the new register connects part of the logical path, and the target branch point is the first branch point that appears along the timing path direction;

[0039] If the traversal reaches the destination register and there is no branch point of logical bifurcation, a portion of the logical path of the target register is deleted or moved.

[0040] In an optional implementation, the process of performing physical design optimization on the target register includes:

[0041] Obtaining a physical design layout of the integrated circuit;

[0042] Extracting path information of each timing path to which the target register belongs in the physical design layout;

[0043] Determining a target timing path to be optimized among the timing paths to which the target register belongs based on the path information;

[0044] The target timing path is optimized and designed.

[0045] In an optional implementation, the path information includes position coordinates of a start register and an end register of the timing path in the physical design layout;

[0046] Determining a target timing path to be optimized among the timing paths to which the target register belongs based on the path information includes:

[0047] For each timing path to which the target register belongs, calculating the inter-stack distance between the starting register and the ending register based on the position coordinates of the starting register and the ending register of the timing path;

[0048] The timing path whose inter-stack distance is greater than a preset inter-stack distance threshold is used as the target timing path to be optimized.

[0049] In an optional implementation, the path information includes a current level corresponding to the timing path;

[0050] Determining a target timing path to be optimized among the timing paths to which the target register belongs based on the path information includes:

[0051] Among the timing paths to which the target register belongs, a timing path whose current number of stages is greater than a maximum allowed number of stages is taken as a target timing path to be optimized, wherein the maximum allowed number of stages is determined based on a target clock frequency of the integrated circuit and a single-stage delay duration.

[0052] In an optional implementation, optimizing the target timing path includes at least one of the following methods:

[0053] shortening the link length of the target timing path;

[0054] Adjusting the metal layer to which the metal line in the target timing path belongs;

[0055] In the clock tree synthesis stage, the clock path length of the starting register or the end register of the target timing path is adjusted.

[0056] In a second aspect, the present application provides a logic code quality inspection device, comprising:

[0057] A first acquisition unit is configured to extract the start register and the end register of all timing paths in the integrated circuit after completing the logic synthesis of the integrated circuit;

[0058] A statistical unit, configured to count the number of subsequent fan-out registers and the number of preceding fan-in registers of each register, wherein the number of subsequent fan-out registers is the total number of the first register connected to the subsequent stage of the register, and the number of preceding fan-in registers is the total number of the first register connected to the preceding stage of the register;

[0059] A second acquiring unit, configured to acquire a register quantity threshold corresponding to the integrated circuit;

[0060] The determination unit is configured to determine that the logic code of the integrated circuit is abnormal if the number of preceding fan-in registers or the number of succeeding fan-out registers corresponding to any register is greater than the register number threshold.

[0061] In a third aspect, the present application provides a server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor. When the processor executes the computer program, the steps of the logical code quality inspection method as described in any one of the first aspects of the present application are implemented.

[0062] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the logic code quality inspection method as described in any one of the first aspects of the present application.

[0063] Based on the above, the logic code quality inspection method provided in this application extracts the starting and ending registers of all timing paths in the integrated circuit after completing logic synthesis of the integrated circuit. The number of subsequent fan-out registers and the number of preceding fan-in registers for each register are counted, and a register quantity threshold corresponding to the integrated circuit is obtained. If the number of preceding fan-in registers or the number of subsequent fan-out registers corresponding to any register is greater than the register quantity threshold, the logic code of the integrated circuit is determined to be abnormal. This method inspects the logic code quality based on the number of subsequent fan-out registers and the number of preceding fan-in registers corresponding to the register. The inspection process is simple and easy to implement. Furthermore, the physical design of the integrated circuit can be divided into logic synthesis and layout and routing. Compared to the prior art method of performing logic code quality inspection after completing layout and routing, the method provided in this application can perform code quality inspection immediately after logic synthesis is completed. Therefore, logic code quality inspection can be completed as early as possible, effectively avoiding the discovery of logic code anomalies after the entire physical design is completed, which helps improve the design efficiency of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0065] Figure 1 This is a flow chart of an integrated circuit logic code quality inspection method provided by this application.

[0066] Figure 2 It is a schematic diagram of the subsequent fan-out register and the preceding fan-out register mentioned in this application.

[0067] Figure 3 It is a schematic diagram of the post-stage fan-out register mentioned in this application.

[0068] Figure 4 It is a schematic diagram of the front-stage fan-in register mentioned in this application.

[0069] Figure 5 It is a schematic diagram of the number of levels of the timing path between the starting register and the end register.

[0070] Figure 6 This application provides a flowchart of a method for determining a register quantity threshold.

[0071] Figure 7 It is the normal distribution curve of the line delay of the metal line in the integrated circuit.

[0072] Figure 8 This is a flowchart of another integrated circuit logic code quality inspection method provided by this application.

[0073] Figure 9 This is a flow chart of the register physical design optimization method provided by this application.

[0074] Figure 10 It is a schematic diagram of the physical layout of an integrated circuit.

[0075] Figure 11 This is a structural block diagram of an integrated circuit logic code quality inspection device provided by this application.

[0076] Figure 12 This is a structural block diagram of another integrated circuit logic code quality inspection device provided by this application.

[0077] Figure 13 This is a structural block diagram of a server provided by this application. DETAILED DESCRIPTION

[0078] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0079] In related technologies, the design process of integrated circuits can be divided into logic design and physical design. Logic design involves writing the corresponding logic code based on the IC's usage scenario, functionality, and related performance requirements, in compliance with relevant protocol standards. Physical design involves converting the logic code from the logic design phase into gate circuits. Based on process requirements, the numerous logic units are placed and wired on the silicon wafer. After feasibility verification, the chip is tape-out and handed over to the process manufacturer for production of the corresponding chip.

[0080] In the current integrated circuit design process, there's a clear disconnect between logic design and physical design: the logic design phase primarily focuses on functional implementation, while timing closure issues often only become apparent during the physical design phase (e.g., after layout and routing) through static timing analysis. As the volume of logic code data continues to increase, iteration times during the physical design phase of very large-scale integrated circuits are becoming increasingly lengthy. If logic code quality issues are discovered only in the later stages of physical design, the logic code may need to be re-adjusted, consuming significant resources and potentially introducing new design risks due to repeated revisions.

[0081] To solve the above problems, the present application provides a logic code quality inspection method, which implements the inspection of logic code quality based on the number of post-stage fan-out registers and the number of pre-stage fan-in registers corresponding to the registers. The inspection process is easy to implement, and the inspection process is performed after the logic synthesis is completed. Compared with the prior art of performing logic code quality inspection after completing layout and routing, the logic code quality inspection can be completed as early as possible, effectively avoiding the discovery of logic code anomalies after completing all physical designs, which helps to improve the design efficiency of integrated circuits.

[0082] The logic code quality inspection method provided by this application is applied to electronic devices, which can be laptops, personal computers (PCs), tablet computers, and other electronic devices that can run the application corresponding to the logic code quality inspection method provided by this application. These are not listed here one by one. Of course, in some cases, it can also be applied to servers on the network side. Figure 1 As shown, the logic code quality inspection method provided by this application includes the following steps.

[0083] S100 , after completing the logic synthesis of the integrated circuit, extracting the starting registers and the ending registers of all the timing paths in the integrated circuit.

[0084] In the related art, the logic design process of an integrated circuit can be further divided into two stages, namely logic synthesis and layout and routing. Compared with the related art which performs a logic code quality check after completing layout and routing, the present application starts to check the logic code quality after completing the logic synthesis of the integrated circuit, so as to determine the logic code quality as soon as possible, and avoid unnecessary subsequent layout and routing operations when the logic code quality is abnormal, thereby wasting a lot of manpower and material resources.

[0085] Integrated circuits can be divided into combinational logic circuits and sequential logic circuits. Combinational logic circuits have outputs that depend solely on their current inputs and lack memory. Sequential logic circuits, in addition to basic logic gates, also contain storage elements such as registers to store past information. Their steady-state output depends not only on their current inputs but also on the state formed by past inputs. Each sequential logic circuit corresponds to a sequential path, and the start and end points of a sequential path are divided by registers. Each sequential path has a register at its starting point, the starting register, and a corresponding register at its end point, the ending register. In related technologies, each sequential path can also be called a stack.

[0086] Static Timing Analysis (STA) is a timing verification technology that is independent of input stimuli. It aims to traverse all timing paths, find the worst-case delay of the sequential logic circuit, and check whether the setup time and hold time meet the requirements. This analysis method mainly determines whether the design can run at the required operating frequency by analyzing the maximum and minimum sequential logic path delays. This analysis method is very convenient, especially in large integrated circuits. It can greatly reduce the simulation workload and time costs. STA is combined with formal verification to ensure the timing correctness of the digital system. The main purpose of STA is to increase the system's operating frequency and increase system stability. By reducing the occurrence of metastable states and controlling the synthesis, mapping, layout, and routing results of the logic, the logic and routing delays can be reduced, thereby increasing the operating frequency.

[0087] More importantly, STA analysis can traverse every timing path in an integrated circuit. Therefore, as an optional implementation, one can first obtain the IC's timing constraint file and the gate netlist after logic synthesis. Based on the timing constraint file, static timing analysis can be performed on the IC's gate netlist to obtain the corresponding analysis results. Finally, the corresponding starting and ending registers for each timing path in the IC can be extracted from the analysis results. The specific execution process of static timing analysis can be referenced to related technologies and will not be detailed here.

[0088] S110 , counting the number of subsequent fan-out registers and the number of preceding fan-in registers of each register.

[0089] Combine Figure 2 As shown, taking register Reg as an example, it can be used as the starting register of a timing path or as the end register of a timing path. Based on this, this application needs to count the number of subsequent fan-out registers connected to the register and the number of previous fan-in registers for each register extracted in S100.

[0090] In an optional embodiment, after extracting all registers in the integrated circuit at S100, a register list can be created to record all registers in the integrated circuit. Furthermore, when executing this step, a traversal method can be used to count the number of subsequent-stage fan-out registers and the number of preceding-stage fan-in registers corresponding to each register in the order recorded in the register list.

[0091] Specific, combined Figure 2 As shown, taking register Reg as an example, starting from the output pin Q of register Reg, trace back to the logic unit that has a direct connection with the Q pin, and then continue to trace downstream in the signal transmission direction from the output segment of the logic unit until encountering the first register connected to the subsequent stage of register Reg. Then stop tracing, and the number of subsequent fan-out registers is increased by 1. This cycle is repeated until all timing paths connected to the subsequent stage of register Reg are traversed, and the number of subsequent fan-out registers corresponding to register Reg is obtained. The final statistical results can be seen in Figure 3 As shown, the number of subsequent fan-out registers mentioned in this application is the total number of the first registers connected to any subsequent register.

[0092] In an optional implementation, after completing the statistics of the number of subsequent fan-out registers corresponding to all registers in the integrated circuit, the registers can also be sorted in descending order according to the number of subsequent fan-out registers, so as to clearly display the number of subsequent fan-out registers connected to each register in the integrated circuit. At the same time, it can also be used for the subsequent execution of S130, which will be expanded in the subsequent content and will not be described in detail here.

[0093] Furthermore, still taking register Reg as an example, starting from the input terminal D of register Reg, trace back to the logic unit that has a direct connection relationship with the D pin, and then continue to trace upstream from the output section of the logic unit in the signal transmission direction until encountering the first register connected to the previous stage of register Reg. Then stop tracing, and the number of fan-in registers of the previous stage is increased by 1. This cycle is repeated until all timing paths connected to the previous stage of register Reg are traversed, and the number of fan-in registers of the previous stage corresponding to register Reg is obtained. The final statistical results can be seen in Figure 4 As shown, the number of front-stage fan-in registers mentioned in this application is the total number of the first registers connected to the front stage of each register.

[0094] It should be noted that the input pins of the register do not allow multi-driven structures. In digital circuit design, if a signal is driven by multiple driving sources at the same time, this may cause the signal value to be in an uncertain state, because different driving sources may send signals at different times, resulting in logical errors or unpredictable behavior. Therefore, when counting the number of fan-in registers in the previous stage, the logic unit traced to the previous level by any register is single, but the signal before the logic unit can be multi-port, such as the common two-input AND gate. When counting, it is necessary to continue to track the units in the previous level of all input ports of the first logic unit connected to the input side of the register to ensure that all timing paths are traversed.

[0095] Referring to the aforementioned method for processing the number of subsequent fan-in registers, after completing the statistics of the number of previous fan-in registers corresponding to all registers in the integrated circuit, the registers can be sorted in descending order according to the number of previous fan-in registers, thereby clearly displaying the number of previous fan-in registers connected to each register in the integrated circuit.

[0096] S120: Obtain a register quantity threshold corresponding to the integrated circuit.

[0097] During the logic code design process, the realization of the integrated circuit's logical functions requires the cooperation of many standard logic units, such as selectors, comparators, adders, multipliers, shift registers, etc. The circuit shapes of these logic units are relatively regular and easy to integrate. By connecting these logic units together according to the design requirements, the corresponding data path can be formed. At the same time, a specially designed control unit controls the various components of the data path to work together according to their respective functional requirements and specific timing relationships.

[0098] In practical applications, the driving capability of each logic unit is limited. When the number of loads connected to any logic unit is greater than its corresponding maximum fan-out value, a buffer needs to be added to meet the driving requirements of all loads.

[0099] Combine Figure 5 As shown, assuming that the maximum fan-out value corresponding to each level of logic unit is 32, the number of fan-out units corresponding to each level of logic unit between register RegA and register RegB cannot exceed 32. Once it exceeds, it is necessary to add a buffer to solve the problem. Figure 5 As shown in the figure, L1_1, L1_2, L1_3, ... are newly added to the first level, and L2_1, L2_2, L2_3, ... are newly added to the second level. Therefore, for the timing path from register RegA to register RegB, L1_1, L2_1, L3_1, ... LN_1 are newly added, totaling N levels of units.

[0100] It is understandable that, taking the subsequent fan-out registers as an example, the increase in the number of subsequent fan-out registers will have an impact on timing in two aspects. On the one hand, the increase in the number of metal wires from a starting register to multiple end registers leads to insufficient routing channels and easy congestion. On the other hand, the increase in the number of logic unit levels in the subsequent timing path of the registers and the introduction of new buffers will lead to an increase in the total delay of the timing path, which will undoubtedly increase the possibility of timing violations. The previous fan-in registers have the same problem and will not be repeated here. It can be seen that if the number of previous fan-in registers or subsequent fan-out registers corresponding to any register is too large, the possibility of timing violations in the timing path to which the register belongs will be greater, and it should be the focus of inspection. Further, combined with Figure 5 As shown in the figure, there is a corresponding relationship between the number of front-stage fan-in registers and the number of back-stage fan-out registers and the number of levels of logic units in the timing path.

[0101] Based on the above content, this application provides a method for obtaining the threshold value of the number of registers corresponding to the integrated circuit. For details, see Figure 6 As shown, the method provided in this embodiment mainly includes the following steps.

[0102] S1201. Obtain design parameters of the integrated circuit, where the design parameters include a target clock frequency, a single-stage delay time, and a target single-stage fan-out value.

[0103] The target clock frequency refers to the clock frequency used by the integrated circuit during actual use, which is usually determined during the logic code design stage of the integrated circuit. The target clock frequency can be determined through corresponding design specifications or design criteria. Of course, the target clock frequency can also be obtained through other means. This application does not limit the specific method of obtaining the target clock frequency.

[0104] The single-stage delay duration can be obtained as follows.

[0105] First, the target unit delay is determined as the delay of the logic unit with the shortest inherent time delay in the integrated circuit. It is understandable that in existing logic unit designs, different logic units correspond to different inherent time delays, that is, to different speed performance thresholds. The higher the speed performance threshold, the faster the signal transmission speed, and accordingly, the shortest inherent time delay. This application uses the delay of the logic unit with the shortest inherent time delay as the target unit delay, which means that if the timing path using the logic unit with the best speed performance has timing violations, then other timing paths will inevitably also have timing violations.

[0106] Furthermore, the line delay of all metal lines in the integrated circuit is segmented and statistically analyzed according to the preset time intervals, and a normal distribution curve is fitted based on the statistical results, and finally the expected value of the line delay calculated based on the obtained normal distribution curve is determined as the target line delay. Figure 7 As shown in the figure, assuming that the preset time interval is 1ps (picosecond), based on the preset time interval, the time intervals of 0-1ps, 1-2ps...29-30ps are used as the horizontal coordinates of the normal distribution function. Secondly, the delay of all metal lines in the integrated circuit in each time interval is counted as the vertical coordinate of the normal distribution function, and the following is constructed: Figure 7 The normal distribution curve shown in Figure 2 is used to calculate the expected value based on the obtained normal distribution curve. , the expected value of the obtained line delay is the target line delay.

[0107] In practical applications, the specific value of the aforementioned preset time interval can be determined based on factors such as the actual computing power of the hardware device and the accuracy requirements of the target line delay, and this application does not impose any restrictions on this. As for the specific process of fitting the normal distribution curve and calculating the expected value, reference can be made to the relevant technical implementation, and this application also does not impose any specific restrictions on this.

[0108] Finally, the sum of the target unit delay and the target line delay is calculated, and the calculated result is used as the single-stage delay length.

[0109] The target single-stage fan-out value can be determined as follows.

[0110] In actual applications, the process manufacturer will provide different single-stage fan-out values allowed by the logic unit. This application uses the single-stage fan-out value provided by the process manufacturer as the preset single-stage fan-out value. Based on this, the integrated circuit is laid out and wired according to different preset single-stage fan-out values, and the initial design results corresponding to each preset single-stage fan-out value are obtained. Afterwards, static timing analysis is performed on each initial design result to obtain the corresponding timing violation result. It can be understood that since each initial design result corresponds to a preset single-stage fan-out value, each preset single-stage fan-out value also corresponds to a timing violation result. Based on this, the preset single-stage fan-out value with the best timing result among the preset single-stage fan-out values is used as the target single-stage fan-out value. As for the specific process of static timing analysis and the evaluation method of timing violation results, both can be implemented with reference to relevant technologies, and this application does not make specific limitations on this. It can be understood that the target single-stage fan-out value determined in the above manner will usually be less than the single-stage maximum fan-out value required by the process manufacturer.

[0111] S1202: Determine a threshold value of the number of registers corresponding to the integrated circuit according to a target clock frequency, a single-stage delay time, and a target single-stage fan-out value.

[0112] First, the maximum allowed number of stages of the integrated circuit is determined based on the target clock frequency and the single-stage delay time.

[0113] Specifically, it can be calculated according to the following formula:

[0114] N=T / D (1)

[0115] Where N represents the maximum allowed number of levels corresponding to the integrated circuit;

[0116] T represents the target clock frequency;

[0117] D represents the single-stage delay length.

[0118] It should be noted that if the calculation result of T / D contains decimals, the value obtained by rounding up the calculation result will be used as the maximum allowable level.

[0119] Secondly, the threshold of the number of registers corresponding to the integrated circuit is determined based on the maximum allowed number of stages and the target single-stage fan-out value.

[0120] Specifically, the register quantity threshold may be calculated according to the following formula.

[0121] M=U N (2)

[0122] Where M represents the register quantity threshold;

[0123] U represents the target single-stage fan-out value.

[0124] S130 : If the number of preceding fan-in registers or the number of succeeding fan-out registers corresponding to any register is greater than a register number threshold, it is determined that the logic code of the integrated circuit is abnormal.

[0125] After the above steps, the number of front-stage fan-in registers and the number of back-stage fan-out registers corresponding to each register in the integrated circuit, as well as the register number threshold for the integrated circuit, have been obtained. Based on this, the number of front-stage fan-in registers and the number of back-stage fan-out registers corresponding to each register are compared with the register number threshold. If the number of front-stage fan-in registers or the number of back-stage fan-out registers for at least one register exceeds the register number threshold, it indicates that the integrated circuit is likely to have a timing violation, and the logic design code of the integrated circuit is determined to be abnormal.

[0126] In an optional embodiment, in S110, each register is sorted in the order of the number of rear-stage fan-out registers from large to small, and each register is sorted in the order of the number of front-stage fan-in registers from large to small. Based on this, when executing this step, the statistical results of each register can be compared with the register quantity threshold in sequence according to the sorting results of the aforementioned steps. It can be understood that the comparison process based on the sorting results can significantly improve the comparison efficiency. For example, if the number of rear-stage fan-out registers and the number of front-stage fan-in registers of the first register in the sorting results are both less than the register quantity threshold, it can be determined that the statistical results of all other registers are less than the register quantity threshold, so that there is no need to perform subsequent comparison processes. Correspondingly, if it is determined that the number of rear-stage fan-out registers and the number of front-stage fan-in registers of any register are both less than the register quantity threshold, the other registers located after the register also do not need to be judged in terms of size relationship with the register quantity threshold.

[0127] In summary, this method implements the inspection of the logic code quality based on the number of post-stage fan-out registers and the number of pre-stage fan-in registers corresponding to the registers. The inspection process is simple and easy to implement. In addition, the physical design of the integrated circuit can be divided into logic synthesis and layout and routing. Compared with the prior art in which the logic code quality is inspected after the layout and routing are completed, the method provided in this application can perform code quality inspection after the logic synthesis is completed. Therefore, the quality inspection of the logic code can be completed as early as possible, effectively avoiding the discovery of logic code anomalies after the completion of the entire physical design, which helps to improve the design efficiency of the integrated circuit.

[0128] Furthermore, this application provides another logic code quality inspection method, see Figure 8 As shown, in Figure 1Based on the embodiment shown, the inspection method provided in this embodiment further includes the following steps:

[0129] S140 , taking a register whose number of previous-stage fan-in registers or subsequent-stage fan-out registers is greater than a register number threshold as a target register.

[0130] When it is determined through the above steps that the logic code of the integrated circuit has quality problems, registers in the integrated circuit whose number of front-stage fan-in registers or rear-stage fan-out registers is greater than the register number threshold are used as target registers.

[0131] In an optional embodiment, in S110, each register is sorted in descending order according to the number of subsequent fan-out registers, and each register is sorted in descending order according to the number of previous fan-in registers. Based on this, when executing this step, the statistical results of each register can be compared with the register quantity threshold in turn according to the sorting results of the previous steps, so as to screen out the target registers whose number of previous fan-in registers or the number of subsequent fan-out registers is greater than the register quantity threshold.

[0132] Correspondingly, since the target register is connected to too many previous-stage fan-in registers or subsequent-stage fan-out registers, the timing path to which the target register belongs is more likely to have a timing violation, and will be the key optimization object of the method provided in this application.

[0133] S150 , performing logic design optimization or physical design optimization on the target register.

[0134] Since the design of the integrated circuit can be modified in both the logic design stage and the physical design stage, this application provides two optimization design ideas, optimizing the target register and the timing path to which the target register belongs in the logic design stage and the physical design stage respectively.

[0135] This application provides the following optimization methods to optimize the logic design of the target register.

[0136] In an optional embodiment, if there are no logic units between adjacent timing paths, that is, in the signal transmission direction, the end register of the upstream timing path is directly connected to the starting register of the adjacent downstream timing path through a metal wire, and there are no logic units, then the target register can be copied to obtain N target registers, where N≥2. Further, the multiple timing paths to which the target register belongs are decoupled into N groups of optimized timing paths, and each group of optimized timing paths is connected to a target register. Assuming that the number of subsequent fan-out registers corresponding to the target register is F, through uniform grouping, the number of subsequent fan-out registers corresponding to each target register after copying will become F / N, thereby significantly reducing the number of subsequent fan-out registers corresponding to each target register obtained by copying. According to the above content, in some cases, due to the reduction in the load of the logic unit, it is even possible to reduce the number of buffers used, thereby reducing the number of levels corresponding to the timing path, further shortening the delay of the timing path, and helping to repair the timing violations of the timing path.

[0137] In another optional embodiment, if there are logic units between adjacent timing paths, the timing path to which the target register belongs cannot be decoupled and split. In this case, starting from the target register, the subsequent timing path can be traversed step by step to find the earliest branch point of the logical bifurcation. If the branch point of the logical bifurcation is found before traversing to any terminal register, the first branch point that appears along the timing path direction is used as the target branch point, and a new register is inserted at the target branch point. The part of the logical path originally connected to the target register is connected through the new register to reduce the fan-out number of the target register, that is, to reduce the number of subsequent fan-out registers to which it is ultimately connected. Correspondingly, if the branch point of the logical bifurcation is not found until the terminal register is traversed, part of the logical path of the target register can be deleted or moved. It should be noted that the premise of this operation is that after deleting or moving the logical path, a logical equivalence check needs to be performed to determine whether the logical function has been modified. If the logic is equivalent, there is no need to change the circuit function described by the logic code. If it is not equivalent, the logical function will be modified.

[0138] It should be noted that the optimization measures in the above logic design stage are all explained using the latter fan-out register as an example. The same optimization method can be used for the former fan-in register, which will not be repeated here.

[0139] If it is difficult to fix and optimize in the logic design stage before the code is completed, logic synthesis and layout and routing can be performed in the conventional way, that is, physical design can be performed. Timing violations caused by congestion and increased timing path delay due to high fan-in or high fan-out problems can also be optimized in the physical design stage. To this end, this application further provides a method for optimizing the target register in the physical design stage, see Figure 9 As shown, the method specifically includes the following steps.

[0140] S1501. Obtain a physical design layout of an integrated circuit.

[0141] After completing the physical design process of the integrated circuit, such as logic synthesis and layout and routing, the physical design layout of the integrated circuit can be obtained. Figure 10 From the physical design layout diagram shown and the related information of the physical design layout in the related art, it can be seen that the physical design layout of the integrated circuit not only records the physical dimensions of each logic unit in the integrated circuit, but also records the position coordinates of each logic power supply in the physical design layout. Of course, the physical design layout also records other related information, which will not be described in detail here.

[0142] S1502 : Extract path information of each timing path to which the target register belongs in the physical design layout.

[0143] During the physical design process, static timing analysis can also be performed on the integrated circuit, and the timing path with timing violations in the integrated circuit can be determined based on the static timing analysis results. In one possible application scenario, the timing path with timing violations is also the timing path with high fan-in or high fan-out determined through the aforementioned steps. In another possible application scenario, the timing path with timing violations does not belong to the timing path with high fan-in or high fan-out, but is a timing violation caused by other reasons. For the latter application scenario, the logic amount of the timing path is often small and the structure is relatively simple. Conventional optimization methods can be used for optimization, such as reducing the timing path delay, replacing faster logic units, and adjusting the clock duration, without having to use the optimization method provided by this application. The optimization method provided by this application is mainly aimed at the former application scenario.

[0144] For each target register determined in the preceding steps, path information for each timing path to which the target register belongs in the physical design layout is extracted, specifically including the position coordinates of the starting and ending registers corresponding to each timing path in the physical design layout. It is understood that for any timing path, one of the starting and ending registers must be the target register. In other words, the target register may be a register whose number of fan-in registers in the previous stage exceeds the register number threshold, or a register whose number of fan-out registers in the subsequent stage exceeds the register number threshold.

[0145] Furthermore, the path information can also include the current level number corresponding to the timing path. Timing path level statistics can be completed during the logic synthesis phase or the physical design phase. Regardless of the specific phase, the current level number is calculated using the same rules: the number of all logic units and buffers between the starting and ending registers in any timing path is counted to obtain the current level number of the corresponding timing path.

[0146] Of course, the path information may also include other information, which will not be described in detail here.

[0147] S1503 : Based on the path information, determine a target timing path to be optimized in each timing path to which the target register belongs.

[0148] In actual applications, the position coordinates of each logic unit of the integrated circuit in the physical design layout are determined in the same preset coordinate system. Therefore, the Manhattan distance between any two logic units can be calculated based on the position coordinates of each logic unit. Based on this, in an optional embodiment, for each timing path to which the target register belongs, the stack distance between the starting register and the end register is calculated based on the position coordinates of the starting register and the end register of the timing path. For example, if the position coordinates of the starting register are (X1, Y1) and the position coordinates of the end register are (X2, Y2), then the stack distance corresponding to the timing path is |X2-X1|+|Y2-Y1|. All timing paths are calculated one by one using the same calculation method until the stack distances of all timing paths to which the target register belongs are obtained.

[0149] Furthermore, the relationship between the inter-stack distance of each timing path and the preset inter-stack distance threshold is compared, and the timing path whose inter-stack distance is greater than the preset inter-stack distance threshold is used as the target timing path to be optimized. As mentioned above, different timing paths may correspond to different levels. The more levels a timing path has, the longer the transmission distance is. The timing paths to which the target registers belong are long and short. Therefore, each timing path may correspond to a different preset inter-stack distance threshold. In an optional embodiment, a mapping relationship between the level of the timing path and the preset distance threshold can be established, and the mapping relationship can be queried according to the current level of different timing paths, thereby determining the preset distance threshold that matches the level of the timing path. Of course, the preset distance threshold that matches the actual situation of the timing path can also be determined by other means, which will not be described in detail here. Without exceeding the core idea of the present application, it also falls within the scope of protection of the present application.

[0150] In another optional embodiment, it is also possible to determine whether the timing path needs to be optimized based on the level of the timing path. Specifically, the current level of each timing path in the timing path to which the target register belongs is counted. The specific statistical method can refer to the above content and will not be repeated here. And further compare the current level of each timing path with the maximum allowed level of the integrated circuit, and take the timing path whose current level is greater than the maximum allowed level in each timing path to which the target register belongs as the target timing path to be optimized, wherein the maximum allowed level is determined based on the target clock frequency of the integrated circuit and the single-stage delay duration. The specific calculation process can be referred to the above. Figure 1 The relevant contents of S1202 in the illustrated embodiment will not be repeated here.

[0151] S1504: Optimize the design of the target timing path.

[0152] After determining the target timing path to be optimized based on the above steps, the target timing path can be optimized. The specific optimization method can be one or more of the following three methods.

[0153] In an optional implementation, the layout of the integrated circuit can be updated, that is, the target timing path is processed during the layout phase, primarily to shorten the link length of the target timing path. Specifically, the single-stage delay length Ds corresponding to the target timing path before optimization and the link length L of the target timing path are obtained. Assuming that the updated link length of the target timing path is X, then X should satisfy the following relationship:

[0154] (3)

[0155] Where X represents the updated link length of the target timing path;

[0156] T represents the target clock frequency of the integrated circuit.

[0157] It is understandable that in practical applications, it is necessary to consider the optimization processing of the front-stage path and the back-stage path of the target register at the same time.

[0158] In another optional embodiment, the metal layer to which the metal wires in the target timing path belong can be adjusted, and the metal wires of the target timing path are preferentially laid out in a high-thickness metal layer with low resistance, that is, the metal wires with the largest delay are preferentially adjusted to the high-thickness metal layer, and the wiring resource priority is dynamically allocated. Specifically, the wiring resource utilization of the high-level metal wires (i.e., the metal wires with thicker metal layers) in the area through which the target timing path passes through the physical design layout is first obtained. If there are no metal wires occupied in the corresponding area, the metal wires of the target timing path are directly laid out in the high-level metal layer; on the contrary, if there are metal wires already laid out in the area, the priority is sorted according to the size of the violation. For example, an integrated circuit has 14 layers of metal wires, and the resistance is sorted from large to small as 1, 2, 3...14. A section of metal wire area with the largest line delay on the target path is selected, and the timing violations of each layer of wires in the area are obtained from the static timing analysis results. The metal selection priority of the target path wiring is adjusted according to the size of the violation. The target path area is then selected for length and width. The length of the area is defined as the length of the metal line, and the width is the area enclosed by the metal line width multiplied by a preset ratio. The specific implementation of updating the level to which the metal line belongs can be referenced in related technologies and will not be detailed here.

[0159] After updating the routing information, if the timing violation still cannot be fixed, other metal wire regions with higher delay rankings on the target timing path are selected and the metal wire weights are adjusted again. This solution prioritizes common paths. This means that multi-fan-out paths can have their metal wire weights adjusted sequentially from their starting point backwards, and multi-fan-in paths can have their metal wire weights adjusted sequentially from their ending point forwards.

[0160] In another optional implementation, the timing path length of the start or end register of the target timing path can be adjusted during the clock tree synthesis phase. Specifically, the clock path length can be shortened for the start register of a high fan-out path, or lengthened for the end register of a high fan-in path. The specific clock path length adjustment method can be implemented by referring to related technologies and will not be described in detail here.

[0161] If the requirements are still not met after the above optimization measures are taken, the above steps can be repeated until the optimized physical design meets the requirements.

[0162] In summary, based on the aforementioned embodiments, the inspection method provided in this embodiment can optimize target registers with high fan-in or high fan-out, and provide a method for screening target timing paths to be optimized based on the distance between stacks and the number of timing path levels. It can efficiently screen target timing paths among multiple timing paths, which helps to improve the design efficiency of integrated circuits and shorten the design cycle of integrated circuits.

[0163] The following describes the logic code quality inspection device provided by the present invention. The logic code quality inspection device provided by the present invention is based on the same application concept as the logic code quality inspection method provided in the embodiments of this application. It can execute the logic code quality inspection method provided in any embodiment of this application and has the corresponding functional modules and beneficial effects of executing the logic code quality inspection method. For technical details not fully described in this embodiment, please refer to the logic code quality inspection method provided in the embodiments of this application and will not be repeated here.

[0164] See also Figure 11 The integrated circuit logic code quality inspection device provided in this embodiment includes the following units:

[0165] A first acquisition unit 10 is configured to extract the start register and the end register of all timing paths in the integrated circuit after completing the logic synthesis of the integrated circuit;

[0166] A statistics unit 20 is used to count the number of subsequent fan-out registers and the number of preceding fan-in registers of each register, where the number of subsequent fan-out registers is the total number of the first register connected to the subsequent stage of the register, and the number of preceding fan-in registers is the total number of the first register connected to the preceding stage of the register;

[0167] A second obtaining unit 30 is configured to obtain a register quantity threshold corresponding to the integrated circuit;

[0168] The determination unit 40 is configured to determine that the logic code of the integrated circuit is abnormal if the number of preceding fan-in registers or the number of succeeding fan-out registers corresponding to any register is greater than the register number threshold.

[0169] Furthermore, this application also provides another integrated circuit logic code quality inspection device, see Figure 12 As shown, in Figure 11 Based on the embodiment shown, the inspection device provided in this embodiment further includes:

[0170] A screening unit 50 is configured to select as target registers the number of which the number of preceding-stage fan-in registers or the number of following-stage fan-out registers is greater than the register number threshold;

[0171] The optimization unit 60 is configured to perform logic design optimization or physical design optimization on the target register.

[0172] Below, reference Figure 13 To describe the server provided by an embodiment of the present invention, the server provided by this embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0173] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 communicate with each other through the communication bus 400; obviously, Figure 13 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are merely optional;

[0174] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0175] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0176] The processor 100 is specifically configured to execute the application program in the memory to implement the steps of the above-mentioned logic code quality inspection method.

[0177] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive, an SD (Secure Digital Memory Card), or an MMC (Multimedia Card). The computer-readable storage medium stores one or more instructions for implementing the aforementioned steps. When executed by one or more processors, these one or more instructions cause the processors to perform the aforementioned logical code quality inspection method. For details on the implementation, please refer to the aforementioned description and will not be elaborated upon here.

[0178] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the steps of the logic code quality inspection method according to various embodiments of the present application described in the above content of this specification.

[0179] The computer program product may be written in any combination of one or more programming languages to implement the program code for performing the operations of the embodiments of the present application, including object-oriented programming languages such as Java, C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0180] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented through hardware, software, firmware, or a combination of some or all of the three.

[0181] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0182] Flowcharts are used in this disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or following steps do not necessarily need to be performed in exact order. Instead, the various steps may be performed in reverse order or simultaneously. Furthermore, other operations may be added to these processes.

[0183] Those skilled in the art will appreciate that all or part of the steps in the above method can be performed by instructing the relevant hardware using a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Alternatively, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software functional modules. The present disclosure is not limited to any particular combination of hardware and software.

[0184] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or highly formal sense unless expressly defined as such herein.

[0185] The above is an illustration of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the above is an illustration of the present disclosure and should not be considered as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A method for checking the quality of logic code, characterized in that: include: After completing the logic synthesis of the integrated circuit, extracting the starting register and the ending register of all timing paths in the integrated circuit; Count the number of subsequent fan-out registers and the number of preceding fan-in registers of each register, where the number of subsequent fan-out registers is the total number of the first register connected to the subsequent stage of the register, and the number of preceding fan-in registers is the total number of the first register connected to the preceding stage of the register; Acquiring design parameters of the integrated circuit, wherein the design parameters include a target clock frequency, a single-stage delay time, and a target single-stage fan-out value; Determining a threshold value of the number of registers corresponding to the integrated circuit according to the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value; If the number of preceding fan-in registers or the number of succeeding fan-out registers corresponding to any register is greater than the register number threshold, it is determined that the logic code of the integrated circuit is abnormal.

2. The method according to claim 1, characterized in that Extracting the starting register and the ending register of all timing paths in the integrated circuit, including: Obtaining a timing constraint file of the integrated circuit and a gate netlist obtained after completing logic synthesis; Static timing analysis is performed on the gate netlist based on the timing constraint file, and the starting register and the ending register corresponding to each timing path are identified through the static timing analysis.

3. The method according to claim 1, characterized in that Determining a register quantity threshold corresponding to the integrated circuit according to the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value includes: Determining a maximum allowable number of stages corresponding to the integrated circuit according to the target clock frequency and the single-stage delay duration; A threshold value of the number of registers corresponding to the integrated circuit is determined according to the maximum allowed number of stages and the target single-stage fan-out value.

4. The method according to claim 1, wherein The process of obtaining the single-stage delay duration includes: determining a delay time of a logic unit with the shortest inherent time delay in the integrated circuit as a target unit delay; Performing segmented statistics on the line delays of all metal lines in the integrated circuit at preset time intervals, and fitting a normal distribution curve based on the statistical results; Determine the expected value of line delay calculated based on the normal distribution curve as the target line delay; The sum of the target unit delay and the target line delay is determined to be the single-stage delay length.

5. The method according to claim 1, wherein The process of obtaining the target single-stage fan-out value includes: According to different preset single-stage fan-out values, completing the layout and routing of the integrated circuit to obtain corresponding initial design results; Performing static timing analysis on each of the initial design results to obtain corresponding timing violation results; The preset single-stage fan-out value corresponding to the optimal timing violation result among the preset single-stage fan-out values is used as the target single-stage fan-out value.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: The registers whose number of previous-stage fan-in registers or subsequent-stage fan-out registers is greater than the register number threshold are used as target registers; Performing logic design optimization or physical design optimization on the target register.

7. The method according to claim 6, characterized in that The process of performing logic design optimization on the target register includes: Copying the target register to obtain N target registers, where N is greater than or equal to 2; Decoupling the target timing path to which the target register belongs into N groups of optimized timing paths; Each group of the optimized timing paths is connected to one of the target registers.

8. The method according to claim 6, characterized in that The process of performing logic design optimization on the target register includes: Starting from the target register, traverse along the subsequent timing path step by step; If there is a branch point of logical bifurcation before traversing to the end register, insert a new register at the target branch point so that the new register connects part of the logical path, and the target branch point is the first branch point that appears along the timing path direction; If the traversal reaches the destination register and there is no branch point of logical bifurcation, a portion of the logical path of the target register is deleted or moved.

9. The method according to claim 6, characterized in that The process of performing physical design optimization on the target register includes: Obtaining a physical design layout of the integrated circuit; Extracting path information of each timing path to which the target register belongs in the physical design layout; Determining a target timing path to be optimized among the timing paths to which the target register belongs based on the path information; The target timing path is optimized and designed.

10. The method according to claim 9, characterized in that The path information includes the position coordinates of the starting register and the ending register of the timing path in the physical design layout; Determining a target timing path to be optimized among the timing paths to which the target register belongs based on the path information includes: For each timing path to which the target register belongs, calculating the inter-stack distance between the starting register and the ending register based on the position coordinates of the starting register and the ending register of the timing path; The timing path whose inter-stack distance is greater than a preset inter-stack distance threshold is used as the target timing path to be optimized.

11. The method according to claim 9, characterized in that The path information includes the current level corresponding to the timing path; Determining a target timing path to be optimized among the timing paths to which the target register belongs based on the path information includes: Among the timing paths to which the target register belongs, a timing path whose current number of stages is greater than a maximum allowed number of stages is taken as a target timing path to be optimized, wherein the maximum allowed number of stages is determined based on a target clock frequency of the integrated circuit and a single-stage delay duration.

12. The method according to claim 9, characterized in that Optimizing the target timing path includes at least one of the following methods: shortening the link length of the target timing path; Adjusting the metal layer to which the metal line in the target timing path belongs; In the clock tree synthesis stage, the clock path length of the starting register or the end register of the target timing path is adjusted.

13. A logic code quality inspection device, characterized in that: include: A first acquisition unit is configured to extract the start register and the end register of all timing paths in the integrated circuit after completing the logic synthesis of the integrated circuit; A statistical unit, configured to count the number of subsequent fan-out registers and the number of preceding fan-in registers of each register, wherein the number of subsequent fan-out registers is the total number of the first register connected to the subsequent stage of the register, and the number of preceding fan-in registers is the total number of the first register connected to the preceding stage of the register; a second acquiring unit, configured to acquire design parameters of the integrated circuit, the design parameters including a target clock frequency, a single-stage delay duration, and a target single-stage fan-out value, and determine a threshold value of the number of registers corresponding to the integrated circuit based on the target clock frequency, the single-stage delay duration, and the target single-stage fan-out value; The determination unit is configured to determine that the logic code of the integrated circuit is abnormal if the number of preceding fan-in registers or the number of succeeding fan-out registers corresponding to any register is greater than the register number threshold.

14. A server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein: When the processor executes the computer program, the steps of the logic code quality checking method according to any one of claims 1 to 12 are implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the logic code quality checking method according to any one of claims 1 to 12 are implemented.

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