Comprehensive method, device, equipment and storage medium for optimizing chip area

Abstract

The present application discloses a comprehensive method, apparatus, device, and storage medium for optimizing chip area, belonging to the field of chip design technology. The method includes: obtaining original timing constraints and a hardware description file, the hardware description file being used to describe the function and structure of the chip circuit; amplifying the clock cycle in the original timing constraints to obtain an amplified timing constraint; based on the amplified timing constraint, executing a logic synthesis process on the hardware description file to obtain a logic netlist, the logic netlist being used to indicate the logical structure of the chip circuit; executing a physical synthesis process based on the logic netlist and the original timing constraints to obtain a physical netlist, the physical netlist being used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit. By relaxing the timing constraints in the logic synthesis stage and using the original timing constraints in the physical synthesis stage, the problem of increased chip area caused by the logic synthesis stage is solved while ensuring timing.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a comprehensive method, device, equipment and storage medium for optimizing chip area. Background Art

[0002] In chip design, synthesis is the process of converting hardware description language code into a netlist, encompassing both logic synthesis and physical synthesis. Logic synthesis converts hardware description language code into a logical netlist, while physical synthesis converts the logical netlist into a physical netlist. The logical netlist describes the logical structure of the chip circuitry, such as the components and connections between them. The physical netlist, on the other hand, not only describes the logical structure but also the physical locations of each circuit component. The synthesis process requires a balance between timing and chip area.

[0003] However, before physical synthesis, synthesis tools rely primarily on logic and estimated physical information for optimization in the absence of physical information. However, due to this lack of physical information, during the optimization phase of logic synthesis, circuit elements are added as much as possible to ensure sufficient timing margin for subsequent physical synthesis. This also means an unreasonable increase in chip area.

[0004] Therefore, it is necessary to improve the synthesis method to more effectively control the chip area while ensuring the timing. Summary of the Invention

[0005] This application provides a comprehensive method, apparatus, device, and storage medium for optimizing chip area. The technical solution is as follows:

[0006] According to one aspect of the present application, a comprehensive method for optimizing chip area is provided, the method comprising:

[0007] Obtaining original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of chip circuits;

[0008] Amplifying the clock period in the original timing constraint to obtain an amplified timing constraint;

[0009] Based on the amplified timing constraints, executing a logic synthesis process on the hardware description file to obtain a logic netlist, wherein the logic netlist is used to indicate a logic structure of the chip circuit;

[0010] Based on the logic netlist and the original timing constraints, a physical synthesis process is executed to obtain a physical netlist, which is used to indicate the logic structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

[0011] According to another aspect of the present application, a comprehensive device for optimizing chip area is provided, the device comprising:

[0012] An acquisition module is used to acquire original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of chip circuits;

[0013] an amplification module, configured to amplify the clock period in the original timing constraint to obtain an amplified timing constraint;

[0014] A logic synthesis module, configured to execute a logic synthesis process on the hardware description file based on the amplified timing constraint to obtain a logic netlist, wherein the logic netlist is used to indicate a logic structure of the chip circuit;

[0015] A physical synthesis module is used to execute a physical synthesis process based on the logical netlist and the original timing constraints to obtain a physical netlist, wherein the physical netlist is used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

[0016] According to another aspect of the present application, a computer device is provided. The computer device includes a processor and a memory. A computer program is stored in the memory. The computer program is loaded and executed by the processor to implement a comprehensive method for optimizing chip area.

[0017] According to another aspect of the present application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium. The computer program is loaded and executed by a processor to implement a comprehensive method for optimizing chip area.

[0018] According to another aspect of the present application, a computer program product is provided, comprising a computer program stored in a computer-readable storage medium, wherein a processor reads and executes the computer program from the computer-readable storage medium to implement a comprehensive method for optimizing chip area.

[0019] The beneficial effects of the technical solution provided by this application include at least:

[0020] The logic synthesis process is performed by amplifying the clock cycle during the logic synthesis phase and executing the logic synthesis process based on the amplified timing constraints. After the logic synthesis process completes and a logical netlist is obtained, the physical synthesis process is executed using the original timing constraints during the layout phase (also known as the physical synthesis phase) to obtain the physical netlist. By amplifying the clock cycle during the logic synthesis phase, the timing constraints are relaxed, preventing excessive addition of circuit components to the logic netlist due to tight timing during the logic synthesis phase, which can lead to an unreasonable increase in at least one of the total number of components or the chip area. The original timing constraints are retained during the physical synthesis phase to ensure that the user's original settings are not changed. Furthermore, since the physical synthesis phase simulates the physical positions of each circuit component in the logic netlist, the physical positions of circuit components can be adjusted to meet the original timing constraints (without adding additional circuit components). Therefore, using the tighter original timing constraints during this phase allows the optimization of at least one of the chip area and the total number of components in the chip circuit to be as close to the real world as possible while maintaining the original timing constraints. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 An architectural diagram of a computer system provided by an exemplary embodiment of the present application is shown;

[0023] Figure 2 A flowchart of a comprehensive method for optimizing chip area provided by an exemplary embodiment of the present application is shown;

[0024] Figure 3 A flowchart of a comprehensive method for optimizing chip area provided by another exemplary embodiment of the present application is shown;

[0025] Figure 4 A flowchart of a comprehensive method for optimizing chip area provided by another exemplary embodiment of the present application is shown;

[0026] Figure 5 A flowchart of a comprehensive method for optimizing chip area provided by another exemplary embodiment of the present application is shown;

[0027] Figure 6 The figure shows an overall flow chart of a comprehensive method for optimizing chip area provided by an exemplary embodiment of the present application;

[0028] Figure 7 shows an overall flow chart of a comprehensive method for optimizing chip area provided by another exemplary embodiment of the present application;

[0029] Figure 8 A schematic diagram of a first integrated process provided by an exemplary embodiment of the present application is shown;

[0030] Figure 9 A schematic diagram of a second integrated process provided by an exemplary embodiment of the present application is shown;

[0031] Figure 10 A schematic diagram of a third integrated process provided by an exemplary embodiment of the present application is shown;

[0032] Figure 11 A structural block diagram of a comprehensive device for optimizing chip area provided by an exemplary embodiment of the present application is shown;

[0033] Figure 12 A schematic structural diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0035] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0036] The terms used in this disclosure are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0037] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, storage, and display, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the information such as the settings operations involved in this application is obtained with full authorization.

[0038] It should be understood that although the terms first, second, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter without departing from the scope of this disclosure. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0039] First, the relevant terms involved in this application are introduced.

[0040] Synthesis: The process of converting a description language into a specific circuit implementation. This process includes two main stages: logical synthesis and physical synthesis. The description language can be a hardware description language (HDL) or another programming language. The present application examples illustrate the use of a hardware description language as an example, but this is not a limitation.

[0041] (1) Logic synthesis: The process of converting hardware description language code into a logic netlist. Logic synthesis requires syntax checking and parsing of the hardware description language code, optimizing the logical expressions in the hardware description language code, and mapping the optimized logical expressions to a specific process library.

[0042] (2) Physical synthesis: The process of converting a logical netlist into a physical netlist. Physical synthesis includes processes such as placement, routing, and optimization. Placement is the process of determining the physical location information of circuit elements in the logical netlist on the chip circuit. The goal of placement is to optimize the placement of cells to reduce wire length and timing delay. Routing is to complete the connection between all circuit elements in the chip circuit based on placement. Routing needs to consider signal integrity, electromagnetic compatibility, and design rule constraints.

[0043] Hardware Description Language (HDL): A programming language used to describe electronic systems and integrated circuits. It can describe a circuit's logical structure, behavior, functionality, and timing characteristics in textual form, without requiring a direct circuit diagram. HDL provides a standardized method for describing and designing complex digital circuits and systems.

[0044] Timing constraints: In digital circuit design, specifications that limit and constrain signal transmission time and timing relationships. User-configurable timing constraints include at least one of the following: clock period; duty cycle; generated clock; input delay; and output delay.

[0045] A clock cycle is the time it takes for a clock signal to complete one full cycle (from high to low and back to high). It is the reciprocal measure of the clock frequency and determines the rate at which data is transferred and processed within a circuit. In IC design, clock cycles are typically measured in nanoseconds (ns) or picoseconds (ps). For example, if a clock frequency is 100 MHz, its clock cycle is 10 nanoseconds.

[0046] A clock's duty cycle is the ratio of the duration of the clock signal's high level during one cycle to the total duration of the cycle. Usually expressed as a percentage, a clock signal with a 50% duty cycle means that during one cycle, the high level lasts half as long as the low level lasts half as long. For example, if a clock signal has a period of 10 nanoseconds and its high level lasts for 5 nanoseconds, its duty cycle is 50%.

[0047] A generated clock is a sub-clock signal derived from a master clock. It typically originates from a circuit module's clock management unit, such as a Mixed-Mode Clock Manager (MMCM) or Phase-Locked Loop (PLL). This clock management unit generates clock signals of varying frequencies to meet the clock frequency requirements of different circuit modules within the design. It also ensures clock synchronization between different circuit modules, eliminates clock skew and jitter, and ensures clock signal stability and consistency. It also supports dynamic phase adjustment, allowing the phase of the clock signal to be shifted as needed to optimize timing performance. Generated clocks can have various relationships with the master clock, including frequency division, frequency multiplication, non-integer frequency multiplication, phase shifting, duty cycle switching, and combinations of these. The primary advantage of a generated clock is that when the master clock changes, the generated clock changes synchronously, maintaining clock consistency. In timing constraints, the generated clock definition should be performed after the master clock definition.

[0048] Input delay is the delay from the clock edge of an upstream chip to the external input port of a downstream chip, such as an FPGA (Field-Programmable Gate Array). It includes chip output delay (Tco) and trace delay (or board delay). Chip output delay refers to the time required for a chip's output signal to reach the input port of the next chip. Trace delay refers to the signal's propagation delay on a printed circuit board (PCB), affected by factors such as signal path length and material properties. Users define input delay to ensure that external input signals arrive and stabilize before the clock edge is captured by the registers in the downstream chip, meeting setup and hold time requirements.

[0049] Output delay is the delay from the clock edge of an internal register to the external output port. It describes the timing characteristics of the internal signal transmission to the output port. It includes internal combinational logic delay and output driver delay. Internal combinational logic delay refers to the signal transmission delay within the internal logic circuit. Output driver delay refers to the signal delay from the internal register to the external port. By defining output delay, the user ensures that the internal signal reaches the external output port before the external chip register captures the clock edge and meets the external chip's setup and hold time requirements.

[0050] Netlist: A file that describes the connections between circuit components. It is typically a text file that contains the following core components:

[0051] Instances: Each circuit element (such as a transistor, resistor, capacitor, logic gate, etc.) appears as an "instance" in the netlist, and each instance has a unique identifier to uniquely identify it in the circuit.

[0052] Ports and connection points (Pins / Ports): The connection point (port) of each component is the "interface" of the circuit element. The number and nature of the ports depend on the type of component.

[0053] Nets: A network describes the connection relationship between components and can be regarded as a "signal path" in a circuit. Signals can be transmitted between components through the network.

[0054] Attributes: The netlist may also contain some additional information, such as component packaging, special properties, voltage, frequency, load, etc. These parameters help designers perform simulation and analysis.

[0055] Process library: A database that describes and stores standard cells and related parameters for a specific process node. It contains detailed information and characteristics of various logic cells (such as logic gates and flip-flops) under specific process conditions. For example, each standard cell has its function, area, power consumption, and timing characteristics (such as setup time, hold time, and propagation delay); characteristics such as resistance and capacitance of wires, which are used to estimate signal propagation delay on the wires; and process parameters, voltage, and temperature ranges for the process node.

[0056] Layout: The physical geometric description of the circuit design, including the size, number, position, and dimensions of transistors, the size and position of wires, etc., and follows a series of design rules and process conditions.

[0057] Figure 1 FIG. 1 shows an architecture diagram of a computer system provided by an exemplary embodiment of the present application. The computer system includes a computer device 110 .

[0058] Optionally, the computer device 110 may be a terminal or a server.

[0059] Optionally, the terminal includes, but is not limited to, mobile phones, tablet computers, intelligent voice interaction devices, game consoles, wearable devices, multimedia playback devices, PCs (Personal Computers), in-vehicle terminals, smart home appliances, and other electronic devices. Optionally, a synthesis tool can be installed and run on the terminal, which supports and assists users in converting hardware description files written in a hardware description language into physical netlists or other representations of chip circuits. Optionally, the synthesis tool can be a suite of tools, with individual software components used to execute different steps in the synthesis process, such as separate software components for logic synthesis and physical synthesis. Alternatively, the synthesis tool can be a single tool, integrating the logic and physical synthesis processes into a single tool.

[0060] Optionally, the synthesis tool may have a GUI (Graphical User Interface); or it may be driven by instructions that require the user to use them directly. When the synthesis tool has a GUI, the synthesis method for optimizing chip area provided in the embodiment of the present application may be integrated into a method corresponding to a control, that is, when the user triggers the control, the synthesis method for optimizing chip area provided in the embodiment of the present application is executed. When the user is required to use instructions to drive directly, the synthesis method for optimizing chip area provided in the embodiment of the present application may be integrated into one or more instructions, such as one instruction corresponding to all steps in the synthesis method for optimizing chip area provided in the embodiment of the present application, or, may be integrated into multiple instructions, that is, one or more steps in the synthesis method for optimizing chip area provided in the embodiment of the present application correspond to one instruction respectively. That is, the embodiment of the present application does not limit the driving method of the synthesis method for optimizing area.

[0061] Optionally, the server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms, but is not limited to these.

[0062] Alternatively, the server can provide backend services for the synthesis tool in the terminal. Specifically, the terminal uploads the original timing constraints and hardware description files entered by the user to the server, which then generates the physical net based on the original timing constraints and hardware description files. Alternatively, the server can provide backend services for synthesis tools in multiple terminals.

[0063] Optionally, the terminal may communicate with the server via a network, such as a wireless or wired network.

[0064] In the absence of a layout in the early stages, for designs with large area, complex logic, and tight timing, the synthesis tool's miscalculation during placement and routing can lead to an unreasonable increase in the number of circuit components and chip area after logic synthesis optimization. During the early stages of logic synthesis, when the logic is complex and timing is tight, the synthesis tool optimizes timing by replacing equivalent logic, which can lead to an increase in the number of components in the circuit. Because the tools lack physical information in the early stages of design, this increase in area due to an increase in component count is somewhat unreasonable. During logic synthesis, some commonly used strategies for closing timing can exacerbate this inefficiency. For example, methods such as increasing clock uncertainty or moderately increasing clock frequency are often used to force the tool to optimize the logic structure as much as possible to meet timing requirements and even leave sufficient timing margin for subsequent placement and routing.

[0065] Figure 2 FIG1 shows a flow chart of a comprehensive method for optimizing chip area provided by an exemplary embodiment of the present application. The method is executed by a computer device, which may be a computer device such as Figure 1 The computer device shown in the figure includes the following steps.

[0066] Step 210: Obtain original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of chip circuits.

[0067] The original timing constraints are set by the user; or, the original timing constraints are default values ​​set by the developer.

[0068] Optionally, the hardware description file stores a hardware description language code, which is a code written in a hardware description language and is used to describe the function and structure of the chip circuit.

[0069] Exemplarily, the hardware description language code includes module definition and behavior description. The module definition is used to describe the structure of the chip circuit, such as the various circuit modules (also called circuit entities) included in the chip circuit. The behavior description is used to describe the function of the chip circuit, such as the behavior of each circuit module in the chip circuit, that is, which circuit modules are called to participate in calculation and which modules are called to participate in judgment in order to realize a certain function, and so on.

[0070] Optionally, obtain original timing constraints and hardware description files; or obtain original timing constraints and hardware description language codes.

[0071] Step 220: Enlarge the clock period in the original timing constraint to obtain an enlarged timing constraint.

[0072] The original timing constraint includes a clock period, which can be referred to as an original clock period. Optionally, the original timing constraint can also include at least one of the following parameters: duty cycle; generated clock; input delay; and output delay.

[0073] Optionally, the amplified timing constraint is obtained by amplifying the clock period in the original timing constraint. That is, the amplified timing constraint includes the amplified clock period. The amplified timing constraint may also include at least one of the following parameters: a clock duty cycle; a generated clock; an input delay; or an output delay. Parameters other than the clock period in the amplified timing constraint may be the same as or different from those in the original timing constraint.

[0074] Exemplarily, the generated clock in the amplified timing constraint is the same as or different from the generated clock in the original timing constraint. For example, the original master clock is 200MHz, that is, the original clock period is 5ns, and the generated clock requires 200MHz, so the multiplication factor is set to 1. If the clock period becomes 10ns after the clock period is amplified, the master clock becomes 100MHz. In order to keep the generated clock at 200MHz, the multiplication factor should be adjusted to 2. At this time, the generated clock in the amplified timing constraint is different from the generated clock in the original timing constraint. The duty cycle in the amplified timing constraint is the same as the duty cycle in the original timing constraint; or, the input delay in the amplified timing constraint is the same as the input delay in the original timing constraint; or, the output delay in the amplified timing constraint is the same as the output delay in the original timing constraint.

[0075] Step 230: Based on the amplified timing constraints, a logic synthesis process is performed on the hardware description file to obtain a logic netlist, which is used to indicate the logic structure of the chip circuit.

[0076] In the process of executing the logic synthesis flow on the hardware description file, the timing is judged by amplifying the timing constraints to obtain the logic netlist.

[0077] Optionally, the logic netlist is used to indicate the logical structure of the chip circuit. That is, the logic netlist is used to indicate the circuit elements included in the chip circuit and the connection relationship between each circuit element. However, the connection relationship between these circuit elements is directly based on the circuit modules and the functions of the circuit modules indicated in the hardware description file. In other words, the connection relationship indicated in the logic netlist is a functional or behavioral connection relationship, and does not take into account the physical relationship between these circuit elements on the circuit board. Among them, the circuit module indicated in the hardware description file can be implemented using one circuit element or multiple circuit elements, depending on the complexity of the function of the circuit module.

[0078] Optionally, the circuit elements in the logic netlist are general-purpose gate circuits, or gate circuits in a target process library. The target process library can be a default process library set by the developer or a process library set by the user. General-purpose gate circuits are unit circuits used to implement basic logical operations, such as AND gates, OR gates, NOT gates, NAND gates, NOR gates, XOR gates, XNOR gates, and so on.

[0079] Optionally, based on the relaxed clock cycle, executing a logic synthesis process on the hardware description file results in a first logic netlist; the total number of components corresponding to the first logic netlist is less than the total number of components corresponding to the second logic netlist; or the chip area corresponding to the first logic netlist is less than the total number of components corresponding to the second logic netlist, and the chip area corresponding to the first logic netlist is less than the chip area corresponding to the second logic netlist. The second logic netlist is obtained by executing a logic synthesis process on the hardware description file based on the original timing constraints. It should be noted that at least one of the total number of components and the chip area mentioned above can be at least one of an estimated total number of components and an estimated chip area obtained by a computer device based on the logic netlist. It can also be at least one of the actual total number of components and the actual chip area of ​​the chip circuit obtained after executing subsequent processes (such as layout) based on the first and second logic netlists. In this case, the subsequent processes executed by the first and second logic netlists and the parameters used in the subsequent processes should be the same or similar.

[0080] Step 240: Based on the logic netlist and the original timing constraints, execute the physical synthesis process to obtain the physical netlist, which is used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

[0081] A physical synthesis process is executed for the logic netlist, and original timing constraints are used in the physical synthesis process to determine timing to obtain a physical netlist; or a physical synthesis process is executed for the logic netlist, and original timing constraints are used in the physical synthesis process to determine or optimize timing to obtain a physical netlist.

[0082] Optionally, a layout process is performed based on the logical netlist and the original timing constraints to obtain a physical netlist; or, a layout process and a routing process are performed based on the logical netlist and the timing constraints to obtain a physical netlist; or, a physical synthesis process is performed based on the logical netlist and the timing constraints to obtain a physical netlist. If the routing process is performed, the physical netlist also indicates the physical connections between the various circuit elements in the chip circuit. This physical connection includes the placement of each circuit element (such as its orientation), the path and width of the wires, and so on. The logical netlist, on the other hand, indicates the connection relationships between the various circuit elements, such as whether port a of circuit element 1 is connected to port a of circuit element 2, and so on.

[0083] Optionally, the physical synthesis process includes a layout process. Alternatively, the physical synthesis process includes a layout process and a routing process. Alternatively, the physical synthesis process includes a layout process, a routing process, and an optimization process.

[0084] It should be noted that the execution of the corresponding process in the embodiment of the present application can be called by the computer device itself. For example, after the user triggers the comprehensive method for optimizing the area, the computer device executes each process according to the execution order of the process shown in steps 210 to 240 above. In the process of the computer device executing each process, the call of instructions may be involved. If the user does not directly trigger the comprehensive method for optimizing the area, but directly uses these instructions to execute the comprehensive process, the effect of the comprehensive method for optimizing the area shown in the embodiment of the present application can also be achieved, that is, the above steps 210 to 240 are no longer actively called by the computer device according to the program, but are executed in response to the user's instruction trigger operation. However, it should be emphasized that this method also falls within the scope of protection of the embodiment of the present application.

[0085] In summary, the method provided in the embodiments of the present application illustrates a synthesis method. This method involves amplifying the clock cycle during the logic synthesis phase and performing a logic synthesis process based on the amplified timing constraints resulting from the amplified clock cycle. After the logic synthesis process concludes and a logical netlist is obtained, the physical synthesis process is executed using the original timing constraints during the layout phase (also known as the physical synthesis phase) to obtain a physical netlist. By amplifying the clock cycle during the logic synthesis phase, the timing constraints are relaxed, preventing excessive addition of circuit components to the logic netlist due to tight timing during the logic synthesis phase, which can lead to an unreasonable increase in at least one of the total number of components or the chip area. The original timing constraints are still used during the physical synthesis phase, both to ensure that the user's original settings are not changed and, because the physical synthesis phase simulates the physical positions of each circuit component in the logic netlist, the physical positions of the circuit components can be adjusted to meet the original timing constraints (without adding additional circuit components). Therefore, using the tighter original timing constraints during this phase can optimize at least one of the chip area and the total number of components of the chip circuit while maintaining the original timing constraints and aligning as closely as possible with real-world scenarios.

[0086] Based on Figure 2 In an optional embodiment, as Figure 3 The above step 220 can be implemented as steps 221 to 223.

[0087] Step 221: Determine an amplification adjustment interval of the clock cycle in the original timing constraints.

[0088] Optionally, the amplification adjustment interval of the clock cycle is a value interval of the clock cycle. The amplification adjustment interval of the clock cycle is set by the developer; or, the amplification adjustment interval of the clock cycle is determined based on the original timing constraints and the amplification ratio interval set by the developer; or, the amplification adjustment interval of the clock cycle is determined based on the original timing constraints and the amplification ratio interval set by the user; or, the amplification adjustment interval of the clock cycle is determined based on the original timing constraints set by the user and the hardware description file.

[0089] Optionally, the clock cycle amplification adjustment interval is a value range of the clock cycle amplification ratio (i.e., an amplification ratio interval). The clock cycle amplification adjustment interval is set by the developer; or, the clock cycle amplification adjustment interval is set by the user; or, the clock cycle amplification adjustment interval is determined based on the original timing constraints set by the user and the hardware description file.

[0090] That is, the embodiment of the present application does not limit the form of expression of the amplification adjustment interval of the clock cycle.

[0091] For example, the developer provides at least one magnification adjustment interval, from which the user can select a magnification adjustment interval by triggering methods such as inputting instructions or clicking a control. Alternatively, the developer provides at least one magnification ratio interval, which includes an upper limit and a lower limit for the magnification ratio. The magnification ratio is used to magnify the clock cycle. For example, when amplifying the clock cycle, the amplified clock cycle = the amplification ratio × the original clock cycle (i.e., the clock cycle in the original timing constraint), in which case the amplification ratio is a value greater than 1. Alternatively, the amplified clock cycle = (1 + the amplification ratio) × the original clock cycle, in which case the amplification ratio is a value greater than 0 and less than 1.

[0092] Exemplarily, the amplification adjustment range for the clock period is determined based on the original timing constraints and hardware description file set by the user. That is, after the user starts the synthesis process or inputs the original timing constraints and hardware description file, the computer device determines the amplification adjustment range for the clock period in the original timing constraints of the hardware description file based on the original timing constraints and the hardware description file.

[0093] Optionally, the amplified adjustment interval of the clock cycle is the effective adjustment interval of the clock cycle. That is, for clock cycles within the effective adjustment interval of the clock cycle, as the value of the clock cycle increases, at least one of the total number of components and the chip area corresponding to the logic netlist obtained after executing the above-mentioned synthesis process will decrease accordingly. However, in some embodiments, the amplified adjustment interval of the clock cycle may include the effective adjustment interval of the clock cycle, or the amplified adjustment interval of the clock cycle is a portion of the effective adjustment interval of the clock cycle. That is, the relationship between the amplified adjustment interval of the clock cycle and the effective adjustment interval of the clock cycle can be a true subset, a true superset, equal, etc.

[0094] Step 222: Determine the optimal clock cycle from the amplified adjustment interval of the clock cycle.

[0095] Optionally, based on the amplification adjustment interval of the clock cycle, an amplified clock cycle is selected from small to large, and it is determined whether the amplified clock cycle is an optimal clock cycle.

[0096] Optionally, the optimal clock cycle is the clock cycle that makes the area parameter of the generated logical netlist less than the target area parameter; or, the optimal clock cycle is the clock cycle that makes the area parameter of the generated physical netlist less than the target area parameter; or, the optimal clock cycle is the clock cycle that makes the area parameter of the generated logical netlist less than or equal to the target area parameter; or, the optimal clock cycle is the clock cycle that makes the area parameter of the generated physical netlist less than or equal to the target area parameter. The area parameter includes at least one of the total number of components and the chip area. Optionally, the target area parameter can be set by the developer, based on expert experience, or by the user. Optionally, the target area parameter includes at least one of the target total number of components and the target chip area. That is, the optimal clock cycle is the clock cycle that makes the total number of components in the generated logical netlist less than or equal to the target total number of components; or, the optimal clock cycle is the clock cycle that makes the chip area of ​​the generated logical netlist less than or equal to the target chip area; or, the optimal clock cycle is the clock cycle that makes the total number of components in the generated logical netlist less than or equal to the target total number of components and makes the chip area of ​​the generated logical netlist less than or equal to the target chip area. Alternatively, the optimal clock cycle refers to a clock cycle that makes the total number of components in the generated physical netlist less than or equal to the target total number of components; or, the optimal clock cycle refers to a clock cycle that makes the chip area of ​​the generated physical netlist less than or equal to the target chip area; or, the optimal clock cycle refers to a clock cycle that makes the total number of components in the generated physical netlist less than or equal to the target total number of components and makes the chip area of ​​the generated physical netlist less than or equal to the target chip area. The physical netlist can be obtained by executing a physical synthesis process based on the original timing constraints, or by executing a physical synthesis process based on the amplified timing constraints corresponding to the optimal clock cycle. It should be noted that the physical netlist here refers to the physical netlist involved in the optimal clock cycle determination process, rather than the physical netlist obtained after executing the chip area optimization synthesis method in step 240. That is, in the optimal clock cycle determination process, the determination can be based on at least one of the estimated total number of components and the estimated chip area corresponding to the logical netlist, or based on at least one of the estimated total number of components and the estimated chip area corresponding to the physical netlist. Generally speaking, since physical information is used in the physical synthesis process, at least one of the estimated total number of components and the estimated chip area corresponding to the obtained physical netlist is more accurate than at least one of the estimated total number of components and the estimated chip area corresponding to the logical netlist. Therefore, the judgment is based on at least one of the estimated total number of components and the estimated chip area corresponding to the physical netlist.

[0097] Step 223: Based on the optimal clock period, obtain the amplification timing constraint.

[0098] Optionally, the clock period in the original timing constraint is adjusted to the optimal clock period to obtain an amplified timing constraint. Alternatively, the clock period in the original timing constraint is adjusted to the optimal clock period, and based on the optimal clock period, relevant parameters in the original timing constraint are adjusted to obtain the amplified timing constraint, such as adjusting the frequency division coefficient, frequency multiplication coefficient, etc. corresponding to the generated clock. The relevant parameters are parameters affected by the adjustment of the clock period.

[0099] In summary, the method provided in the embodiments of the present application illustrates a method for first determining an amplification adjustment range for a clock cycle, then determining an optimal clock cycle from this amplification adjustment range, and obtaining an amplification timing constraint based on this optimal clock cycle. This method, which obtains the amplification timing constraint and then executes the synthesis process based on this amplification timing constraint, allows for more reasonable relaxation of the clock cycle during the synthesis process, compared to randomly obtaining an amplification timing constraint, thereby minimizing at least one of the total number of components and chip area while satisfying the timing constraint.

[0100] Next, it is shown how to determine the enlarged adjustment interval of the clock cycle based on the original timing constraints and the hardware description file, how to determine the optimal clock cycle from the enlarged adjustment interval of the clock cycle, and how to improve the logic synthesis process.

[0101] 1. Determination of the magnification adjustment range.

[0102] Based on Figure 3 In an optional embodiment, as Figure 4 As shown, the above step 221 can be implemented as steps 310 to 360.

[0103] Step 310: Determine original area parameters based on original timing constraints.

[0104] The original area parameter includes at least one of the original total number of components and the original chip area. That is, at least one of the original total number of components and the original chip area is determined based on the original timing constraints.

[0105] In some embodiments, step 310 can be implemented as follows: based on the original timing constraints, executing a first logic synthesis process and a layout process on the hardware description file to obtain original area parameters; or, based on the original timing constraints, executing a first logic synthesis process on the hardware description file to obtain original area parameters; or, based on the original timing constraints, executing a first logic synthesis process, a layout process, and a routing process on the hardware description file to obtain original area parameters; or, based on the original timing constraints, executing a first logic synthesis process and a physical synthesis process on the hardware description file to obtain original area parameters.

[0106] That is, based on the original timing constraints, a first logic synthesis process and a layout process are executed on the hardware description file to obtain at least one of the original total number of components and the original chip area; or, based on the original timing constraints, a first logic synthesis process is executed on the hardware description file to obtain at least one of the original total number of components and the original chip area; or, based on the original timing constraints, a first logic synthesis process, a layout process and a routing process are executed on the hardware description file to obtain at least one of the original total number of components and the original chip area; or, based on the original timing constraints, a first logic synthesis process and a physical synthesis process are executed on the hardware description file to obtain at least one of the original total number of components and the original chip area.

[0107] Optionally, the first logic synthesis process includes an optimization process, which is used to adjust the expected area parameters corresponding to the logic netlist based on the timing constraints, that is, the optimization process is used to adjust at least one of the expected total number of components and the expected chip area corresponding to the logic netlist based on the timing constraints. In the case where the physical synthesis process also includes an optimization process, the optimization process included in the first logic synthesis process can be referred to as the first optimization process, and the optimization process in the physical synthesis can be referred to as the second optimization process. The first optimization process is used to adjust at least one of the expected total number of components and the expected chip area corresponding to the logic netlist based on the timing constraints. The second optimization process is used to adjust at least one of the expected total number of components and the expected chip area corresponding to the physical netlist based on the timing constraints. In the above-mentioned step 310 and its corresponding optional embodiments, the first optimization process and the second optimization process both use the original timing constraints.

[0108] Step 320: Determine the i-th magnification ratio, where i is a positive integer.

[0109] Optionally, the initial value of i is 1.

[0110] Optionally, the first magnification ratio is an initial value set by a user; or, the first magnification ratio is a default value set by a developer.

[0111] Optionally, the first amplification ratio is used to indicate a lower limit of the amplification adjustment interval of the clock cycle.

[0112] Exemplarily, the method further includes: obtaining a first amplification ratio; and determining a lower limit of the amplification adjustment interval of the clock cycle based on the first amplification ratio. The first amplification ratio is set by a user.

[0113] Optionally, when i is greater than 1, the i-th amplification ratio is greater than the i-1-th amplification ratio.

[0114] In some embodiments, when i is greater than 1, the i-th magnification ratio is determined based on at least one of the 1st magnification ratio and the (i-1)th magnification ratio.

[0115] For example, the n magnification ratios determined in n cycles satisfy an arithmetic progression, where n is a positive integer. That is, when i is greater than 1, the i-th magnification ratio = the i-1-th magnification ratio + d; or, in other words, the i-th magnification ratio = the 1-th magnification ratio + (i-1) × d. Where d is the tolerance, and is typically a positive number, this tolerance can be set by either the user or the developer.

[0116] For example, the n magnification ratios determined in n cycles satisfy a geometric progression. That is, when i is greater than 2, the i-th magnification ratio = the i-1-th magnification ratio × q; or, the i-th magnification ratio = the 1st magnification ratio × q i-1 Wherein, q is a common ratio, and generally speaking, q is a positive number greater than 1. The common ratio can be set by the user or by the developer.

[0117] For example, the n amplification ratios determined in n cycles satisfy the exponential growth law. That is, when i is greater than 1, the i-th amplification ratio = the 1st amplification ratio × e k×(i-1) , where e is the base of the natural logarithm and k is the growth constant. k can be set by the user or by the developer.

[0118] It should be noted that the n amplification ratios determined in n cycles can also be set based on other growth patterns, such as logarithmic growth patterns, power law growth patterns, and so on. In other words, the present embodiment does not limit the method for setting the i-th amplification ratio. Developers or users can use corresponding amplification ratio determination formulas based on actual needs. The present embodiment does not list the amplification ratio determination formulas one by one, but the scope of protection of the present embodiment is not limited thereto.

[0119] Step 330: Based on the i-th amplification ratio, amplify the clock period in the original timing constraint to obtain the i-th amplified timing constraint.

[0120] Optionally, based on the i-th amplification ratio, the clock cycle in the original attribute constraint is amplified to obtain the i-th clock cycle; based on the i-th clock cycle and the original timing constraint, the i-th amplified timing constraint is obtained.

[0121] Exemplarily, the original clock cycle in the original timing constraint is replaced with the i-th clock cycle to obtain the i-th amplified timing constraint; or, the original clock cycle in the original timing constraint is replaced with the i-th clock cycle, and the relevant parameters in the original timing constraint are adjusted based on the i-th clock cycle to obtain the i-th amplified timing constraint, such as adjusting the division coefficient, multiplication coefficient, etc. corresponding to the generated clock.

[0122] Step 340 : Determine the i-th area parameter based on the i-th amplification timing constraint.

[0123] Optionally, at least one of the i-th total number of components and the i-th chip area is determined based on the i-th amplification timing constraint.

[0124] Optionally, step 340 can be implemented as follows: based on the i-th amplification timing constraint, executing the first logic synthesis process and the layout process to obtain the i-th area parameter; or, based on the i-th amplification timing constraint, executing the first logic synthesis process to obtain the i-th area parameter; or, based on the i-th amplification timing constraint, executing the first logic synthesis process, the layout process and the routing process to obtain the i-th area parameter; or, based on the i-th amplification timing constraint, executing the first logic synthesis process and the physical synthesis process to obtain the i-th area parameter.

[0125] Optionally, based on the i-th amplification timing constraint, a first logic synthesis process and a layout process are executed to obtain at least one of the i-th total number of components and the i-th chip area; or, based on the i-th amplification timing constraint, the first logic synthesis process is executed to obtain at least one of the i-th total number of components and the i-th chip area; or, based on the i-th amplification timing constraint, the first logic synthesis process, the layout process and the routing process are executed to obtain at least one of the i-th total number of components and the i-th chip area; or, based on the i-th amplification timing constraint, the first logic synthesis process and the physical synthesis process are executed to obtain at least one of the i-th total number of components and the i-th chip area.

[0126] Optionally, the first logic synthesis process includes an optimization process for adjusting the estimated area parameters corresponding to the logic netlist based on timing constraints. Specifically, the optimization process is used to adjust at least one of the estimated total number of components and the estimated chip area corresponding to the logic netlist based on timing constraints. If the physical synthesis process also includes an optimization process, the optimization process included in the first logic synthesis process can be referred to as the first optimization process, while the optimization process in the physical synthesis process can be referred to as the second optimization process. The first optimization process is used to adjust at least one of the estimated total number of components and the estimated chip area corresponding to the logic netlist based on timing constraints. The second optimization process is used to adjust at least one of the estimated total number of components and the estimated chip area corresponding to the physical netlist based on timing constraints. In step 340 and its corresponding optional embodiments, both the first and second optimization processes use the i-th amplified timing constraints; alternatively, the first optimization process uses the i-th amplified timing constraints, while the second optimization process uses the original timing constraints. This embodiment of the present application illustrates the example of both the first and second optimization processes using the i-th amplified timing constraints, but this is not a limitation.

[0127] It should be noted that in the first logic synthesis process and the physical synthesis process, other processes besides the optimization process may also need to use timing constraints. In this case, these processes will maintain the same timing constraints as the optimization process. That is, the timing constraints used by these processes can refer to the timing constraints used by the above-mentioned first optimization process and the second optimization process. The timing constraints used by other processes in this embodiment of the application will not be repeated.

[0128] Step 350: Determine an i-th area parameter reduction value based on at least one of the original area parameter and the i-th area parameter.

[0129] Optionally, at least one of the i-th component total number reduction value and the i-th chip area reduction value is determined based on at least one of the original component total number, the original chip area, the i-th component total number and the i-th chip area.

[0130] Optionally, the decrease value of the total number of i-th elements is determined based on at least one of the original total number of elements and the i-th total number of elements; or, the decrease value of the i-th chip area is determined based on at least one of the original chip area and the i-th chip area; or, the decrease value of the total number of i-th elements is determined based on at least one of the original total number of elements and the i-th total number of elements, and the decrease value of the i-th chip area is determined based on at least one of the original chip area and the i-th chip area.

[0131] In some embodiments, step 350 can be implemented as follows: when i is 1, based on the original area parameter and the first area parameter, determine the first area parameter decrease value; when i is greater than 1, based on the i-th area parameter and the i-1-th area parameter, determine the i-th area parameter decrease value; wherein, the i-1-th area parameter is determined based on the i-1-th amplification timing constraint corresponding to the i-1-th amplification ratio.

[0132] Optionally, when i is 1, a first total number of components is reduced based on the original total number of components and the first total number of components; or, a first chip area reduction is determined based on the original chip area and the first chip area; or, a first total number of components is reduced based on the original total number of components and the first total number of components, and a first chip area reduction is determined based on the original chip area and the first chip area. When i is greater than 1, an i-th total number of components is reduced based on the i-th total number of components and the i-1th total number of components; or, a i-th chip area reduction is determined based on the i-th chip area and the i-1th chip area; or, a i-th total number of components is reduced based on the i-th total number of components and the i-1th total number of components, and a i-th chip area reduction is determined based on the i-th chip area and the i-1th chip area. The i-1th total number of components is determined based on the i-1th amplification timing constraint corresponding to the i-1th amplification ratio; and the i-1th chip area is determined based on the i-1th amplification timing constraint corresponding to the i-1th amplification ratio.

[0133] The method for determining at least one of the total number of i-1th components and the i-1th chip area based on the i-1th amplification timing constraint may refer to the above step 340 and will not be repeated here.

[0134] Exemplarily, the decrease in the total number of the first component is equal to the difference between the total number of the first component and the original total number of components; or, in other words, the decrease in the total number of the first component is equal to the absolute value of the difference between the total number of the first component and the original total number of components. The decrease in the area of ​​the first chip is equal to the difference between the area of ​​the first chip and the original chip area; or, in other words, the decrease in the area of ​​the first chip is equal to the absolute value of the difference between the area of ​​the first chip and the original chip area. The decrease in the total number of the i-th component is equal to the difference between the total number of the i-th component and the total number of the i-1th component; or, in other words, the decrease in the total number of the i-th component is equal to the absolute value of the difference between the total number of the i-th component and the total number of the i-1th component. The decrease in the area of ​​the i-th chip is equal to the difference between the area of ​​the i-th chip and the area of ​​the i-1th chip; or, in other words, the decrease in the area of ​​the i-th chip is equal to the absolute value of the difference between the area of ​​the i-th chip and the area of ​​the i-1th chip.

[0135] Step 360: When the decrease value of the area parameter of the i-th element does not meet the first condition, set i=i+1 and start again from the step of determining the i-th amplification ratio until the decrease value of the i-th area parameter meets the first condition, and determine the i-th amplification ratio as the upper limit of the amplification adjustment range of the clock cycle.

[0136] Optionally, when at least one of the decrease value of the total number of i-th components and the decrease value of the i-th chip area does not meet the first condition, let i=i+1, and start again from the step of determining the i-th amplification ratio until at least one of the decrease value of the total number of i-th components and the decrease value of the i-th chip area meets the first condition, and determine the i-th amplification ratio as the upper limit of the amplification adjustment range of the clock cycle.

[0137] Optionally, when at least one of the decrease value of the total number of i-th components and the decrease value of the i-th chip area does not meet the first condition, let i=i-1, and restart the execution from the above step 320 until at least one of the decrease value of the total number of i-th components and the decrease value of the i-th chip area meets the first condition, and determine that the i-th amplification ratio is the upper limit of the amplification adjustment range of the clock cycle.

[0138] In some embodiments, when at least one of the i-th component total number decrease value and the i-th chip area decrease value meets the first condition, the i-1-th amplification ratio can also be used as the lower limit of the amplification adjustment range of the clock cycle. This embodiment itself does not limit this.

[0139] Optionally, the first condition includes at least one of the following: the i-th area parameter decrease value is less than a first threshold value; the i-th area parameter decrease value is equal to 0. It should be noted that when determining whether the area parameter satisfies the condition, the embodiment of the present application is not limited to the case of being equal to, that is, the first condition may also be that the first area parameter decrease value is less than or equal to the first threshold value. The same applies to the determination of other conditions, which will not be elaborated here.

[0140] Optionally, the area parameter includes at least one of the total number of components and the chip area. In such cases, the threshold corresponding to the i-th decrease in the total number of components and the threshold corresponding to the i-th decrease in the chip area may be the same or different. For example, the first condition may include at least one of the following: the i-th decrease in the total number of components is less than threshold 1; the i-th decrease in the chip area is less than threshold 2; the i-th decrease in the total number of components is equal to zero; or the i-th decrease in the chip area is equal to zero. Threshold 1 and Threshold 2 may be the same or different.

[0141] Optionally, when determining the amplification adjustment interval for a clock cycle only considers the total number of components, the first condition includes at least one of the following: the i-th decrease in the total number of components is less than a threshold value 1; the i-th decrease in the total number of components is equal to 0. When determining the amplification adjustment interval for a clock cycle only considers the chip area, the first condition includes at least one of the following: the i-th decrease in the chip area is less than a threshold value 2; the i-th decrease in the chip area is equal to 0. When determining the amplification adjustment interval for a clock cycle considers both the total number of components and the chip area, the first condition includes at least one of the following: the i-th decrease in the total number of components is less than a threshold value 1; the i-th decrease in the chip area is less than a threshold value 2; the i-th decrease in the total number of components is equal to 0; the i-th decrease in the chip area is equal to 0.

[0142] Alternatively, if the i-th component total number decrease value does not satisfy the first condition, the step of determining the i-th amplification ratio is set to i+1, and the process is restarted from the step of determining the i-th amplification ratio until the i-th component total number decrease value satisfies the first condition, and the i-th amplification ratio is determined as the upper limit of the amplification adjustment range of the clock cycle. Alternatively, if the i-th chip area decrease value does not satisfy the first condition, the step of determining the i-th amplification ratio is set to i+1, and the process is restarted from the step of determining the i-th amplification ratio until the i-th chip area decrease value satisfies the first condition, and the i-th amplification ratio is determined as the upper limit of the amplification adjustment range of the clock cycle. Alternatively, if both the i-th component total number decrease value and the i-th chip area decrease value do not satisfy the first condition, the step of determining the i-th amplification ratio is set to i+1, and the process is restarted from the step of determining the i-th amplification ratio until both the i-th component total number decrease value and the i-th chip area decrease value satisfy the first condition, and the i-th amplification ratio is determined as the upper limit of the amplification adjustment range of the clock cycle.

[0143] The first threshold may be set by a developer, or by a user, or based on expert experience, for example, 5%×the original area parameter.

[0144] In summary, the method provided by the embodiment of the present application obtains a clock cycle amplification adjustment range that meets the conditions by executing a synthesis process based on the original timing constraints and the hardware description file. Compared with the amplification adjustment range directly set based on experience, since in the process of determining the amplification adjustment range, a complete synthesis process is directly executed according to the amplified timing constraints to obtain at least one of the total number of components and the chip area after synthesis, it is determined whether it is supported to continue to amplify the clock cycle to reduce at least one of the total number of components and the chip area. In this way, an amplification adjustment range that can achieve the best result can be determined as much as possible. In addition, in this process, the logic synthesis process used is the first synthesis process, that is, the synthesis process that includes the optimization process. Due to the lack of physical information in this optimization process, at least one of the total number of components and the chip area obtained based on the first synthesis process will be larger than that of the second synthesis process that does not perform the optimization process. However, precisely because of this feature, the amplification adjustment range obtained based on the first synthesis process can be larger, ensuring that it can include the amplification adjustment range that can achieve the best result as much as possible.

[0145] 2. Determination of the optimal clock period.

[0146] Based on Figure 3 In an optional embodiment, as Figure 5 As shown, the above step 222 can be implemented as steps 410 to 460.

[0147] Step 410: Determine the first clock cycle based on the lower limit of the amplification adjustment range of the clock cycle.

[0148] Optionally, the amplification adjustment interval of the clock cycle is a value interval of the clock cycle; the lower limit of the amplification adjustment interval of the clock cycle is determined to be the first clock cycle, that is, the first clock cycle is the lower limit of the amplification adjustment interval of the clock cycle. Alternatively, the amplification adjustment interval of the clock cycle is an amplification ratio interval corresponding to the clock cycle; based on the lower limit of the amplification adjustment interval of the clock cycle, a minimum amplification ratio is determined, and based on the minimum amplification ratio and the original clock cycle, the first clock cycle is determined.

[0149] Step 420: Determine a first enlarged timing constraint based on the first clock cycle and the original timing constraint; and obtain a first area parameter based on the first enlarged timing constraint.

[0150] Optionally, a first enlarged timing constraint is determined based on the first clock cycle and the original timing constraint; and at least one of a first total number of components and a first chip area is obtained based on the first enlarged timing constraint.

[0151] Optionally, based on the first clock cycle and the original timing constraint, the first amplified timing constraint may be determined by referring to step 223 or step 330 above, which will not be described in detail here.

[0152] In some embodiments, obtaining a first area parameter based on the first amplified timing constraint includes: executing a second logic synthesis process and a layout process on the hardware description file based on the first amplified timing constraint to obtain the first area parameter; or executing a second synthesis process on the hardware description file based on the first amplified timing constraint to obtain the first area parameter; or executing a second synthesis process, a layout process, and a routing process on the hardware description file based on the first amplified timing constraint to obtain the first area parameter; or executing a second logic synthesis process and a physical synthesis process on the hardware description file based on the first amplified timing constraint to obtain the first area parameter.

[0153] In some embodiments, based on the first enlarged timing constraint, at least one of the first total number of components and the first chip area is obtained, including: based on the first enlarged timing constraint, executing a second logic synthesis process and a layout process on the hardware description file to obtain at least one of the first total number of components and the first chip area; or, based on the first enlarged timing constraint, executing a second synthesis process on the hardware description file to obtain at least one of the first total number of components and the first chip area; or, based on the first enlarged timing constraint, executing a second synthesis process, a layout process and a routing process on the hardware description file to obtain at least one of the first total number of components and the first chip area; or, based on the first enlarged timing constraint, executing a second logic synthesis process and a physical synthesis process on the hardware description file to obtain at least one of the first total number of components and the first chip area.

[0154] In some embodiments, the second logic synthesis flow does not include an optimization process. The optimization process is used to adjust the estimated total number of components and estimated chip area corresponding to the logic netlist based on timing constraints. Optionally, the physical synthesis flow includes an optimization process. Each process in the physical synthesis flow, including the optimization process, may use the first amplified timing constraints or the original timing constraints, which is not limited in this embodiment of the present application.

[0155] Step 430: Determine the j-th clock cycle based on the amplification adjustment interval of the clock cycle, where j is a positive integer greater than 1.

[0156] Optionally, the initial value of j is 2.

[0157] In some embodiments, the amplification adjustment interval of the clock cycle is a value interval of the clock cycle; the jth clock cycle is determined based on the amplification adjustment interval of the clock cycle. Alternatively, the amplification adjustment interval of the clock cycle is an amplification ratio interval corresponding to the clock cycle; the jth amplification ratio is determined based on the amplification adjustment interval of the clock cycle, and the jth clock cycle is determined based on the jth amplification ratio and the original clock cycle.

[0158] Optionally, when j is greater than 1, the j-th magnification ratio is greater than the j-1-th magnification ratio.

[0159] In some embodiments, when j is greater than 1, the j-th clock cycle is determined based on at least one of the 1st clock cycle and the j-1th clock cycle.

[0160] For example, the n clock cycles determined in n cycles satisfy an arithmetic progression, where n is a positive integer. That is, when j is greater than 1, the jth clock cycle = the j-1th clock cycle + d; or, in other words, the jth clock cycle = the 1st clock cycle + (j-1) × d. d is the tolerance, and is typically a positive number. This tolerance can be set by the user or the developer.

[0161] For example, for the n clock cycles determined in n rounds of loops, a geometric progression is satisfied. That is, when j is greater than 2, the jth clock cycle = the j-1th clock cycle × q; or, the jth clock cycle = the 1st clock cycle × q j-1 Wherein, q is a common ratio, and generally speaking, q is a positive number greater than 1. The common ratio can be set by the user or by the developer.

[0162] For example, the n clock cycles determined in n rounds of loops satisfy the exponential growth law. That is, when j is greater than 1, the jth clock cycle = the 1st clock cycle × e k×(j-1) , where e is the base of the natural logarithm and k is the growth constant. k can be set by the user or by the developer.

[0163] It should be noted that the n clock cycles determined in n cycles can also be set based on other growth laws, such as logarithmic growth law, power law growth law, etc. In other words, the embodiments of the present application do not limit the setting method of the j-th clock cycle. Developers or users can use the corresponding clock cycle determination formula based on actual needs. The embodiments of the present application will not list the clock cycle determination formula one by one, but the scope of protection of the embodiments themselves is not limited to this.

[0164] Step 440: Determine the jth amplified timing constraint based on the jth clock cycle and the original timing constraint; and obtain the jth area parameter based on the jth amplified timing constraint.

[0165] Optionally, based on the jth clock cycle and the original timing constraint, a jth amplified timing constraint is determined; and based on the jth amplified timing constraint, at least one of a jth total number of components and a jth chip area is obtained.

[0166] Optionally, based on the j-th clock cycle and the original timing constraint, the j-th amplified timing constraint may be determined by referring to the above step 223 or step 330 , which will not be repeated here.

[0167] In some embodiments, based on the j-th amplification timing constraint, obtaining the j-th area parameter includes: based on the j-th amplification timing constraint, executing a second logic synthesis process and a layout process on the hardware description file to obtain the j-th area parameter; or, based on the j-th amplification timing constraint, executing a second logic synthesis process on the hardware description file to obtain the j-th area parameter; or, based on the j-th amplification timing constraint, executing a second synthesis process, a layout process, and a routing process on the hardware description file to obtain the j-th area parameter; or, based on the j-th amplification timing constraint, executing a second logic synthesis process and a physical synthesis process on the hardware description file to obtain the j-th area parameter.

[0168] In some embodiments, based on the j-th amplification timing constraint, at least one of the j-th total number of components and the j-th chip area is obtained, including: based on the j-th amplification timing constraint, executing a second logic synthesis process and a layout process on the hardware description file to obtain at least one of the j-th total number of components and the j-th chip area; or, based on the j-th amplification timing constraint, executing a second logic synthesis process on the hardware description file to obtain at least one of the j-th total number of components and the j-th chip area; or, based on the j-th amplification timing constraint, executing a second synthesis process, a layout process and a routing process on the hardware description file to obtain at least one of the j-th total number of components and the j-th chip area; or, based on the j-th amplification timing constraint, executing a second logic synthesis process and a physical synthesis process on the hardware description file to obtain at least one of the j-th total number of components and the j-th chip area.

[0169] In some embodiments, the second logic synthesis flow does not include an optimization process. The optimization process is used to adjust the estimated total number of components and estimated chip area corresponding to the logic netlist based on timing constraints. Optionally, the physical synthesis flow includes an optimization process. Each process in the physical synthesis flow, including the optimization process, may use the j-th amplified timing constraint or the original timing constraint, which is not limited in this embodiment of the present application.

[0170] Step 450: Determine a jth area parameter decrease value based on at least one of the first area parameter and the jth area parameter.

[0171] Optionally, at least one of a jth component total number reduction value and a jth area reduction value is determined based on at least one of the first component total number, the first chip area, the jth component total number, and the jth chip area.

[0172] Optionally, the decrease value of the total number of j-th elements is determined based on at least one of the total number of the 1st elements and the total number of the j-th elements; or, the decrease value of the j-th chip area is determined based on at least one of the 1st chip area and the j-th chip area; or, the decrease value of the total number of j-th elements is determined based on at least one of the total number of the 1st elements and the total number of the j-th elements, and the decrease value of the j-th chip area is determined based on at least one of the 1st chip area and the j-th chip area.

[0173] In some embodiments, step 450 can be implemented as follows: when j is 2, based on the first area parameter and the second area parameter, determine the second area parameter decrease value; when j is greater than 2, based on the jth area parameter and the j-1th area parameter, determine the jth area parameter; wherein the j-1th area parameter is determined based on the j-1th amplification timing constraint.

[0174] Optionally, when j is 2, a reduction value for the second total number of components is determined based on the first total number of components and the second total number of components; or, a reduction value for the second chip area is determined based on the first chip area and the second chip area; or, a reduction value for the second total number of components is determined based on the first total number of components and the second total number of components, and a reduction value for the second chip area is determined based on the first chip area and the second chip area. When j is greater than 2, a reduction value for the jth total number of components is determined based on the jth total number of components and the j-1th total number of components; or, a reduction value for the jth chip area is determined based on the jth chip area and the j-1th chip area; or, a reduction value for the jth total number of components is determined based on the jth total number of components and the j-1th total number of components, and a reduction value for the jth chip area is determined based on the j-1th chip area. The j-1th total number of components is determined based on the j-1th amplification timing constraint; and the j-1th chip area is determined based on the j-1th amplification timing constraint.

[0175] The method for determining at least one of the j-1th total number of components and the j-1th chip area based on the j-1th amplification timing constraint may refer to the above step 440 and will not be repeated here.

[0176] The calculation of the second component total number reduction value, the second chip area reduction value, the j-th component total number reduction value, and the j-th chip area reduction value may refer to the above step 350 and will not be repeated here.

[0177] Step 460: When the j-th area parameter decrease value does not meet the second condition, set j=j+1, and start again from the step of determining the j-th clock cycle based on the amplification adjustment interval of the clock cycle until the j-th area parameter decrease value meets the second condition, and determine the j-th clock cycle as the optimal clock cycle.

[0178] Optionally, when at least one of the j-th component total number decrease value and the j-th chip area decrease value does not meet the second condition, let j=j+1, and start again from the step of determining the j-th clock cycle based on the clock cycle amplification adjustment interval until at least one of the j-th component total number decrease value and the j-th chip area decrease value meets the second condition, and determine the j-th clock cycle as the optimal clock cycle.

[0179] Optionally, when at least one of the j-th component total number decrease value and the j-th chip area decrease value does not meet the second condition, set j=j+1, and restart execution from step 430 until at least one of the j-th component total number decrease value and the j-th chip area decrease value meets the second condition, and determine that the j-th clock cycle is the optimal clock cycle.

[0180] In some embodiments, when at least one of the jth component total number reduction value and the jth chip area reduction value meets the first condition, the j-1th clock cycle can also be used as the optimal clock cycle, which is not limited in this embodiment.

[0181] Optionally, the second condition includes at least one of the following: the j-th area parameter decrease value is less than a second threshold; the j-th area parameter decrease value is equal to 0.

[0182] Optionally, the area parameter includes at least one of the total number of components and the chip area. When the area parameter includes both the total number of components and the chip area, the threshold corresponding to the jth decrease in the total number of components and the threshold corresponding to the jth decrease in the chip area may be the same or different. For example, the second condition includes at least one of the following: the jth decrease in the total number of components is less than threshold 1; the jth decrease in the chip area is less than threshold 2; the jth decrease in the total number of components is equal to 0; or the jth decrease in the chip area is equal to 0. Threshold 1 and Threshold 2 may be the same or different. It should be noted that the first threshold, second threshold, threshold 1, and threshold 2 shown in the embodiments of this application are merely illustrative; different values ​​may be used for the same description in different embodiments. Specifically, in "1. Determining the Amplification Adjustment Interval" and "2. Determining the Optimal Clock Period," Threshold 1 is used as the threshold for both the i-th and j-th decreases in the total number of components. However, the corresponding values ​​for the i-th and j-th decreases in the total number of components may be the same or different. The same applies to Threshold 2.

[0183] Optionally, when determining the optimal clock period only considers the total number of components, the second condition includes at least one of the following: the jth decrease in the total number of components is less than a threshold value of 1; the jth decrease in the total number of components is equal to 0. When determining the optimal clock period only considers chip area, the second condition includes at least one of the following: the jth decrease in chip area is less than a threshold value of 2; the jth decrease in chip area is equal to 0. When determining the optimal clock period considers both the total number of components and chip area, the second condition includes at least one of the following: the jth decrease in the total number of components is less than a threshold value of 1; the jth decrease in chip area is less than a threshold value of 2; the jth decrease in the total number of components is equal to 0; the jth decrease in chip area is equal to 0.

[0184] Alternatively, if the j-th component total number decrease value does not satisfy the second condition, j is set to j+1, and the process is restarted from the step of determining the j-th clock period based on the amplification adjustment interval of the clock period until the j-th component total number decrease value satisfies the second condition, and the j-th amplification ratio is determined as the upper limit of the amplification adjustment interval of the clock period. Alternatively, if the j-th chip area decrease value does not satisfy the second condition, j is set to j+1, and the process is restarted from the step of determining the j-th clock period based on the amplification adjustment interval of the clock period until the j-th chip area decrease value satisfies the second condition, and the j-th amplification ratio is determined as the upper limit of the amplification adjustment interval of the clock period. Alternatively, if the j-th component total number decrease value and the j-th chip area decrease value do not satisfy the second condition, j is set to j+1, and the process is restarted from the step of determining the j-th clock period based on the amplification adjustment interval of the clock period until the j-th component total number decrease value and the j-th chip area decrease value satisfy the second condition, and the j-th amplification ratio is determined as the upper limit of the amplification adjustment interval of the clock period.

[0185] In addition, it should be noted that during the execution of the above-mentioned step 430, it should be ensured that the j-th clock cycle is less than the upper limit of the adjustment interval of the clock cycle. That is, when the j-th clock cycle exceeds the adjustment interval of the clock cycle and the second condition is still not met, the judgment of the optimal timing constraint should be terminated and an error message should be displayed.

[0186] In summary, the method provided in the embodiment of the present application shows a method for determining the optimal clock cycle. The optimal clock cycle refers to the clock cycle that can make the physical netlist obtained after executing the synthesis process an optimal result. In the process of determining the optimal clock cycle, the clock cycle is gradually increased starting from the lower limit of the amplified adjustment range. The larger the clock cycle, the looser the timing constraint. At this time, the total number of components and chip area will be smaller in the logic synthesis process. However, since there is a physical synthesis process later, the physical synthesis process is based on the original timing constraint. The original timing constraint is a tight timing constraint. The tighter the timing constraint, the more total components and chip area will be obtained. That is, in the process of determining the optimal clock cycle, it is a process of first loosening and then releasing. In this process, there will be an optimal result that can meet the timing constraint and achieve a smaller total number of components and chip area. The clock cycle corresponding to this optimal result is the optimal clock cycle. In the process of determining the optimal clock cycle, the synthesis process executed is consistent with the final synthesis process, which can ensure that the optimal clock cycle is applied to the above Figure 3 The method shown in its optional embodiment can also achieve the best result, ensuring the reliability of the method.

[0187] 3. Improvement of logic synthesis process.

[0188] In some embodiments, the above-mentioned step 230 includes: executing a second logic synthesis process on the hardware description file based on the amplified timing constraints to obtain a logic netlist; wherein the second logic synthesis process does not include an optimization process, and the optimization process is used to adjust the estimated area parameters corresponding to the logic netlist based on the timing constraints.

[0189] Optionally, the optimization process is used to adjust at least one of an estimated total number of components and an estimated chip area corresponding to the logic netlist based on the timing constraint.

[0190] Optionally, the optimization process adjusts at least one of the estimated total number of components and the estimated chip area corresponding to the logic netlist based on timing constraints. Generally speaking, relaxed timing constraints (e.g., a longer clock period) make it easier to meet timing constraints during logic netlist generation. This means that there is no need to add circuit elements (e.g., registers) between circuit modules to ensure that each circuit module meets timing constraints. In other words, generally speaking, relaxed timing constraints can generate a logic netlist with a smaller total number of components and a smaller chip area. However, for the optimization process in the logic synthesis process, since it cannot know the physical information corresponding to the chip circuit, it can only optimize based on the logical structure of the existing chip circuit. Therefore, during the optimization, in order to ensure that the subsequent physical synthesis process can more easily meet the timing constraints, a relatively loose optimization policy will be adopted to ensure that each circuit module or timing path in the chip circuit can have a larger timing margin, which will correspondingly lead to an increase in the total number of components and at least one of the chip area. However, in fact, in the physical synthesis process, there is a more accurate optimization process (because the optimization process can obtain physical information), so the optimization process that causes an unreasonable increase in at least one of the total number of components and the chip area can be omitted in the logic synthesis stage, that is, the second logic synthesis process is executed here.

[0191] It should be noted that the above “1. Determination of the amplification adjustment interval” and “2. Determination of the optimal clock period” can be implemented as independent embodiments or as a combined embodiment.

[0192] The embodiment of the present application relaxes the problem of unreasonable increase of circuit elements and area caused by unreasonable over-optimization of logic circuits during synthesis by increasing the clock cycle. The range of clock cycle magnification is found through iteration. Then, by adjusting the steps of the synthesis process, the clock cycle is magnified in the early stage of synthesis, and the clock cycle is retracted in the later stage, and it is iterated within the adjustable range of the clock cycle. While meeting the timing results, the result of minimizing the number of circuit elements and area is iterated, thereby achieving the result of optimizing the chip area without affecting the final timing results. For example, Figure 6 and Figure 7 shown.

[0193] For example, it is necessary to first determine the amplification adjustment range of the clock cycle, such as Figure 6 shown.

[0194] Step 1: Execute the first synthesis process to obtain the total number of original components and the original chip area.

[0195] For example, the first comprehensive process is as follows Figure 8 As shown, the first synthesis flow includes a first logic synthesis flow 10 and a physical synthesis flow 20. Throughout the first synthesis flow, original timing constraints 30 are used.

[0196] Specifically, the first logic synthesis process 10 includes a refinement process 11, a general mapping process 12, a mapping process 13, and a logic optimization process 14. Each process corresponds to a different instruction. It should be noted that the following instructions for each process and the descriptions of each instruction are for illustrative purposes only. For different synthesis tools, the instructions used and the functions corresponding to the instructions may vary to some extent, but the scope of protection of this embodiment is not limited thereto.

[0197] For example, the elaborate directive in elaboration flow 11 is the elaborate directive, which creates a design hierarchy consisting of a top-level design and its referenced subdesigns from Verilog or System Verilog modules or VHDL entities / architectures. If no top-level design is specified, all modules not instantiated by other modules are elaborated as top-level modules along with their subdesigns. This directive converts each module / architecture into a design represented in a structured netlist. It also performs semantic checking, sequential register (flip-flop / latch) inference, and high-level HDL optimizations. Instances of undefined modules or entities are marked as unresolved, and the corresponding modules / entities are reported as black boxes.

[0198] The instruction for the generic mapping flow 12 is syn_generic. This instruction takes a detailed and fully constrained design as input and synthesizes it into a netlist of generic gates by performing high-level RTL (Register Transfer Level) and datapath optimization.

[0199] The command for mapping step 13 is syn_map. This command maps the design from generic gates to the process library while optimizing for optimal performance, power, and area. Multiple implementations of a given logic cone are evaluated, and the one that meets timing constraints while minimizing area and power is selected. After the initial mapping phase, further refinement is achieved by progressively optimizing the netlist to restore area and power while maintaining timing.

[0200] The logic optimization flow14 is executed using the syn_opt directive. This directive takes a mapped design as input and incrementally optimizes timing, area, and power. If you do not specify spatial or physical flow options, syn_opt performs pure logic optimizations, even when invoked on a design database generated by physically-aware mapping.

[0201] Specifically, the physical synthesis flow 20 includes placement and physical optimization flows 21, corresponding to the command place&opt. This executes a pre-CTS (Clock Tree Synthesis) flow with placement and pre-clock tree synthesis optimizations. Using place_opt_design, users can perform both placement and pre-CTS optimizations with a single command.

[0202] Step 2: Set the initial amplification ratio a% of the clock cycle and the total number of components decrease threshold.

[0203] It should be noted that the judgment here is made based on the decrease in the total number of components as an example, but it can also be made based on at least one of the decrease in the total number of components and the decrease in the chip area. In this case, it is necessary to set at least one of the decrease threshold of the total number of components and the decrease threshold of the chip area.

[0204] Step 3: Execute the second integrated process.

[0205] Among them, the second comprehensive process is as follows Figure 9 As shown, the second synthesis process is similar to the first synthesis process, and will not be described in detail here. The difference between the second synthesis process and the first synthesis process is that the second synthesis process uses the amplified timing constraint 31 with amplified clock period.

[0206] After executing the second synthesis process, the total number of components after the clock cycle is amplified is obtained.

[0207] Step 4: Determine the reduction value of the total number of components.

[0208] Based on the original component count and the component count after the amplified clock period, a component count reduction value is determined.

[0209] Step 5: Determine whether the total number of components reduced is higher than a threshold.

[0210] Determine whether the total number of components decreased by a value greater than the total number of components decreased threshold. If the total number of components decreased by a value greater than the total number of components decreased threshold, execute step 6; if the total number of components decreased by a value less than the total number of components decreased threshold, jump to step 7.

[0211] Step 6: Increase the clock cycle amplification ratio.

[0212] The method for determining the clock cycle amplification ratio may refer to the above step 320 and will not be repeated here.

[0213] Step 7: Determine the amplification adjustment range of the clock cycle.

[0214] When the total number of components decreases by no more than the total number of components decrease threshold, the current clock cycle is determined as the upper limit of the amplification adjustment range of the clock cycle, thereby obtaining the amplification adjustment range.

[0215] After the amplification adjustment range is determined, the optimal clock period that can achieve the best result can be determined from the amplification adjustment range.

[0216] Step 1: determining an initial clock period based on a lower limit of the amplification adjustment range.

[0217] The initial clock period is determined as the lower limit of the amplification adjustment range.

[0218] Step 2, the third comprehensive process.

[0219] The third comprehensive process is as follows Figure 10 The third synthesis flow includes a second logic synthesis flow 40 and a physical synthesis flow 20. Compared to the first logic synthesis flow 10, the second logic synthesis flow 40 eliminates the logic optimization flow, thus avoiding the unreasonable increase in the total number of components and chip area caused by the logic optimization flow. The physical synthesis flow 20 included in the third synthesis flow uses the original timing constraints and the logic net reports obtained from the second synthesis flow 40 to perform layout and physical optimization.

[0220] Step 3: Determine whether the timing constraints are met.

[0221] After executing the third synthesis process, determine whether the generated physical netlist meets the timing constraints. If not, jump to step 7; if yes, continue to step 4.

[0222] Step 4: Determine whether the total number of components is reduced.

[0223] Determine whether the total number of components in the physical netlist generated by the third synthesis process is reduced compared to the physical netlist generated after the last execution of the third synthesis process. If reduced, continue to step 5; if not, jump to step 7.

[0224] Step 5: Zoom in on the clock period.

[0225] Continue to amplify the clock cycle. For details, please refer to the above step 430, which will not be repeated here.

[0226] Step 6: Determine whether the amplified clock period is still within the amplification adjustment range.

[0227] Determine whether the amplified clock period is still within the amplification adjustment range. If not, execute step 7; if still within the amplification adjustment range, jump to step 2.

[0228] Step 7, end.

[0229] After obtaining the optimal clock cycle, the third synthesis process is executed to obtain the best result.

[0230] Please refer to Figure 11 , which shows a block diagram of the structure of a comprehensive device for optimizing chip area provided by an exemplary embodiment of the present application. The device has the function of implementing the above-mentioned comprehensive method example for optimizing chip area, and the function can be implemented by hardware or by hardware executing corresponding software. The device can be the computer device described above, or it can be set in a computer device. Figure 11 As shown, the apparatus may include: an acquisition module 510 , an amplification module 520 , a logic synthesis module 530 , and a physical synthesis module 540 .

[0231] The acquisition module 510 is used to acquire original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of the chip circuits.

[0232] The amplification module 520 is configured to amplify the clock period in the original timing constraint to obtain an amplified timing constraint.

[0233] The logic synthesis module 530 is used to execute a logic synthesis process on the hardware description file based on the amplified timing constraint to obtain a logic netlist, where the logic netlist is used to indicate the logic structure of the chip circuit.

[0234] The physical synthesis module 540 is used to execute the layout process based on the logical netlist and the original timing constraints to obtain a physical netlist, which is used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

[0235] In some embodiments, the amplification module 520 includes a determination submodule and an amplification submodule.

[0236] The determination submodule is configured to determine an amplification adjustment interval of the clock cycle in the original timing constraint.

[0237] The determination submodule is further configured to determine an optimal clock cycle from the amplification adjustment interval of the clock cycle, wherein the optimal clock cycle is a clock cycle that makes the area parameter of the generated logical netlist or the physical netlist smaller than the target area parameter.

[0238] The amplification submodule is used to obtain the amplification timing constraint based on the optimal clock period.

[0239] In some embodiments, the determination submodule is further used to determine the original area parameter based on the original timing constraint; determine the i-th amplification ratio, where i is a positive integer; based on the i-th amplification ratio, amplify the clock cycle in the original timing constraint to obtain the i-th amplified timing constraint; determine the i-th area parameter based on the i-th amplified timing constraint; determine the i-th area parameter decrease value based on the original area parameter and at least one of the i-th area parameter; if the i-th area parameter decrease value does not meet the first condition, set i=i+1, and restart the step of determining the i-th amplification ratio until the i-th area parameter decrease value meets the first condition, and determine the i-th amplification ratio as the upper limit of the amplification adjustment range of the clock cycle.

[0240] In some embodiments, the determination submodule is further used to determine the first area parameter decrease value based on the original area parameter and the first area parameter when i is 1; and to determine the i-th area parameter decrease value based on the i-th area parameter and the i-1-th area parameter when i is greater than 1; wherein the i-1-th area parameter is determined based on the i-1-th amplification timing constraint corresponding to the i-1-th amplification ratio.

[0241] In some embodiments, the determination submodule is further configured to execute a first logic synthesis process and a physical synthesis process on the hardware description file based on the original timing constraints to obtain the original area parameter.

[0242] In some embodiments, the determination submodule is further configured to execute the first logic synthesis process and the physical synthesis process based on the i-th amplification timing constraint to obtain the i-th area parameter.

[0243] In some embodiments, the first logic synthesis flow includes an optimization flow for adjusting an estimated area parameter corresponding to the logic netlist based on timing constraints.

[0244] In some embodiments, the acquisition module 510 is further configured to acquire a first amplification ratio; and determine a lower limit of the amplification adjustment interval of the clock cycle based on the first amplification ratio.

[0245] In some embodiments, the first condition includes at least one of the following: the i-th area parameter decrease value is less than a first threshold; the i-th area parameter decrease value is equal to 0.

[0246] In some embodiments, the determination submodule is further used to determine the first clock cycle based on the lower limit of the amplification adjustment interval of the clock cycle; determine the first amplification timing constraint based on the first clock cycle and the original timing constraint; and obtain the first area parameter based on the first amplification timing constraint; determine the jth clock cycle based on the amplification adjustment interval of the clock cycle, where j is a positive integer greater than 1; determine the jth amplification timing constraint based on the jth clock cycle and the original timing constraint; and obtain the jth area parameter based on the jth amplification timing constraint; determine the jth area parameter decrease value based on at least one of the first area parameter and the jth area parameter; if the jth area parameter decrease value does not meet the second condition, set j=j+1, and re-start from the step of determining the jth clock cycle based on the amplification adjustment interval of the clock cycle until the jth area parameter decrease value meets the second condition, and determine the jth clock cycle as the optimal clock cycle.

[0247] In some embodiments, the determination submodule is further configured to execute a second logic synthesis process and a physical synthesis process on the hardware description file based on the first amplification timing constraint to obtain the first area parameter.

[0248] In some embodiments, the determination submodule is further configured to execute the second logic synthesis process and the physical synthesis process on the hardware description file based on the j-th amplification timing constraint to obtain the j-th area parameter.

[0249] In some embodiments, the determination submodule is further used to determine the second area parameter decrease value based on the first area parameter and the second area parameter when j is 2; and to determine the jth area parameter decrease value based on the jth area parameter and the j-1th area parameter when j is greater than 2; wherein the j-1th area parameter is determined based on the j-1th amplification timing constraint.

[0250] In some embodiments, the second condition includes at least one of the following: the j-th area parameter decrease value is less than a second threshold; the j-th area parameter decrease value is equal to 0.

[0251] In some embodiments, the logic synthesis module 530 is further used to execute a second logic synthesis process on the hardware description file based on the amplified timing constraints to obtain the logic netlist; wherein the second logic synthesis process does not include an optimization process, and the optimization process is used to adjust the estimated area parameters corresponding to the logic netlist based on the timing constraints.

[0252] It should be noted that the above embodiments provide devices that implement their functions using only the division of the above functional modules as examples. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the devices and method embodiments provided in the above embodiments are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0253] Figure 12 A schematic structural diagram of a computer device provided by an exemplary embodiment of the present application is shown.

[0254] The computer device 800 includes a central processing unit (CPU) 801, a system memory 804 including a random access memory (RAM) 802 and a read-only memory (ROM) 803, and a system bus 805 connecting the system memory 804 and the CPU 801. The computer device 800 also includes a basic input / output system (I / O system) 806 that facilitates information transmission between various components within the computer device, and a mass storage device 807 for storing an operating system 813, application programs 814, and other program modules 815.

[0255] The basic input / output system 806 includes a display 808 for displaying information and an input device 809 such as a mouse and keyboard for user input. The display 808 and the input device 809 are both connected to the central processing unit 801 via an input / output controller 810 connected to the system bus 805. The basic input / output system 806 may also include an input / output controller 810 for receiving and processing input from a variety of other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 810 also provides output to a display screen, printer, or other types of output devices.

[0256] The mass storage device 807 is connected to the central processing unit 801 via a mass storage controller (not shown) connected to the system bus 805. The mass storage device 807 and its associated computer-readable storage medium provide non-volatile storage for the computer device 800. In other words, the mass storage device 807 may include a computer-readable storage medium (not shown) such as a hard disk or a compact disc read-only memory (CD-ROM) drive.

[0257] Without loss of generality, the computer-readable storage medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable storage instructions, data structures, program modules, or other data. Computer storage media include RAM, ROM, Erasable Programmable Read-Only Memory (EPROM), Electronically Erasable Programmable Read-Only Memory (EEPROM), flash memory or other solid-state storage technologies, CD-ROM, Digital Versatile Disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, disk storage or other magnetic storage devices. Of course, those skilled in the art will appreciate that computer storage media are not limited to the aforementioned types. The aforementioned system memory 804 and mass storage device 807 may be collectively referred to as memory.

[0258] The memory stores one or more programs, and the one or more programs are configured to be executed by one or more central processing units 801. The one or more programs contain instructions for implementing the above-mentioned method embodiments. The central processing unit 801 executes the one or more programs to implement the methods provided by the above-mentioned method embodiments.

[0259] According to various embodiments of the present application, the computer device 800 may also be connected to a remote computer device on a network, such as the Internet, for operation. Specifically, the computer device 800 may be connected to a network 812 via a network interface unit 811 connected to the system bus 805. Alternatively, the network interface unit 811 may be used to connect to other types of networks or remote computer device systems (not shown).

[0260] The memory also includes one or more programs, which are stored in the memory and include steps executed by a computer device in the method provided in the embodiment of the present application.

[0261] In an exemplary embodiment, the present application provides a chip comprising at least one of a programmable logic circuit and program instructions, which is used to implement the comprehensive method for optimizing chip area provided by the above method embodiment when the chip is running on a computer device.

[0262] In an exemplary embodiment, a non-transitory computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is executed by a processor, the computer program implements the above-mentioned integrated method for optimizing chip area.

[0263] In an exemplary embodiment, a computer program product is further provided. When the computer program product is executed by a processor, it is used to implement the above-mentioned integrated method for optimizing chip area.

[0264] It should be understood that the "multiple" mentioned in this article refers to two or more. The character " / " generally indicates that the objects associated with each other are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution order between the steps. In some other embodiments, the above steps may also be executed in a non-numbered order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the opposite order to that shown in the figure. This embodiment of the application is not limited to this.

[0265] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A comprehensive method for optimizing chip area, characterized in that: The method comprises: Obtaining original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of chip circuits; Amplifying the clock period in the original timing constraint to obtain an amplified timing constraint; Based on the amplified timing constraints, executing a logic synthesis process on the hardware description file to obtain a logic netlist, wherein the logic netlist is used to indicate a logic structure of the chip circuit; Based on the logic netlist and the original timing constraints, a physical synthesis process is executed to obtain a physical netlist, which is used to indicate the logic structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

2. The method according to claim 1, characterized in that The step of amplifying the clock period in the original timing constraint to obtain the amplified timing constraint includes: Determining an amplification adjustment interval of a clock cycle in the original timing constraint; Determining an optimal clock cycle from the amplification adjustment interval of the clock cycle, the optimal clock cycle being a clock cycle that makes an area parameter of the generated logical netlist or the generated physical netlist smaller than a target area parameter; The amplification timing constraint is obtained based on the optimal clock period.

3. The method according to claim 2, characterized in that The determining of the amplification adjustment interval of the clock cycle in the original timing constraint includes: Determining original area parameters based on the original timing constraints; Determine the i-th magnification ratio, where i is a positive integer; Amplifying the clock period in the original timing constraint based on the i-th amplification ratio to obtain an i-th amplified timing constraint; determining an i-th area parameter based on the i-th amplification timing constraint; determining an i-th area parameter decrease value based on at least one of the original area parameter and the i-th area parameter; When the i-th area parameter decrease value does not meet the first condition, let i=i+1, and start again from the step of determining the i-th amplification ratio until the i-th area parameter decrease value meets the first condition, and determine the i-th amplification ratio as the upper limit of the amplification adjustment range of the clock cycle.

4. The method according to claim 3, characterized in that The determining, based on at least one of the original area parameter and the i-th area parameter, a decrease value of the i-th area parameter comprises: When i is 1, determining a first area parameter reduction value based on the original area parameter and the first area parameter; When i is greater than 1, determining a decrease value of the i-th area parameter based on the i-th area parameter and the i-1-th area parameter; The (i-1)th area parameter is determined based on the (i-1)th amplification timing constraint corresponding to the (i-1)th amplification ratio.

5. The method according to claim 3, characterized in that The determining of the original area parameter based on the original timing constraint includes: Based on the original timing constraints, executing a first logic synthesis process and the physical synthesis process on the hardware description file to obtain the original area parameter; The determining the i-th area parameter based on the i-th amplification timing constraint includes: Based on the i-th amplification timing constraint, the first logic synthesis process and the physical synthesis process are executed to obtain the i-th area parameter.

6. The method according to claim 5, characterized in that The first logic synthesis process includes an optimization process, and the optimization process is used to adjust the estimated area parameter corresponding to the logic netlist based on timing constraints.

7. The method according to claim 3, characterized in that The method further comprises: Acquiring a first amplification ratio; and determining a lower limit of the amplification adjustment interval of the clock cycle based on the first amplification ratio.

8. The method according to claim 3, characterized in that The first condition includes at least one of the following: the i-th area parameter decrease value is less than a first threshold; the i-th area parameter decrease value is equal to 0.

9. The method according to any one of claims 2 to 8, characterized in that: The determining of the optimal clock cycle from the amplification adjustment interval of the clock cycle includes: determining a first clock cycle based on a lower limit of the amplification adjustment interval of the clock cycle; determining a first amplified timing constraint based on the first clock cycle and the original timing constraint; and obtaining a first area parameter based on the first amplified timing constraint; Determining a j-th clock cycle based on the amplification adjustment interval of the clock cycle, where j is a positive integer greater than 1; determining a jth amplified timing constraint based on the jth clock cycle and the original timing constraint; and obtaining a jth area parameter based on the jth amplified timing constraint; determining a jth area parameter decrease value based on at least one of the first area parameter and the jth area parameter; When the j-th area parameter decrease value does not meet the second condition, set j=j+1, and start again from the step of determining the j-th clock cycle based on the amplification adjustment interval of the clock cycle until the j-th area parameter decrease value meets the second condition, and determine the j-th clock cycle as the optimal clock cycle.

10. The method according to claim 9, characterized in that The obtaining of a first area parameter based on the first amplification timing constraint includes: Based on the first amplification timing constraint, executing a second logic synthesis process and the physical synthesis process on the hardware description file to obtain the first area parameter; Based on the j-th amplification timing constraint, obtaining the j-th area parameter includes: Based on the j-th amplification timing constraint, the second logic synthesis process and the physical synthesis process are executed on the hardware description file to obtain the j-th area parameter.

11. The method according to claim 9, characterized in that Determining a j-th area parameter decrease value based on at least one of the first area parameter and the j-th area parameter includes: When j is 2, determining a second area parameter decrease value based on the first area parameter and the second area parameter; When j is greater than 2, determining a decrease value of the jth area parameter based on the jth area parameter and the j-1th area parameter; The j-1th area parameter is determined based on the j-1th amplification timing constraint.

12. The method according to claim 9, characterized in that The second condition includes at least one of the following: the j-th area parameter decrease value is less than a second threshold; the j-th area parameter decrease value is equal to 0.

13. The method according to any one of claims 1 to 8, characterized in that: The step of performing a logic synthesis process on the hardware description file based on the amplified timing constraint to obtain a logic netlist includes: Based on the amplified timing constraint, executing a second logic synthesis process on the hardware description file to obtain the logic netlist; The second logic synthesis flow does not include an optimization process, and the optimization process is used to adjust the estimated area parameters corresponding to the logic netlist based on timing constraints.

14. A comprehensive device for optimizing chip area, characterized in that: The device comprises: An acquisition module is used to acquire original timing constraints and hardware description files, where the hardware description files are used to describe the functions and structures of chip circuits; an amplification module, configured to amplify the clock period in the original timing constraint to obtain an amplified timing constraint; A logic synthesis module, configured to execute a logic synthesis process on the hardware description file based on the amplified timing constraint to obtain a logic netlist, wherein the logic netlist is used to indicate a logic structure of the chip circuit; A physical synthesis module is used to execute a physical synthesis process based on the logical netlist and the original timing constraints to obtain a physical netlist, wherein the physical netlist is used to indicate the logical structure of the chip circuit and the physical location information of each circuit element in the chip circuit.

15. A computer device, characterized in that: The computer device includes a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the comprehensive method for optimizing chip area according to any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the comprehensive method for optimizing chip area according to any one of claims 1 to 13.

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