Gate drive circuit and display panel

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel, the gate driving circuit comprises N cascaded GOA circuit units, the nth GOA circuit unit comprises a first pull-down control module, the control end of the first pull-down control module is connected with a first pull-down signal end, and the control end of the first pull-down control module is connected with a second pull-down signal end; the output end of the first pull-down control module is respectively connected with the control voltage end, the stage transmission output end and the driving output end of the nth stage GOA circuit unit, and the first pull-down control module is used for discharging the voltage on the control voltage end, the stage transmission output end and the driving output end and maintaining the voltage to a second target voltage; according to the display panel, the problem of unstable Q point potential caused by leakage current is solved, the GOA charging effect is effectively improved, the design of a narrow-frame product is facilitated, and the product competitiveness of the display panel is improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of display drive technology, and in particular relates to a gate drive circuit and a display panel. Background Art

[0002] With the development of TFT-LCD display technology, narrow-border display screens have become the main trend in the development of high-quality display screens due to their simplicity, beauty, and large visible area of ​​the same size. In particular, small-size display screens have higher and higher requirements for narrow borders, and the application of GOA (Gate On Array, array substrate row drive) technology has become more frequent. GOA technology uses the array process of liquid crystal display panels to manufacture gate drive circuits on array substrates to achieve a drive method of scanning the gate row by row, which can save a separate gate drive integrated circuit part, not only reducing the material cost and production cost of display devices, but also reducing the panel border design, which is more in line with the development trend of display panels.

[0003] However, it is found in related technologies that due to the increase in temperature in the GOA area, the leakage in the transistor devices in the driving circuit increases, and the high leakage current at the control voltage end (Q point) in the GOA circuit will cause the gate drive signal (Gout) output waveform to be distorted, causing display abnormalities within the surface and reducing the display effect of the panel. Summary of the invention

[0004] The present application provides a gate drive circuit and a display panel, which solves the problem of unstable Q-point potential caused by leakage current, effectively improves the GOA charging effect and is conducive to the design of narrow-frame products, thereby improving the product competitiveness of the display panel.

[0005] In the first aspect, the present application provides a gate drive circuit, which includes: N cascaded GOA circuit units, the nth-level GOA circuit unit includes a control voltage terminal, a level transmission output terminal and a drive output terminal, and the nth-level GOA circuit unit also includes: a storage capacitor, the first end of the storage capacitor is connected to the control voltage terminal, and the second end of the storage capacitor is connected to the drive output terminal; a pre-charge module, the control end of the pre-charge module is connected to the level transmission output terminal of the ni-th level GOA circuit unit, the first end of the pre-charge module is connected to the drive output terminal of the ni-th level GOA circuit unit, and the second end of the pre-charge module is connected to the control voltage terminal, and is used to pre-charge the voltage on the control voltage terminal through the gate drive signal output by the ni-th level GOA circuit unit; an output module, the control end of the output module is connected to the output end of the pre-charge module, the first end of the output module is connected to the clock signal end, and the first end of the output module is connected to the clock signal end. The second end is connected to the second end of the storage capacitor, and is used to output a gate drive signal under the action of the first target voltage on the control voltage end and the clock signal output by the clock signal end; a level transmission module, the control end of the level transmission module is connected to the control voltage end of the n-th level GOA circuit unit, the first end of the level transmission module is connected to the clock signal end, and the second end of the level transmission module is connected to the pre-charge module of the n+i-th level GOA circuit unit, and is used to output a level transmission signal under the action of the first target voltage on the control voltage end and the clock signal output by the clock signal end; a first pull-down control module, the control end of the first pull-down control module is connected to the first pull-down signal end, and the output end of the first pull-down control module is respectively connected to the control voltage end, the level transmission output end and the driving output end of the n-th level GOA circuit unit, and is used to discharge the voltages on the control voltage end, the level transmission output end and the driving output end, and maintain them to the second target voltage.

[0006] Optionally, the nth-level GOA circuit unit also includes: a second pull-down control module, the control end of the second pull-down control module is connected to the second pull-down signal end, and the output end of the second pull-down control module is respectively connected to the control voltage end, the stage transmission output end and the drive output end of the nth-level GOA circuit unit, for discharging the voltages on the control voltage end, the stage transmission output end and the drive output end, and maintaining them to the second target voltage.

[0007] Optionally, the pre-charge module includes: a first transistor, the control end of the first transistor is connected to the level transmission output end of the ni-th level GOA circuit unit, the first end of the first transistor is connected to the driving output end of the ni-th level GOA circuit unit, and the second end of the first transistor is connected to the control voltage end.

[0008] Optionally, the output module includes: a second transistor, a control end of the second transistor is connected to the second end of the first transistor, a first end of the second transistor is connected to the clock signal end, and the second end of the second transistor serves as a driving output end.

[0009] Optionally, the stage transmission module includes: a third transistor, a control end of the third transistor is connected to the second end of the first transistor, a first end of the third transistor is connected to the clock signal end, and a second end of the third transistor serves as a stage transmission output end.

[0010] Optionally, the first pull-down control module and the second pull-down control module both include: a fourth transistor, a control end of the fourth transistor is connected to the control voltage end, and a second end of the fourth transistor is connected to the first low-level end; a fifth transistor, a control end of the fifth transistor is connected to the first pull-down signal end or the second pull-down signal end, a first end of the fifth transistor is connected to the control end of the fifth transistor, and a second end of the fifth transistor is connected to the first end of the fourth transistor; a sixth transistor, a control end of the sixth transistor is connected to the second end of the fifth transistor, a first end of the sixth transistor is connected to the stage transmission output end, and a second end of the sixth transistor is connected to the first low-level end; a seventh transistor, a control end of the seventh transistor is connected to the control end of the sixth transistor, a first end of the seventh transistor is connected to the control voltage end, and a second end of the seventh transistor is connected to the first low-level end; an eighth transistor, a control end of the eighth transistor is connected to the control end of the sixth transistor, a first end of the eighth transistor is connected to the drive output end, and a second end of the eighth transistor is connected to the first low-level end.

[0011] Optionally, the first pull-down control module and the second pull-down control module both include: a fourth transistor, a control end of the fourth transistor is connected to the control voltage end, and a second end of the fourth transistor is connected to the first low-level end; a fifth transistor, a control end of the fifth transistor is connected to the first pull-down signal end or the second pull-down signal end, a first end of the fifth transistor is connected to the control end of the fifth transistor, and a second end of the fifth transistor is connected to the first end of the fourth transistor; a sixth transistor, a control end of the sixth transistor is connected to the second end of the fifth transistor, a first end of the sixth transistor is connected to the stage transmission output end, and a second end of the sixth transistor is connected to the first low-level end; a seventh transistor, a control end of the seventh transistor is connected to the control end of the sixth transistor, a first end of the seventh transistor is connected to the control voltage end, and a second end of the seventh transistor is connected to the second low-level end; an eighth transistor, a control end of the eighth transistor is connected to the control end of the sixth transistor, a first end of the eighth transistor is connected to the drive output end, and a second end of the eighth transistor is connected to the first low-level end.

[0012] Optionally, the first pull-down control module and the second pull-down control module also include: a ninth transistor, the control end of the ninth transistor is connected to the stage transmission output end of the n+ stage GOA circuit unit, the first end of the ninth transistor is connected to the first end of the fifth transistor, and the second end of the ninth transistor is connected to the second end of the fifth transistor.

[0013] Optionally, the second low level is lower than the first low level.

[0014] In a second aspect, the present application provides a display panel comprising a display area and a non-display area, wherein the display area comprises a plurality of scan lines; the non-display area comprises the gate drive circuit, and the drive output end of each GOA circuit unit in the gate drive circuit is electrically connected to at least one scan line.

[0015] The technical solution provided by this application has at least the following beneficial effects:

[0016] The present application can realize low-potential pull-down and maintenance of the control voltage terminal, the stage transmission output terminal and the drive output terminal through the first pull-down control module; the present application reduces the circuit modules connected to the control voltage terminal without affecting the circuit action kinetic energy, which not only reduces the number of transistors related to the control voltage terminal (Q point), but also reduces the overall number of transistors in the GOA circuit unit, thereby reducing the risk of Q-point potential instability caused by leakage current while reducing the volume of the gate drive circuit, effectively improving the GOA charging effect and facilitating the design of narrow-frame products, thereby improving the product competitiveness of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0018] Figure 1 Shown is a schematic diagram of a transistor characteristic curve provided in an embodiment of the present application.

[0019] Figure 2 Shown is a waveform distortion schematic diagram provided in an embodiment of the present application.

[0020] Figure 3 Shown is a structural schematic diagram of a GOA circuit unit provided in an embodiment of the present application.

[0021] Figure 4 Shown is a circuit diagram of a first GOA circuit unit provided in an embodiment of the present application.

[0022] Figure 5 Shown is a circuit diagram of a second GOA circuit unit provided in an embodiment of the present application.

[0023] Figure 6 Shown is a circuit driving timing diagram provided in an embodiment of the present application.

[0024] Description of reference numerals:

[0025] 100, GOA circuit unit; 110, pre-charge module; 120, output module; 130, level transmission module; 140, first pull-down control module; 150, second pull-down control module;

[0026] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; C1, storage capacitor;

[0027] Qn, control voltage terminal; Cn, stage transmission output terminal; Gn, drive output terminal; CKn, clock signal terminal; LC1, first pull-down signal terminal; LC2, second pull-down signal terminal; Vss1, first low level terminal; Vss2, second low level terminal. DETAILED DESCRIPTION

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0029] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the present application.

[0030] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0031] The inventors of the present application have found that the existing GOA circuit generally includes a plurality of unit modules such as a pre-charge unit, an output unit, a stage transmission unit, a pull-down unit, a pull-up unit, a pull-down maintenance unit 1 and a pull-down maintenance unit 2. However, each unit module includes a plurality of TFT transistors, so that the number of TFT transistors connected to the control voltage terminal (Q point) is relatively large; the leakage curve of the TFT transistor is as shown in FIG. Figure 1 As shown in the figure, the leakage current of the TFT transistor is different with the difference of the gate-source voltage Vgs; in addition, as the temperature of the GOA region increases, the leakage current of the TFT transistor also increases; when there are a large number of TFTs related to the Q point (the TFT related to the Q point in this application refers to: a TFT whose source or drain is directly connected to the Q point), its leakage current will cause the high voltage of the Q point to collapse, resulting in the distortion of the output waveform of the G point (drive signal output terminal) Gout, such as Figure 2 As shown, Qout1 and Gout1 are the normal output waveforms of Q point and G point, and Qout2 and Gout2 are the abnormal output waveforms of Q point and G point caused by the leakage current of TFT transistor; the abnormal G point waveform will cause mischarging problems between pixels within the surface, affecting the display effect of the picture.

[0032] In order to solve the problem that the high leakage current at the Q point causes the output waveform of the gate drive signal to be distorted, the present application provides a gate drive circuit, which specifically includes the following embodiments:

[0033] The gate driving circuit provided in this embodiment includes N cascaded GOA circuit units 100. Figure 3 FIG. 1 is a schematic diagram of the structure of a GOA circuit unit provided in an embodiment of the present application; Figure 3 As shown, the nth stage GOA circuit unit 100 includes a control voltage terminal Qn, a stage transmission output terminal Fn and a driving output terminal Gn; wherein, Figure 3 In the figure, Qn represents the control voltage terminal of the n-th level GOA circuit unit 100, Fn represents the level transmission output terminal of the n-th level GOA circuit unit 100, Gn represents the driving output terminal of the n-th level GOA circuit unit 100, CKn represents the clock signal terminal of the n-th level GOA circuit unit 100, Fn-i represents the level transmission output terminal of the ni-th level GOA circuit unit 100, and Gn-i represents the driving output terminal of the ni-th level GOA circuit unit 100.

[0034] In this embodiment, the n-th level GOA circuit unit 100 further includes: a storage capacitor C1, a pre-charge module 110, an output module 120 and a level transmission module 130, the first end of the storage capacitor C1 is connected to the control voltage terminal Qn, and the second end of the storage capacitor C1 is connected to the drive output terminal Gn; the control end of the pre-charge module 110 is connected to the level transmission output terminal of the ni-th level GOA circuit unit 100, the first end of the pre-charge module 110 is connected to the drive output terminal of the ni-th level GOA circuit unit 100, and the second end of the pre-charge module 110 is connected to the control voltage terminal Qn, and is used to pre-charge the voltage on the control voltage terminal through the gate drive signal output by the ni-th level GOA circuit unit 100; the control end of the output module 120 is connected to the pre-charge module 1 10, the first end of the output module 120 is connected to the clock signal terminal CKn, and the second end of the output module 120 is connected to the second end of the storage capacitor C1, and is used to output the gate drive signal under the action of the first target voltage on the control voltage terminal Qn and the clock signal output by the clock signal terminal CKn; the control end of the level transmission module 130 is connected to the control voltage terminal Qn of the n-th level GOA circuit unit 100, the first end of the level transmission module 130 is connected to the clock signal terminal CKn, and the second end of the level transmission module 130 is connected to the pre-charge module 110 of the n+i-th level GOA circuit unit 100, and is used to output the level transmission signal under the action of the first target voltage on the control voltage terminal Qn and the clock signal output by the clock signal terminal CKn.

[0035] It should be noted that the variable i in this embodiment can take any value of 1, 2, 3, 4, 5, etc., and this application takes i=2 as an example; the voltage on the control voltage terminal Qn in this embodiment controls the output of the drive signal and the level transmission signal, which belongs to an important node (commonly known as the Q point) in the GOA circuit unit 100. The drive signal output by the drive output terminal of the n-2 level GOA circuit unit 100 pre-charges the control voltage terminal Qn of the n-level GOA circuit unit 100 and stores it in the storage capacitor C1. Before the clock signal of the n-level GOA circuit unit 100 arrives, the control voltage terminal Qn is in the first target voltage in advance; optionally, the first target voltage is a high level, which can control the conduction of the output module 120 and the level transmission module 130, and output the gate drive signal and the level transmission signal at the same time.

[0036] In this embodiment, the n-th level GOA circuit unit 100 also includes a first pull-down control module 140, the control end of the first pull-down control module 140 is connected to the first pull-down signal end LC1, and the output end of the first pull-down control module 140 is respectively connected to the control voltage end Qn, the stage transmission output end Fn and the driving output end Gn of the n-th level GOA circuit unit 100, and is used to discharge the voltage on the control voltage end Qn, the stage transmission output end Fn and the driving output end Gn, and maintain them to the second target voltage.

[0037] It should be noted that the voltage properties of the first target voltage and the second target voltage in this embodiment are opposite, that is, the first target voltage is a high level, and the second target voltage is a low level; wherein, the first target voltage can control the output module 120 to output a driving signal, and the second target voltage causes the output module 120 to stop outputting a driving signal; therefore, the function of the first pull-down control module 140 is to pull down the potentials on the control voltage terminal Qn, the driving output terminal Gn, and the stage transmission output terminal Fn to the second target voltage through the first pull-down signal outputted by the first pull-down signal terminal LC1 after the output of the driving signal of the current stage is completed, so that the output module 120 and the stage transmission module 130 of the current stage are completely turned off. In addition, in order to ensure that the low potentials of the control voltage terminal Qn, the stage transmission output terminal Fn, and the driving output terminal Gn of the current stage are not interfered by leakage current or other signals, the low potentials of the above three terminals are also maintained through the first pull-down control module 140.

[0038] It can be seen that the present application can realize the low potential pull-down and maintenance of the control voltage terminal Qn, the stage transmission output terminal Fn and the drive output terminal Gn through the first pull-down control module 140; the present application reduces the circuit modules connected to the control voltage terminal Qn without affecting the circuit action kinetic energy, which not only reduces the number of transistors related to the control voltage terminal Qn (Q point), but also reduces the overall number of transistors in the GOA circuit unit 100, thereby reducing the risk of Q point potential instability caused by leakage current while reducing the volume of the gate drive circuit, effectively improving the GOA charging effect and facilitating the design of narrow-frame products, thereby improving the product competitiveness of the display panel.

[0039] In one embodiment, the n-th level GOA circuit unit 100 further includes: a second pull-down control module 150, the control end of the second pull-down control module 150 is connected to the second pull-down signal end LC2, and the output end of the second pull-down control module 150 is respectively connected to the control voltage end Qn, the stage transmission output end Fn and the driving output end Gn of the n-th level GOA circuit unit 100, for discharging the voltages on the control voltage end Qn, the stage transmission output end Fn and the driving output end Gn, and maintaining them to the second target voltage;

[0040] It should be noted that the first pull-down control module 140 and the second pull-down control module 150 are redundant designs. In order to extend the life of the device, the two pull-down control modules are alternately turned on between different frames, that is to say: in the current frame, the first pull-down control module 140 is controlled to be in a working state by the first pull-down signal, and in the next frame, the second pull-down control module 150 is controlled to be in a working state by the second pull-down signal.

[0041] Figure 4 FIG. 1 is a circuit diagram of a first GOA circuit unit provided in an embodiment of the present application; Figure 4 As shown, the pre-charge module 110 includes: a first transistor T1, the control end of the first transistor T1 is connected to the level transmission output end of the ni-th level GOA circuit unit 100, the first end of the first transistor T1 is connected to the driving output end of the ni-th level GOA circuit unit 100, and the second end of the first transistor T1 is connected to the control voltage end Qn. Specifically, the first transistor T1 is an N-type MOS tube, which is turned on when a high level is input to the control end; when the level transmission output end of the ni-th level GOA circuit unit 100 outputs a high level, the first transistor T1 is turned on, and the gate drive signal output by the driving output end of the ni-th level GOA circuit unit 100 charges the storage capacitor C1 connected to the control voltage end Qn.

[0042] In one embodiment, if Figure 4As shown, the output module 120 includes: a second transistor T2, a control end of the second transistor T2 is connected to the second end of the first transistor T1, a first end of the second transistor T2 is connected to the clock signal end CKn, and a second end of the second transistor T2 is used as a driving output end Gn. Specifically, the second transistor T2 in this embodiment is an N-type MOS tube; when the control voltage end Qn is at a high level, the second transistor T2 is turned on, and the clock signal is output as a driving signal to the scan line in the panel through the driving output end Gn.

[0043] In one embodiment, if Figure 4 As shown, the stage transmission module 130 includes: a third transistor T3, the control end of the third transistor T3 is connected to the second end of the first transistor T1, the first end of the third transistor T3 is connected to the clock signal end CKn, and the second end of the third transistor T3 is used as the stage transmission output end Fn. Specifically, the third transistor T3 in this embodiment is an N-type MOS tube; when the control voltage end Qn is at a high level, the third transistor T3 is turned on, and the clock signal is output as a stage transmission signal to other stages through the stage transmission output end Fn.

[0044] In one embodiment, if Figure 4 As shown, the first pull-down control module 140 and the second pull-down control module 150 both include: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8; the control end of the fourth transistor T4 is connected to the control voltage end Qn, and the second end of the fourth transistor T4 is connected to the first low level end Vss1; the control end of the fifth transistor T5 is connected to the first pull-down signal end LC1 or the second pull-down signal end LC2, the first end of the fifth transistor T5 is connected to the control end of the fifth transistor T5, and the second end of the fifth transistor T5 is connected to the first end of the fourth transistor T4; the sixth transistor T6 is connected to the control end of the fifth transistor T5, and the second end of the fifth transistor T5 is connected to the first end of the fourth transistor T4; The control end of the seventh transistor T7 is connected to the control end of the sixth transistor T6, the first end of the seventh transistor T7 is connected to the control voltage end Qn, and the second end of the seventh transistor T7 is connected to the first low level end Vss1; the control end of the eighth transistor T8 is connected to the control end of the sixth transistor T6, the first end of the eighth transistor T8 is connected to the driving output end Gn, and the second end of the eighth transistor T8 is connected to the first low level end Vss1.

[0045] In another embodiment, the first pull-down control module 140 and the second pull-down control module 150 also include: a ninth transistor T9, the control end of the ninth transistor T9 is connected to the level transmission output end Fn of the n+ level GOA circuit unit 100, the first end of the ninth transistor T9 is connected to the first end of the fifth transistor T5, and the second end of the ninth transistor T9 is connected to the second end of the fifth transistor T5.

[0046] It should be noted that the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 in the present embodiment are all N-type MOS tubes; since the circuit designs of the first pull-down control module 140 and the second pull-down control module 150 are completely the same, their working principles are also the same; this time, the first pull-down control module 140 is taken as an example to illustrate its working principle:

[0047] (1) When the control voltage terminal Qn is at a high level, the fourth transistor T4 is turned on. Figure 4 The voltage of the node Pn in is pulled down to the first low level; thereby, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. Even if the first pull-down signal terminal LC1 continues to output a high level, the voltages on the control voltage terminal Qn, the stage transmission output terminal Fn and the drive output terminal Gn cannot be pulled down; therefore, the fourth transistor T4 is controlled by the control voltage terminal Qn to maintain a high level on the control voltage terminal Qn.

[0048] (2) When the control voltage terminal Qn is at a low level (that is, when the current stage completes the output of the driving signal), the fourth transistor T4 is turned off, and the voltage on the node Pn is controlled by the fifth transistor T5; the first pull-down signal terminal LC1 continuously outputs a high level in the current frame to turn on the fifth transistor T5, and pulls the voltage on the node Pn to a high level, so that the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned on, thereby continuously pulling down the voltage of the stage transmission output terminal Fn through the turned-on sixth transistor T6, continuously pulling down the voltage on the control voltage terminal Qn through the turned-on seventh transistor T7, and continuously pulling down the voltage on the driving output terminal Gn through the turned-on eighth transistor T8, thereby maintaining the voltages on the control voltage terminal Qn, the stage transmission output terminal Fn and the driving output terminal Gn at the second target voltage.

[0049] (3) When the stage transmission output terminal of the n+jth stage GOA circuit unit 100 outputs a high level, the ninth transistor T9 is turned on, and the voltage on the first pull-down signal terminal LC1 is pulled down through the low level on the node Pn, and the GOA circuit operates abnormally.

[0050] Figure 5 FIG. 4 is a circuit diagram of a second GOA circuit unit provided in an embodiment of the present application; Figure 5 and Figure 4 The only difference is that the second end of the seventh transistor T7 is connected in a different way. Figure 4 The second end of the seventh transistor T7 is connected to the first low level end Vss1 which is the same as other transistors, and Figure 5 The second end of the seventh transistor T7 is connected to the second low level end Vss2 which is different from other transistors; the purpose of connecting the source of the seventh transistor T7 to the second low level end Vss2 in this embodiment is to reduce the off-state leakage current of the device by adjusting the gate-source voltage of the seventh transistor T7 alone; Figure 1 It can be seen that the leakage current is the smallest at a certain point of the gate-source voltage Vgs; Figure 4 and Figure 5 It can be seen that the transistors with off-state leakage current on the control voltage terminal Qn are the first transistor T1 and the seventh transistor T7. The gate-source voltage of the first transistor T1 cannot be adjusted. Therefore, by adjusting the gate-source voltage on the seventh transistor T7, the leakage current on the control voltage terminal Qn can be reduced to a minimum.

[0051] It should also be noted that in this embodiment, the source of the seventh transistor T7 is connected to the second low level terminal Vss2, which adjusts its leakage current without affecting the voltage of other transistors or nodes; in this embodiment, the second low level terminal Vss2 is smaller than the first low level terminal Vss1.

[0052] Figure 6 The following is a circuit driving timing diagram provided by an embodiment of the present application, which is described by taking 8 CKs (high frequency clock signals), N-2 / N+4 stage transmission and G3 output as an example:

[0053] (1) During the time period t1, LC1 is at a high level, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 work to clear the noise on the control voltage terminal Qn, the stage transmission output terminal Fn and the driving output terminal Gn.

[0054] (2) In the time period t2, LC1 is at a high level, G1 and F1 are turned on, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are working, and since the Q point is at a high level, the fourth transistor T4 is turned on, causing the P point to be at a low level, so the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are in the off state.

[0055] (3) In the time period t3, LC1 and CK3 are at high level, the second transistor T2 is charged, and due to the existence of the capacitor, the Q point level rises again, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 work, and G3 is output.

[0056] (4) During the time period t4, LC1 is at a high level, CK3 becomes a low level, and the second transistor T2 is discharged. At this time, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are working. Due to the existence of the storage capacitor C1, Q3 continues to maintain a high level (the voltage will decrease, but will not reach VSS, forming the right shoulder of the Q point). At this time, P3 is at a low level.

[0057] (5) During the time period t5, LC1 is at a high level, F7 is turned on, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are working, the charge of the storage capacitor C1 is released, the Q point is at a low level, and the P point is at a high level, and the noise on the control voltage terminal Qn, the stage transmission output terminal Fn and the drive output terminal Gn is continuously cleared.

[0058] To sum up, the gate drive circuit provided in this application reduces the risk of high-temperature leakage by reducing the number of transistors related to the control voltage end without affecting the circuit actuation function; it can not only reduce the GOA product frame, but also reduce the Q-node leakage risk, effectively improve the GOA charging effect, and greatly improve the long-term stability of GOA.

[0059] In one embodiment, the present application provides a display panel including a display area and a non-display area, the display area including multiple scan lines; the non-display area includes the gate drive circuit in the above embodiment, and the drive output end of each GOA circuit unit in the gate drive circuit is electrically connected to at least one scan line.

[0060] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0061] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0062] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A gate drive circuit, characterized in that: The gate drive circuit comprises: N cascaded GOA circuit units, the n-th level GOA circuit unit comprises a control voltage terminal, a level transmission output terminal and a drive output terminal, and the n-th level GOA circuit unit further comprises: A storage capacitor, wherein a first end of the storage capacitor is connected to the control voltage end, and a second end of the storage capacitor is connected to the drive output end; A pre-charge module, wherein the control end of the pre-charge module is connected to the level transmission output end of the ni-th level GOA circuit unit, the first end of the pre-charge module is connected to the driving output end of the ni-th level GOA circuit unit, and the second end of the pre-charge module is connected to the control voltage end, and is used to pre-charge the voltage on the control voltage end through the gate drive signal output by the ni-th level GOA circuit unit; an output module, wherein a control end of the output module is connected to an output end of the pre-charge module, a first end of the output module is connected to a clock signal end, and a second end of the output module is connected to a second end of the storage capacitor, and is used to output a gate drive signal under the action of a first target voltage on the control voltage end and a clock signal output by the clock signal end; A level transmission module, wherein the control end of the level transmission module is connected to the control voltage end of the n-th level GOA circuit unit, the first end of the level transmission module is connected to the clock signal end, and the second end of the level transmission module is connected to the pre-charge module of the n+i-th level GOA circuit unit, and is used to output a level transmission signal under the action of the first target voltage on the control voltage end and the clock signal output by the clock signal end; A first pull-down control module, wherein the control end of the first pull-down control module is connected to the first pull-down signal end, and the output end of the first pull-down control module is respectively connected to the control voltage end, the stage transmission output end and the driving output end of the n-th stage GOA circuit unit, for discharging the voltages on the control voltage end, the stage transmission output end and the driving output end, and maintaining them to a second target voltage.

2. The gate driving circuit according to claim 1, characterized in that: The nth level GOA circuit unit also includes: A second pull-down control module, wherein the control end of the second pull-down control module is connected to the second pull-down signal end, and the output end of the second pull-down control module is respectively connected to the control voltage end, the stage transmission output end and the driving output end of the n-th stage GOA circuit unit, for discharging the voltages on the control voltage end, the stage transmission output end and the driving output end, and maintaining them to a second target voltage.

3. The gate drive circuit according to claim 1 or 2, characterized in that: The pre-charging module comprises: A first transistor, wherein the control end of the first transistor is connected to the stage transmission output end of the ni-th stage GOA circuit unit, the first end of the first transistor is connected to the driving output end of the ni-th stage GOA circuit unit, and the second end of the first transistor is connected to the control voltage end.

4. The gate driving circuit according to claim 3, characterized in that: The output module comprises: A second transistor, wherein the control end of the second transistor is connected to the second end of the first transistor, the first end of the second transistor is connected to the clock signal end, and the second end of the second transistor serves as a driving output end.

5. The gate driving circuit according to claim 3, characterized in that: The level transmission module comprises: A third transistor, wherein the control end of the third transistor is connected to the second end of the first transistor, the first end of the third transistor is connected to the clock signal end, and the second end of the third transistor serves as a stage transmission output end.

6. The gate driving circuit according to claim 2, characterized in that: The first pull-down control module and the second pull-down control module both include: a fourth transistor, wherein a control terminal of the fourth transistor is connected to the control voltage terminal, and a second terminal of the fourth transistor is connected to the first low level terminal; a fifth transistor, wherein the control terminal of the fifth transistor is connected to the first pull-down signal terminal or the second pull-down signal terminal, the first terminal of the fifth transistor is connected to the control terminal of the fifth transistor, and the second terminal of the fifth transistor is connected to the first terminal of the fourth transistor; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the second terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the stage transmission output terminal, and a second terminal of the sixth transistor is connected to the first low level terminal; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the sixth transistor, a first terminal of the seventh transistor is connected to the control voltage terminal, and a second terminal of the seventh transistor is connected to the first low level terminal; An eighth transistor, wherein the control end of the eighth transistor is connected to the control end of the sixth transistor, the first end of the eighth transistor is connected to the driving output end, and the second end of the eighth transistor is connected to the first low level end.

7. The gate driving circuit according to claim 2, characterized in that: The first pull-down control module and the second pull-down control module both include: a fourth transistor, wherein a control terminal of the fourth transistor is connected to the control voltage terminal, and a second terminal of the fourth transistor is connected to the first low level terminal; a fifth transistor, wherein the control terminal of the fifth transistor is connected to the first pull-down signal terminal or the second pull-down signal terminal, the first terminal of the fifth transistor is connected to the control terminal of the fifth transistor, and the second terminal of the fifth transistor is connected to the first terminal of the fourth transistor; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the second terminal of the fifth transistor, a first terminal of the sixth transistor is connected to the stage transmission output terminal, and a second terminal of the sixth transistor is connected to the first low level terminal; a seventh transistor, wherein a control terminal of the seventh transistor is connected to the control terminal of the sixth transistor, a first terminal of the seventh transistor is connected to the control voltage terminal, and a second terminal of the seventh transistor is connected to the second low level terminal; An eighth transistor, wherein the control end of the eighth transistor is connected to the control end of the sixth transistor, the first end of the eighth transistor is connected to the driving output end, and the second end of the eighth transistor is connected to the first low level end.

8. The gate drive circuit according to claim 6 or 7, characterized in that: The first pull-down control module and the second pull-down control module further include: A ninth transistor, wherein the control end of the ninth transistor is connected to the stage transmission output end of the n+ stage GOA circuit unit, the first end of the ninth transistor is connected to the first end of the fifth transistor, and the second end of the ninth transistor is connected to the second end of the fifth transistor.

9. The gate driving circuit according to claim 7, characterized in that: The second low level is lower than the first low level.

10. A display panel, comprising a display area and a non-display area, wherein the display area comprises a plurality of scan lines; characterized in that: The non-display area includes the gate driving circuit according to any one of claims 1 to 9, and the driving output end of each GOA circuit unit in the gate driving circuit is electrically connected to at least one scanning line.

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