Semiconductor device, operating method thereof, and memory system

Abstract

The invention provides a semiconductor device, an operating method thereof, and a memory system. The semiconductor device includes a reference voltage circuit to generate a reference voltage; the charge pump is used for generating an output voltage according to the reference voltage; a charge pump detection circuit to detect the output voltage of the charge pump; and the power consumption control circuit is used for enabling the reference voltage circuit to stop working in a first time period. According to the semiconductor device and the operation method thereof, especially in a standby mode, due to the fact that the work of the charge pump of the reference voltage circuit is periodically recovered, namely the reference voltage and the output voltage are periodically refreshed, lower standby power consumption can be obtained, and the purpose of power consumption control is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a semiconductor device, an operation method thereof, and a storage system. Background Art

[0002] A charge pump circuit is a DC-DC circuit that can generate a module operating voltage higher than the source voltage. It is widely used especially in non-volatile memories, such as generating programming and erasing high voltages for floating gate devices in EEPROM and flash memories.

[0003] Flash memory has a data storage function and includes NAND flash memory and NOR flash memory. However, both NAND flash memory and NOR flash memory face the problem of power consumption. The power consumption problem has always been an important indicator for flash memory, especially for mobile devices powered by batteries. Therefore, how to reduce power consumption is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the present application provides a semiconductor device, an operation method thereof, and a storage system that can reduce the power consumption of the semiconductor device and obtain lower standby power consumption.

[0005] To solve the above problems, the present application provides a semiconductor device, which includes:

[0006] A reference voltage circuit for generating a reference voltage;

[0007] A charge pump for generating an output voltage according to the reference voltage;

[0008] A charge pump detection circuit for detecting the output voltage of the charge pump; and

[0009] A power consumption control circuit for stopping the reference voltage circuit from working in a first time period.

[0010] In some embodiments, the power consumption control circuit includes a delay control circuit for starting the delay of the first time period after the output voltage reaches a target value, so that the reference voltage circuit stops working within the first time period.

[0011] In some embodiments, after the delay of the first time period ends, the delay control circuit first starts the reference voltage circuit, and after a second time period, detects whether the output voltage meets the requirements through the charge pump detection circuit.

[0012] In some embodiments, the charge pump detection circuit further includes a component configured to, when it detects that the output voltage is not lower than a preset value, cause the reference voltage circuit and the charge pump to continue to suspend operation, and start a delay for the first time period.

[0013] In some embodiments, the charge pump detection circuit further includes a component configured to, when it detects that the output voltage of the charge pump is lower than a preset value, cause the charge pump to start operating.

[0014] In some embodiments, the detection of the output voltage by the charge pump detection circuit includes either intermittent detection or continuous detection.

[0015] In some embodiments, the power consumption control circuit includes an energy storage circuit configured to, after the output voltage reaches the target value, cause the reference voltage circuit to stop operating for one first time period and maintain the reference voltage.

[0016] In some embodiments, the energy storage circuit includes: a capacitor configured to maintain the reference voltage; and a switch located between the capacitor and the reference voltage circuit and configured to disconnect the capacitor from the reference voltage circuit after the output voltage reaches the target value.

[0017] In some embodiments, the charge pump detection circuit is further configured to, when it detects that the output voltage is lower than a preset value, cause the reference voltage circuit and the charge pump to start operating, and end the stop operation of the reference voltage circuit for the first time period.

[0018] In some embodiments, when the charge pump detection circuit detects that the output voltage is lower than a preset value, it first causes the reference voltage circuit to operate, and after conducting the switch for a third time period, it causes the charge pump to operate.

[0019] In some embodiments, after the charge pump stops operating for the first time period, it starts operating earlier than the reference circuit.

[0020] In some embodiments, the charge pump start-stop cycle is executed N times, and the reference voltage circuit start-stop cycle is executed once, where N is a positive integer greater than or equal to 1.

[0021] In some embodiments, the semiconductor device further includes a charge pump voltage division circuit configured to extract the output voltage of the charge pump and supply it to the charge pump detection circuit.

[0022] This application also provides an operation method for a semiconductor device, and the operation method includes:

[0023] Generating a reference voltage through a reference voltage circuit;

[0024] Generate an output voltage through a charge pump based on the reference voltage; and,

[0025] Detect the output voltage of the charge pump, and cause the reference voltage circuit to stop working in a first time period.

[0026] In some embodiments, the step of causing the reference voltage circuit to stop working in the first time period includes, after the output voltage reaches a target value, starting a delay of the first time period and causing the reference voltage circuit to stop working within the first time period.

[0027] In some embodiments, the method further includes, after the delay ends, first starting the reference voltage circuit, and after a second time period, detecting whether the output voltage meets the requirements through the charge pump detection circuit.

[0028] In some embodiments, the method further includes, when the charge pump detection circuit detects that the output voltage is not lower than a preset value, causing the reference voltage circuit and the charge pump to pause working, starting a delay of the first time period, and causing the reference voltage circuit to repeat the stop working in the first time period.

[0029] In some embodiments, the method further includes, when the charge pump detection circuit detects that the output voltage of the charge pump is lower than a preset value, causing the charge pump to start working.

[0030] In some embodiments, the step of detecting the output voltage of the charge pump includes one of intermittent detection and continuous detection.

[0031] In some embodiments, the step of causing the reference voltage circuit to stop working within the first time period includes: maintaining the reference voltage through an energy storage circuit, and after the output voltage reaches a target value, causing the reference voltage circuit to stop working for one first time period.

[0032] In some embodiments, the step of maintaining the reference voltage through an energy storage circuit includes: receiving and maintaining the reference voltage through a switch and a capacitor, and after the output voltage reaches a target value, disconnecting the switch.

[0033] In some embodiments, the method further includes: when the charge pump detection circuit detects that the output voltage is lower than a preset value, causing the reference voltage circuit and the charge pump to start working, and causing the reference voltage circuit to end the stop working in the first time period.

[0034] In some embodiments, the step of causing the reference voltage circuit and the charge pump to start operating when the charge pump detection circuit detects that the output voltage is lower than a preset value includes: the reference voltage circuit starts operating first, and after the switch is turned on for a third time period, the charge pump starts operating.

[0035] In some embodiments, the method further includes: after stopping operating in the first time period, causing the charge pump to start operating before the reference circuit, and causing the charge pump start-stop cycle to be executed N times and the reference voltage circuit start-stop cycle to be executed once, where N is a positive integer greater than or equal to 1.

[0036] The present application also provides a memory system, characterized by including: the semiconductor device described above; and a controller configured to control the semiconductor device.

[0037] The semiconductor device, its operation method, and the storage system provided by the present application, by setting the voltage generator in the memory to include: a reference voltage circuit for generating a reference voltage; a charge pump for generating an output voltage according to the reference voltage; a charge pump detection circuit for detecting the output voltage of the charge pump; and a power consumption control circuit for causing the reference voltage circuit to stop operating in a first time period; especially in the standby mode, due to periodically resuming the operation of the reference voltage circuit and the charge pump, that is, periodically refreshing the reference voltage and the output voltage, a lower standby power consumption can be obtained, thereby achieving the purpose of power consumption control. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the technical solutions in some embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0039] Figure 1 It is a schematic block diagram of an exemplary memory disclosed in the embodiments of the present application.

[0040] Figure 2 For Figure 1 It is a schematic block diagram of the voltage generator in the shown memory.

[0041] Figure 3A For Figure 2 It is a schematic block diagram of a voltage generator in the shown memory.

[0042] Figure 3B For Figure 3A It is a related voltage timing diagram of the shown voltage generator.

[0043] Figure 4A Schematic block diagram of another voltage generator in the memory shown Figure 2

[0044] Figure 4B Schematic voltage timing diagram of the voltage generator shown Figure 4A

[0045] Figure 5 Exemplary step diagram in the operation method of the semiconductor device shown in the embodiments of the present application

[0046] Figure 6 Schematic system block diagram of a memory system provided by the present application Detailed implementation manners

[0047] Hereinafter, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in some embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0048] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0049] The present application may repeat reference numerals and / or reference letters in different embodiments. Such repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or arrangements discussed.

[0050] First, please refer to Figure 1 , Figure 1 which shows a schematic block diagram of a semiconductor device with the memory 400 as an exemplary semiconductor device provided in some embodiments of the present application. The memory 400 includes a memory array 420 and other peripheral circuits (not labeled). As Figure 1 ​​As shown, the peripheral circuit may at least include other components outside the memory array 420, such as page buffer / sense amplifier 411, column decoder / bit line driver 412, row decoder / word line driver 413, voltage generator 414, control logic unit 415, register 416, interface 417, and data bus 418, etc. It should be understood that in some examples, the peripheral circuit may also include other circuits not shown in Figure 1 the figure.

[0051] Figure 1 The block diagram shown can be applied to, for example, two-dimensional or three-dimensional flash type (NAND / NOR flash) or memory type (DRAM) memories, with the difference lying in the different memory arrays 420. Therefore, the memory array 420 can be, for example, the memory array of a two-dimensional or three-dimensional flash type (NAND / NOR flash) or memory type (DRAM) memory, and the memory can include DRAM, PCRAM, FeRAM, MRAM, etc. The memory array 420 has at least one large-sized block storage platform (Giant Block, GB), and the storage platform at least includes a majority of memory cells arranged in an array (refer to Figure 3A and Figure 3B ). The majority of memory cells can be appropriately arranged according to the two-dimensional or three-dimensional structure, and can also be appropriately arranged according to the NAND, NOR, or DRAM architecture.

[0052] The page buffer / sense amplifier 411 can be configured to read data from the memory array 420 and program (also called "write") data to the memory array 420 according to the control signal from the control logic unit 415. Specifically, in one example, the page buffer / sense amplifier 411 can store the data of a memory page to be programmed to the memory array 420. In another example, the page buffer / sense amplifier 411 can also perform the operation of sensing the low-power signal representing the data stored in the memory cell from the bit line BL, and amplify the small voltage swing of the low-power signal to a recognizable logic level during the read operation. The page buffer / sense amplifier 411 among them can have different arrangements and combinations according to the type of the memory array 420 and the design of the bit line BL. For example, it can be multiple page buffer / sense amplifiers 411 that cooperate with multiple groups of bit line groups.

[0053] The column decoder / bit line driver 412 can be configured to be controlled by the control logic unit 415 and select one or more columns of memory cells by applying the bit line voltage generated from the voltage generator 414. The column decoder / bit line driver 412 can also have different arrangements and combinations according to the type and design of the memory array 420. For example, it can be multiple groups of column decoder / bit line drivers 412.

[0054] The row decoder / word line driver 413 can be configured to be controlled by the control logic unit 415 to select different memory cells in the memory array 420. The row decoder / word line driver 413 can also be configured to drive the word line WL using the word line voltage generated from the voltage generator 414. The row decoder / word line driver 413 can also have different arrangements and combinations according to the type and design of the memory array 420. For example, it can be multiple groups of row decoder / word line drivers 413.

[0055] Therefore, the voltage generator 414 includes a charge pump, which can be configured to be controlled by the control logic unit 415 and generate the word line voltage, bit line voltage, and the required current to be supplied to the memory array 420.

[0056] The control logic unit 415 can be coupled to each circuit in the peripheral circuit 410 described above (such as the page buffer / sense amplifier 411, column decoder / bit line driver 412, row decoder / word line driver 413, and voltage generator 414), and control the operation of each circuit.

[0057] The register 416 can be coupled to the control logic unit 415 and can at least include a status register, command register, and address register to store the status information, command operation code (OP code), and address for controlling the operation of each of the above circuits.

[0058] The interface 417 can be coupled to the control logic unit 415 and act as a control buffer to perform buffering of the control commands received from the Figure 1 controller and relay the commands to the control logic unit 415 for operation, and perform buffering of the status information received from the control logic unit 415 and relay the commands to an external controller (not shown) for operation. Further, the interface 417 can also be coupled to the column decoder / bit line driver 412 via the data bus 418 and act as a data I / O (Input / Output) interface and data buffer to perform buffering of data and relay the data to the memory array 420 for operation, and perform the operation of relaying or buffering data from the memory array 420.

[0059] In some embodiments, the storage array 420 may be a NOR-type or NAND-type flash memory architecture, or may be a memory architecture such as 1T1C or 1TXC type (T represents a transistor, C represents a capacitive storage cell, and X represents a quantity). Additionally, the storage array may be a 3D architecture in addition to a 2D architecture. Such architectures are well-known to those skilled in the art and will not be described in detail herein, nor will they be used to limit the scope of application of this application. As long as they can apply the technical concept of this application, they are within the scope of this application.

[0060] In the standby mode of the Nor flash, the control logic unit 415 still generates a voltage higher than zero through the charge pump in the voltage generator 414 and refreshes it periodically, which greatly increases the power consumption of the circuit. And power consumption is an important indicator for various memories, especially for Nor flash, and this is even more so for mobile devices powered by batteries. Therefore, how to reduce the read power consumption is an urgent problem to be solved.

[0061] In addition, in the standby mode of the Nor flash, the internal reference voltage circuit is always in operation and generates a reference voltage that does not change with process, voltage, and temperature. Using this reference voltage, the charge pump inside the chip can generate a fixed voltage higher than the power supply voltage for a read operation. The power consumption of the reference voltage circuit and the power consumption generated by the charge pump refreshing the voltage periodically are the two parts that account for the largest proportion of the standby power consumption of the Nor flash.

[0062] Furthermore, although the above is exemplified by a flash memory for the application example of the charge pump, it can be understood that there are quite a lot of semiconductor devices using a charge pump, not limited to memories. The memory 400 is only an exemplary application description representing the semiconductor devices disclosed in this application. Therefore, the semiconductor devices described in this application may be the voltage generator 414 itself or the memory 400. Hereinafter, only the voltage generator 414 will be used as an example of the semiconductor devices disclosed in this application for illustration. That is, the semiconductor devices 200 / 200a / 200 described below correspond to the voltage generator 414 exemplified above.

[0063] To solve the problem of power consumption, Figure 2 A schematic block diagram of a semiconductor device 200 as the aforementioned voltage generator 414 according to an embodiment of this application is disclosed.

[0064] As Figure 2As shown, the semiconductor device 200 according to an embodiment of the present application includes: a reference voltage circuit 210 for generating a reference voltage; a charge pump 220 for generating an output voltage according to the reference voltage; a charge pump detection circuit 230 for detecting the output voltage of the charge pump; and a power consumption control circuit 240 for causing the reference voltage circuit to stop operating within a first time period.

[0065] Specifically, the reference voltage circuit 210 is one of the most commonly used circuit modules in an integrated circuit chip. Almost all types of chips require a reference voltage circuit, so the power consumption of the reference voltage is part of the chip's power consumption. In some embodiments, the reference voltage circuit may include a bandgap reference voltage circuit, especially a CMOS bandgap reference voltage circuit, which can not only provide the reference voltage or current required by the system, but also has the advantages of low power consumption, high integration, and simple design, and is widely used in analog integrated circuits and hybrid integrated circuits. However, in the embodiments of the present application, the following descriptions are only given by taking the reference voltage circuit as an example. After the reference voltage circuit 210 starts to operate, it provides an accurate reference voltage Vref for the charge pump 220. Since the circuit design of the reference voltage circuit or the bandgap reference voltage circuit 210 itself is not the focus of the present application, the reference voltage circuit 210 is directly represented by a block diagram in the present application. Those skilled in the art can implement it based on the block diagram, so no further detailed description is given here.

[0066] The charge pump 220 is a DC-DC circuit that can generate an output voltage Vcp higher than the aforementioned reference voltage Vref as the module operating voltage, and is particularly widely used in non-volatile memories, such as generating the programming and erasing high voltages of floating gate devices in EEPROM and flash memories. The charge pump 220 usually uses a capacitor (not shown) as an energy storage component to generate an output voltage Vcp larger than the input voltage, or to generate a negative output voltage Vcp. The charge pump 220 also includes some switching components (not shown) to control the voltage connected to the capacitor. For example, it can cooperate with a two-stage cycle to generate a higher pulsed voltage output with a lower input voltage. In the first stage of the cycle, the capacitor is connected to the power supply terminal and thus charged to the same voltage as the power supply. In the first stage, the circuit configuration is adjusted so that the capacitor and the power supply voltage are in series. If the effect of leakage current is not considered and no load is assumed, its output voltage will be twice the input voltage (the original power supply voltage plus the voltage across the capacitor). The pulsed characteristics of the higher output voltage Vcp can be filtered by an output filter capacitor.

[0067] The charge pump 220 also includes other circuits to control the periodic switching of the switching components. Generally, the switching frequency is in the range of dozens of kHz to several MHz. A higher refresh switching frequency can reduce the required capacitors, so that the charge to be stored in a shorter time is also smaller. The capacitors used in the charge pump are generally referred to as flying capacitors. In addition, the output voltage Vcp of the charge pump is related to the load. If the load is larger, its average voltage will be lower. Depending on the control method and circuit architecture, the charge pump can perform voltage doubling, tripling, voltage inversion, multiplying the voltage by a fraction (such as ×3 / 2, ×4 / 3, ×2 / 3, etc.), and can also quickly switch between different modes to generate an output voltage Vcp of any magnitude and make the output voltage Vcp reach a target value Vtag. That is, after the charge pump 220 starts to work, it can generate an output voltage Vcp that reaches the target value Vtag according to the reference voltage Vref provided by the reference voltage circuit 210.

[0068] Similarly, since the circuit design of the charge pump 220 itself is not the focus of this application, the charge pump 220 is directly represented by a block diagram in this application. A person skilled in the art can implement it based on the block diagram, so no further detailed description is added.

[0069] The charge pump detection circuit 230 is a circuit used to detect the output voltage Vcp of the charge pump 220. It can achieve the detection of the output voltage Vcp through devices such as resistors, or it can be any other suitable device that can detect the output voltage Vcp.

[0070] The power consumption control circuit 240 is used to stop the reference voltage circuit from working within the first time period. Specifically, some embodiments will be used below to illustrate the power consumption control circuit 240.

[0071] First, as Figure 3A shown, in some embodiments, Figure 2 the power consumption control circuit 240 shown is a delay control circuit 240a. The delay control circuit 240a is used to start the delay of the first time period after the output voltage Vcp reaches the target value Vtag, so that the reference voltage circuit 210 stops working within the first time period Td.

[0072] Specifically, the delay control circuit 240a can be any suitable delay circuit, such as an RC delay circuit or a counter delay circuit. Similarly, since the circuit design of the delay control circuit 240a itself is not the focus of this application, the delay control circuit 240a is directly represented by a block diagram in this application. A person skilled in the art can implement it based on the block diagram, so no further detailed description is added.

[0073] After the output voltage Vcp of the charge pump 220 reaches the preset target value Vtag, the delay control circuit 240a is started to count by the enable signal Vtag_EN output by the charge pump detection circuit 230, and a disable signal DIS is generated to the reference voltage circuit 210, so that the reference voltage circuit 210 stops working within the first time period Td of counting. When the reference voltage circuit 210 stops working and does not generate the reference voltage Vref, the charge pump 220 will also stop working accordingly.

[0074] In some embodiments, after the delay Td has passed, that is, after the delay time has ended, the delay control circuit 240a generates an enable signal EN to start the reference voltage circuit 210, and after the second time period T2_3, it is detected by the charge pump detection circuit 230 whether the output voltage Vcp meets the requirements.

[0075] Specifically, as Figure 3B shown, Figure 3B display Figure 3A the relevant voltage timing diagram of the semiconductor device 200a shown. In Figure 3B it, the timing T1 represents the reference voltage Vref generated by the reference voltage circuit 210, and the output voltage Vcp of the charge pump 220 reaches the target value Vtag, thus starting the delay of the first time period Td. The first time period Td is the time between the timings T1 and T2. The delay control circuit 240a sends out the disable signal DIS at the rising edge at the timing T1, so that the reference voltage circuit 210 and the charge pump 220 stop working; after the first time period Td has passed, at the timing T2, the enable signal EN is sent out at the falling edge to make the reference voltage circuit 210 resume working. It should be understood here that the time intervals of each timing T1 / T2 / T3, etc. in the figure do not represent the actual time, but only represent the sequence, and the waveforms shown are schematic diagrams and do not represent the real rising and falling rates.

[0076] In some embodiments, after the reference voltage circuit 210 resumes working, it takes some time to stabilize. Therefore, the charge pump 220 can resume working after the reference voltage Vref reaches the preset value, that is, after the second time period T2_3 has passed. Since the charge pump detection circuit 230 is used to detect the output voltage Vcp of the charge pump 220, the charge pump detection circuit 230 can also stop working when the charge pump 220 stops working. Of course, in some embodiments, the charge pump 220 and the charge pump detection circuit 230 can also be enabled by the enable signal EN of the delay control circuit 240a to resume working at the timing T2 like the reference voltage circuit 210, and there is no limitation here.

[0077] Also, in some embodiments, the enable signal EN can also be sent toFigure 3A The charge pump voltage dividing circuit 260 shown. Also, the charge pump detection circuit 230 can also be controlled by the enable signal EN of the delay control circuit 240a, and the enable signal EN for the charge pump detection circuit 230 can also be sent only at timing T3, but Figure 3B no indication is made thereon.

[0078] Figure 3B The variation of the output voltage Vcp of the charge pump 220 at timings T1, T2, and T3 is also shown. That is, at timing T1, the output voltage Vcp reaches the target value Vtag, the reference voltage circuit 210 and the charge pump 220 stop working, and the output voltage Vcp will slowly decrease according to the load condition until timing T3, when the charge pump 220 resumes working and then rises again. After reaching the target value Vtag at timing NT1, another cycle of delay control starts.

[0079] Furthermore, in some embodiments, the charge pump detection circuit 230 is further configured to pause the operation of the reference voltage circuit 210 and the charge pump 220 and start the delay Td when it detects that the output voltage Vcp is not lower than the preset value Vmin.

[0080] In some embodiments, the charge pump detection circuit 230 further includes a component configured to start the operation of the reference voltage circuit 210 and start the operation of the charge pump 220 when it detects that the output voltage Vcp of the charge pump 220 is lower than the preset value Vmin.

[0081] Specifically, in some embodiments, the charge pump detection circuit 230 can be set to continuously detect the output voltage Vcp of the charge pump 220 for a long time, but it can also be intermittently detect the output voltage Vcp of the charge pump 220. If it is intermittently detected, when it detects that the output voltage Vcp is not lower than the preset value Vmin, in addition to continuously pausing the operation of the reference voltage circuit 210 and the charge pump 220, the delay of the first time period is started, and a new cycle is started, so that the reference voltage circuit 210 repeats to stop working within the first time period Td; the intermittent time can be determined according to the design.

[0082] If the charge pump detection circuit 230 is continuously detecting, when it is not lower than the preset value Vmin, the reference voltage circuit 210 and the charge pump 220 can be continuously paused, but the delay is not started. It is not until the reference voltage circuit 210 and the charge pump 220 are started to work because they are lower than the preset value Vmin and stop working because they reach the target value Vtag that the delay of the first time period Td is started.

[0083] In some embodiments, the first time period Td can last for a relatively long time. For example, it can last for multiple detection cycles of the charge pump detection circuit, or the first time period Td ends only after the charge pump has experienced multiple cycles of stopping and starting (stop-start cycles). It can be understood that when the charge pump 220 starts and stops N times, where N is greater than or equal to 1, that is, the start-stop cycle occurs multiple times, the reference voltage circuit 210 starts and stops only once. This is because the leakage of the reference voltage circuit 210 (especially the bandgap reference voltage circuit) is smaller than that of the charge pump, so this can be done. Through the setting of the delay control circuit 240a described above, in the standby mode, by periodically resuming the operation of the reference voltage circuit 210 and the charge pump 220, that is, by periodically refreshing the reference voltage Vref and the output voltage Vcp, lower standby power consumption can be obtained, thus achieving the purpose of power consumption control. Moreover, by using the charge pump detection circuit 230 to detect the voltage of the reference voltage circuit 210, the reference voltage detection circuit is omitted, which can reduce the chip area and power consumption.

[0084] Secondly, as Figure 4A shown, in some embodiments, Figure 2 the power consumption control circuit 240 shown is an energy storage circuit 240b. That is, according to some other embodiments of the present application, as Figure 4A shown, the semiconductor device 200b formed according to the embodiments of the present application includes: a reference voltage circuit 210 for generating a reference voltage; a charge pump 220 for generating an output voltage according to the reference voltage; a charge pump detection circuit 230 for detecting the output voltage of the charge pump; and an energy storage circuit 240b for starting to maintain the reference voltage Vref and stopping the operation of the reference voltage circuit 210 after the output voltage Vcp reaches the target value Vtag.

[0085] Figure 4A The difference between the semiconductor device 200b shown and Figure 3A the semiconductor device 200a shown lies in the difference of the power consumption control circuit 240. That is, Figure 3A the delay control circuit 240a is taken as Figure 2 an example of the power consumption control circuit 240 shown, while Figure 4A the energy storage circuit 240b is taken as Figure 2 another example of the power consumption control circuit 240 shown. The other reference voltage circuit 210, charge pump 220, charge pump detection circuit 230, and charge pump voltage dividing circuit 260 are the same. Therefore, in Figure 4A the embodiments shown, the repeated description of these components is omitted.

[0086] Specifically, as Figure 4AAs shown, the energy storage circuit 240b includes a capacitor C1 and a switch S1. The switch S1 is located between the capacitor C1 and the reference voltage circuit 210. After the output voltage Vcp generated by the charge pump 220 reaches the target value Vtag, the switch S1 is used to stop the operation of the reference voltage circuit 210, disconnect the capacitor C1 from the reference voltage circuit 210, and maintain the reference voltage Vref on the charged capacitor C1.

[0087] In some embodiments, the charge pump detection circuit 230 is further configured to, when detecting that the output voltage Vcp is lower than the preset value Vmin, resume the operation of the reference voltage circuit 210 and the charge pump 220, and end the stop operation of the reference voltage circuit 210 in the first time period.

[0088] That is, from the time when the reference voltage circuit 210 stops operating and the reference voltage Vref is provided by the capacitor C1 until the output voltage Vcp of the charge pump 220 is too low and the reference voltage circuit 210 resumes operation, this period of time is equivalent to the first time period Td in the delay of the semiconductor device 200a. Therefore, under the implementation of the energy storage circuit 240b in the semiconductor device 200b, there is also a delay of the first time period Td' equivalent to the aforementioned first time period Td, that is, the reference voltage circuit 210 stops operating within the first time period Td'. Different from the delay control circuit 240a, in this example, the length of the first time period Td' depends on whether the output voltage Vcp of the charge pump 220 is too low, and thus depends on the power consumption of the load of the charge pump 220. However, it can be understood that in some embodiments, it may not depend on the power consumption of the load of the charge pump 220, but on the leakage degree of the charge pump 220 itself, or other various possible factors.

[0089] In some embodiments, when the charge pump detection circuit 230 detects that the output voltage Vcp is lower than the preset value Vmin, it will first make the reference voltage circuit 210 operate, and after turning on the switch S1 for a third time period, that is, after the reference voltage Vref is stabilized, it will then make the charge pump 220 operate.

[0090] Of course, in some embodiments, the reference voltage circuit 210, the charge pump 220, the charge pump detection circuit 230, and the switch S1 can also be made to start operating and conducting simultaneously.

[0091] In some embodiments, the charge pump detection circuit 230 is further configured to, when detecting that the output voltage Vcp reaches the target value Vtag, stop the operation of the reference voltage circuit 210 and the charge pump 220, disconnect the switch S1, and start another cycle of reference voltage maintenance. Specifically, asFigure 4B as shown Figure 4B display Figure 4A the relevant voltage timing diagram of the semiconductor device 200b shown. In Figure 4B it, timing T0 represents that the reference voltage circuit 210 starts to power on, generates the original reference voltage Vref0, the switch S1 is also closed and conducts, and the capacitor C1 starts to be charged to generate the reference voltage Vref. After the reference voltage Verf is stable, the charge pump 220 is started by the enable signal PUMP_EN and starts to establish Vcp. Timing T1 represents that the output voltage Vcp of the charge pump 220 reaches the target value Vtag, so that the reference voltage circuit 210 and the charge pump 220 stop working, the switch S1 is disconnected, and a cycle of reference voltage maintenance (equivalent to the delay in the previous embodiment) starts. It should be understood here that the time intervals of each timing T1 / T2 / T3, etc. in the figure do not represent actual time, but are only used to represent the sequence, and the waveforms shown are schematic diagrams and do not represent the real rise and fall rates.

[0092] When the output voltage Vcp of the charge pump 220 decreases gradually after being output to the load, by timing T2, the charge pump detection circuit 230 detects that it is lower than the preset value Vmin, so that the reference voltage circuit 210 and the charge pump 220 resume working, and the reference voltage circuit 210 ends the stop working in the first time period Td'. Since when resuming work, the reference voltage circuit 210 will work first to generate the original reference voltage Vref0, and after the switch S1 is conducted for a third time period, the charge pump 220 will work, so the charge pump enable signal PUMP_EN will be sent out one third time period later than timing T2, and the charge pump 220 will resume working some time later than timing T2, that is, timing T3.

[0093] In some embodiments, the enable signal PUMP_EN of the charge pump detection circuit 230 can also be started simultaneously with the reference voltage circuit 210 and the switch S1. At this time, Figure 4B the rising edge of PUMP_EN in it is simultaneous with timing T2, rather than Figure 4B being delayed by one third time period as shown, this is not shown separately, but only explained here.

[0094] After the charge pump 220 and the reference voltage circuit 210 both resume working, that is, when the output voltage Vcp reaches the target value Vtag, the reference voltage circuit 210 and the charge pump 220 are stopped working again, the switch S1 is disconnected, and another cycle of reference voltage maintenance starts, that is, enters timing NT1.

[0095] In Figure 4BIn it, the operations of the capacitor C1 and the switch S1 at the time sequences T1 and T2 are shown together. S1_C represents that the switch is closed and conducting, and S1_O represents that the switch is open. Also, in some embodiments, since the charge pump detection circuit 230 is used to perform low-voltage detection on the charge pump 220 instead of detecting whether the reference voltage is too low, the refresh (i.e., resuming operation) of the reference voltage circuit 210 will be arranged to be refreshed when the charge pump is refreshed.

[0096] However, it can be understood that because the charge pump has a relatively high chance of leakage and the reference voltage circuit has relatively less leakage, in some embodiments, the charge pump detection circuit can also be configured to, when detecting that the output voltage is lower than a preset value, first make the charge pump work for refreshing, and if the output voltage is still lower than the preset value, then make the reference voltage circuit start to work for refreshing, that is, one start-stop cycle.

[0097] In this way, the first time period Td' will last for a relatively long time. For example, it lasts for multiple detection cycles of the charge pump detection circuit or after the charge pump experiences multiple stop and start cycles, the first time period Td' ends. Therefore, the start-stop cycle (refresh frequency) of the charge pump will be more than that of the reference voltage circuit 210. That is, for example, the charge pump start-stop cycle is executed N times and the reference voltage circuit start-stop cycle is executed once, where N is a positive integer greater than or equal to 1. It can be understood that this is because the leakage of the reference voltage circuit is small and also because of the voltage maintaining effect brought by the energy storage device 240b.

[0098] Of course, in some embodiments, it is not necessary to use "first make the charge pump work for refreshing, and if the output voltage is still lower than the preset value" as the premise for refreshing the reference circuit. Instead, based on the low leakage of the reference voltage, it can be directly set that the charge pump is refreshed (the start-stop cycle is executed) N times and the reference is refreshed (the start-stop cycle is executed) once.

[0099] Also, in some embodiments, when the charge pump is in the working state, the charge pump detection circuit will also be in the working state. However, as described above, this detection can be intermittent detection or continuous detection.

[0100] The above control of the switch S1 and the reference voltage circuit 210, although Figure 4A the relevant control signal connections are not shown in, those skilled in the art can understand that these control signals can be issued by the charge pump detection circuit 230, or can be performed through, for example, the logic control unit 415 in the memory 400, or other control units in the voltage generator 414, the semiconductor devices 200a / 200b. Therefore, not being specially marked does not affect the implementation of the embodiments of this application.

[0101] In some embodiments, the semiconductor device 200a / 200b further includes a charge pump voltage dividing circuit 260 for taking out the output voltage Vcp of the charge pump 220 and supplying it to the charge pump detection circuit 230. Specifically, as Figure 3A shown in Figure 4A FIG. Figure 4A , the charge pump detection circuit 230 can obtain the output voltage Vcp of the charge pump 220 through a charge pump voltage dividing circuit 260. This charge pump voltage dividing circuit 260 can also be obtained by resistor voltage division, but it can also be any other device that can generate voltage division, and is not limited herein.

[0102] Similarly, through the setting of the energy storage circuit 240b described above, in the standby mode, by periodically operating the reference voltage circuit 210 and the charge pump 220, that is, by periodically refreshing the reference voltage Vref and the output voltage Vcp, lower standby power consumption can be obtained, thereby achieving the purpose of power consumption control.

[0103] Compared with the semiconductor device exemplified by the memory above, the embodiments of the present application further provide an operation method of a semiconductor device, as Figure 5 shown in Figure 5 FIG. Figure 5 , which shows an exemplary step diagram in the operation method of a semiconductor device according to an embodiment of the present application.

[0104] The operation method of the semiconductor device according to the embodiment of the present application includes:

[0105] Generating a reference voltage through a reference voltage circuit (S11);

[0106] Generating an output voltage through a charge pump according to the reference voltage (S12); and

[0107] Detecting the output voltage of the charge pump and stopping the operation of the reference voltage circuit in a first time period (S13).

[0108] In some embodiments, the step of stopping the operation of the reference voltage circuit in the first time period includes: after the output voltage Vcp reaches the target value Vtag, starting the delay of the first time period and stopping the operation of the reference voltage circuit 210 within the first time period Td.

[0109] In some embodiments, the method further includes, after the delay of the first time period ends, first starting the reference voltage circuit 210, and after a second time period T2_3, detecting whether the output voltage Vcp meets the requirements through the charge pump detection circuit 230.

[0110] In some embodiments, the method further includes: when the charge pump detection circuit 230 detects that the output voltage Vcp is not lower than the preset value Vmin, suspending the operation of the reference voltage circuit 210 and the charge pump 220, starting the delay of the first time period, and causing the reference voltage circuit 210 to repeat the stop operation of the first time period Td.

[0111] In some embodiments, the method further includes: when the charge pump detection circuit 230 detects that the output voltage Vcp of the charge pump 220 is lower than the preset value Vmin, causing the charge pump 220 to start working.

[0112] In some embodiments, the step of causing the reference voltage circuit to stop working within the first time period includes: maintaining the reference voltage Vref through the energy storage circuit 240b, and when the output voltage Vcp reaches the target value Vtag, causing the reference voltage circuit 210 to stop working.

[0113] In some embodiments, the step of maintaining the reference voltage through the energy storage circuit includes: receiving and maintaining the reference voltage Vref through a switch S1 and a capacitor C1, and when the output voltage Vcp reaches the target value Vtag, disconnecting the switch S1.

[0114] In some embodiments, the method further includes: when the charge pump detection circuit 230 detects that the output voltage Vcp is lower than the preset value Vmin, causing the reference voltage circuit 210 and the charge pump 220 to start working, and causing the reference voltage circuit 210 to end the stop operation of the first time period Td.

[0115] In some embodiments, the step of causing the reference voltage circuit and the charge pump to start working when the charge pump detection circuit detects that the output voltage is lower than the preset value includes: the reference voltage circuit 210 starts working first, and after conducting the switch S1 for a third time period, the charge pump 220 starts working.

[0116] For the specific content of the steps of the above operation methods, reference can be made to the corresponding description of the semiconductor devices 200a / 200b before, and thus it can be understood; therefore, it will not be repeated here, but only the key points will be described.

[0117] Through the operation method of the semiconductor device shown in the embodiments of the present application, in the standby mode, by periodically resuming the operation of the reference voltage circuit 210 and the charge pump 220, that is, by periodically refreshing the reference voltage Vref and the output voltage Vcp, lower standby power consumption can be obtained, and the purpose of power consumption control can be achieved. Moreover, the reference voltage detection circuit is omitted, which can reduce the chip area and power consumption.

[0118] Finally, refer to Figure 6 , Figure 6 which shows a schematic block diagram of an exemplary electronic system 100 having a memory system 110 disclosed in accordance with some embodiments of the present application. The electronic system 100 can be, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0119] As Figure 6 shown, the above-mentioned electronic system 100 can at least include a storage system 110 and a host 120. The storage system 110 has a controller 111 and one or more memories 112. The memory 112 can be the semiconductor device 400 as described above. The host 120 can be a processor of the electronic device (e.g., a central processing unit, CPU) or a system on a chip (SoC) (e.g., an application processor, AP). Specifically, the host 120 can be configured to send data to the memory 112 or receive data from the memory 112.

[0120] According to some embodiments, the controller 111 is coupled to the memory 112 and the host 120 and is configured to control the memory 112. Further, the controller 111 can manage the data stored in the memory 112 and communicate with the host 120. In some embodiments, the controller 111 is designed to operate in a low duty cycle environment, which can be a universal serial bus (USB) flash drive or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0121] The controller 111 can communicate with an external device (e.g., the host 120) according to a specific communication protocol. For example, the controller 111 can communicate with the external device through at least one of various interface protocols, which can be, for example, the Universal Serial Bus (USB) protocol, the Multimedia Card (MMC) protocol, the Peripheral Component Interconnect (PCI) protocol, the Peripheral Component Interconnect Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Device Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, and the FireWire interface protocol, etc.

[0122] A storage system provided by some embodiments of the present application has the same beneficial effects as the above-mentioned memory 112 or semiconductor device 400.

[0123] The semiconductor device, its operation method, and the memory system provided by the present application are configured such that the voltage generator or the semiconductor device includes: a reference voltage circuit for generating a reference voltage; a charge pump for generating an output voltage according to the reference voltage; a charge pump detection circuit for detecting the output voltage of the charge pump; and a power consumption control circuit for stopping the operation of the reference voltage circuit in a first time period. That is, in the standby mode, by periodically resuming the operation of the reference voltage circuit 210 and the charge pump 220 and periodically refreshing the reference voltage Vref and the output voltage Vcp, a lower standby power consumption can be obtained, thereby achieving the purpose of power consumption control. Moreover, the reference voltage detection circuit is omitted, which can reduce the chip area and power consumption.

[0124] In summary, although the present application has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that, the semiconductor device includes: a reference voltage circuit for generating a reference voltage; a charge pump for generating an output voltage according to the reference voltage; a charge pump detection circuit for detecting the output voltage of the charge pump; and a power consumption control circuit for stopping the operation of the reference voltage circuit in a first time period.

2. The semiconductor device according to claim 1, characterized in that, the power consumption control circuit includes a delay control circuit for starting the delay of the first time period after the output voltage reaches a target value, so that the reference voltage circuit stops operating within the first time period.

3. The semiconductor device according to claim 2, characterized in that, after the delay of the delay control circuit ends in the first time period, the reference voltage circuit is first started, and after a second time period, the charge pump detection circuit is used to detect whether the output voltage meets the requirements.

4. The semiconductor device according to claim 3, characterized in that, the charge pump detection circuit further includes a circuit for, when detecting that the output voltage is not lower than a preset value, continuing to pause the operation of the reference voltage circuit and the charge pump, and starting the delay of the first time period; and when detecting that the output voltage of the charge pump is lower than the preset value, starting the operation of the charge pump.

5. The semiconductor device according to claim 1, characterized in that, the detection of the output voltage by the charge pump detection circuit includes either discontinuous detection or continuous detection.

6. The semiconductor device according to claim 1, characterized in that, the power consumption control circuit includes an energy storage circuit for stopping the operation of the reference voltage circuit for one first time period after the output voltage reaches the target value and maintaining the reference voltage.

7. The semiconductor device according to claim 6, characterized in that, the energy storage circuit includes: a capacitor for maintaining the reference voltage; and a switch located between the capacitor and the reference voltage circuit for disconnecting the capacitor from the reference voltage circuit after the output voltage reaches the target value.

8. The semiconductor device according to claim 2 or 7, characterized in that, the charge pump detection circuit is further used for, when detecting that the output voltage is lower than the preset value, starting the operation of the reference voltage circuit and the charge pump, so that the reference voltage circuit ends the stop operation of the first time period; or first starting the operation of the reference voltage circuit, and after conducting the switch for a third time period, starting the operation of the charge pump.

9. The semiconductor device according to claim 2 or 6, characterized in that, after the charge pump stops operating in the first time period, it starts operating earlier than the reference circuit.

10. The semiconductor device according to claim 9, characterized in that, the charge pump start-stop cycle is executed N times, and the reference voltage circuit start-stop cycle is executed 1 time, where N is a positive integer greater than or equal to 1.

11. An operation method of a semiconductor device, characterized in that, the operation method includes: generating a reference voltage through a reference voltage circuit; Generate an output voltage through a charge pump based on the reference voltage; and, Detect the output voltage of the charge pump and cause the reference voltage circuit to stop operating for a first time period.

12. The method for operating a semiconductor device according to claim 1, wherein, The step of causing the reference voltage circuit to stop operating for a first time period includes starting a delay of the first time period after the output voltage reaches a target value, and causing the reference voltage circuit to stop operating within the first time period.

13. The method for operating a semiconductor device according to claim 12, wherein, The method further includes, after the delay of the first time period ends, first starting the reference voltage circuit, and after a second time period, detecting whether the output voltage meets the requirements through the charge pump detection circuit.

14. The method for operating a semiconductor device according to claim 13, wherein, The method further includes, when the charge pump detection circuit detects that the output voltage is not lower than a preset value, causing the reference voltage circuit and the charge pump to pause operation, starting a delay of the first time period, causing the reference voltage circuit to repeat stopping operation in the first time period, and when the output voltage of the charge pump is lower than the preset value, causing the charge pump to start operating.

15. The method for operating a semiconductor device according to claim 13, wherein, The step of detecting the output voltage of the charge pump includes one of intermittent detection and continuous detection.

16. The method for operating a semiconductor device according to claim 11, wherein, The step of causing the reference voltage circuit to stop operating for a first time period includes: maintaining the reference voltage through an energy storage circuit, and after the output voltage reaches a target value, causing the reference voltage circuit to stop operating for one first time period.

17. The method for operating a semiconductor device according to claim 16, wherein, The step of maintaining the reference voltage through an energy storage circuit includes: receiving and maintaining the reference voltage through a switch and a capacitor, and after the output voltage reaches a target value, disconnecting the switch.

18. The method for operating a semiconductor device according to claim 12 or 17, wherein, The method further includes: when the charge pump detection circuit detects that the output voltage is lower than a preset value, causing the reference voltage circuit and the charge pump to start operating, and ending the stop operation of the reference voltage circuit in the first time period; or, causing the reference voltage circuit to start operating first, and after conducting the switch for a third time period, then causing the charge pump to operate.

19. The method for operating a semiconductor device according to claim 12 or 16, wherein, The method further includes: after stopping operation in the first time period, causing the charge pump to start operating earlier than the reference circuit, and causing the charge pump start-stop cycle to be executed N times, and the reference voltage circuit start-stop cycle to be executed 1 time, where N is a positive integer greater than or equal to 1.

20. A memory system, wherein, Comprises: A semiconductor device according to any one of claims 1 to 10; and a controller configured to control the semiconductor device.

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