Memory device, operating method thereof, memory system, and sensing circuit

Abstract

The embodiment of the invention provides a memory device, an operating method thereof, a memory system and a sensing circuit. The memory device includes: a memory cell array; a first sensing circuit coupled to the memory cell array through a first data line pair; a second sensing circuit coupled to the first data line pair through a second data line pair; an isolation circuit between the first data line pair and the second data line pair; the control circuit is configured as follows: in a first sensing stage, the first sensing circuit is controlled to amplify a data signal to a first sensing signal, and the isolation circuit is controlled to connect the first data line pair and the second data line pair; in a second sensing stage and a pre-charging stage after the second sensing stage, the isolation circuit is controlled to disconnect the first data line pair and the second data line pair, and in the second sensing stage, the second sensing circuit is controlled to amplify the first sensing signal to a second sensing signal; in the pre-charging stage, the second sensing circuit is controlled to charge the second data line pair to a pre-charging voltage.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and particularly to a memory device, an operation method thereof, a memory system, and a sensing circuit. Background Art

[0002] Memory devices and their systems are storage devices used to store information in modern information technology. As people's requirements for storage devices continue to increase, there is much room for improvement in memory devices and their systems. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a memory device, an operation method thereof, a memory system, and a sensing circuit.

[0004] In a first aspect, embodiments of the present application provide a memory device including: a memory cell array; a first sensing circuit, which is coupled to the memory cell array through a first data line pair and is configured to amplify a data signal received from the memory cell array to a first sensing signal; a second sensing circuit, which is coupled to the first data line pair through a second data line pair and is configured to amplify the first sensing signal to a second sensing signal; an isolation circuit located between the first data line pair and the second data line pair; and a control circuit, which is coupled to the first sensing circuit, the second sensing circuit, and the isolation circuit and is configured to: in a first sensing stage, control the first sensing circuit to amplify the data signal to the first sensing signal, and control the isolation circuit to connect the first data line pair and the second data line pair to transmit the first sensing signal to the second data line pair; in a second sensing stage after the first sensing stage and a precharging stage after the second sensing stage, control the isolation circuit to disconnect the first data line pair and the second data line pair, and in the second sensing stage, control the second sensing circuit to amplify the first sensing signal to the second sensing signal, and in the precharging stage, control the second sensing circuit to charge the second data line pair to a precharging voltage.

[0005] In some embodiments, the control circuit is further configured to: in a precharging stage before the first sensing stage, control the isolation circuit to disconnect the first data line pair and the second data line pair, and control the first sensing circuit to charge the first data line pair to a precharging voltage.

[0006] In some embodiments, the control circuit includes an isolation signal generation circuit, which is configured to: receive a first pulse signal and a first sensing enable signal, and output an isolation signal according to the first pulse signal and the first sensing enable signal; the isolation circuit is configured to receive the isolation signal and connect or disconnect the first data line pair and the second data line pair based on the isolation signal.

[0007] In some embodiments, the isolation signal generation circuit includes: a pulse cancellation circuit; the pulse cancellation circuit is configured to, in response to the first pulse signal switching to the inactive state, the output isolation signal starts to be in the first logic state; in response to the first sense enable signal switching to the enable state, the output isolation signal switches from the first logic state to the second logic state; the isolation circuit is configured to, in response to the isolation signal being in the first logic state, connect the first data line pair and the second data line pair, or, in response to the isolation signal being in the second logic state, disconnect the first data line pair and the second data line pair.

[0008] In some embodiments, the pulse cancellation circuit includes: a pulse generation circuit and an RS latch; the input terminal of the pulse generation circuit receives the first pulse signal, and the output terminal outputs a second pulse signal; when the first pulse signal switches to the inactive state, the second pulse signal is in the second logic state; the reset terminal of the RS latch receives the second pulse signal, the set terminal receives the delayed signal corresponding to the first sense enable signal, and the output terminal outputs the isolation signal.

[0009] In some embodiments, the control circuit further includes: a first precharge signal generation circuit, a second precharge signal generation circuit, and a second sense enable signal generation circuit; the first precharge signal generation circuit is configured to: generate a first precharge signal according to the first pulse signal; the second precharge signal generation circuit is configured to: generate a second precharge signal according to the first sense enable signal; the second sense enable signal generation circuit is configured to: generate a second sense enable signal according to the first sense enable signal; the first sense circuit includes: a first sense amplifier and a first precharge circuit; the second sense circuit includes: a second sense amplifier and a second precharge circuit; in the precharge stage before the first sense stage, the first precharge circuit is configured to receive the first precharge signal and, in response to the first precharge signal being in the active state, charge the first data line pair to the precharge voltage; in the first sense stage, the first sense amplifier is configured to, after the first data line pair is charged, amplify the data signal to the first sense signal; in the second sense stage, the second sense amplifier is configured to receive the second sense enable signal and, in response to the second sense enable signal being in the enable state, amplify the first sense signal to the second sense signal; in the precharge stage after the second sense stage, the second precharge circuit is configured to, in response to the second precharge signal being in the active state, charge the second data line pair to the precharge voltage.

[0010] In some embodiments, the first pre-charge signal generation circuit includes: two first inverters connected in series; the input terminals of the two inverters connected in series receive a first pulse signal, and the output terminal outputs a first pre-charge signal; the second sense enable signal generation circuit includes: a first delay circuit and two second inverters connected in series; the input terminal of the first delay circuit receives a first sense enable signal, the output terminal is connected to the input terminals of the two second inverters connected in series, and the output terminals of the two second inverters connected in series output a second sense enable signal; the second pre-charge signal generation circuit includes: a second delay circuit, a third delay circuit, an OR-NOT gate, a third inverter, and a fourth inverter; the input terminal of the second delay circuit receives a first sense enable signal, the output terminal is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the input terminal of the third delay circuit, the first input terminal of the OR-NOT gate is connected to the output terminal of the third delay circuit, the second input terminal of the OR-NOT gate is connected to the output terminal of the second delay circuit, the output terminal of the OR-NOT gate is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter outputs a second pre-charge signal.

[0011] In some embodiments, the first data line pair includes a first sense output line and a first complementary sense output line; the second data line pair includes a second sense output line and a second complementary sense output line; the first sense amplifier and the first pre-charge circuit are both coupled between the first sense output line and the first complementary sense output line; the second sense amplifier and the second pre-charge circuit are both coupled between the second sense output line and the second complementary sense output line.

[0012] In some embodiments, the isolation circuit includes a first transistor coupled between the first sense output line and the second sense output line and a second transistor coupled between the first complementary sense output line and the second complementary sense output line; the gates of the first transistor and the second transistor are both connected and receive an isolation signal.

[0013] In some embodiments, the memory device further includes: a column decoding circuit; the column decoding circuit is coupled between the first data line pair and the bit line pair of the memory cell array, and is configured to receive a column decoding signal and control the connection or disconnection between the first sense output line pair and the bit line pair of the memory cell array.

[0014] In some embodiments, the memory device of any one of the above embodiments includes a dynamic random access memory.

[0015] In a second aspect, an embodiment of the present application provides a memory system, including: one or more memory devices of any one of the embodiments in the first aspect; and a memory controller, which is coupled to the memory device and controls the memory device.

[0016] In a third aspect, an embodiment of the present application provides an operation method for a memory device, where the memory device includes: a memory cell array; a first sensing circuit coupled to the memory cell array through a first data line pair; a second sensing circuit coupled to the first data line pair through a second data line pair; an isolation circuit located between the first data line pair and the second data line pair; and the operation method includes: in a first sensing stage, controlling the first sensing circuit to amplify a data signal received from the memory cell array to a first sensing signal, and controlling the isolation circuit to connect the first data line pair and the second data line pair to transmit the first sensing signal to the second data line pair; in a second sensing stage after the first sensing stage and a pre-charging stage after the second sensing stage, controlling the isolation circuit to disconnect the first data line pair and the second data line pair, and in the second sensing stage, controlling the second sensing circuit to amplify the first sensing signal to a second sensing signal, and in the pre-charging stage, controlling the second sensing circuit to charge the second data line pair to a pre-charging voltage.

[0017] In some embodiments, the operation method further includes: in a pre-charging stage before the first sensing stage, controlling the isolation circuit to disconnect the first data line pair and the second data line pair, and controlling the first sensing circuit to charge the first data line pair to a pre-charging voltage.

[0018] In a fourth aspect, an embodiment of the present application provides a sensing circuit, including: a first sensing circuit coupled to an initial data line pair through a first data line pair; a second sensing circuit coupled to the first data line pair through a second data line pair; an isolation circuit located between the first data line pair and the second data line pair; and a control circuit coupled to the first sensing circuit, the second sensing circuit, and the isolation circuit and configured to: in a first sensing stage, control the first sensing circuit to amplify a data signal on the initial data line pair to a first sensing signal on the first data line pair, and control the isolation circuit to connect the first data line pair and the second data line pair to transmit the first sensing signal to the second data line pair; in a second sensing stage after the first sensing stage and a pre-charging stage after the second sensing stage, control the isolation circuit to disconnect the first data line pair and the second data line pair, and in the second sensing stage, control the second sensing circuit to amplify the first sensing signal transmitted to the second data line pair to a second sensing signal, and in the pre-charging stage, control the second sensing circuit to charge the second sensing signal of the second data line pair to a pre-charging voltage.

[0019] In each embodiment of the present application, during the operation of a multi-stage sense amplifier (including a first sensing circuit and a second sensing circuit), by improving the timing of the control signal, the control isolation circuit is made to disconnect the first data line pair and the second data line pair during the pre-charge stage after the second sensing stage, thereby eliminating the problem that it is difficult to reach the expected intermediate voltage level during the pre-charge stage due to the connection of the first data line pair and the second data line pair after the second sensing stage, and further making the performance of the memory device more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. is a schematic diagram of a memory device having a sensing circuit provided by an embodiment of the present application;

[0021] Figure 2 FIG. is a schematic diagram of an operation process of a sensing circuit provided by an embodiment of the present application;

[0022] Figure 3 FIG. is a schematic diagram of a control circuit of a first sensing circuit provided by an embodiment of the present application;

[0023] Figure 4 FIG. is a timing diagram of a first control circuit provided by an embodiment of the present application;

[0024] Figure 5 FIG. is a schematic diagram of a control circuit of a second sensing circuit provided by an embodiment of the present application;

[0025] Figure 6 FIG. is a timing diagram of a second control circuit provided by an embodiment of the present application;

[0026] Figure 7 FIG. is a schematic diagram of an isolation signal generation circuit provided by an embodiment of the present application;

[0027] Figure 8 FIG. is a schematic diagram of a pulse cancellation circuit provided by an embodiment of the present application;

[0028] Figure 9 FIG. is a schematic diagram of a first pre-charge signal generation circuit provided by an embodiment of the present application;

[0029] Figure 10 FIG. is a schematic diagram of a second pre-charge signal generation circuit provided by an embodiment of the present application;

[0030] Figure 11 FIG. is a schematic diagram of a second sense enable signal generation circuit provided by an embodiment of the present application;

[0031] Figure 12 FIG. is a schematic diagram of a pulse generation circuit provided by an embodiment of the present application;

[0032] Figure 13Schematic diagram of the delay circuit provided by the embodiment of the present application;

[0033] Figure 14 For Figure 5 Schematic diagram of another exemplary circuit arrangement of the control circuit;

[0034] Figure 15 For Figure 1 Schematic diagram of another exemplary circuit arrangement of the memory device;

[0035] Figure 16 Schematic diagram of the simulation timing of the first control circuit provided by the embodiment of the present application;

[0036] Figure 17 Schematic diagram of the simulation timing of the second control circuit provided by the embodiment of the present application;

[0037] Figure 18 Schematic diagram of the composition structure of the exemplary dynamic random access memory according to an embodiment of the present application;

[0038] Figure 19 Schematic diagram of a memory system provided by the embodiment of the present application. Detailed implementation manners

[0039] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the embodiments of the present application and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0040] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application may be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0041] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0042] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion. And when discussing the second element, component, region, layer, or portion, it does not imply that there must be a first element, component, region, layer, or portion in the present application.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0044] To fully understand the present application, detailed steps and detailed structures will be presented in the following description to explain the technical solutions of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.

[0045] Reference Figure 1 、 Figure 2 、 Figure 3 and Figure 4, an embodiment of the present application provides a memory device 10, including: a memory cell array 101; a first sensing circuit 102 coupled to the memory cell array 101 through a first data line pair DL / DL_N; a second sensing circuit 108 coupled to the first data line pair DL / DL_N through a second data line pair SSA_DL / SSA_DL_N; an isolation circuit 114 located between the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N; and a control circuit 301, the control circuit 301 is coupled to the first sensing circuit 102, the second sensing circuit 108 and the isolation circuit 114, and is configured to perform the following steps: S201, a pre-charge stage before the first sensing stage, pre-charge the first data line pair DL / DL_N to a first pre-charge voltage; S202, the first sensing stage, amplify the data signal received from the memory cell array 101 to a first sensing signal through the first sensing circuit 102, that is, establish a first voltage difference between the first data line pair DL / DL_N; S203, the second sensing stage, amplify the received first sensing signal to a second sensing signal through the second sensing circuit 108, that is, establish a second voltage difference between the second data line pair SSA_DL / SSA_DL_N; wherein, the second voltage difference is greater than the first voltage difference; S204, a pre-charge stage after the second sensing stage, pre-charge the second data line pair SSA_DL / SSA_DL_N to a second pre-charge voltage; S205, execute the above steps S201 to S204 to implement the operation process of the sensing circuit in the next cycle.

[0046] In the embodiment of the present application, the sense amplifier of the memory device 10 is a multi-stage sense amplifier (including a first sensing circuit and a second sensing circuit), which can accelerate the data reading from the first data line pair DL / DL_N to the second data line pair SSA_DL / SSA_DL_N (which can be understood as the Local Bank Data Line (LBDL)), and reduce the overall sensing voltage and delay of the memory bank of the memory device 10. The multi-stage sense amplifiers need to work together, which puts higher requirements on the matching of control signals and timing. The control signals of the multi-stage sense amplifiers can achieve better performance when correctly matched with the timing.

[0047] The operation process of the sense amplifier should occur step by step. For example, the pre-charge of the sense amplifier and the sense of the sense amplifier should occur step by step. Specifically, refer to Figure 1 and Figure 2, the first data line pair DL / DL_N is precharged, the data signal received from the memory cell array 101 is amplified to a first sense signal by the first sense circuit 102, the first sense signal received is amplified to a second sense signal by the second sense circuit 108, and the precharging of the second data line pair SSA_DL / SSA_DL_N should occur step by step. The control signal of the sense amplifier generated by the control circuit 301 is crucial, and the control signal can vary according to specific conditions, such as the process, voltage, and temperature conditions or the timing mismatch of the original signal.

[0048] Reference Figure 3 and Figure 4 , in some embodiments, the control circuit 301 includes: a first precharge signal generation circuit, an isolation signal generation circuit, a second sense enable signal generation circuit, and a second precharge signal generation circuit.

[0049] Reference Figure 3 , the isolation signal generation circuit includes: an OR gate 3018; the first terminal of the OR gate 3018 receives the signal of the first pulse signal ypulse after passing through the inverter 5042, the second terminal receives the delayed signal SA_enable_1 corresponding to the first sense enable signal SA_enable, and the output terminal outputs the isolation signal dl_rd_inv.

[0050] Generally, the first power supply voltage of the first sense circuit is 2*VDD1M (which can be understood as the first voltage difference of the first sense signal between the first data line pair DL / DL_N), and the first precharge voltage VDD1M of the first sense circuit is half of the first power supply voltage 2*VDD1M; the second precharge power supply voltage of the second sense circuit is 2*VDD2H (which can be understood as the second voltage difference of the second sense signal between the second data line pair SSA_DL / SSA_DL_N), and the second precharge voltage VDD1H of the second sense circuit is half of the second precharge power supply voltage 2*VDD2H; the first precharge voltage VDD1M and the first power supply voltage 2*VDD1M are both less than the second precharge voltage VDD2H.

[0051] Reference Figure 4 , in the precharge stage after the second sense stage, due to the timing mismatch of the input signal, the isolation signal dl_rd_inv is still at a logic low level ( Figure 4 the part shown by the dashed oval box EDL in 3 to time t 4During the time interval), the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N are both pre-charged. This situation may lead to unknown problems. The sense amplification in the first sensing stage of the first sensing circuit and the pre-charging of the second sensing circuit occur simultaneously. Moreover, the first power supply voltage 2*VDD1M of the first sensing circuit belongs to the medium voltage level, and the second pre-charging voltage VDD2H of the second sensing circuit belongs to the high voltage level. The first power supply voltage 2*VDD1M is less than the second pre-charging voltage VDD2H. Therefore, it is not easy for the second data line pair SSA_DL / SSA_DL_N to be pre-charged to the second pre-charging voltage VDD2H, and it is more difficult for the first power supply voltage 2*VDD1M of the first sensing circuit to be pre-charged than the second pre-charging voltage VDD2H of the second sensing circuit and VDD2H - δ (understood as the voltage within the allowable error range of the second pre-charging voltage VDD2H).

[0052] In view of this, embodiments of the present application provide a memory device, an operation method thereof, a memory system, and a sensing circuit, which can optimize the correct matching of the control signal and timing of the sense amplifier, so that the memory device achieves better performance.

[0053] Refer to Figure 1 、 Figure 2 、 Figure 5 and Figure 6, in a first aspect, an embodiment of the present application provides a memory device 10, including: a memory cell array 101; a first sensing circuit 102, the first sensing circuit 102 is coupled to the memory cell array 101 through a first data line pair DL / DL_N, and is configured to amplify the data signal received from the memory cell array 101 to a first sensing signal; a second sensing circuit 108, the second sensing circuit 108 is coupled to the first data line pair DL / DL_N through a second data line pair SSA_DL / SSA_DL_N, and is configured to amplify the first sensing signal to a second sensing signal; an isolation circuit 114, located between the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N; and a control circuit, the control circuit is coupled to the first sensing circuit 102, the second sensing circuit 108 and the isolation circuit 114, and is configured to: in a first sensing stage, control the first sensing circuit 102 to amplify the data signal to the first sensing signal, and control the isolation circuit 114 to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and transmit the first sensing signal to the second data line pair SSA_DL / SSA_DL_N; in a second sensing stage after the first sensing stage and a pre-charging stage after the second sensing stage, control the isolation circuit 114 to disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and in the second sensing stage, control the second sensing circuit 108 to amplify the first sensing signal to the second sensing signal, and in the pre-charging stage, control the second sensing circuit 108 to charge the second data line pair SSA_DL / SSA_DL_N to a pre-charging voltage.

[0054] In some embodiments, the memory device 10 includes a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random-Access Memory (SDRAM), or a Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM). In some embodiments, the memory device 10 may further include a Static Random-Access Memory (SRAM).

[0055] In the embodiment of the present application, in the pre-charging stage before the first sensing stage, in the time interval before the moment t 1 before; the first sensing stage, at the moment t 1 and t 2The time interval between; the second sensing stage, at time t 2 and t 3 The time interval between; the pre-charge stage after the second sensing stage, at time t 3 and t 5 The time interval between; the pre-charge stage before the first sensing stage of the next cycle, at time t 5 The time interval after, or, the pre-charge stage before starting the first sensing stage of the cycle at the time interval after time t 5 The time interval after. In some embodiments, the pre-charge stage after the second sensing stage includes a second sensing circuit pre-charge stage and a second sensing circuit pre-charge completion stage. The second sensing circuit pre-charge stage is the time interval between time t 3 and t 4 which is used to represent the time interval from the pre-charge start time to the completion time of the second sensing stage; the second sensing circuit pre-charge completion stage is the time interval between time t 4 and t 5 which is used to represent that there is a certain time interval between the start time of the pre-charge stage before the first sensing stage and the completion time of the second sensing circuit pre-charge stage.

[0056] In the embodiments of the present application, the logical states of the signals can be represented as logical state "0" and logical state "1". Logical state "0" and logical state "1" are respectively represented as logical low level and logical high level, or, respectively represented as logical high level and logical low level. Hereinafter, taking logical state "0" and logical state "1" being respectively represented as logical low level and logical high level as an example.

[0057] In the embodiments of the present application, during the operation of the multi-stage sense amplifier (including the first sensing circuit and the second sensing circuit), by improving the timing of the control signal, during the pre-charge stage after the second sensing stage, the control isolation circuit 114 disconnects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N. That is to say, during the pre-charge stage after the second sensing stage, the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N are isolated by the isolation circuit 114, thereby eliminating the problem that the pre-charge is difficult to reach the expected intermediate voltage level due to the connection of the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N during the pre-charge stage after the second sensing stage, and further making the performance of the memory device more stable.

[0058] Refer to Figure 1 、 Figure 2 、 Figure 5 and Figure 6, in some embodiments, the control circuit 501 is further configured to: in a pre-charging stage before the first sensing stage, control the isolation circuit 114 to disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and control the first sensing circuit 102 to charge the first data line pair DL / DL_N to a pre-charging voltage.

[0059] In this way, in the first sensing stage, the control isolation circuit 114 connects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, while in the pre-charging stage before the first sensing stage, the second sensing stage, and the pre-charging stage after the first sensing stage, the control isolation circuit 114 disconnects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N.

[0060] Exemplarily, in S201, the pre-charging stage before the first sensing stage, the control isolation circuit 114 disconnects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and controls the first sensing circuit 102 to charge the first data line pair DL / DL_N to the pre-charging voltage; in S202, the first sensing stage, the control isolation circuit 114 connects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, so that the first sensing signal of the first data line pair DL / DL_N is transmitted to the second data line pair SSA_DL / SSA_DL_N; in S203, the second sensing stage, the control isolation circuit 114 disconnects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and controls the second sensing circuit 108 to amplify the first sensing signal of the second data line pair SSA_DL / SSA_DL_N to a second sensing signal; in S204, the pre-charging stage after the second sensing stage, the control isolation circuit 114 disconnects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and controls the second sensing circuit 108 to charge the second data line pair DL / DL_N to the pre-charging voltage.

[0061] It should be noted that Figure 4 and Figure 6 the falling edge of the isolation signal dl_rd_inv shown in

[0062] In an embodiment of the present application, during the operation of a multi-stage sense amplifier (including a first sense circuit and a second sense circuit), by improving the timing of the control signal, only in the first sensing stage, the isolation circuit 114 is controlled to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N. In the pre-charge stage before the first sensing stage, in the second sensing stage, and in the pre-charge stage after the second sensing stage, the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N are isolated by the isolation circuit 114, thereby eliminating the problem that the pre-charge is difficult to reach the expected intermediate voltage level due to the connection of the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N in the pre-charge stage after the second sensing stage, and further making the performance of the memory device more stable.

[0063] Reference Figure 7 , in some embodiments, the control circuit 501 includes an isolation signal generation circuit 5012, and the isolation signal generation circuit 5012 is configured to: receive a first pulse signal ypulse and a first sense enable signal SA_enable, and output an isolation signal dl_rd_inv according to the first pulse signal ypulse and the first sense enable signal SA_enable; the isolation circuit 114 is configured to receive the isolation signal dl_rd_inv and connect or disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N based on the isolation signal dl_rd_inv.

[0064] In some specific embodiments, the first pulse signal ypulse is used to connect or disconnect the first sense output line pair and the bit line pair BL / BLN of the memory cell array. Exemplarily, the first pulse signal ypulse is used to connect the first sense output line pair and the bit line pair BL / BLN of the memory cell array in the first logic state, and the data signal of the memory cell array can be transmitted to the first sense circuit through the bit line pair BL / BLN; the first pulse signal ypulse is used to disconnect the first sense output line pair and the bit line pair BL / BLN of the memory cell array in the second logic state, and the data signal of the memory cell array cannot be transmitted to the first sense circuit through the bit line pair BL / BLN.

[0065] In some specific embodiments, the first sense enable signal SA_enable is used to enable or disable the second sense circuit. Exemplarily, the first sense enable signal SA_enable is used to enable the second sense circuit in the first logic state, and start the second sense circuit to amplify the received first sense signal to a second sense signal; the first sense enable signal SA_enable is used to disable the second sense circuit in the second logic state, and does not start the second sense circuit.

[0066] In some specific embodiments, the isolation signal dl_rd_inv generated at the rising edge of the first pulse signal ypulse is in a logic low level state, which is used to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N. The isolation signal dl_rd_inv generated at the rising edge of the first sense enable signal SA_enable is in a logic high level state, which is used to disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N.

[0067] In this way, in the time interval between time t 1 and t 2 and in the time interval between the rising edge of the first pulse signal ypulse and the rising edge of the first sense enable signal SA_enable, the isolation signal dl_rd_inv is in a logic low level state, which is used to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N. Outside the rising edge of the first pulse signal ypulse and outside the rising edge of the first sense enable signal SA_enable, the isolation signal dl_rd_inv is in a logic high level state, which is used to disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N.

[0068] Referring to Figure 8 , in some embodiments, the isolation signal generation circuit includes: a pulse cancellation circuit 5014; the pulse cancellation circuit 5014 is configured to, in response to the first pulse signal ypulse switching to an inactive state, the output isolation signal dl_rd_inv starts to be in a first logic state; in response to the first sense enable signal SA_enable switching to an enabled state, the output isolation signal dl_rd_inv switches from the first logic state to a second logic state; the isolation circuit 114 is configured to, in response to the isolation signal dl_rd_inv being in the first logic state, connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, or, in response to the isolation signal dl_rd_inv being in the second logic state, disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N.

[0069] Here, the first logical state represents the logical state "0", i.e., the logical low level, and the second logical state represents the logical state "1", i.e., the logical high level; the active state / non - active state of the first pulse signal ypulse is indicated by the logical state "0" / logical state "1" respectively; the enabled state / non - enabled state of the first sensing enable signal SA_enable is indicated by the logical state "1" / logical state "0" respectively.

[0070] Exemplarily, the pulse cancellation circuit 5014 is configured such that, in response to the first pulse signal ypulse switching from the logical state "0" to the logical state "1" (non - active state), the output isolation signal dl_rd_inv starts to be in the logical state "0" (the first logical state); in response to the first sensing enable signal SA_enable switching from the logical state "0" to the logical state "1" (enabled state), the output isolation signal dl_rd_inv switches from the logical state "0" to the logical state "1"; the isolation circuit 114 is configured such that, in response to the isolation signal dl_rd_inv being in the logical state "0", it connects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, or, in response to the isolation signal dl_rd_inv being in the logical state "1", it disconnects the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N.

[0071] Reference Figure 8 , in some embodiments, the pulse cancellation circuit 5014 includes: a pulse generation circuit 5016 and an RS latch 5018; the input terminal of the pulse generation circuit 5016 receives the first pulse signal ypulse, and the output terminal outputs a second pulse signal ypulse_1; when the first pulse signal ypulse switches to the non - active state, the second pulse signal ypulse_1 is in the second logical state; the reset terminal R of the RS latch 5016 receives the second pulse signal ypulse_1, the set terminal S receives the delayed signal SA_enable_1 corresponding to the first sensing enable signal SA_enable, and the output terminal outputs the isolation signal dl_rd_inv.

[0072] In some specific embodiments, reference Figure 12, the pulse generation circuit 5016 includes a third inverter 5038, a third delay circuit 5034, a NOR gate 5036, and a fourth inverter 5040; the input terminal of the third inverter 5038 receives the first sense enable signal SA_enable, the output terminal of the third inverter 5038 is connected to the input terminal of the third delay circuit 5034, the first input terminal of the NOR gate 5036 is connected to the output terminal of the third delay circuit 5034, the second input terminal of the NOR gate 5036 receives the first sense enable signal SA_enable, the output terminal of the NOR gate 5036 is connected to the input terminal of the fourth inverter 5040, and the output terminal of the fourth inverter 5040 outputs the second precharge signal dl_rd_en.

[0073] Exemplarily, the pulse generation circuit 5016 generates a second pulse signal ypulse_1 at the rising edge of the first pulse signal ypulse, and the second pulse signal ypulse_1 is in a logic high level state; the RS latch 5018 outputs the isolation signal dl_rd_inv in a logic low level state when the second pulse signal ypulse_1 is in a logic high level state, and outputs the isolation signal dl_rd_inv in a logic high level state when the delayed signal SA_enable_1 corresponding to the first sense enable signal SA_enable is in a logic high level state.

[0074] In this way, at time t 1 and t 2 In the time interval between, in the time interval between the rising edge of the first pulse signal ypulse and the rising edge of the first sense enable signal SA_enable, the isolation signal dl_rd_inv is in a logic low level state, used to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N. Outside the rising edge of the first pulse signal ypulse and outside the rising edge of the first sense enable signal SA_enable, the isolation signal dl_rd_inv is in a logic high level state, used to disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N.

[0075] Compared with Figure 3 The isolation signal generation circuit shown, in the embodiment of the present application, several logic gates need to be added to implement the control logic of the sense amplifier, and the cost of the several added logic gates is not significant. Regardless of how mismatched the timing between the first pulse signal ypulse and the first sense enable signal SA_enable is, the isolation circuit 114 is only at time t 1 and t 2The time interval therebetween, i.e., is opened during the time interval between the rising edge of the first pulse signal ypulse and the rising edge of the first sense enable signal SA_enable, to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N.

[0076] Reference Figure 9 、 Figure 10 and Figure 11 , in some embodiments, the control circuit 501 further includes: a first precharge signal generation circuit 5024, a second precharge signal generation circuit 5026, and a second sense enable signal generation circuit 5028; the first precharge signal generation circuit 5024 is configured to: generate a first precharge signal dlpe according to the first pulse signal ypulse; the second precharge signal generation circuit 5026 is configured to: generate a second precharge signal dl_rd_en according to the first sense enable signal SA_enable; the second sense enable signal generation circuit 5028 is configured to: generate a second sense enable signal dl_rd_oe according to the first sense enable signal SA_enable; the first sense circuit 102 includes: a first sense amplifier 104 and a first precharge circuit 106; the second sense circuit 108 includes: a second sense amplifier 112 and a second precharge circuit 110; during the precharge stage before the first sense stage, the first precharge circuit 106 is configured to receive the first precharge signal dlpe and charge the first data line pair DL / DL_N to the precharge voltage in response to the first precharge signal dlpe being in an active state; during the first sense stage, the first sense amplifier 104 is configured to amplify the data signal to a first sense signal after the charging of the first data line pair DL / DL_N is completed; during the second sense stage, the second sense amplifier 112 is configured to receive the second sense enable signal dl_rd_oe and amplify the first sense signal to a second sense signal in response to the second sense enable signal dl_rd_oe being in an enabled state; during the precharge stage after the second sense stage, the second precharge circuit 110 is configured to charge the second data line pair to the precharge voltage in response to the second precharge signal dl_rd_en being in an active state.

[0077] Reference Figure 9 、 Figure 10 and Figure 11, in some embodiments, the first pre-charge signal generation circuit 5024 includes: two first inverters 5042 and 5044 connected in series; the input ends of the two inverters 5042 and 5044 connected in series receive the first pulse signal ypulse, and the output ends output the first pre-charge signal dlpe; the second sense enable signal generation circuit 5026 includes: a first delay circuit and two second inverters 5046 and 5048 connected in series; the input end of the first delay circuit 5030 receives the first sense enable signal SA_enable, and the output end is connected to the input ends of the two second inverters 5046 and 5048 connected in series, and the output ends of the two second inverters 5046 and 5048 connected in series output the second sense enable signal dl_rd_oe; the second pre-charge signal generation circuit 5028 includes: a second delay circuit 5032, a third delay circuit 5034, a NOR gate 5036, a third inverter 5038, and a fourth inverter 5040; the input end of the second delay circuit 5032 receives the first sense enable signal SA_enable, and the output end is connected to the input end of the third inverter 5038, the output end of the third inverter 5038 is connected to the input end of the third delay circuit 5034, the first input end of the NOR gate 5036 is connected to the output end of the third delay circuit 5034, the second input end of the NOR gate 5036 is connected to the output end of the second delay circuit 5032, the output end of the NOR gate 5036 is connected to the input end of the fourth inverter 5040, and the output end of the fourth inverter 5040 outputs the second pre-charge signal dl_rd_en.

[0078] Hereinafter, the first delay circuit 5030, the second delay circuit 5032, and the third delay circuit 5034 may have the same or similar circuit structures. Exemplarily, with reference to Figure 13 , it may be composed of four NOR gates INV1, INV2, INV3, and INV4 connected in series.

[0079] Figure 14 For Figure 5 a schematic diagram of another exemplary circuit arrangement of the control circuit, Figure 5 the control circuit shown can be specifically set as Figure 14 the control circuit shown.

[0080] Figure 14 The fourth delay circuit 5031 shown in Figure 3 may have the same or similar circuit structure as the first delay circuit 5030, the second delay circuit 5032, or the third delay circuit 5034. It should be noted that Figure 3 the difference between the control circuit shown in Figure 14 and the control circuit shown in Figure 14 lies in the different isolation signal generation circuits. Figure 3The first precharge signal generation circuit, the second sense enable signal generation circuit, and the second precharge signal generation circuit shown can be respectively referred to Figure 14 for the first precharge signal generation circuit, the second sense enable signal generation circuit, and the second precharge signal generation circuit.

[0081] Figure 15 is Figure 1 a schematic diagram of another exemplary circuit arrangement of the memory device of. Refer to Figure 1 or Figure 15 , in some embodiments, the first data line pair DL / DL_N includes a first sense output line DL and a first complementary sense output line DL_N; the second data line pair SSA_DL / SSA_DL_N includes a second sense output line SSA_DL and a second complementary sense output line SSA_DL_N; the first sense amplifier 104 and the first precharge circuit 106 are both coupled between the first sense output line DL and the first complementary sense output line DL_N; the second sense amplifier 112 and the second precharge circuit 110 are both coupled between the second sense output line SSA_DL and the second complementary sense output line SSA_DL_N.

[0082] Refer to Figure 1 or Figure 15 , in some embodiments, the isolation circuit 114 includes a first transistor M1 coupled between the first sense output line DL and the second sense output line SSA_DL and a second transistor M2 coupled between the first complementary sense output line DL_N and the second complementary sense output line SSA_DL_N; the gates of the first transistor M1 and the second transistor M2 are both connected and receive an isolation signal dl_rd_inv.

[0083] Exemplarily, the first transistor M1 and the second transistor M2 are PMOS transistors, the isolation signal dl_rd_inv is in a logic low level state, and both the first transistor M1 and the second transistor M2 are turned on; the isolation signal dl_rd_inv is in a logic high level state, and both the first transistor M1 and the second transistor M2 are turned off.

[0084] Refer to Figure 15, in some embodiments, the first precharge circuit 106 includes a plurality of PMOS transistors Te1, Te2, Te3 coupled between the first sense output line DL and the second sense output line SSA_DL. The gates of the plurality of PMOS transistors Te1, Te2, Te3 are connected and receive the first precharge signal dlpe. The first sense amplifier 104 includes a first PMOS transistor Tp1, a second PMOS transistor Tp2, a first NMOS transistor Tn1, a second NMOS transistor Tn2 connected in a cross-coupled manner, and a third NMOS transistor Tn3 and a fourth NMOS transistor Tn4. The gate of the third NMOS transistor Tn3 receives the first precharge signal dlpe. The drain of the third NMOS transistor Tn3 is connected to the sources of the first NMOS transistor Tn1 and the second NMOS transistor Tn2. The source of the third NMOS transistor Tn3 is connected to the drain of the fourth NMOS transistor Tn4. The gate of the fourth NMOS transistor Tn4 receives the first sense enable signal SA_enable. The source of the fourth NMOS transistor Tn4 is connected to the ground reference voltage. The source terminals of the first PMOS transistor Tp1 and the second PMOS transistor Tp2 are connected to the power supply voltage. Wherein, the source of the first PMOS transistor Tp1 and the drain of the first NMOS transistor Tn1 are coupled to the first sense output line DL, and the source of the second PMOS transistor Tp2 and the drain of the second NMOS transistor Tn2 are coupled to the first complementary sense output line DL_N.

[0085] Exemplarily, in the precharge stage before the first sense stage, the first precharge signal dlpe is in the logic low level state, the third NMOS transistor Tn3 is in the open state, and the source terminals of the cross-coupled first NMOS transistor Tn1 and second NMOS transistor Tn2 are disconnected from the ground reference voltage, so that the first sense amplifier 104 is in the disabled state. At the same time, the first precharge circuit 106 is in the enabled state, and the first data line pair DL / DL_N is charged to the precharge voltage.

[0086] Exemplarily, in the first sense stage, both the first precharge signal dlpe and the first sense enable signal SA_enable are in the logic high level state. The third NMOS transistor Tn3 and the fourth NMOS transistor Tn4 are in the conducting state. The source terminals of the cross-coupled first PMOS transistor Tp1 and second PMOS transistor Tp2 receive the power supply voltage signal, and the source terminals of the first NMOS transistor Tn1 and the second NMOS transistor Tn2 receive the ground reference voltage signal, so that the first sense amplifier 104 is in the enabled state, and the data signal received by the first data line pair DL / DL_N is amplified to the first sense signal. At the same time, the first precharge circuit 106 is in the disabled state.

[0087] ReferenceFigure 15 , in some embodiments, the second pre - charge circuit 110 includes a plurality of PMOS transistors Te4, Te5, Te6 coupled between the first complementary sense output line DL_N and the second complementary sense output line SSA_DL_N. The gates of the plurality of PMOS transistors Te4, Te5, Te6 are connected and receive the second pre - charge signal dl_rd_en. The second sense amplifier 112 includes a third PMOS transistor Tp3, a fourth PMOS transistor Tp4, a fifth NMOS transistor Tn5, a sixth NMOS transistor Tn6 which are cross - coupled, and a seventh NMOS transistor Tn7 and an eighth NMOS transistor Tn8; the gate of the seventh NMOS transistor Tn7 receives the second pre - charge signal dl_rd_en, the drain of the seventh NMOS transistor Tn7 is connected to the sources of the fifth NMOS transistor Tn5 and the sixth NMOS transistor Tn6, and the source of the seventh NMOS transistor Tn7 is connected to the drain of the eighth NMOS transistor Tn8; the gate of the eighth NMOS transistor Tn8 receives the second sense enable signal dl_rd_oe, and the source of the eighth NMOS transistor Tn8 is connected to the ground reference voltage; the source terminals of the third PMOS transistor Tp3 and the fourth PMOS transistor Tp4 are connected to the power supply voltage: wherein, the source of the third PMOS transistor Tp3 and the drain of the fifth NMOS transistor Tn5 are coupled to the second sense output line SSA_DL, and the source of the fourth PMOS transistor Tp4 and the drain of the sixth NMOS transistor Tn6 are coupled to the second complementary sense output line SSA_DL_N.

[0088] Exemplarily, in the second sensing stage, both the second pre - charge signal dl_rd_en and the second sense enable signal dl_rd_oe are in the logic high level state. The third NMOS transistor Tn3 and the fourth NMOS transistor Tn4 are in the conducting state. The sources of the first PMOS transistor Tp1 and the second PMOS transistor Tp2 receive the power supply voltage signal, and the sources of the first NMOS transistor Tn1 and the second NMOS transistor Tn2 receive the ground reference voltage signal, so that the second sense amplifier 112 is in the enabled state, amplifying the first sense signal received by the second data line pair SSA_DL / SSA_DL_N to the second sense signal. At the same time, the second pre - charge circuit 110 is in the disabled state.

[0089] Exemplarily, in the pre-charge stage after the second sensing stage, the second pre-charge signal dl_rd_en is in a logic low state, the third NMOS transistor Tn3 is in an open state, and the source terminals of the cross-coupled first NMOS transistor Tn1 and second NMOS transistor Tn2 are disconnected from the ground reference voltage, so that the second sense amplifier 112 is in a disabled state. At the same time, the second pre-charge circuit 110 is in an enabled state, and the second data line pair SSA_DL / SSA_DL_N is charged to the pre-charge voltage.

[0090] Figure 16 The first control circuit provided by the embodiment of the present application ( Figure 3 The control circuit shown) of the simulation timing diagram. Figure 16 The timing diagram can be understood as being applied to Figure 3 The timing obtained from the control circuit shown. At time t 3 And t 5 Between the time intervals, that is, in the pre-charge stage after the second sensing stage, due to the timing mismatch of the input signals, the isolation signal dl_rd_inv is still in a logic low state, and the first data line pair DL / DL_N to the second data line pair SSA_DL / SSA_DL_N is in a connected state. During the enabling period of the second pre-charge signal dl_rd_en (the time interval between time t 3 To time t 4 Between the time intervals), it causes both the first data line pair DL / DL_N to the second data line pair SSA_DL / SSA_DL_N to be pre-charged, and it is difficult for the second sensing circuit to pre-charge the second data line pair SSA_DL / SSA_DL_N to VDD2H and VDD2H - δ, resulting in an obvious voltage difference in the second data line pair SSA_DL / SSA_DL_N in the time interval after time t 4 This situation may lead to unknown timing matching problems.

[0091] Figure 17 The second control circuit provided by the embodiment of the present application ( Figure 15 The control circuit shown) of the simulation timing diagram. Figure 17 The timing diagram can be understood as being applied to Figure 15 The timing obtained from the control circuit shown. Only at time t 2 And t 3The time interval therebetween, i.e., in the first sensing phase, the isolation circuit 114 is controlled to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N. In the pre-charging phase before the first sensing phase, in the second sensing phase, and in the pre-charging phase after the second sensing phase, the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N are isolated by the isolation circuit 114. At time t 3 and t 5 The time interval therebetween, i.e., in the pre-charging phase after the second sensing phase, the isolation signal dl_rd_inv is at a logic high level, the first data line pair DL / DL_N to the second data line pair SSA_DL / SSA_DL_N are in a disconnected state, and the second pre-charging signal dl_rd_en enables a time period (the time interval between time t 3 and time t 4 therebetween), only the second data line pair SSA_DL / SSA_DL_N are pre-charged, which will not cause the first data line pair DL / DL_N to the second data line pair SSA_DL / SSA_DL_N to be pre-charged. The second sensing circuit pre-charges the second data line pair SSA_DL / SSA_DL_N to VDD2H and VDD2H - δ. The problem of timing mismatch caused by the connection of the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N in the pre-charging phase after the second sensing phase is eliminated, the timing of the control signal of the sense amplifier generated by the control circuit 501 is improved, and the operation process of the sense amplifier is more reasonable.

[0092] Reference Figure 15 , in some embodiments, the memory device 10 further includes: a column decoding circuit 118; the column decoding circuit 118 is coupled between the first data line pair DL / DL_N and the bit line pair BL / BLN of the memory cell array, and is configured to receive a column decoding signal and control the connection or disconnection of the first sense output line pair DL / DL_N and the bit line pair BL / BLN of the memory cell array.

[0093] Hereinafter, the column decoding signal can be understood as the first pulse signal ypulse in the above embodiments.

[0094] Reference Figure 15 , in some embodiments, the column decoding circuit 118 includes a third transistor M3 coupled between the bit line BL and the first sense output line DL, and a fourth transistor M4 coupled between the complementary bit line BLN and the first complementary sense output line DL_N; the gates of the third transistor M3 and the fourth transistor M4 are both connected and receive the column decoding signal.

[0095] Exemplarily, the third transistor M3 and the fourth transistor M4 are NMOS transistors. When the column decoding signal is in the logic high level state / logic low level state, both the third transistor M3 and the fourth transistor M4 are turned on / turned off.

[0096] Reference Figure 15 , in some embodiments, the memory device 10 further includes other data control circuits 116: The other data control circuits 116 include a column selection circuit 120; The column selection circuit 120 is coupled between the second data line pair SSA_DL / SSA_DL_N and the local input / output line pair IO / IO_N, and is configured to receive a column selection signal and control the connection or disconnection between the second data line pair SSA_DL / SSA_DL_N and the local input / output line pair IO / IO_N.

[0097] Exemplarily, by the column selection signal, when the second data line pair SSA_DL / SSA_DL_N is connected to the local input / output line pair IO / IO_N, the outside world can read specific data information from the local input / output line pair IO / IO_N.

[0098] Reference Figure 15 , in some embodiments, the other data control circuits 116 further include: a write driver circuit 122; The write driver circuit 122 is coupled to the local input / output line pair IO / IO_N and is configured to receive a write enable signal and write an external data signal from the local input / output line pair IO / IO_N to the memory cell array.

[0099] In some embodiments, the memory device of any one of the above embodiments includes a dynamic random access memory.

[0100] Figure 18 It is a schematic diagram of the composition structure of an exemplary dynamic random access memory according to an embodiment of the present application. Figure 18 The right side of shows the circuit of the storage unit in the DRAM. The DRAM includes at least one DRAM chip (Die). Each DRAM chip includes a memory cell array. The memory cell array includes a plurality of memory cells 201 arranged in an array. Each memory cell 201 includes a transistor T (Transistor) and a capacitor C (Capacitor). The main principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cell array uses rows (Rows) and columns (Columns) to specify addresses. By specifying the intersection of a row and a column (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform operations such as reading, writing, or refreshing the data stored therein.

[0101] Figure 18 The left side shows the memory cell array and part of the peripheral circuits in the DRAM. It should be noted that the row decoding circuit responds to the address input to the row decoding circuit, selects the word line to select the row of memory cells to be accessed. The row decoding circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoding circuit selects one or more bit lines to input our output data into a part of the row of memory cells corresponding to the selected word line.

[0102] In the embodiments of the present application, during the operation of the multi-stage sense amplifier (including the first sense circuit and the second sense circuit), by improving the timing of the control signal, during the pre-charge stage after the first and second sense stages, the control isolation circuit disconnects the first data line pair and the second data line pair, thereby eliminating the problem that the pre-charge is difficult to reach the expected intermediate voltage level due to the connection of the first data line pair and the second data line pair during the pre-charge stage after the second sense stage. The timing of the control signal of the sense amplifier generated by the control circuit is improved, and further, the operation process of the sense amplifier of the memory device is made more reasonable and stable.

[0103] Reference Figure 19 Second, the embodiments of the present application provide a memory system 30, including: one or more memory devices 10 as described in any one of the embodiments of the first aspect; and a memory controller 20, which is coupled to the memory device 10 and controls the memory device 10.

[0104] In some embodiments, the memory device 10 includes DRAM, SDRAM or DDR4 SDRAM, SRAM. In some embodiments, the memory controller 20 can control the overall operation of the memory system 30, such as write operation, read operation and refresh operation. In some specific embodiments, the memory controller 20 is configured to store data in the memory device 10, or read the data stored in the memory device 10.

[0105] In some embodiments, the memory controller 20 is further configured to store various information (such as metadata information and mapping table) required for the operation of the memory system 30 in the memory device 10, and can access the non-volatile memory device based on the information stored in the memory device 10. Third, the embodiments of the present application provide an operation method of a memory device, the memory device 10, reference Figure 1 Or Figure 15, including: a memory cell array 101; a first sensing circuit 102 coupled to the memory cell array 101 through a first data line pair DL / DL_N; a second sensing circuit 108 coupled to the first data line pair DL / DL_N through a second data line pair SSA_DL / SSA_DL_N; an isolation circuit 114 located between the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N; the operation method includes: in a first sensing stage, controlling the first sensing circuit 102 to amplify the data signal received from the memory cell array to a first sensing signal, and controlling the isolation circuit 114 to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N to transmit the first sensing signal to the second data line pair SSA_DL / SSA_DL_N; in a second sensing stage after the first sensing stage and a pre-charging stage after the second sensing stage, controlling the isolation circuit 114 to disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and in the second sensing stage, controlling the second sensing circuit to amplify the first sensing signal to a second sensing signal, and in the pre-charging stage, controlling the second sensing circuit to charge the second data line pair to a pre-charging voltage.

[0106] In some embodiments, the operation method further includes: in a pre-charging stage before the first sensing stage, controlling the isolation circuit 114 to disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and controlling the first sensing circuit 102 to charge the first data line pair DL / DL_N to a pre-charging voltage.

[0107] The memory device used in the operation method of the memory device provided in the embodiments of the third aspect of the present application is the same as or similar to the memory device in the embodiments of the third aspect above. For the technical features not disclosed in detail in the embodiments of the present application, please refer to the memory device in the embodiments of the first aspect above for understanding, and will not be elaborated here.

[0108] In a fourth aspect, embodiments of the present application provide a sensing circuit, refer to Figure 1 or Figure 15, including: a first sensing circuit 102 coupled to an initial data line pair through a first data line pair DL / DL_N; a second sensing circuit 108 coupled to the first data line pair DL / DL_N through a second data line pair SSA_DL / SSA_DL_N; an isolation circuit 114 located between the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N; and a control circuit 501 coupled to the first sensing circuit 102, the second sensing circuit 108, and the isolation circuit 114, and configured to: in a first sensing stage, control the first sensing circuit 102 to amplify a data signal on the initial data line pair to a first sensing signal on the first data line pair DL / DL_N, and control the isolation circuit 114 to connect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N to transmit the first sensing signal to the second data line pair SSA_DL / SSA_DL_N; in a second sensing stage after the first sensing stage and a precharging stage after the second sensing stage, control the isolation circuit 114 to disconnect the first data line pair DL / DL_N and the second data line pair SSA_DL / SSA_DL_N, and in the second sensing stage, control the second sensing circuit to amplify the first sensing signal transmitted to the second data line pair SSA_DL / SSA_DL_N to a second sensing signal, and in the precharging stage, control the second sensing circuit 108 to charge the second sensing signal of the second data line pair SSA_DL / SSA_DL_N to a precharging voltage.

[0109] In some embodiments, the sensing circuit can be used for memory devices including DRAM, SDRAM or DDR4 SDRAM, SRAM.

[0110] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0111] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the specification and drawings of the present application under the inventive concept of the present application, or any direct / indirect application in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A memory device, characterized in that, comprising: a memory cell array; a first sensing circuit, which is coupled to the memory cell array through a first data line pair and is configured to amplify the data signal received from the memory cell array to a first sensing signal; a second sensing circuit, which is coupled to the first data line pair through a second data line pair and is configured to amplify the first sensing signal to a second sensing signal; an isolation circuit located between the first data line pair and the second data line pair; and a control circuit, which is coupled to the first sensing circuit, the second sensing circuit and the isolation circuit and is configured to: in a first sensing stage, control the first sensing circuit to amplify the data signal to the first sensing signal, and control the isolation circuit to connect the first data line pair and the second data line pair to transmit the first sensing signal to the second data line pair; in a second sensing stage after the first sensing stage and in a pre-charge stage after the second sensing stage, control the isolation circuit to disconnect the first data line pair and the second data line pair, and in the second sensing stage, control the second sensing circuit to amplify the first sensing signal to the second sensing signal, and in the pre-charge stage, control the second sensing circuit to charge the second data line pair to a pre-charge voltage.

2. The memory device according to claim 1, characterized in that, the control circuit is further configured to: in a pre-charge stage before the first sensing stage, control the isolation circuit to disconnect the first data line pair and the second data line pair, and control the first sensing circuit to charge the first data line pair to the pre-charge voltage.

3. The memory device according to claim 2, characterized in that, the control circuit includes an isolation signal generation circuit, and the isolation signal generation circuit is configured to: receive a first pulse signal and a first sensing enable signal, and output an isolation signal according to the first pulse signal and the first sensing enable signal; the isolation circuit is configured to receive the isolation signal and connect or disconnect the first data line pair and the second data line pair based on the isolation signal.

4. The memory device according to claim 3, characterized in that, the isolation signal generation circuit includes: a pulse cancellation circuit; the pulse cancellation circuit is configured to, in response to the first pulse signal switching to an inactive state, the output isolation signal starts to be in a first logic state; in response to the first sensing enable signal switching to an enabled state, the output isolation signal switches from the first logic state to a second logic state; the isolation circuit is configured to, in response to the isolation signal being in the first logic state, connect the first data line pair and the second data line pair, or, in response to the isolation signal being in the second logic state, disconnect the first data line pair and the second data line pair.

5. The memory device according to claim 4, characterized in that, The pulse elimination circuit includes: a pulse generation circuit and an RS latch; The input end of the pulse generation circuit receives the first pulse signal, and the output end outputs a second pulse signal; when the first pulse signal switches to the non-active state, the second pulse signal is in the second logic state; The reset end of the RS latch receives the second pulse signal, the set end receives the delayed signal corresponding to the first sense enable signal, and the output end outputs the isolation signal.

6. The memory device according to claim 3, wherein, The control circuit further includes: a first precharge signal generation circuit, a second precharge signal generation circuit, and a second sense enable signal generation circuit; The first precharge signal generation circuit is configured to: generate a first precharge signal according to the first pulse signal; the second precharge signal generation circuit is configured to: generate a second precharge signal according to the first sense enable signal; the second sense enable signal generation circuit is configured to: generate a second sense enable signal according to the first sense enable signal; The first sense circuit includes: a first sense amplifier and a first precharge circuit; the second sense circuit includes: a second sense amplifier and a second precharge circuit; In the precharge stage before the first sense stage, the first precharge circuit is configured to receive the first precharge signal and, in response to the first precharge signal being in the active state, charge the first data line pair to the precharge voltage; in the first sense stage, the first sense amplifier is configured to, after the first data line pair is charged, amplify the data signal to the first sense signal; In the second sense stage, the second sense amplifier is configured to receive the second sense enable signal and, in response to the second sense enable signal being in the enabled state, amplify the first sense signal to the second sense signal; in the precharge stage after the second sense stage, the second precharge circuit is configured to, in response to the second precharge signal being in the active state, charge the second data line pair to the precharge voltage.

7. The memory device according to claim 6, wherein, The first precharge signal generation circuit includes: two first inverters connected in series; the input ends of the two inverters connected in series receive the first pulse signal, and the output end outputs the first precharge signal; The second sense enable signal generation circuit includes: a first delay circuit and two second inverters connected in series; the input end of the first delay circuit receives the first sense enable signal, the output end is connected to the input ends of the two second inverters connected in series, and the output ends of the two second inverters connected in series output the second sense enable signal; The second pre-charge signal generating circuit includes: a second delay circuit, a third delay circuit, an OR-NOT gate, a third inverter, and a fourth inverter; an input end of the second delay circuit receives the first sensing enable signal, an output end thereof is connected to an input end of the third inverter, an output end of the third inverter is connected to an input end of the third delay circuit, a first input end of the OR-NOT gate is connected to an output end of the third delay circuit, a second input end of the OR-NOT gate is connected to an output end of the second delay circuit, an output end of the OR-NOT gate is connected to an input end of the fourth inverter, and an output end of the fourth inverter outputs the second pre-charge signal.

8. The memory device according to claim 6, wherein, the first data line pair includes a first sensing output line and a first complementary sensing output line; the second data line pair includes a second sensing output line and a second complementary sensing output line; the first sensing amplifier and the first pre-charge circuit are both coupled between the first sensing output line and the first complementary sensing output line; the second sensing amplifier and the second pre-charge circuit are both coupled between the second sensing output line and the second complementary sensing output line.

9. The memory device according to claim 8, wherein, the isolation circuit includes a first transistor coupled between the first sensing output line and the second sensing output line and a second transistor coupled between the first complementary sensing output line and the second complementary sensing output line; a gate of the first transistor and a gate of the second transistor are both connected and receive the isolation signal.

10. The memory device according to claim 1, wherein, the memory device further includes: a column decoding circuit; the column decoding circuit is coupled between the first data line pair and a bit line pair of the memory cell array, and is configured to receive a column decoding signal and control connection or disconnection between the first sensing output line pair and the bit line pair of the memory cell array.

11. The memory device according to any one of claims 1 to 10, wherein, the memory device includes a dynamic random access memory.

12. A memory system, wherein, includes: one or more memory devices according to any one of claims 1 to 11; and a memory controller, which is coupled to the memory device and controls the memory device.

13. An operation method of a memory device, wherein, the memory device includes: a memory cell array; a first sensing circuit coupled to the memory cell array through a first data line pair; a second sensing circuit coupled to the first data line pair through a second data line pair; an isolation circuit located between the first data line pair and the second data line pair; the operation method includes: In the first sensing stage, control the first sensing circuit to amplify the data signal received from the memory cell array to a first sensing signal, and control the isolation circuit to connect the first data line pair and the second data line pair to transmit the first sensing signal to the second data line pair; In the second sensing stage after the first sensing stage and in the pre-charging stage after the second sensing stage, control the isolation circuit to disconnect the first data line pair and the second data line pair, and in the second sensing stage, control the second sensing circuit to amplify the first sensing signal to a second sensing signal, and in the pre-charging stage, control the second sensing circuit to charge the second data line pair to a pre-charging voltage.

14. The operation method according to claim 13, wherein, the operation method further includes: In the pre-charging stage before the first sensing stage, control the isolation circuit to disconnect the first data line pair and the second data line pair, and control the first sensing circuit to charge the first data line pair to the pre-charging voltage.

15. A sensing circuit, wherein, comprising: A first sensing circuit coupled to an initial data line pair through a first data line pair; A second sensing circuit coupled to the first data line pair through a second data line pair; An isolation circuit located between the first data line pair and the second data line pair; and A control circuit coupled to the first sensing circuit, the second sensing circuit, and the isolation circuit, and configured to: In the first sensing stage, control the first sensing circuit to amplify the data signal on the initial data line pair to a first sensing signal on the first data line pair, and control the isolation circuit to connect the first data line pair and the second data line pair to transmit the first sensing signal to the second data line pair; In the second sensing stage after the first sensing stage and in the pre-charging stage after the second sensing stage, control the isolation circuit to disconnect the first data line pair and the second data line pair, and in the second sensing stage, control the second sensing circuit to amplify the first sensing signal transmitted to the second data line pair to a second sensing signal, and in the pre-charging stage, control the second sensing circuit to charge the second sensing signal of the second data line pair to a pre-charging voltage.

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