Memory system, operating method of memory system,

Abstract

The embodiment of the invention provides a memory system and an operation method thereof, electronic equipment and a storage medium. The memory system includes: a nonvolatile memory device including a plurality of memory cells, the plurality of memory cells including a target memory cell; and the memory controller is coupled with the nonvolatile memory device and is configured to execute a refresh operation on a memory unit adjacent to the target memory unit when the number of times of executing the write operation by the target memory unit within a preset duration is greater than a preset threshold value.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and particularly to a memory system, an operation method thereof, an electronic device, and a storage medium. Background Art

[0002] A non-volatile memory device is a storage device used to store information in modern information technology. Among them, flash memory, as a typical non-volatile semiconductor memory, has advantages such as high storage density, controllable production cost, appropriate programming / erasing speed, and retention characteristics, and has gradually become the mainstream product in the storage market.

[0003] Memory systems such as solid state drives (SSDs) used in personal computers and servers, and universal flash storage (UFS) used in mobile phones and various embedded systems, usually use flash memory as their permanent storage medium. Therefore, how to further improve the performance of the memory system has become an urgent problem in the industry. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure propose a memory system, an operation method thereof, an electronic device, and a storage medium. The memory system includes: a non-volatile memory device including a plurality of storage units, where the plurality of storage units include a target storage unit; and a memory controller coupled to the non-volatile memory device and configured to: when the number of write operations performed by the target storage unit within a preset duration is greater than a preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

[0005] In some embodiments, the memory controller is configured to: obtain the number of write operations performed by the target storage unit within the preset duration and the preset threshold; where different preset durations correspond to different preset thresholds.

[0006] In some embodiments, a first preset duration corresponds to a first preset threshold; the memory controller is further configured to: when the number of write operations performed by the target storage unit within the first preset duration is greater than the first preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

[0007] In some embodiments, a second preset duration corresponds to a second preset threshold; the second preset duration is greater than the first preset duration; the ratio between the first preset threshold and the first preset duration is a first ratio, and the ratio between the second preset threshold and the second preset duration is a second ratio, and the first ratio is greater than the second ratio; the memory controller is further configured to: when the number of write operations performed by the target storage unit within the first preset duration is less than or equal to the first preset threshold, obtain the number of write operations performed by the target storage unit within the second preset duration and the second preset threshold; wherein, when the number of write operations performed by the target storage unit within the second preset duration is greater than the second preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

[0008] In some embodiments, a third preset duration corresponds to a third preset threshold; the third preset duration is greater than the second preset duration; the ratio between the third preset threshold and the third preset duration is a third ratio, and the second ratio is greater than the third ratio; the memory controller is further configured to: when the number of write operations performed by the target storage unit within the second preset duration is less than or equal to the second preset threshold, obtain the number of write operations performed by the target storage unit within the third preset duration and the third preset threshold; wherein, when the number of write operations performed by the target storage unit within the third preset duration is greater than the third preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

[0009] In some embodiments, the non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; the plurality of storage units are coupled to the plurality of word lines and the plurality of bit lines, and each word line and each bit line are in contact connection to an address line driver through corresponding address lines; the memory controller is further configured to: determine the first preset threshold corresponding to the first preset duration according to the distance between the target storage unit and the address line contacts of the word line and / or bit line where the target storage unit is located.

[0010] In some embodiments, the memory controller is specifically configured to: when the distance between the target storage unit and the address line of the word line and / or bit line where the target storage unit is located is a first distance, determine that the first preset threshold is a first value; when the distance between the target storage unit and the address line of the word line and / or bit line where the target storage unit is located is a second distance, determine that the first preset threshold is a second value; when the distance between the target storage unit and the address line of the word line and / or bit line where the target storage unit is located is a third distance, determine that the first preset threshold is a third value; the first distance is less than the second distance, and the second distance is less than the third distance; the first value is less than the second value, and the second value is less than the third value.

[0011] In some embodiments, the memory controller is further configured to: obtain the number of write operations performed by the target storage unit within the preset duration through a Bloom filter and / or a temporal pyramid filter.

[0012] In some embodiments, the memory controller is further configured to: after the adjacent storage unit of the target storage unit performs a refresh operation, clear the number of write operations performed by the target storage unit within the preset duration.

[0013] In some embodiments, the non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; the plurality of storage units are coupled to the plurality of word lines and the plurality of bit lines; the memory controller is further configured to: perform a refresh operation on the storage unit adjacent to the target storage unit along the word line extension direction, and / or, perform a refresh operation on the storage unit adjacent to the target storage unit along the bit line extension direction.

[0014] In some embodiments, the memory system includes a storage-class memory system, and the non-volatile memory device includes a phase change memory.

[0015] Embodiments of the present disclosure also propose an electronic device, including: a host system and a memory system coupled to the host system, where: the memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the non-volatile memory device includes a plurality of memory cells, and the plurality of memory cells include a target memory cell; the host system is configured to: during the process of performing a write operation on the target memory cell, store the number of times the target memory cell performs the write operation in a filter of the host system; the memory controller is configured to: obtain the number of times the target memory cell performs a write operation within a preset time period from the filter, and compare the number of write operations with a preset threshold; when the number of write operations is greater than the preset threshold, perform a refresh operation on adjacent memory cells of the target memory cell.

[0016] Embodiments of the present disclosure also propose an operation method for a memory system, the memory system including a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the non-volatile memory device includes a plurality of memory cells, and the plurality of memory cells include a target memory cell;

[0017] The operation method includes: comparing the number of times the target memory cell performs a write operation within a preset time period with a preset threshold; when the number of times the target memory cell performs a write operation within the preset time period is greater than the preset threshold, perform a refresh operation on adjacent memory cells of the target memory cell.

[0018] In some embodiments, the operation method further includes: before performing the comparison, obtaining the number of times the target memory cell performs a write operation within the preset time period and the preset threshold; where, according to different preset time periods, the corresponding preset thresholds are different.

[0019] In some embodiments, a first preset time period corresponds to a first preset threshold; the step of when the number of times the target memory cell performs a write operation within the preset time period is greater than the preset threshold, performing a refresh operation on adjacent memory cells of the target memory cell includes: when the number of times the target memory cell performs a write operation within the first preset time period is greater than the first preset threshold, performing a refresh operation on adjacent memory cells of the target memory cell.

[0020] In some embodiments, the second preset duration corresponds to a second preset threshold; the second preset duration is greater than the first preset duration; the ratio between the first preset threshold and the first preset duration is a first ratio, the ratio between the second preset threshold and the second preset duration is a second ratio, and the first ratio is greater than the second ratio; the operation method further includes: when the number of write operations performed by the target storage unit within the first preset duration is less than or equal to the first preset threshold, obtaining the number of write operations performed by the target storage unit within the second preset duration and the second preset threshold; comparing the number of write operations performed by the target storage unit within the second preset duration with the second preset threshold; when the number of write operations performed by the target storage unit within the second preset duration is greater than the second preset threshold, performing a refresh operation on adjacent storage units of the target storage unit.

[0021] In some embodiments, the third preset duration corresponds to a third preset threshold; the third preset duration is greater than the second preset duration; the ratio between the third preset threshold and the third preset duration is a third ratio, and the second ratio is greater than the third ratio;

[0022] The operation method further includes: when the number of write operations performed by the target storage unit within the second preset duration is less than or equal to the second preset threshold, obtaining the number of write operations performed by the target storage unit within the third preset duration and the third preset threshold; comparing the number of write operations performed by the target storage unit within the third preset duration with the third preset threshold; when the number of write operations performed by the target storage unit within the third preset duration is greater than the third preset threshold, performing a refresh operation on adjacent storage units of the target storage unit.

[0023] In some embodiments, the non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; the plurality of storage units are coupled to the plurality of word lines and the plurality of bit lines, and each word line and each bit line are connected to an address line driver through corresponding address line contacts; the operation method further includes: determining the first preset threshold corresponding to the first preset duration according to the distance between the target storage unit and the address line contacts of the word line and / or bit line where the target storage unit is located.

[0024] In some embodiments, determining the first preset threshold corresponding to the first preset duration according to the distance between the target storage unit and the address line of the word line and / or bit line where the target storage unit is located includes: when the distance between the target storage unit and the address line of the word line and / or bit line where the target storage unit is located is a first distance, determining the first preset threshold as a first value; when the distance between the target storage unit and the address line of the word line and / or bit line where the target storage unit is located is a second distance, determining the first preset threshold as a second value; when the distance between the target storage unit and the address line of the word line and / or bit line where the target storage unit is located is a third distance, determining the first preset threshold as a third value; the first distance is less than the second distance, and the second distance is less than the third distance; the first value is less than the second value, and the second value is less than the third value.

[0025] In some embodiments, the operation method further includes: obtaining the number of write operations performed by the target storage unit within the preset duration through a Bloom filter and / or a temporal pyramid filter.

[0026] In some embodiments, the operation method further includes: after a refresh operation is performed on an adjacent storage unit of the target storage unit, clearing the number of write operations performed by the target storage unit within the preset duration.

[0027] In some embodiments, the non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; the plurality of storage units are coupled to the plurality of word lines and the plurality of bit lines; the operation method further includes: performing a refresh operation on a storage unit adjacent to the target storage unit along the extending direction of the word line, and / or, performing a refresh operation on a storage unit adjacent to the target storage unit along the extending direction of the bit line.

[0028] An embodiment of the present disclosure also provides a storage medium, on which executable instructions are stored. When the executable instructions are executed by a memory controller, the steps of the method as described in the above embodiments of the present disclosure can be implemented.

[0029] Embodiments of the present disclosure provide a memory system, an operation method thereof, an electronic device, and a storage medium. The memory system includes: a non-volatile memory device including a plurality of memory cells, where the plurality of memory cells include target memory cells; and a memory controller coupled to the non-volatile memory device and configured to: when the number of write operations performed by the target memory cells within a preset time period is greater than a preset threshold, perform a refresh operation on adjacent memory cells of the target memory cells. In the embodiments of the present disclosure, by counting the number of write operations performed by the target memory cells within a preset time period and performing a refresh operation on adjacent memory cells of the target memory cells when the number of write operations within the preset time period is greater than the preset threshold, the write interference caused by frequent write operations to adjacent memory cells of the target memory cells can be reduced. Moreover, during the process of monitoring the number of write operations of the target memory cells and performing a refresh operation on adjacent memory cells, memory cells damaged due to frequent writing and reading can be filtered out, thereby improving the access performance of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a block diagram of a memory system provided by an embodiment of the present disclosure;

[0031] Figure 2 is a schematic flowchart of an operation method of a memory system provided by an embodiment of the present disclosure;

[0032] Figure 3 is a schematic diagram of a counting process of a Bloom filter provided by an embodiment of the present disclosure;

[0033] Figure 4 is a schematic flowchart of using a Bloom filter to count and determine whether to perform a refresh operation on adjacent memory cells provided by an embodiment of the present disclosure;

[0034] Figure 5 is a schematic diagram of the correspondence between a logical page and a logical block provided by an embodiment of the present disclosure;

[0035] Figure 6 is a schematic diagram of the correspondence between an electrical distance and a first preset threshold provided by an embodiment of the present disclosure;

[0036] Figure 7 is a schematic diagram of the arrangement of a target memory cell and adjacent memory cells provided by an embodiment of the present disclosure;

[0037] Figure 8 is a schematic diagram of a counting process of a time pyramid filter provided by an embodiment of the present disclosure;

[0038] Figure 9Schematic flowchart of counting by using a Bloom filter and a time pyramid filter and determining whether to perform a refresh operation on adjacent storage units provided by an embodiment of the present disclosure. Detailed implementation manners

[0039] The exemplary embodiments disclosed in the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0040] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail. In the drawings, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0041] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure. And when discussing a second element, component, region, layer, or portion, it does not necessarily mean that there is a first element, component, region, layer, or portion in the present disclosure.

[0042] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the attached drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0044] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the attached drawings. The attached drawings are for reference and illustration only and are not used to limit the embodiments of the present disclosure.

[0045] New non-volatile memories represented by flash memory (Flsah), phase change memory (Phase Change Memory, PCM), resistive random access memory (Resistive Random Access Memory, RRAM), ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM), magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), and carbon nanotube random access memory (Nantero’s CNT Random Access Memory, NRAM) have the storage advantages of fast access speed, low power consumption, and non-volatility, thus making the application of non-volatile memories more and more extensive.

[0046] Taking PCM as an example, the basic principle of PCM is as follows: An electrical pulse with a relatively large signal value and a short duration (i.e., high and narrow) is applied to the phase change memory cell. Under the action of Joule heat, etc., a part of the phase change memory layer in the initial crystalline state melts due to the temperature being higher than the melting temperature. After interrupting the electrical pulse, the melted part rapidly cools and stays in the amorphous state with low atomic order, thus completing the conversion from low resistance to high resistance. This is the erasure (Reset) process. In this process, the melted part is called the programming volume. If an electrical pulse with a relatively small signal value and a long duration (i.e., low and wide) is applied, so that the temperature within the programming volume reaches above the crystallization temperature and below the melting temperature, and lasts for a sufficient time to crystallize the amorphous structure within the programming volume, a low-resistance state is obtained. This is the write (Set) process. The read process of PCM is to apply a low and relatively narrow electrical pulse to the phase change memory cell, keep the phase change memory layer below the crystallization temperature, and measure the resistance of the phase change memory cell.

[0047] However, in actual operation, high-frequency access (such as writing and reading) to the same memory cell will seriously interfere with the memory cells adjacent (in physical location) to the accessed memory cell, and even affect other memory cells connected to the same word line (WL) or bit line (BL). To avoid the adjacent memory cells of a accessed memory cell being interfered and causing the entire PCM to fail, wear leveling is usually adopted to evenly distribute the write counts to different memory cells; however, since it is necessary to monitor all memory cells over a large range and for a long time, it is very difficult to track write interference at the system level. In other words, it is very difficult to track all the write counts of each memory cell over a long time interval. Based on this, how to implement the monitoring of write interference and subsequent operations is the key to improving the access performance of PCM.

[0048] In view of this, the embodiments of the present disclosure provide a memory system, its operation method, an electronic device, and a storage medium. Among them, the embodiments of the present disclosure provide an operation method for a memory system, as Figure 1 shown, Figure 1 is a block diagram of a memory system provided by an embodiment of the present disclosure. The memory system 100 includes: a non-volatile memory device 110 and a memory controller 120. The memory controller 120 is coupled to the non-volatile memory device 110. The non-volatile memory device 110 may include a plurality of memory blocks 111 (also called physical blocks). Each memory block may include a plurality of memory cells. Among the plurality of memory cells, there is a target memory cell 112. Herein, the target memory cell 112 is any one or more of the plurality of memory blocks. In the embodiments of the present disclosure, the target memory cell is the memory cell that is accessed at a high frequency among the plurality of memory cells.

[0049] AsFigure 2 As shown Figure 2 Figure 2 is a schematic flowchart of an implementation process of an operation method for a memory system provided by an embodiment of the present disclosure; the operation method includes the following steps: Step S201: Compare the number of write operations performed by a target storage unit within a preset time period with a preset threshold; Step S202: When the number of write operations performed by the target storage unit within the preset time period is greater than the preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

[0050] That is to say, in the embodiment of the present disclosure, the number of write operations performed on the target storage unit is monitored and tracked. By determining whether the number of write operations performed by the target storage unit within the preset time period exceeds the preset threshold, the impact and degree of impact caused by the write interference generated by the write operation on the target storage unit and its adjacent storage units are determined, and further, whether to perform subsequent operations on the target storage unit and its adjacent storage units, such as refreshing and recycling, is determined.

[0051] In some embodiments, the operation method further includes: before the comparison, obtain the number of write operations performed by the target storage unit within the preset time period and the preset threshold; wherein, according to different preset time periods, the corresponding preset thresholds are different.

[0052] In some specific embodiments, in order to facilitate determining whether the number of write operations performed by the target storage unit within different preset time periods (such as short term and long term) is greater than a certain preset threshold, multiple values can be set for the preset time period, and correspondingly, the preset threshold also includes multiple; in the embodiment of the present disclosure, the preset time period includes three time periods, such as a first preset time period S1, a second preset time period S2, and a third preset time period S3, the third preset time period S3 is greater than the second preset time period S2, and the second preset time period S2 is greater than the first preset time period S1, that is, S3 > S2 > S1. Each time period corresponds to a different preset threshold. Based on this, the preset threshold includes three different thresholds, such as a first preset threshold R1, a second preset threshold R2, and a third preset threshold R3, the third preset threshold R3 is greater than the second preset threshold R2, and the second preset threshold R2 is greater than the first preset threshold R1, that is, R3 > R2 > R1. Here, the first preset time period S1 corresponds to the first preset threshold R1, the second preset time period S2 corresponds to the second preset threshold R2, and the third preset time period S3 corresponds to the third preset threshold R3.

[0053] In some embodiments, the ratio between the first preset threshold R1 and the first preset duration S1 is the first ratio L1, the ratio between the second preset threshold R2 and the second preset duration S2 is the second ratio L2, and the ratio between the third preset threshold R3 and the third preset duration S3 is the third ratio L3. Here, the first ratio L1 is greater than the second ratio L2, and the second ratio L2 is greater than the third ratio L3, that is, L1 > L2 > L3. It should be understood that the first ratio L1, the second ratio L2, and the third ratio L3 respectively represent the write density within different durations. Different preset durations result in different write densities. Among them, the write density within the first preset duration S1 is greater than the write density within the second preset duration S2, and the write density within the second preset duration S2 is greater than the write density within the third preset duration S3.

[0054] Exemplarily, obtain the number of write operations WC1 performed by the target storage unit within the first preset duration and the corresponding first preset threshold R1, and compare the number of write operations WC1 performed within the first preset duration with the first preset threshold R1. Among them, when the number of write operations WC1 performed by the target storage unit within the first preset duration is greater than the first preset threshold R1, it indicates that the number of write operations performed within the first preset duration is relatively large, and the write interference generated seriously affects the adjacent storage units of the target storage unit. At this time, a refresh operation is performed on the adjacent storage units of the target storage unit. When the number of write operations WC1 performed by the target storage unit within the first preset duration S1 is less than or equal to the first preset threshold R1, it indicates that the number of write operations performed within the first preset duration is relatively small, and the write interference generated has a relatively small impact on the adjacent storage units of the target storage unit. At this time, the adjacent storage units of the target storage unit are not refreshed temporarily. Further, the number of write operations WC2 performed by the target storage unit within the second preset duration S2 and the second preset threshold R2 can be obtained.

[0055] Exemplarily, after obtaining the number of write operations WC2 performed by the target storage unit within the second preset duration and the corresponding second preset threshold R2, compare the number of write operations WC2 performed within the second preset duration with the second preset threshold R2. Similarly, when the number of write operations WC2 performed by the target storage unit within the second preset duration is greater than the second preset threshold R2, a refresh operation is performed on the adjacent storage units of the target storage unit. When the number of write operations WC2 performed by the target storage unit within the second preset duration S2 is less than or equal to the second preset threshold R2, the adjacent storage units of the target storage unit are not refreshed temporarily at this time. Further, the number of write operations WC3 performed by the target storage unit within the third preset duration S3 and the third preset threshold R3 can be obtained.

[0056] Exemplarily, after obtaining the number of write operations WC3 performed by the target storage unit within the third preset time period and the corresponding third preset threshold R3, compare the number of write operations WC3 performed within the third preset time period with the third preset threshold R3. Similarly, when the number of write operations WC3 performed by the target storage unit within the third preset time period S3 is greater than the third preset threshold R3, perform a refresh operation on the adjacent storage units of the target storage unit. When the number of write operations WC3 performed by the target storage unit within the third preset time period S3 is less than or equal to the third preset threshold R3, do not perform a refresh operation on the adjacent storage units of the target storage unit at this time.

[0057] In some embodiments, the first preset time period can be 10 milliseconds to 50 seconds, the second preset time period can be 100 to 1000 seconds, and the third preset time period is 5000 seconds to 20000 seconds or even more. The first preset threshold R1, the second preset threshold R2, and the third preset threshold R3 can be correspondingly set according to the different preset time periods. Exemplarily, the first preset time period is 1 second (s), the second preset time period is 100 seconds (s), and the third preset time period is 10000 seconds (s). The first preset threshold R1, the second preset threshold R2, and the third preset threshold R3 are empirical values set by the accessed storage unit according to the actual affected degree; Exemplarily, the first preset threshold R1 is 600 to 1000 times, the second preset threshold R2 is 5000 times, and the third preset threshold R3 is 50000 times. Among them, when the number of write operations WC1 performed by the target storage unit within 1 s is greater than 600 (~1000) times, perform a refresh operation on the adjacent storage units of the target storage unit. When the number of write operations WC2 performed by the target storage unit within 100 s is greater than 5000 times, perform a refresh operation on the adjacent storage units of the target storage unit. When the number of write operations WC3 performed by the target storage unit within 10000 s is greater than 50000 times, perform a refresh operation on the adjacent storage units of the target storage unit.

[0058] In some embodiments, the operation method further includes: after performing a refresh operation on the adjacent storage units of the target storage unit, clear the number of write operations performed by the target storage unit within the preset time period. In this way, the interference of previous counting information on subsequent counting can be avoided.

[0059] In some specific embodiments, the number of write operations performed by the target storage unit within different preset time periods can be obtained through a Bloom Filter and / or a time pyramid filter.

[0060] The following combines Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、Figure 8 , Figure 9 and embodiments to describe in detail how to obtain the number of write operations performed by a target storage unit within different preset time periods through a Bloom filter and a time pyramid filter, and subsequent operations thereof. Figure 3 Schematic diagram of a counting process of a Bloom filter provided by an embodiment of the present disclosure; Figure 4 Schematic diagram of a process of using a Bloom filter for counting and determining whether to perform a refresh operation on an adjacent storage unit provided by an embodiment of the present disclosure; Figure 5 Schematic diagram of a corresponding relationship between a logical page and a logical block provided by an embodiment of the present disclosure; Figure 6 Schematic diagram of a corresponding relationship between an electrical distance and a first preset threshold provided by an embodiment of the present disclosure; Figure 7 Schematic diagram of an arrangement of a target storage unit and its adjacent storage units provided by an embodiment of the present disclosure; Figure 8 Schematic diagram of a counting process of a time pyramid filter provided by an embodiment of the present disclosure; Figure 9 Schematic diagram of a process of using a Bloom filter and a time pyramid filter for counting and determining whether to perform a refresh operation on an adjacent storage unit.

[0061] In the embodiments of the present disclosure, a Bloom filter is used to count and record the number of write operations performed by a target storage unit in the short term (the first preset time period); a Bloom filter and a time pyramid filter are used to record the number of write operations performed by a target storage unit in the long term (the second preset time period, the third preset time period). In some other embodiments, other filters may also be used for counting, which will not be elaborated here.

[0062] Exemplarily, referring to Figure 3 , the Bloom filter is a two counting bloomfilter. In this Bloom filter, a forward Bloom filter CBF1 is used to store forward data, and a reverse Bloom filter CBF2 is used to store reverse data. When an address is written, it is written into the forward Bloom filter and the reverse Bloom filter respectively. When querying whether an address exists, it is necessary to check both the forward Bloom filter and the reverse Bloom filter. Only when both judge that it exists can it be determined that the address may exist. On this basis, when querying the number of write operations of an address, the value corresponding to the corresponding bit in the forward Bloom filter or the reverse Bloom filter can be checked.

[0063] Referring to Figure 3, the host sends an instruction to indicate writing data into a certain logical page of a logical block. Among them, the address corresponding to the logical block in the instruction is the logical block address (LBA), and the address corresponding to the logical page is the logical page address (LPA); after receiving the instruction, the buffer (such as SRAM) writes the logical page address of the target storage unit corresponding to the written data into the Bloom filter, and completes the queue through the medium.

[0064] As Figure 3 shown, the LBA ID is the logical block address (Logical Block Address, LBA) corresponding to multiple storage units. When each write operation is performed, the corresponding LBA ID (such as Figure 3 the LBA ID3 shown) will be written into the forward Bloom filter CBF1 and the reverse Bloom filter CBF2. Specifically, taking LBA ID3 as the input, three hash values (H1, H2, H3) are calculated using three hash functions respectively. In the bit array of the forward Bloom filter, the bits corresponding to H1, H2, and H3 are incremented by 1, indicating that the write count of LBA ID3 in the forward Bloom filter CBF1 is increased by 1. Similarly, taking LBA ID3 as the input, three hash values are calculated using three hash functions respectively. In the bit array of the reverse Bloom filter CBF2, the bits corresponding to H1, H2, and H3 are incremented by 1, indicating that the write count of LBA ID3 in the reverse Bloom filter CBF2 is increased by 1.

[0065] Subsequently, when alternately querying the forward Bloom filter CBF1 and the reverse Bloom filter CBF2, the same hash function can be used to calculate the hash value, and it can be checked whether the corresponding bit is 1 to determine whether the corresponding LBA ID3 exists in the forward Bloom filter CBF1 and the reverse Bloom filter CBF2; further, the write count of LBA ID3 can be determined according to the value of the corresponding bit in the forward Bloom filter CBF1.

[0066] It should be noted that when the values of the three bits corresponding to H1, H2, and H3 in the bit array corresponding to the forward Bloom filter CBF1 / reverse Bloom filter CBF2 are different, the smallest value among the three bits is used as the write count of LBA ID3. It should be noted that Figure 3The monitoring time interval of the Bloom filter shown is 1 second, that is, the first preset duration is 1 second; in some other embodiments, the monitoring time interval of the Bloom filter can also be 100 milliseconds or 10 seconds, etc. In some embodiments, during the process of alternately querying the forward and reverse Bloom filters, the previous Bloom filter can be cleared after each query to reset the state of the Bloom filter for the next query. At the next time point, continue to alternately query the two Bloom filters and clear the previously queried Bloom filter to achieve periodic query operations.

[0067] Reference Figure 4 , step S401, submit an instruction to query the write count of the target storage unit.

[0068] Step S402, read the logical page address LPA of each storage unit in the non-volatile memory device.

[0069] Step S403, periodically select the write logical page address.

[0070] Step S404, query the number of write operations performed by the logical address (LPA_i) of the target storage unit on the Bloom filter within the preset duration, for example, the number of write operations WC1 performed by the target storage unit within the first preset duration. Reference Figure 5 , Figure 5 shows a schematic diagram of the correspondence between the logical block address and the logical page address; wherein, the non-volatile memory device includes a plurality of logical blocks (Block0…Blockb), each logical block (Block) includes a plurality of logical pages (Page), and the logical address (LPA_i) of the target storage unit is determined by decoding the code word corresponding to the logical block address.

[0071] Step S405, judge the size relationship between the number of write operations WC1 performed by the target storage unit within the first preset duration and the first preset threshold R1; wherein, when the number of write operations WC1 performed within the first preset duration is greater than the first preset threshold R1, step S406 is executed. When the number of write operations WC1 performed within the first preset duration is less than or equal to the first preset threshold R1, step S408 is executed.

[0072] Step S406: Perform a refresh operation on the adjacent memory cells of the target memory cell. It should be understood that after determining the logical address (LPA_i) of the target memory cell, according to the mapping table corresponding to the logical address and the physical address, the physical address (PPA_i) of the target memory cell and the physical addresses of the adjacent memory cells of the target memory cell are PPA_i + 1 and PPA_i - 1 respectively. Here, only PPA_i + 1 and PPA_i - 1 are shown for the memory cells adjacent to the target memory cell PPA_i. A detailed description of the adjacent memory cells will be given later, so it will not be elaborated here.

[0073] Step S407: Clear the number of write operations performed on the target memory cell in the first preset duration in the Bloom filter. It should be understood that by clearing the corresponding count of the Bloom filter, a periodic query operation can be achieved, and interference from previous query information to subsequent queries can be avoided. At the same time, the memory occupancy of the Bloom filter can also be reduced.

[0074] Step S408: Temporarily do not perform a refresh operation on the adjacent memory cells of the target memory cell.

[0075] Step S409: Obtain the number of write operations performed in a longer preset duration, such as WC2.

[0076] As mentioned above, the memory cells adjacent to the target memory cell PPA_i also include other memory cells connected to the same word line WL or bit line BL as the target memory cell. However, different adjacent memory cells are at different distances from the target memory cell and are affected by write interference to different degrees. Based on this, different preset thresholds are set for adjacent memory cells at different distances in the embodiments of the present disclosure.

[0077] Specifically, the non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; a plurality of memory cells are coupled to the plurality of word lines and the plurality of bit lines, and each word line and each bit line are in contact connection with an address line driver through a corresponding address line; based on this, the operation method further includes: determining a first preset threshold corresponding to the first preset duration according to the distance between the target memory cell and the address line contact of the word line and / or bit line where the target memory cell is located.

[0078] Here, the distance between the target storage cell and the address line contact of the word line and / or bit line where the target storage cell is located is the electrical distance (ED). After the non-volatile memory device is manufactured, the positions of the word line and the bit line are determined. Therefore, the address line contacts connecting the word line and the address line contacts connecting the bit line are also determined. Therefore, the electrical distances between the target storage cell and the address line contacts of the word line and the bit line are also determined. Based on this, according to the different electrical distances, the values of the first preset threshold corresponding to the first preset duration are different.

[0079] In some embodiments, when the distance between the target storage cell and the address line contact of the word line and / or bit line where the target storage cell is located is the first distance, the first preset threshold is determined to be the first value; when the distance between the target storage cell and the address line contact of the word line and / or bit line where the target storage cell is located is the second distance, the first preset threshold is determined to be the second value; when the distance between the target storage cell and the address line contact of the word line and / or bit line where the target storage cell is located is the third distance, the first preset threshold is determined to be the third value; the first distance is less than the second distance, and the second distance is less than the third distance; the first value is less than the second value, and the second value is less than the third value.

[0080] Exemplarily, referring to Figure 6 , the first distance NN is less than the second distance MM, and the second distance MM is less than the third distance FF, that is, NN < MM < FF. The first value is 600, the second value is 800, and the third value is 1000; in other words, when the electrical distance between the target storage cell and the address line contact of the word line and / or bit line where the target storage cell is located is larger, the value of the first preset threshold is larger.

[0081] Based on this, in some embodiments, the operation method further includes: performing a refresh operation on the storage cells adjacent to the target storage cell along the word line extension direction, and / or, performing a refresh operation on the storage cells adjacent to the target storage cell along the bit line extension direction.

[0082] Exemplarily, referring to Figure 7 , the storage cells (PPA_j-2, PPA_j-1, PPA_j+1, PPA_j+2) adjacent to the target storage cell (PPA_j) along the word line (WL) extension direction, and the storage cells (PPA_j-4, PPA_j-3, PPA_j+3, PPA_j+4) adjacent to the target storage cell (PPA_j) along the bit line (BL) extension direction. Based on the different degrees of influence of write interference on adjacent storage cells, different storage cells adjacent to the target storage cell can be selected to perform the refresh operation.

[0083] Referring to Figure 3 、 Figure 8 、Figure 9 , obtain the number of write operations WC2 of the target storage unit within the second preset duration and the number of write operations WC3 within the third preset duration through a Bloom filter and a time pyramid filter.

[0084] Exemplarily, in combination with Figure 8 , Figure 9 , step S901, issue a query instruction.

[0085] Step S902, obtain the number of write operations WC2 of the target storage unit within the second preset duration by combining and using a Bloom filter and a time pyramid filter. For example, the second preset duration is 100 seconds; using the Bloom filter, alternately query the forward Bloom filter CBF1 and the reverse Bloom filter CBF2 50 times each, and obtain the number of writes for each query, such as N1, N2... N100, and accumulate the 100 query values to obtain the number of write operations WC2 of the target storage unit within 100s.

[0086] Step S903, every time the second preset duration is reached, compare the obtained number of write operations WC2 of the target storage unit with the second preset threshold to determine whether the number of write operations WC2 of the target storage unit is greater than the second preset threshold.

[0087] When the number of write operations WC2 of the target storage unit is greater than the second preset threshold, execute step S904 to perform a refresh operation on the adjacent storage units of the target storage unit.

[0088] When the number of write operations WC2 of the target storage unit is less than the second preset threshold, execute step S905 to obtain the number of write operations WC3 of the target storage unit within the third preset duration. For example, the third preset duration is 10,000 seconds; using the time pyramid filter, obtain the number of write operations within 100s for 100 times, M1, M2... M100, and accumulate the 100 write operation numbers to obtain the number of write operations WC3 of the target storage unit within 10,000s.

[0089] Step S906, every time the third preset duration is reached, compare the obtained number of write operations WC3 of the target storage unit with the third preset threshold to determine whether the number of write operations WC3 of the target storage unit is greater than the third preset threshold. When the number of write operations WC3 of the target storage unit is greater than the third preset threshold, execute step S904 to perform a refresh operation on the adjacent storage units of the target storage unit.

[0090] Based on this, the write count of the target storage unit is monitored in the long term or short term through a Bloom filter and / or a time pyramid filter, and when the write count within a certain preset duration (long term or short term) is greater than a corresponding preset threshold, a refresh operation is performed on the adjacent storage units of the target storage unit; in this way, the write interference caused by frequent write operations to the adjacent storage units of the target storage unit can be reduced; and during the process of monitoring the write count of the target storage unit and performing the refresh operation on the adjacent storage units, storage units damaged due to frequent writing and reading can be filtered out, thereby improving the access performance of the memory system.

[0091] Based on the above operation method, an embodiment of the present disclosure further provides a memory system, including: a non-volatile memory device including a plurality of memory blocks, the memory blocks including a plurality of storage units, and the plurality of storage units including a first storage unit; and a memory controller coupled to the non-volatile memory device and configured to: when the number of write operations performed by the first storage unit within a preset duration is greater than a preset threshold, perform a refresh operation on the adjacent storage units of the first storage unit.

[0092] In some embodiments, the memory controller is configured to: obtain the number of write operations performed by the first storage unit within a preset duration and the preset threshold; wherein, when the preset duration is different, the corresponding preset threshold is different.

[0093] In some embodiments, the memory controller is further configured to: when the number of write operations performed by the first storage unit within a first preset duration is greater than a first preset threshold, perform a refresh operation on the adjacent storage units of the first storage unit; when the number of write operations performed by the first storage unit within a second preset duration is greater than a second preset threshold, perform a refresh operation on the adjacent storage units of the first storage unit; the first preset duration is less than the second preset duration; the ratio between the first preset threshold and the first preset duration is a first ratio, the ratio between the second preset threshold and the second preset duration is a second ratio, and the first ratio is greater than the second ratio.

[0094] In some embodiments, the memory controller is further configured to: when the number of write operations performed by the first storage unit within the first preset duration is less than or equal to the first preset threshold; obtain the number of write operations performed by the first storage unit within a second preset duration and the second preset threshold; and when the number of write operations performed by the first storage unit within the second preset duration is greater than the second preset threshold, perform a refresh operation on the adjacent storage units of the first storage unit.

[0095] In some embodiments, the memory controller is further configured to: when the number of write operations performed by the first storage unit within the second preset duration is less than or equal to the second preset threshold; obtain the number of write operations performed by the first storage unit within the third preset duration and the third preset threshold; the second preset duration is less than the third preset duration; the ratio between the third preset threshold and the third preset duration is the third ratio, and the second ratio is greater than the third ratio; when the number of write operations performed by the first storage unit within the third preset duration is greater than the third preset threshold, perform a refresh operation on the adjacent storage units of the first storage unit.

[0096] In some embodiments, the memory block includes a plurality of word lines and a plurality of bit lines; the plurality of storage units are coupled to the plurality of word lines and the plurality of bit lines, and each word line and each bit line are connected to an address line driver through corresponding address line contacts; the memory controller is further configured to: determine the first preset threshold corresponding to the first preset duration according to the distance between the first storage unit and the address line contacts of the word line and / or bit line where the first storage unit is located.

[0097] In some embodiments, the memory controller is specifically configured to: when the distance between the first storage unit and the address line contacts of the word line and / or bit line where the first storage unit is located is the first distance, determine that the first preset threshold is the first value; when the distance between the first storage unit and the address line contacts of the word line and / or bit line where the first storage unit is located is the second distance, determine that the first preset threshold is the second value; when the distance between the first storage unit and the address line contacts of the word line and / or bit line where the first storage unit is located is the third distance, determine that the first preset threshold is the third value; the first distance is less than the second distance, and the second distance is less than the third distance; the first value is less than the second value, and the second value is less than the third value.

[0098] In some embodiments, the memory controller is further configured to: obtain the number of write operations performed by the first storage unit within the preset duration through a Bloom filter and / or a time pyramid filter.

[0099] In some embodiments, the memory controller is further configured to: after performing a refresh operation on the adjacent storage units of the first storage unit, clear the number of write operations performed by the first storage unit within the preset duration.

[0100] In some embodiments, the memory block includes a plurality of word lines and a plurality of bit lines; the plurality of memory cells are coupled to the plurality of word lines and the plurality of bit lines; the memory controller is further configured to: perform a refresh operation on a memory cell adjacent to the first memory cell along the extending direction of the word line, and / or, on a memory cell adjacent to the first memory cell along the extending direction of the bit line.

[0101] In some embodiments, the memory system includes a storage class memory system, and the non-volatile memory device includes a phase change memory.

[0102] Embodiments of the present disclosure further provide an electronic device, including: a host system and a memory system coupled to the host system, wherein: the memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the non-volatile memory device includes a plurality of memory blocks, the memory block includes a plurality of memory cells, and the plurality of memory cells include a first memory cell; the host system is configured to: during a write operation on the first memory cell, store the number of times the first memory cell performs the write operation in a filter of the host system; the memory controller is configured to: obtain from the filter the number of times the first memory cell performs a write operation within a preset time period, and compare the number of write operations with a preset threshold; when the number of write operations is greater than the preset threshold, perform a refresh operation on adjacent memory cells of the first memory cell.

[0103] Embodiments of the present disclosure further provide a storage medium, on which executable instructions are stored, and when the executable instructions are executed by a memory controller, the steps of the operation method as described in the above embodiments of the present disclosure can be implemented.

[0104] In some specific embodiments, the storage medium may be a magnetic random access memory, a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory, etc.; it may also be various devices including one or any combination of the above memory devices.

[0105] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, and may be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as an independent program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0106] As an example, executable instructions may or may not correspond to files in a file system and may be stored as part of a file that holds other programs or data. For example, they may be stored in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program being discussed, or in multiple cooperating files (such as files that store one or more modules, subroutines, or portions of code).

[0107] It should be understood that the phrase "one embodiment" or "an embodiment" mentioned throughout the specification means that a particular feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout the specification are not necessarily referring to the same embodiment. Additionally, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of the present disclosure, the magnitudes of the sequence numbers of the above processes do not imply the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are merely for description and do not represent the superiority or inferiority of the embodiments.

[0108] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. As described above, this is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory system, characterized in that, comprising: a non-volatile memory device including a plurality of memory cells, and a target memory cell among the plurality of memory cells; and a memory controller coupled to the non-volatile memory device and configured to: when the number of write operations performed by the target memory cell within a preset duration is greater than a preset threshold, perform a refresh operation on adjacent memory cells of the target memory cell.

2. The memory system according to claim 1, characterized in that, the memory controller is configured to: obtain the number of write operations performed by the target memory cell within the preset duration and the preset threshold; wherein, different preset durations correspond to different preset thresholds.

3. The memory system according to claim 2, characterized in that, a first preset duration corresponds to a first preset threshold; the memory controller is further configured to: when the number of write operations performed by the target memory cell within the first preset duration is greater than the first preset threshold, perform a refresh operation on adjacent memory cells of the target memory cell.

4. The memory system according to claim 3, characterized in that, a second preset duration corresponds to a second preset threshold; the second preset duration is greater than the first preset duration; the ratio between the first preset threshold and the first preset duration is a first ratio, the ratio between the second preset threshold and the second preset duration is a second ratio, and the first ratio is greater than the second ratio; the memory controller is further configured to: when the number of write operations performed by the target memory cell within the first preset duration is less than or equal to the first preset threshold, obtain the number of write operations performed by the target memory cell within the second preset duration and the second preset threshold; wherein, when the number of write operations performed by the target memory cell within the second preset duration is greater than the second preset threshold, perform a refresh operation on adjacent memory cells of the target memory cell.

5. The memory system according to claim 4, characterized in that, a third preset duration corresponds to a third preset threshold; the third preset duration is greater than the second preset duration; the ratio between the third preset threshold and the third preset duration is a third ratio, and the second ratio is greater than the third ratio; the memory controller is further configured to: when the number of write operations performed by the target memory cell within the second preset duration is less than or equal to the second preset threshold, obtain the number of write operations performed by the target memory cell within the third preset duration and the third preset threshold; wherein, when the number of write operations performed by the target memory cell within the third preset duration is greater than the third preset threshold, perform a refresh operation on adjacent memory cells of the target memory cell.

6. The memory system according to claim 3, characterized in that, The non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; the plurality of memory cells are coupled to the plurality of word lines and the plurality of bit lines, and each of the word lines and each of the bit lines are in contact connection to an address line driver through a corresponding address line; The memory controller is further configured to: Determine the first preset threshold corresponding to the first preset duration according to the distance between the target memory cell and the contact of the address line of the word line and / or bit line where the target memory cell is located.

7. The memory system according to claim 6, wherein, The memory controller is specifically configured to: When the distance between the target memory cell and the contact of the address line of the word line and / or bit line where the target memory cell is located is a first distance, determine that the first preset threshold is a first value; When the distance between the target memory cell and the contact of the address line of the word line and / or bit line where the target memory cell is located is a second distance, determine that the first preset threshold is a second value; When the distance between the target memory cell and the contact of the address line of the word line and / or bit line where the target memory cell is located is a third distance, determine that the first preset threshold is a third value; The first distance is less than the second distance, and the second distance is less than the third distance; the first value is less than the second value, and the second value is less than the third value.

8. The memory system according to claim 2, wherein, The memory controller is further configured to: Obtain the number of write operations performed by the target memory cell within the preset duration through a Bloom filter and / or a time pyramid filter.

9. The memory system according to claim 1, wherein, The memory controller is further configured to: After a refresh operation is performed on an adjacent memory cell of the target memory cell, clear the number of write operations performed by the target memory cell within the preset duration.

10. The memory system according to claim 1, wherein, The non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; the plurality of memory cells are coupled to the plurality of word lines and the plurality of bit lines; The memory controller is further configured to: Perform a refresh operation on a memory cell adjacent to the target memory cell along the extension direction of the word line, and / or, perform a refresh operation on a memory cell adjacent to the target memory cell along the extension direction of the bit line.

11. The memory system according to claim 1, wherein, The memory system includes a storage-class memory system, and the non-volatile memory device includes a phase change memory.

12. An electronic device, wherein, comprises: A host system and a memory system coupled to the host system, wherein: The memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the non-volatile memory device includes a plurality of memory cells, and the plurality of memory cells include a target memory cell; The host system is configured to store, in a filter of the host system, the number of times the target storage unit performs a write operation during the process of performing the write operation on the target storage unit; The memory controller is configured to: Obtain, from the filter, the number of times the target storage unit performs a write operation within a preset time period, and compare the number of write operations with a preset threshold; When the number of write operations is greater than the preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

13. An operation method of a memory system, characterized in that, The memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the non-volatile memory device includes a plurality of storage units, and the plurality of storage units include a target storage unit; The operation method includes: Compare the number of times the target storage unit performs a write operation within a preset time period with a preset threshold; When the number of times the target storage unit performs a write operation within the preset time period is greater than the preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

14. The operation method according to claim 13, characterized in that, The operation method further includes: Before performing the comparison, obtain the number of times the target storage unit performs a write operation within the preset time period and the preset threshold; wherein, corresponding to different preset time periods, the corresponding preset thresholds are different.

15. The operation method according to claim 14, characterized in that, A first preset time period corresponds to a first preset threshold; The step of, when the number of times the target storage unit performs a write operation within the preset time period is greater than the preset threshold, performing a refresh operation on adjacent storage units of the target storage unit includes: When the number of times the target storage unit performs a write operation within the first preset time period is greater than the first preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

16. The operation method according to claim 15, characterized in that, A second preset time period corresponds to a second preset threshold; the second preset time period is greater than the first preset time period; The ratio between the first preset threshold and the first preset time period is a first ratio, the ratio between the second preset threshold and the second preset time period is a second ratio, and the first ratio is greater than the second ratio; The operation method further includes: When the number of times the target storage unit performs a write operation within the first preset time period is less than or equal to the first preset threshold, obtain the number of times the target storage unit performs a write operation within the second preset time period and the second preset threshold; Compare the number of times the target storage unit performs a write operation within the second preset time period with the second preset threshold; When the number of times the target storage unit performs a write operation within the second preset time period is greater than the second preset threshold, perform a refresh operation on adjacent storage units of the target storage unit.

17. The operation method according to claim 16, It is characterized in that The third preset duration corresponds to a third preset threshold; the third preset duration is greater than the second preset duration; The ratio between the third preset threshold and the third preset duration is a third ratio, and the second ratio is greater than the third ratio; The operation method further includes: When the number of write operations performed by the target storage unit within the second preset duration is less than or equal to the second preset threshold, obtain the number of write operations performed by the target storage unit within the third preset duration and the third preset threshold; Compare the number of write operations performed by the target storage unit within the third preset duration with the third preset threshold; When the number of write operations performed by the target storage unit within the third preset duration is greater than the third preset threshold, perform a refresh operation on the adjacent storage unit of the target storage unit.

18. The operation method according to claim 15, It is characterized in that The non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; the plurality of storage units are coupled to the plurality of word lines and the plurality of bit lines, and each word line and each bit line are connected to an address line driver through corresponding address line contacts; The operation method further includes: Determine the first preset threshold corresponding to the first preset duration according to the distance between the target storage unit and the address line contact of the word line and / or bit line where the target storage unit is located.

19. The operation method according to claim 18, It is characterized in that The determining the first preset threshold corresponding to the first preset duration according to the distance between the target storage unit and the address line contact of the word line and / or bit line where the target storage unit is located includes: When the distance between the target storage unit and the address line contact of the word line and / or bit line where the target storage unit is located is a first distance, determine the first preset threshold as a first value; When the distance between the target storage unit and the address line contact of the word line and / or bit line where the target storage unit is located is a second distance, determine the first preset threshold as a second value; When the distance between the target storage unit and the address line contact of the word line and / or bit line where the target storage unit is located is a third distance, determine the first preset threshold as a third value; The first distance is less than the second distance, and the second distance is less than the third distance; the first value is less than the second value, and the second value is less than the third value.

20. The operation method according to claim 14, It is characterized in that The operation method further includes: Obtain the number of write operations performed by the target storage unit within the preset duration through a Bloom filter and / or a time pyramid filter.

21. The operation method according to claim 13, It is characterized in that The operation method further includes: After performing a refresh operation on the adjacent storage unit of the target storage unit, clear the number of write operations performed by the target storage unit within the preset duration.

22. The operation method according to claim 13, It is characterized in that The non-volatile memory device further includes a plurality of word lines and a plurality of bit lines; the plurality of memory cells are coupled to the plurality of word lines and the plurality of bit lines; The operation method further includes: Performing a refresh operation on a memory cell disposed adjacent to the target memory cell along the word line extending direction, and / or on a memory cell disposed adjacent to the target memory cell along the bit line extending direction.

23. A storage medium, characterized in that, An executable instruction is stored on the storage medium, and when the executable instruction is executed by a memory controller, the steps of the method according to any one of claims 13-22 can be implemented.

Images