Method of operating memory device

Abstract

A method of operating a memory device is provided herein. The method of operating the memory device may include: pre-charging a first channel of a first plug corresponding to a first selection line and a second channel of a second plug corresponding to a second selection line; applying one of a program enable voltage and a program disable voltage to the first channel; applying one of a program enable voltage and a program disable voltage to the second channel; and programming a memory cell selected from among the memory cells included in the first plug and the second plug.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to methods of operating a memory device, and more particularly, to a method of operating a memory device having a three-dimensional (3D) structure. Background Art

[0002] A memory device may include a memory cell array for storing data and peripheral circuits configured to perform a programming operation, a read operation, or an erase operation on the memory cell array.

[0003] The memory cell array may include a plurality of memory blocks disposed between a bit line and a source line, and each memory block may include, for example, plugs extending from a substrate in a vertical direction. Each plug may include a source select transistor, a memory cell, and a drain select transistor.

[0004] The gate of the source select transistor may be connected to a source select line, the gate of the memory cell may be connected to a word line, and the gate of the drain select transistor may be connected to a drain select line.

[0005] Among the drain select lines connected to the selected memory block, one drain select line may be selected, and the remaining drain select lines may not be selected.

[0006] Because the memory cells corresponding to the selected drain select line and the memory cells corresponding to the unselected drain select line are connected to the same word line, when the selected memory cells included in the plugs of the selected drain select line are programmed, the threshold voltage of the unselected memory cells included in the plugs of the unselected drain select line may increase. Summary of the Invention

[0007] Embodiments of the present disclosure may provide a method of operating a memory device. The method may include the steps of: pre-charging a first channel of a first plug corresponding to a first select line and a second channel of a second plug corresponding to a second select line; applying one of a programming enable voltage and a programming inhibit voltage to the first channel; applying one of a programming enable voltage and a programming inhibit voltage to the second channel; and programming the memory cells selected from among the memory cells included in the first plug and the second plug.

[0008] Embodiments of the present disclosure may provide a method of operating a memory device. The method may include the steps of: pre-charging a first channel of a first plug and a second channel of a second plug, wherein the first plug and the second plug correspond to a first select line; pre-charging a third channel of a third plug and a fourth channel of a fourth plug, wherein the third channel and the fourth channel correspond to a second select line; applying one of a program enable voltage and a program inhibit voltage to each of the first channel, the second channel, the third channel, and the fourth channel; and programming a memory cell selected from among the memory cells included in the first plug, the second plug, the third plug, and the fourth plug.

[0009] Embodiments of the present disclosure may provide a method of operating a memory device. The method may include the steps of: pre-charging a first channel of a first plug corresponding to a first select line, a second channel of a second plug corresponding to the first select line, a third channel of a third plug corresponding to a second select line, and a fourth channel of a fourth plug corresponding to the second select line; applying a program enable voltage to the first channel of the first plug and the third channel of the third plug when the first plug and the third plug are selected plugs; applying a program inhibit voltage to the second channel of the second plug and the fourth channel of the fourth plug when the second plug and the fourth plug are unselected plugs; and programming a memory cell selected from among the memory cells included in the first plug and the third plug of a memory block. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram illustrating an arrangement of a memory cell array and a peripheral circuit according to an embodiment of the present disclosure.

[0012] Figure 3 is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0013] Figure 4 is a flowchart illustrating a method of programming operation of a memory device according to the present disclosure.

[0014] Figure 5 is a perspective view illustrating a structure of a memory block according to a first embodiment of the present disclosure.

[0015] Figure 6 is a layout diagram illustrating a connection relationship between a memory block and a page buffer according to a first embodiment of the present disclosure.

[0016] Figure 7A and Figure 7Bis a table including voltages and transistor states during a programming operation according to a first embodiment of the present disclosure when at least one plug is not selected.

[0017] Figure 8A and Figure 8B is a table including voltages and transistor states during a programming operation according to a first embodiment of the present disclosure when all plugs are selected plugs.

[0018] Figure 9A and Figure 9B is a diagram for sequentially explaining a programming operation according to a first embodiment of the present disclosure when all plugs are unselected plugs.

[0019] Figure 10 is a perspective view showing the structure of a memory block according to a second embodiment of the present disclosure.

[0020] Figure 11 is a layout diagram showing the connection relationship between a memory block and a page buffer according to a second embodiment of the present disclosure.

[0021] Figure 12A and Figure 12B is a table including voltages and transistor states during a programming operation according to a second embodiment of the present disclosure when at least one plug is not selected.

[0022] Figure 13A and Figure 13B is a table including voltages and transistor states during a programming operation according to a second embodiment of the present disclosure when all plugs are selected plugs.

[0023] Figure 14A and Figure 14B is a table including voltages and transistor states during a programming operation according to a second embodiment of the present disclosure when all plugs are unselected plugs.

[0024] Figure 15 is a perspective view showing the structure of a memory block according to a third embodiment of the present disclosure.

[0025] Figure 16 is a layout diagram showing the connection relationship between a memory block and a page buffer according to a third embodiment of the present disclosure.

[0026] Figure 17A and Figure 17B is a table including voltages and transistor states during a programming operation according to a third embodiment of the present disclosure when at least one plug is not selected.

[0027] Figure 18A and Figure 18Bis a table including voltages and transistor states during a programming operation according to a third embodiment of the present disclosure when all plugs are selected plugs.

[0028] Figure 19A and Figure 19B is a table including voltages and transistor states during a programming operation according to a third embodiment of the present disclosure when all plugs are unselected plugs.

[0029] Figure 20 is a diagram showing an embodiment of a memory card system including a memory device according to the present disclosure.

[0030] Figure 21 is a diagram showing an embodiment of a solid state drive (SSD) system including a memory device according to the present disclosure. DETAILED DESCRIPTION

[0031] The specific structures or function descriptions disclosed herein describe embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure should not be construed as limited to the embodiments described below, and may be modified in various forms and replaced with other equivalent embodiments.

[0032] Although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from other elements. The phrase "disposed on" includes being disposed on or above or touching, but not necessarily making electrical contact. As used herein, contact includes electrical coupling or electrical connection. Terms such as "top", "bottom", "above", "below", "beneath", "above", "upper", "lower", "uppermost", "vertical" and other terms implying spatial relationships are used only for ease of description or reference to the drawings, and are not limiting.

[0033] Various embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Cross-hatching throughout the drawings indicates corresponding or similar regions between the drawings, rather than indicating the materials of the regions.

[0034] Various embodiments of the present disclosure relate to a method of operating a memory device, which can suppress an increase in the threshold voltage of unselected memory cells.

[0035] Figure 1 is a diagram showing a memory device.

[0036] Referring to Figure 1 , the memory device 100 includes a memory cell array 110 and a peripheral circuit 180.

[0037] The memory cell array 110 includes a first memory block BLK1 to a j-th memory block BLKj, where j is a positive integer. When referring to the memory blocks BLK1 to BLKj, it includes each of the memory blocks BLK1, BLK2, BLK3, ..., to BLKn such as the memory blocks BLK1 to BLKj. Each of the memory blocks BLK1 to BLKj includes memory cells capable of storing data. The drain select line DSL, the word line WL, the source select line SSL, and the source line SL are connected to each of the memory blocks BLK1 to BLKj, and the bit line BL is commonly connected to the memory blocks BLK1 to BLKj.

[0038] Each of the memory blocks BLK1 to BLKj is formed in a three-dimensional (3D) structure. Each memory block having a 3D structure includes memory cells stacked on a substrate in a vertical or Z direction as shown in, for example, the figure.

[0039] According to the programming scheme, each memory cell stores 1-bit data or 2-bit or more data. For example, the scheme of storing 1-bit data in one memory cell is called the single-level cell (SLC) scheme, the scheme of storing 2-bit data in one memory cell is called the multi-level cell (MLC) scheme. The scheme of storing 3-bit data in one memory cell is called the triple-level cell (TLC) scheme, and the scheme of storing 4-bit data in one memory cell is called the quad-level cell (QLC) scheme.

[0040] The peripheral circuit 180 performs a programming operation including storing data in the memory cell array 110, a read operation including outputting data stored in the memory cell array 110, and an erase operation including erasing data stored in the memory cell array 110. For example, the peripheral circuit 180 includes a voltage generator 120, a row decoder 130, a page buffer bank 140, a column decoder 150, an input / output circuit 160, and a control circuit 170.

[0041] The voltage generator 120 generates various operation voltages Vop for any one of the programming operation, the read operation, and the erase operation in response to the operation code OPCD. For example, the voltage generator 120 generates a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verify voltage, a read voltage, a pass voltage, and an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 is applied to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL of the memory block selected by the row decoder 130.

[0042] The programming voltage is the voltage applied to the selected word line among the word lines WL during a programming operation, and is used to increase the threshold voltage of the memory cells coupled to the selected word line. The conduction voltage is applied to the drain select line DSL and the source select line SSL, and is used to turn on the drain select transistor and the source select transistor. The cutoff voltage is applied to the drain select line DSL and the source select line SSL, and is used to turn off the drain select transistor and the source select transistor. For example, the cutoff voltage may be 0V. The precharge voltage may be a voltage higher than 0V, and is applied to the bit line during a read operation. The verify voltage is used during a verify operation including determining whether the threshold voltage of the selected memory cell has increased to a target level. The verify voltage may be set to various levels according to the target level, and is applied to the selected word line.

[0043] The read voltage is applied to the selected word line during a read operation performed on the selected memory cell. For example, the read voltage may be set to various levels according to the programming scheme of the selected memory cell. The pass voltage is the voltage applied to the unselected word lines among the word lines WL during a programming operation or a read operation, and is used to turn on the memory cells coupled to the unselected word lines.

[0044] The erase voltage is used during an erase operation including erasing the memory cells included in the selected memory block, and is applied to the source line SL.

[0045] The row decoder 130 is configured to send the operation voltage Vop to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL respectively coupled to the memory block selected according to the row address RADD. For example, the row decoder 130 is coupled to the voltage generator 120 through the global line GL, and is coupled to the memory blocks BLK1 to BLKj through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0046] The page buffer group 140 includes multiple (j) page buffers (not shown) respectively coupled to the memory blocks BLK1 to BLKj. The page buffers are coupled to the memory blocks BLK1 to BLKj through the corresponding bit lines BL. During a read operation, in response to the page buffer control signal PBSIG, the page buffers sense the current or voltage of the bit line whose current or voltage changes with the threshold voltage of the selected memory cell, and temporarily store the sensed data.

[0047] The column decoder 150 is configured to facilitate data transfer between the page buffer bank 140 and the input / output circuit 160 in response to receiving a column address CADD. For example, the column decoder 150 is coupled to the page buffer bank 140 through column lines CL and transmits an enable signal through the column lines CL. The page buffers included in the page buffer bank 140 receive data from the input / output circuit 160 or output data to the input / output circuit 160 through data lines DL in response to the enable signal.

[0048] The input / output circuit 160 is configured to receive or output a command CMD, an address ADD, and data through input / output lines I / O. For example, the input / output circuit 160 transmits the command CMD and the address ADD received from an external controller through the input / output lines I / O to the control circuit 170, and transmits the data received from the external controller through the input / output lines I / O to the page buffer bank 140. Alternatively, the input / output circuit 160 outputs the data DATA received from the page buffer bank 140 to the external controller through the input / output lines I / O.

[0049] The control circuit 170 may output an opcode OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. For example, when the command CMD input to the control circuit 170 is a command corresponding to a programming operation, the control circuit 170 controls the devices included in the peripheral circuit 180 such that a programming operation is performed on the memory block selected by the address ADD. When the command CMD input to the control circuit 170 is a command corresponding to a read operation, the control circuit 170 controls the devices included in the peripheral circuit 180 such that a read operation is performed on the memory block selected by the address and the read data is output. When the command CMD input to the control circuit 170 is a command corresponding to an erase operation, the control circuit 170 controls the devices included in the peripheral circuit 180 such that an erase operation is performed on the selected memory block.

[0050] The control circuit 170 changes and outputs the opcode OPCD and the page buffer control signal PBSIG such that multiple plugs connected to different drain selection lines in the selected memory block are simultaneously programmed during a programming operation. For example, the control circuit 170 outputs the opcode OPCD to apply a conduction voltage to multiple drain selection lines connected to the selected memory block, and outputs the page buffer control signal PBSIG to select multiple plugs connected to the multiple drain selection lines.

[0051] Figure 2 is a diagram showing the arrangement of a memory cell array and a peripheral circuit.

[0052] Referring to Figure 2, a memory cell array 110 is disposed on a peripheral circuit 180. The memory cell array 110 includes memory blocks BLK1 to BLKj. Each of the memory blocks BLK1 to BLKj includes plugs extending in the Z direction (e.g., as shown in Figure 5 or Figure 6 ). Each plug includes a source select transistor, a memory cell, and a drain select transistor. The memory blocks BLK1 to BLKj are spaced apart from each other in the Y direction and extend in the X direction. The consecutive memory blocks BLK1 to BLKj can be separated by a slit SLT.

[0053] The memory blocks BLK1 to BLKj can be disposed between a bit line BL and a source line SL. The bit line BL can be disposed on the memory blocks BLK1 to BLKj, and the source line SL can be disposed below the memory blocks BLK1 to BLKj. Accordingly, the source line SL can be disposed between the memory cell array 110 and the peripheral circuit 180. The bit line BL can be connected to the plugs at the top of the memory blocks BLK1 to BLKj, and the source line SL can be connected to the plugs at the bottom of the memory blocks BLK1 to BLKj.

[0054] Although as shown in Figure 2 , the bit line BL is disposed on or above the memory cell array 110 and the source line SL is disposed below the memory cell array 110, the source line SL can be disposed on or above the memory cell array 110 and the bit line BL can be disposed below or beneath the memory cell array 110.

[0055] Although the embodiments of the present disclosure described herein are based on a structure in which the bit line BL is disposed on or above the memory cell array 110, the embodiments of the present disclosure are also applicable to a structure in which the bit line BL is disposed below or beneath the memory cell array 110.

[0056] Figure 3 is a circuit diagram showing a memory block.

[0057] Referring to Figure 3 , as an example, the first memory block BLK1 among the memory blocks BLK1 to BLKj as shown in Figure 2 is shown.

[0058] The first memory block BLK1 includes a plurality of cell strings ST connected between a source line SL and first to fourth bit lines BL1 to BL4. The cell strings ST are included in the plugs. Referring to Figure 4 to describe the plugs. Although four bit lines BL1 to BL4 are shown in Figure 3 , additional bit lines can be connected to each memory block. According to the arrangement order, the first bit line BL1 and the third bit line BL3 are odd bit lines BLo, and the second bit line BL2 and the fourth bit line BL4 are even bit lines Ble.

[0059] The cell strings ST are commonly connected to the source line SL. Among the cell strings ST, the cell strings ST arranged along the X direction are connected to the first bit line BL1 to the fourth bit line BL4, and the cell strings ST arranged along the Y direction are connected to any one of the bit lines BL1 to BL4.

[0060] Each cell string ST includes a source selection transistor SST, memory cells MC1 to MCn, and a drain selection transistor DST.

[0061] The source selection transistor SST is connected between the source line SL and the first memory cell MC1, and the drain selection transistor DST is connected between the nth memory cell MCn and the corresponding bit line, where n is a positive integer. The memory cells MC1 to MCn are connected between the source selection transistor SST and the drain selection transistor DST. The number of drain selection transistors DST and the number of source selection transistors SST are not limited to Figure 3 those shown. In addition to the memory cells MC1 to MCn, dummy cells may be connected between the drain selection transistor DST and the source selection transistor SST. The memory cells MC1 to MCn store user data or normal data, and the dummy cells store dummy data.

[0062] The gates of the drain selection transistors DST included in different cell strings ST are connected to the drain selection line DSL1 or DSL2. The gates of the memory cells MC1 to MCn included in different cell strings ST are respectively connected to the word lines WL1 to WLn. The gates of the source selection transistors SST included in different cell strings ST are connected to the source selection line SSL1 or SSL2. A group of memory cells arranged in the X direction and connected to the same word line included in the cell string ST may be referred to as a page PG. In the memory device, a programming operation or a read operation on a selected memory block may be performed based on the page PG.

[0063] The drain selection line may be divided into or include a first drain selection line DSL1 and a second drain selection line DSL2. The drain selection lines DSL1 and DSL2 extend in the X direction and are arranged in parallel along the Y direction. The cell string ST is divided into a first cell string ST1 connected to the first drain selection line DSL1 and a second cell string ST2 connected to the second drain selection line DSL2.

[0064] During a programming operation, when the first drain select line DSL1 is selected and the second drain select line DSL2 is not selected, the first memory cell group 31 corresponding to the first drain select line DSL1 is the target of the programming operation, and the second memory cell group 32 corresponding to the second drain select line DSL2 is excluded as the target of the programming operation. Therefore, when the first drain select line DSL1 is selected, the memory cells included in the first memory cell group 31 are selected. When the second drain select line DSL2 is not selected, the memory cells included in the second memory cell group 32 are not selected. When the first drain select line DSL1 is not selected, the memory cells included in the first memory cell group 31 are not selected. When the second drain select line DSL2 is selected, the memory cells included in the second memory cell group 32 are selected.

[0065] During a programming operation, when the first drain select line DSL1 is selected, a conduction voltage is applied to the first drain select line DSL1, and when the first drain select line DSL1 is not selected, a cut-off voltage is applied to the first drain select line DSL1. The conduction voltage is a voltage that turns on the drain select transistor connected to the first drain select line DSL1, and the cut-off voltage is a voltage that turns off the drain select transistor connected to the first drain select line DSL1.

[0066] During a programming operation, when a conduction voltage is applied to the first drain select line DSL1 and a cut-off voltage is applied to the second drain select line DSL2, the threshold voltages of the memory cells included in the second memory cell group 32 are maintained in the previous state, while the memory cells included in the first memory cell group 31 are programmed.

[0067] In order to maintain the threshold voltages of the memory cells included in the second memory cell group 32, a channel boosting operation for increasing the channel voltage is performed on the second cell string ST2.

[0068] Since the selected word line to which the programming voltage is applied is commonly connected to the first memory cell group 31 and the second memory cell group 32, a programming disturbance DS may occur in the second memory cell group 32 adjacent to the first memory cell group 31 in the Y direction. Programming disturbance refers to the situation or phenomenon in which the threshold voltage of an unselected memory cell increases.

[0069] In order to reduce programming disturbance, the present embodiment discloses a programming operation performed simultaneously on the first cell string ST1 connected to the first drain select line DSL1 and the second cell string ST2 connected to the second drain select line DSL2.

[0070] Figure 4FIG. is a flowchart showing a method of a programming operation of a memory device according to the present disclosure. The method is performed, for example, by various components of the peripheral circuit 180.

[0071] Referring Figure 4 , when the programming operation of the selected memory block starts, channels of plugs among the plugs included in the selected memory block, which are connected to different select transistors, are precharged S41. The different select transistors refer to transistors connected to different select lines. For example, the different select transistors include a drain select transistor connected to a first drain select line and a drain select transistor connected to a second drain select line. When a precharge voltage is applied through a bit line and a conduction voltage is applied to the first drain select line DSL1 and the second drain select line DSL2, the precharge voltage is applied to the channels of the plugs connected to the first drain select line DSL1 and the second drain select line DSL2. The precharge voltage may be a positive voltage higher than 0V. Since all the drain select transistors connected to the first drain select line DSL1 and the second drain select line DSL2 are turned on, the precharge voltage can be applied to the channels of the plugs connected to the first drain select line DSL1 and the second drain select line DSL2 at the same time.

[0072] When the channels of the plugs connected to different select transistors are precharged with the precharge voltage, each plug is classified S42 as a selected plug or an unselected plug.

[0073] The selected plugs and the unselected plugs are classified according to the data input to the page buffer. For example, the plugs connected to the page buffer with the input data "0" are classified as selected plugs, and the plugs connected to the page buffer with the input data "1" are classified as unselected plugs.

[0074] When at least one plug connected to a different select transistor is determined S42 as an unselected plug, a programming enable voltage is applied S43 to the channel of the selected plug, and a programming inhibit voltage is applied S43 to the channel of the unselected plug. For example, the page buffer with the input data "0" applies the programming enable voltage to the corresponding bit line, and the page buffer with the input data "1" applies the programming inhibit voltage to the corresponding bit line. The programming enable voltage may be 0V or a positive voltage lower than the programming inhibit voltage. The programming inhibit voltage may be a positive voltage higher than the programming enable voltage.

[0075] When all the plugs connected to different select transistors are determined S42 as selected plugs, a programming enable voltage is applied S44 to the channels of the selected plugs.

[0076] When all the plugs connected to different select transistors are determined S42 as unselected plugs, a programming inhibit voltage is applied S45 to the channels of the unselected plugs.

[0077] In other words, when the plug is an unselected plug, the memory cell of the unselected plug is an unselected memory cell, and when the plug is a selected plug, the memory cell of the selected plug is a selected memory cell. When the selected memory cell is included in the first plug and the second plug, a programming enable voltage is applied to the first channel of the first plug and the second channel of the second plug. When the second plug is an unselected plug and the selected memory cell is included in the first plug and not included in the second plug, a programming enable voltage is applied to the first channel of the first plug, and a programming inhibit voltage is applied to the second channel of the second plug. When the first plug and the second plug are unselected plugs and the selected memory cell is not included in the first plug and not included in the second plug, a programming inhibit voltage is applied to the first channel of the first plug and the second channel of the second plug. When the selected memory cell is included in each of the multiple plugs, a programming voltage is applied to the channel of each of the multiple plugs. When the selected memory cell is not included in at least one of the multiple plugs, a programming voltage is applied to the channel of each of the plugs among the multiple plugs that includes the selected memory cell; and a programming inhibit voltage is applied to the channel of the plug among the multiple plugs that does not include the selected memory cell. When the selected memory cell is not included in any of the multiple plugs, a programming inhibit voltage is applied to each channel of the multiple plugs.

[0078] After applying the programming enable voltage and the programming inhibit voltage S43, S44, S45, a pass voltage is applied to the unselected word line and a programming voltage is applied to the selected word line. Alternatively, after the pass voltage is applied to the unselected word line and the selected word line, the programming voltage can be applied to the selected word line. The pass voltage can be a voltage capable of turning on the memory cell and can be adjusted to various levels. The pass voltage can be at different levels according to the position of the unselected word line. When the pass voltage is applied to the selected word line, the level of the pass voltage applied to the selected word line can be different from the level of the pass voltage applied to the unselected word line. The programming voltage is a voltage capable of increasing the threshold voltage of the memory cell.

[0079] When the programming voltage is applied to the selected word line for a predetermined period of time, a verification operation S47 is performed. The verification operation includes determining whether the threshold voltage of the selected memory cell has reached or increased to a target voltage. During the verification operation, a verification voltage is applied to the selected word line. The verification voltage can be a positive voltage lower than the programming voltage and can be changed according to the target voltage.

[0080] When the execution result of the verification operation is determined S47 to be passed, the programming operation for the selected page is terminated or ended. When the execution result of the verification operation is determined S47 to be failed, the programming voltage is increased S48 to further perform the programming operation on the selected page. When the programming voltage is increased by a preset step voltage, the method is executed again starting from the precharge S41 process. This can be repeatedFigure 4 The method is repeated until the result of the verification operation is determined to pass in S47.

[0081] Examples of the structure of a memory block for performing the Figure 4 method according to various embodiments are described.

[0082] Figure 5 FIG. is a perspective view showing the structure of a memory block according to a first embodiment of the present disclosure.

[0083] Referring to Figure 5 , a part of the memory block including word lines and drain select lines is shown. The word lines WL(n - 3) to WLn are stacked, and the first drain select line DSL1 and the second drain select line DSL2 are provided above the topmost n-th word line WLn among the word lines. The word lines WL(n - 3) to WLn are spaced apart from the first drain select line DSL1 and the second drain select line DSL2. The first drain select line DSL1 is spaced apart from the second drain select line DSL2 through a divided region DV extending in the X direction.

[0084] The first drain select line DSL1 and the second drain select line DSL2 are in contact with plugs arranged along the first row R1 and the second row R2. For example, the first plug P1 arranged along the first row R1 and the third plug P3 arranged along the second row R2 are in contact with the first drain select line DSL1, and the second plug P2 arranged along the first row R1 and the fourth plug P4 arranged along the second row R2 are in contact with the second drain select line DSL2. The first plug P1 and the third plug P3 penetrate the first drain select line DSL1 and the word lines WL(n - 3) to WLn. The second plug P2 and the fourth plug P4 penetrate the second drain select line DSL2 and the word lines WL(n - 3) to WLn.

[0085] In Figure 5 the remaining region of the memory block not shown, the first plug P1 to the fourth plug P4 penetrate the remaining word lines W1 to WL(n - 4) and the source select line.

[0086] The first row R1 of the first plug P1 and the first row R1 of the second plug P2 may be symmetric with respect to the divided region DV, and the second row R2 of the third plug P3 and the second row R2 of the fourth plug P4 may be symmetric with respect to the divided region DV.

[0087] The plugs P1 to P4 may have the same structure. Referring to the cross-section of any one of the plugs P1 to P4 (for example, the first plug P1) in the plane 51, the first plug P1 includes a core pillar CP that forms a memory cell or a select transistor, a channel layer CH, a tunnel isolation layer TX, a charge trapping layer CTL, and a blocking layer BX. The core pillar CP may have a cylindrical shape and may be formed of an insulating material or a conductive material. The channel layer CH may have a cylindrical shape surrounding or encircling the outer surface of the core pillar CP and may be formed of polysilicon. The tunnel isolation layer TX may have a cylindrical shape surrounding or encircling the outer surface of the channel layer CH and may be formed of an oxide layer. The charge trapping layer CTL may have a cylindrical shape surrounding the outer surface of the tunnel isolation layer TX and may be formed of a nitride layer. The blocking layer BX may have a cylindrical shape surrounding or encircling the outer surface of the charge trapping layer CTL and may be formed of an oxide layer.

[0088] The first bit lines BL1 to the tenth bit lines BL10 are arranged on the first plug P1 to the fourth plug P4. Figure 5 A part of the memory block is shown. The number of bit lines is not limited to Figure 5 the number of bit lines shown. The bit lines BL1 to BL10 may extend individually along the Y direction and may be spaced apart from each other along the X direction. Two bit lines are arranged on each of the first plug P1 to the fourth plug P4, and one of the two bit lines contacts one plug. For example, assuming that the first bit line BL1 and the second bit line BL2 are arranged on the first plug P1 and the second plug P2, the first bit line BL1 contacts the first plug P1, and the second bit line BL2 contacts the second plug P2. The third bit line BL3 and the fourth bit line BL4 are arranged on the third plug P3 and the fourth plug P4, where the third bit line BL3 contacts the third plug P3 and the fourth bit line BL4 contacts the fourth plug P4.

[0089] Figure 6 is a layout diagram showing the connection relationship between the memory block and the page buffer according to the first embodiment of the present disclosure.

[0090] Referring to Figure 5 and Figure 6 , the first bit lines BL1 to the ninth bit lines BL9 are respectively connected to the first page buffer PB1 to the ninth page buffer PB9. For example, the first bit line BL1, the third bit line BL3, the fifth bit line BL5, the seventh bit line BL7, and the ninth bit line BL9 are respectively connected to the first page buffer PB1, the third page buffer PB3, the fifth page buffer PB5, the seventh page buffer PB7, and the ninth page buffer PB9. The second bit line BL2, the fourth bit line BL4, the sixth bit line BL6, and the eighth bit line BL8 are respectively connected to the second page buffer PB2, the fourth page buffer PB4, the sixth page buffer PB6, and the eighth page buffer PB8.

[0091] One of the first plugs P1 contacts different bit lines among the first bit line BL1, the fifth bit line BL5, and the ninth bit line BL9, and each contact is made through a different contact CT. For example, the contact CT is an electrical conductor such as between the channel layer CH of the plug and the bit line. One of the second plugs P2 contacts the second bit line BL2 through one contact CT, and a different second plug P2 contacts the sixth bit line BL6 through a different contact CT. One of the third plugs P3 contacts the third bit line BL3 through one contact CT, and a different third plug P3 contacts the seventh bit line BL7 through a different contact CT. One of the fourth plugs P4 contacts the fourth bit line BL4 through one contact CT, and a different fourth plug P4 contacts the eighth bit line BL8 through a different contact CT.

[0092] When a conduction voltage is applied to the first drain select line DSL1, the first plug P1 is connected to the first page buffer PB1, the fifth page buffer PB5, and the ninth page buffer PB9 through the contact CT and the first bit line BL1, the fifth bit line BL5, and the ninth bit line BL9 respectively, and the third plug P3 is connected to the third page buffer PB3 and the seventh page buffer PB7 through the contact CT and the third bit line BL3 and the seventh bit line BL7 respectively.

[0093] When a conduction voltage is applied to the second drain select line DSL2, the second plug P2 is connected to the second page buffer PB2 and the sixth page buffer PB6 through the contact CT and the second bit line BL2 and the sixth bit line BL6 respectively, and the fourth plug P4 is connected to the fourth page buffer PB4 and the eighth page buffer PB8 through the contact CT and the fourth bit line BL4 and the eighth bit line BL8 respectively.

[0094] When a conduction voltage is applied to the first drain select line DSL1 and the second drain select line DSL2 simultaneously, the first plug P1 is electrically connected to the first page buffer PB1, the fifth page buffer PB5, and the ninth page buffer PB9 simultaneously, the second plug P2 is electrically connected to the second page buffer PB2 and the sixth page buffer PB6 simultaneously, the third plug P3 is electrically connected to the third page buffer PB3 and the seventh page buffer PB7 simultaneously, and the fourth plug P4 is electrically connected to the fourth page buffer PB4 and the eighth page buffer PB8 simultaneously.

[0095] Therefore, during the programming operation, the programming operation can be performed simultaneously on the first plug P1 and the third plug P3 that contact the first drain select line DSL1 and the second plug P2 and the fourth plug P4 that contact the second drain select line DSL2.

[0096] For example, when a conduction voltage is simultaneously applied to the first drain select line DSL1 and the second drain select line DSL2, plugs P1 to P4 are simultaneously enabled. Among the memory cells included in plugs P1 to P4, the selected memory cells are classified as selected memory cells or unselected memory cells according to the data input to page buffers PB1 to PB9.

[0097] Accordingly, each of the enabled plugs P1 to P4 is classified as a selected plug or an unselected plug according to the data input to page buffers PB1 to PB9. For example, the plug corresponding to the page buffer with input data "0" is a selected plug, and the plug corresponding to the page buffer with input data "1" is an unselected plug. Classifying each plug as a selected plug or an unselected plug depends on the data input to the corresponding page buffer, and the classification can be changed. For example, according to the settings of the memory device, the plug corresponding to the page buffer with input data "0" can be an unselected plug, and the plug corresponding to the page buffer with input data "1" can be a selected plug. In the following embodiments, the unselected plug corresponds to data "1", and the selected plug corresponds to data "0".

[0098] During a programming operation, all plugs P1 to P4 that contact the first drain select line DSL1 and the second drain select line DSL2 are enabled, and the selected plugs and unselected plugs among the enabled plugs are classified as selected or unselected. Accordingly, some first plugs P1 and third plugs P3 that contact the first drain select line DSL1 are selected plugs according to the data input to page buffers PB1, PB3, PB5, PB7, and PB9, and the remaining plugs are unselected plugs. Some plugs P2 and P4 that contact the second drain select line DSL2 are selected plugs according to the data input to page buffers PB2, PB4, PB6, and PB8, and the remaining plugs are unselected plugs.

[0099] As a result, during a programming operation, when the enabled plugs and disabled plugs are separated by a split region between the first drain select line DSL1 and the second drain select line DSL2, all the disabled plugs are unselected plugs. Accordingly, the potential difference between the enabled plugs and the disabled plugs increases, and programming disturbance may occur in some of the disabled plugs.

[0100] During a programming operation, when all plugs that contact the first drain select line DSL1 and the second drain select line DSL2 are enabled, the selected plugs and unselected plugs are arranged regardless of the first drain select line DSL1 and the second drain select line DSL2, thereby reducing the potential difference between the plugs, and as a result, programming disturbance can be alleviated.

[0101] Since the plugs that contact the first drain select line DSL1 and the second drain select line DSL2 can be selected plugs or unselected plugs according to the data input to the page buffer, programming operations of various examples are described.

[0102] Figure 7A and Figure 7B is a table including voltages and transistor states during a programming operation according to a first embodiment of the present disclosure when at least one plug is not selected.

[0103] Referring to Figure 6 and Figure 7A , in this example, the plug that contacts the first drain select line DSL1 is the selected plug Sel_PL connected to the first bit line BL1, and the plug that contacts the second drain select line DSL2 is the unselected plug Unsel_PL connected to the second bit line BL2. For example, the selected plug Sel_PL is the plug connected to the bit line to which a programming enable voltage is applied. The bit line to which a programming enable voltage is applied is the bit line connected to the page buffer for the input data "0". The unselected plug Unsel_PL is the plug connected to the bit line to which a programming inhibit voltage is applied. The bit line to which a programming inhibit voltage is applied is the bit line connected to the page buffer for the input data "1".

[0104] The ground voltage GND is applied to the source line SL, and all source select transistors SST are turned off. As a result, the selected plug Sel_PL and the unselected plug Unsel_PL are not connected to the source line SL. A pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage capable of turning on the memory cell. The level of the pass voltage Vpass can be one of various different values higher than 0V. A conduction voltage Von is applied to the first drain select line DSL1 and the second drain select line DSL2. Since the conduction voltage Von is applied to the first drain select line DSL1 and the second drain select line DSL2, the drain select transistors DST connected to the drain select lines DSL1 and DSL2 are turned on.

[0105] A precharge voltage Vpre is applied to the first bit line BL1 and the second bit line BL2. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0106] Since all the drain select transistors DST connected to the drain select lines DSL1 and DSL2 are turned on, the precharge voltage Vpre applied to the first bit line BL1 is applied to the first channel 1CH of the selected plug Sel_PL, and the precharge voltage Vpre applied to the second bit line BL2 is applied to the second channel 2CH of the unselected plug Unsel_PL. Accordingly, the channels 1CH and 2CH can be precharged to the precharge voltage Vpre simultaneously.

[0107] Referring to Figure 6 and Figure 7B , after the first channel 1CH and the second channel 2CH are precharged, as described with reference to Figure 7A , according to the data of the page buffer connected to the bit lines BL1 and BL2, the programming enable voltage Val is applied to the first bit line BL1, and the programming inhibit voltage Vinh is applied to the second bit line BL2. In this example, the data input to the page buffer connected to the first bit line BL1 is "0", and the data input to the page buffer connected to the second bit line BL2 is "1". When the data "0" is the data for increasing the threshold voltage of the memory cell and the data "1" is the data for maintaining the threshold voltage of the memory cell in the previous state, the page buffer inputting the data "0" outputs the programming enable voltage Val through the corresponding bit line, and the page buffer inputting the data "1" outputs the programming inhibit voltage Vinh through the corresponding bit line. Therefore, as described with reference to Figure 7A , the plug to which the programming enable voltage Val is applied is the selected plug Sel_PL, and the plug to which the programming inhibit voltage Vinh is applied is the unselected plug Unsel_PL. The programming inhibit voltage Vinh can be a positive voltage higher than the programming enable voltage Val.

[0108] Because the drain select transistors DST connected to the drain select lines DSL1 and DSL2 are turned on, the programming enable voltage Val applied to the first bit line BL1 is transmitted to the first channel 1CH of the selected plug Sel_PL, and the programming inhibit voltage Vinh applied to the second bit line BL2 is transmitted to the second channel 2CH of the unselected plug Unsel_PL. Therefore, the voltage of the first channel 1CH is reduced to the programming enable voltage Val, and the voltage of the second channel 2CH is increased to the programming inhibit voltage Vinh. Because the source select transistor SST is turned on, the voltage of the first channel 1CH is at a voltage level lower than the voltage level of the programming enable voltage Val, and the voltage of the second channel 2CH is at a voltage level lower than the voltage level of the programming inhibit voltage Vinh.

[0109] To increase the threshold voltage of the selected memory cell among the memory cells connected to the selected word line Sel_WL, the voltage Vpass is applied to the unselected word line Unsel_WL, and the programming voltage Vpgm is applied to the selected word line Sel_WL. The memory cells connected to the selected word line Sel_WL among the memory cells included in the selected plug Sel_PL are the selected memory cells, and the memory cells connected to the selected word line Sel_WL among the memory cells included in the unselected plug Unsel_PL are the unselected memory cells.

[0110] A conduction voltage is applied to the source selection line, so that the source selection transistor SST is turned on. As a result, the first channel 1CH of the selected plug Sel_PL and the second channel 2CH of the unselected plug Unsel_PL are electrically connected to the source line SL. Consequently, the voltage of the first channel 1CH is less than or equal to the programming enable voltage Val, and the voltage of the second channel 2CH is less than or equal to the programming inhibit voltage Vinh.

[0111] Although not shown in the figures, in other embodiments, a positive voltage higher than 0V may be applied to the source line SL and a cut-off voltage may be applied to the source selection line to prevent the channel voltage of the unselected plug Unsel_PL from decreasing.

[0112] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming enable voltage Val applied to the first channel 1CH, the selected memory cells of the selected plug Sel_PL are programmed. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of the selected memory cells is equal to or higher than the reference voltage difference.

[0113] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming inhibit voltage Vinh applied to the second channel 2CH, the unselected memory cells of the unselected plug Unsel_PL are prohibited from being programmed. For example, the voltage difference between the gate and the channel of the unselected memory cells is lower than the reference voltage difference.

[0114] Even when the voltage of the second channel 2CH is lower than the programming inhibit voltage Vinh, the level of the programming inhibit voltage Vinh is high enough to prevent the threshold voltage of the unselected memory cells from increasing, and the programming inhibit voltage Vinh continues to be supplied to the second channel 2CH through the second bit line BL2. Therefore, the memory cells among the memory cells included in the unselected plug Unsel_PL that are connected to the selected word line Sel_WL are prohibited from being programmed.

[0115] Figure 8A and Figure 8B is a table including voltages and transistor states during a programming operation according to the first embodiment of the present disclosure when all plugs are selected plugs.

[0116] Referring to Figure 6 and Figure 8A , in this example, the plug in contact with the first drain selection line DSL1 is the selected plug Sel_PL connected to the first bit line BL1, and the plug in contact with the second drain selection line DSL2 is the selected plug Sel_PL connected to the second bit line BL2. For example, the selected plug Sel_PL is a plug connected to a bit line to which a programming enable voltage is applied. The bit line to which a programming enable voltage is applied is a bit line connected to a page buffer for inputting data "0".

[0117] A ground voltage GND is applied to the source line SL, and all source selection transistors SST are turned off. As a result, the selected plug Sel_PL is not connected to the source line SL. A pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage capable of turning on the memory cell. A turn-on voltage Von is applied to the drain selection lines DSL1 and DSL2. Since the turn-on voltage Von is applied to the drain selection lines DSL1 and DSL2, the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on.

[0118] A precharge voltage Vpre is applied to the first bit line BL1 and the second bit line BL2. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0119] Since all the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on, the precharge voltage Vpre applied to the first bit line BL1 is applied to the first channel 1CH of the selected plug Sel_PL, and the precharge voltage Vpre applied to the second bit line BL2 is applied to the second channel 2CH of the selected plug Sel_PL. Therefore, the channels 1CH and 2CH can be precharged to the precharge voltage Vpre simultaneously.

[0120] Refer to Figure 6 and Figure 8B , after the channels 1CH and 2CH are precharged as described in reference Figure 8A , a program enable voltage Val is applied to the first bit line BL1 and the second bit line BL2 according to the data of the page buffers connected to the first bit line BL1 and the second bit line BL2. In this example, the data input to the page buffers connected to the first bit line BL1 and the second bit line BL2 are both "0". When the data "0" is data for increasing the threshold voltage of the memory cell, the page buffer that inputs the data "0" outputs the program enable voltage Val through the corresponding bit line.

[0121] Since the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on, the program enable voltage Val applied to the bit lines BL1 and BL2 is transmitted to the channels 1CH and 2CH of the selected plug Sel_PL. Therefore, the voltages of the channels 1CH and 2CH are reduced to the program enable voltage Val. Since the source selection transistors SST are turned on, the voltages of the channels 1CH and 2CH are at a voltage level lower than the voltage level of the program enable voltage Val.

[0122] To increase the threshold voltage of the selected memory cells among the memory cells connected to the selected word line Sel_WL, a voltage Vpass is applied to the unselected word line Unsel_WL, and a programming voltage Vpgm is applied to the selected word line Sel_WL.

[0123] A conduction voltage is applied to the source selection line, so that the source selection transistor SST conducts. As a result, the first channel 1CH of the selected plug Sel_PL and the second channel 2CH of the selected plug Sel_PL are electrically connected to the source line SL. Consequently, the voltages of the channels 1CH and 2CH are lower than or equal to the programming enable voltage Val.

[0124] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming enable voltage Val applied to the channels 1CH and 2CH, the selected memory cells of the selected plug Sel_PL are programmed. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of the selected memory cell is equal to or higher than the reference voltage difference.

[0125] Since all the memory cells among the memory cells included in the selected plug Sel_PL that are connected to the selected word line Sel_WL are selected memory cells, the selected memory cells corresponding to different drain selection lines DSL1 and DSL2 and adjacent to each other can be programmed simultaneously.

[0126] In this way, the memory cells adjacent to each other are programmed simultaneously, whereby the voltage difference between the adjacent memory cells is reduced. Accordingly, programming disturbance between adjacent memory cells can be prevented.

[0127] Figure 9A and Figure 9B are tables including voltages and transistor states during the programming operation according to the first embodiment of the present disclosure when all plugs are unselected plugs.

[0128] Referring to Figure 6 and Figure 9A , in this example, the plug in contact with the first drain selection line DSL1 is the unselected plug Unsel_PL connected to the first bit line BL1, and the plug in contact with the second drain selection line DSL2 is the unselected plug Unsel_PL connected to the second bit line BL2. For example, the unselected plug Unsel_PL is a plug connected to a bit line to which a programming inhibition voltage is applied. The bit line to which the programming inhibition voltage is applied is a bit line connected to a page buffer for inputting data "1".

[0129] A ground voltage GND is applied to the source line SL, and all source selection transistors SST are turned off. As a result, the unselected plug Unsel_PL is not connected to the source line SL. A pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage capable of turning on the memory cell. A turn-on voltage Von is applied to the first drain selection line DSL1 and the second drain selection line DSL2. Since the turn-on voltage Von is applied to the first drain selection line DSL1 and the second drain selection line DSL2, the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on.

[0130] A precharge voltage Vpre is applied to the first bit line BL1 and the second bit line BL2. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0131] Since all the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on, the precharge voltage Vpre applied to the first bit line BL1 is applied to the first channel 1CH of the unselected plug Unsel_PL, and the precharge voltage Vpre applied to the second bit line BL2 is applied to the second channel 2CH of the unselected plug Unsel_PL. Accordingly, the channels 1CH and 2CH can be precharged to the precharge voltage Vpre simultaneously.

[0132] Referring to Figure 6 and Figure 9B , after the first channel 1CH and the second channel 2CH are precharged as described with reference to Figure 9A , a program inhibit voltage Vinh is applied to the bit lines BL1 and BL2 according to the data of the page buffers connected to the bit lines BL1 and BL2. In this example, the data input to the page buffers connected to the bit lines BL1 and BL2 is "1". When the data "1" is data for maintaining the threshold voltage of the memory cell in the previous state, the page buffer that inputs the data "1" outputs the program inhibit voltage Vinh through the corresponding bit line. Accordingly, as described with reference to Figure 9A , the plug to which the program inhibit voltage Vinh is applied is the unselected plug Unsel_PL.

[0133] Since the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on, the program inhibit voltage Vinh applied to the bit lines BL1 and BL2 is transmitted to the first channel 1CH and the second channel 2CH of the unselected plug Unsel_PL. Accordingly, the voltages of the channels 1CH and 2CH increase to the program inhibit voltage Vinh. Since the source selection transistors SST are turned on, the voltages of the channels 1CH and 2CH are at a voltage level lower than the voltage level of the program inhibit voltage Vinh.

[0134] To increase the threshold voltage of the selected memory cells among the memory cells connected to the selected word line Sel_WL, a voltage Vpass is applied to the unselected word line Unsel_WL, and a programming voltage Vpgm is applied to the selected word line Sel_WL. Among the memory cells included in the unselected plug Unsel_PL, the memory cells connected to the selected word line Sel_WL are unselected memory cells.

[0135] A conduction voltage is applied to the source selection line, so that the source selection transistor SST is turned on. As a result, channels 1CH and 2CH are electrically connected to the source line SL. Consequently, the voltages of channels 1CH and 2CH are lower than or equal to the programming inhibition voltage Vinh.

[0136] Although not shown in the figure, in other embodiments, a positive voltage higher than 0V may be applied to the source line SL and a cut-off voltage may be applied to the source selection line to prevent the channel voltage of the unselected plug Unsel_PL from decreasing.

[0137] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming inhibition voltage Vinh applied to the first channel 1CH and the second channel 2CH, the unselected memory cells of the unselected plug Unsel_PL are prohibited from being programmed. For example, the voltage difference between the gate and the channel of the unselected memory cell is lower than the reference voltage difference. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of the unselected memory cell is lower than the reference voltage difference.

[0138] Even when the voltages of channels 1CH and 2CH are lower than the programming inhibition voltage Vinh, the level of the programming inhibition voltage Vinh is high enough to prevent the threshold voltage of the unselected memory cells from increasing, and the programming inhibition voltage Vinh continues to be supplied to channels 1CH and 2CH through the bit lines BL1 and BL2. Therefore, when a programming operation is performed on the selected memory cells connected to the selected word line Sel_WL, the memory cells connected to the selected word line Sel_WL among the memory cells included in the unselected plug Unsel_PL are prohibited from being programmed.

[0139] Figure 10 is a perspective view showing the structure of a memory block according to a second embodiment of the present disclosure.

[0140] Refer to Figure 10, in the memory block according to the second embodiment, plug contacts the drain select lines DSL1 and DSL2 arranged along the first row R1 to the fourth row R4. For example, the first plug P1 arranged along the first row R1, the third plug P3 arranged along the second row R2, the fifth plug P5 arranged along the third row R3, and the seventh plug P7 arranged along the fourth row R4 contact the first drain select line DSL1. The second plug P2 arranged along the first row R1, the fourth plug P4 arranged along the second row R2, the sixth plug P6 arranged along the third row R3, and the eighth plug P8 arranged along the fourth row R4 contact the second drain select line DSL2. The first plug P1, the third plug P3, the fifth plug P5, and the seventh plug P7 penetrate the first drain select line DSL1 and the word lines WLn to WL(n - 3). The second plug P2, the fourth plug P4, the sixth plug P6, and the eighth plug P8 penetrate the second drain select line DSL2 and the word lines WLn to WL(n - 3).

[0141] In Figure 10 the remaining area of the memory block not shown, the plugs P1 to P8 penetrate the remaining word lines W1 to WL(n - 4) and the source select line.

[0142] The first row R1 of the first plug P1 and the first row R1 of the second plug P2 may be symmetric with respect to the division region DV, the second row R2 of the third plug P3 and the second row R2 of the fourth plug P4 may be symmetric with respect to the division region DV, the third row R3 of the fifth plug P5 and the third row R3 of the sixth plug P6 may be symmetric with respect to the division region DV, and the fourth row R4 of the seventh plug P7 and the fourth row R4 of the eighth plug P8 may be symmetric with respect to the division region DV.

[0143] The plugs P1 to P8 may have the same structure. The planar structure or cross-section of each of the plugs P1 to P8 is similar to the structure described with reference to Figure 5 description.

[0144] Multiple bit lines BL1 to BL4 are arranged on the plugs P1 to P8. Figure 10 Shows a part of the memory block. The number of bit lines is not limited to Figure 10 the number of bit lines shown. For convenience of description, only four bit lines (e.g., bit lines BL1 to BL4) are shown. The bit lines BL1 to BL4 extend along the Y direction and are spaced apart from each other along the X direction. The four bit lines are arranged on each of the plugs P1 to P8, and each of the four bit lines contacts one plug. For example, assuming that the bit lines BL1 to BL4 are arranged on the plugs P1, P2, P5, and P6, the first bit line BL1 contacts one of the first plugs P1, the second bit line BL2 contacts one of the second plugs P2, the third bit line BL3 contacts one of the fifth plugs P5, and the fourth bit line BL4 contacts one of the sixth plugs P6.

[0145] Figure 11 is a layout diagram showing the connection relationship between a memory block and a page buffer according to a second embodiment of the present disclosure.

[0146] Referring to Figure 10 and Figure 11 , the first bit line BL1 to the fourth bit line BL4 are respectively connected to the first page buffer PB1 to the fourth page buffer PB4.

[0147] Describe the first plug P1, the second plug P2, the fifth plug P5, and the sixth plug P6 that contact any one of the bit lines BL1 to BL4.

[0148] The first plug P1 contacts the first bit line BL1 through the contact CT. The second plug P2 contacts the second bit line BL2 through the contact CT. The fifth plug P5 contacts the third bit line BL3 through the contact CT. The sixth plug P6 contacts the fourth bit line BL4 through the contact CT.

[0149] When a conduction voltage is applied to the first drain select line DSL1, the first plug P1 is electrically connected to the first page buffer PB1 through the contact CT and the first bit line BL1, and the fifth plug P5 is electrically connected to the third page buffer PB3 through the contact CT and the third bit line BL3.

[0150] When a conduction voltage is applied to the second drain select line DSL2, the second plug P2 is electrically connected to the second page buffer PB2 through the contact CT and the second bit line BL2, and the sixth plug P6 is electrically connected to the fourth page buffer PB4 through the contact CT and the fourth bit line BL4.

[0151] When a conduction voltage is simultaneously applied to the first drain select line DSL1 and the second drain select line DSL2, the first plug P1 is electrically connected to the first page buffer PB1, and at the same time the second plug P2 is electrically connected to the second page buffer PB2.

[0152] During a programming operation, even if the first plug P1 and the second plug P2 are simultaneously selected, the first plug P1 is electrically connected to the first page buffer PB1 and the second plug P2 is electrically connected to the second page buffer PB2, so that programming operations can be simultaneously performed on the first plug P1 and the second plug P2.

[0153] Because the plugs that contact the drain select lines DSL1 and DSL2 can be selected plugs or unselected plugs according to the data input to the page buffer, various examples of programming operations are described.

[0154] Figure 12A and Figure 12Bis a table including voltages and transistor states during a programming operation according to the second embodiment of the present disclosure when at least one plug is not selected.

[0155] Refer to Figure 11 and Figure 12A , in this example, the plug contacting the first drain select line DSL1 is the selected plug Sel_PL coupled to the bit lines BL1 and BL3, and the plug contacting the second drain select line DSL2 is the selected plug Sel_PL coupled to the second bit line BL2 and the unselected plug Unsel_PL coupled to the fourth bit line BL4. The selected plug Sel_PL is the plug coupled to the bit line to which a programming enable voltage is applied. The bit line to which a programming enable voltage is applied is the bit line coupled to the page buffer for the input data "0". The unselected plug Unsel_PL is the plug coupled to the bit line to which a programming inhibit voltage is applied. The bit line to which a programming inhibit voltage is applied is the bit line coupled to the page buffer for the input data "1".

[0156] The ground voltage GND is applied to the source line SL, and all source select transistors SST are turned off. As a result, the selected plug Sel_PL and the unselected plug Unsel_PL are not coupled to the source line SL. A pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage capable of turning on the memory cell. A turn-on voltage Von is applied to the first drain select line DSL1 and the second drain select line DSL2, and can be applied to the drain select lines DSL1 and DSL2 simultaneously. Since the turn-on voltage Von is applied to the first drain select line DSL1 and the second drain select line DSL2, the drain select transistors DST coupled to the drain select lines DSL1 and DSL2 are turned on.

[0157] A precharge voltage Vpre is applied to the bit lines BL1 to BL4. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0158] Because all the drain select transistors DST coupled to the drain select lines DSL1 and DSL2 are turned on, the precharge voltage Vpre applied to the bit lines BL1 to BL3 is applied to the channels 1CH to 3CH of the selected plug Sel_PL, and the precharge voltage Vpre applied to the fourth bit line BL4 is applied to the fourth channel 4CH of the unselected plug Unsel_PL. Accordingly, the channels 1CH to 4CH can be precharged to the precharge voltage Vpre simultaneously.

[0159] Refer to Figure 11 and Figure 12B , in channels 1CH to 4CH as referred to in Figure 12AAfter the described pre-charging, according to the data of the page buffers connected to the bit lines BL1 to BL4, the programming enable voltage Val is applied to the bit lines BL1 to BL3, and the programming inhibit voltage Vinh is applied to the fourth bit line BL4. In this example, the data input to the page buffers connected to the bit lines BL1 to BL3 is "0", and the data input to the page buffer connected to the fourth bit line BL4 is "1". When the data "0" is the data for increasing the threshold voltage of the memory cell and the data "1" is the data for maintaining the threshold voltage of the memory cell in the previous state, the page buffer inputting the data "0" outputs the programming enable voltage Val through the corresponding bit line, and the page buffer inputting the data "1" outputs the programming inhibit voltage Vinh through the corresponding bit line. Thus, as described with reference to Figure 12A The plug to which the programming enable voltage Val is applied is the selected plug Sel_PL, and the plug to which the programming inhibit voltage Vinh is applied is the unselected plug Unsel_PL. The programming inhibit voltage Vinh can be a positive voltage higher than the programming enable voltage Val.

[0160] Since the drain select transistors DSTs connected to the select lines DSL1 and DSL2 are turned on, the programming enable voltage Val applied to the bit lines BL1 to BL3 is transmitted to the channels 1CH to 3CH of the selected plug Sel_PL, and the programming inhibit voltage Vinh applied to the fourth bit line BL4 can be transmitted to the fourth channel 4CH of the unselected plug Unsel_PL. Thus, the voltages of the first channel 1CH, the second channel 2CH, and the third channel 3CH are reduced to the programming enable voltage Val, and the voltage of the fourth channel 4CH is increased to the programming inhibit voltage Vinh. Since the source select transistor SST is turned on, the voltages of the channels 1CH to 3CH are at a voltage level lower than the voltage level of the programming enable voltage Val, and the voltage of the fourth channel 4CH is at a voltage level lower than the voltage level of the programming inhibit voltage Vinh.

[0161] To increase the threshold voltage of the selected memory cells among the memory cells connected to the selected word line Sel_WL, the voltage Vpass is applied to the unselected word line Unsel_WL, and the programming voltage Vpgm is applied to the selected word line Sel_WL. The memory cells among those included in the selected plug Sel_PL that are connected to the selected word line Sel_WL are the selected memory cells, and the memory cells among those included in the unselected plug Unsel_PL that are connected to the selected word line Sel_WL are the unselected memory cells.

[0162] A conduction voltage is applied to the source selection line, so that the source selection transistor SST is turned on. Accordingly, the channels 1CH to 3CH of the selected plug Sel_PL and the fourth channel 4CH of the unselected plug Unsel_PL are electrically connected to the source line SL. As a result, the voltages of the channels 1CH to 3CH are lower than or equal to the programming enable voltage Val, and the voltage of the fourth channel 4CH is lower than or equal to the programming inhibit voltage Vinh.

[0163] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming enable voltage Val applied to each of the channels 1CH to 3CH, the selected memory cells of the selected plug Sel_PL are programmed. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of each selected memory cell is equal to or higher than the reference voltage difference.

[0164] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming inhibit voltage Vinh applied to the fourth channel 4CH, the unselected memory cells of the unselected plug Unsel_PL are prohibited from being programmed. For example, the voltage difference between the gate and the channel of the unselected memory cell is lower than the reference voltage difference.

[0165] Even when the voltage of the fourth channel 4CH is lower than the programming inhibit voltage Vinh, the level of the programming inhibit voltage Vinh is high enough to prevent the threshold voltage of the unselected memory cell from increasing, and the programming inhibit voltage Vinh continues to be supplied to the fourth channel 4CH through the fourth bit line BL4. Accordingly, the memory cells among the memory cells included in the unselected plug Unsel_PL that are connected to the selected word line Sel_WL are prohibited from being programmed.

[0166] Figure 13A and Figure 13B is a table including voltages and transistor states during the programming operation according to the second embodiment of the present disclosure when all plugs are selected plugs.

[0167] Referring to Figure 11 and Figure 13A In this example, the plug that contacts the first drain selection line DSL1 is the selected plug Sel_PL that is connected to the first bit line BL1 and the third bit line BL3, and the plug that contacts the second drain selection line DSL2 is the selected plug Sel_PL that is connected to the second bit line BL2 and the fourth bit line BL4. Each selected plug Sel_PL is a plug that is connected to a bit line to which a programming enable voltage is applied. The bit line to which a programming enable voltage is applied is a bit line that is connected to a page buffer that inputs data "0".

[0168] The ground voltage GND is applied to the source line SL, and all source selection transistors SST are turned off. As a result, the selected plug Sel_PL is not connected to the source line SL. The pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage capable of turning on the memory cells. The turn-on voltage Von is applied to the drain selection lines DSL1 and DSL2, and can be applied to the drain selection lines DSL1 and DSL2 simultaneously. Since the turn-on voltage Von is applied to the drain selection lines DSL1 and DSL2, the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on.

[0169] The precharge voltage Vpre is applied to the bit lines BL1 to BL4. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0170] Since all the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on, the precharge voltage Vpre applied to the bit lines BL1 to BL4 is applied to the channels 1CH to 4CH of the selected plug Sel_PL. Therefore, the channels 1CH to 4CH can be precharged to the precharge voltage Vpre simultaneously.

[0171] Refer to Figure 11 and Figure 13B , after the channels 1CH to 4CH are precharged as described in reference to Figure 13A , the program enable voltage Val is applied to the bit lines BL1 to BL4 according to the data of the page buffers connected to the bit lines BL1 to BL4. In this example, the data input to the page buffers connected to the bit lines BL1 to BL4 is "0". When the data "0" is the data for increasing the threshold voltage of the memory cells and the data "1" is set as the data for maintaining the threshold voltage of the memory cells in the previous state, the page buffers inputting the data "0" output the program enable voltage Val through the corresponding bit lines. As described in reference to Figure 13A , the plug to which the program enable voltage Val is applied is the selected plug Sel_PL.

[0172] Since the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on, the program enable voltage Val applied to the bit lines BL1 to BL4 is transmitted to the channels 1CH to 4CH of the selected plug Sel_PL. Therefore, the voltage of the channels 1CH to 4CH is reduced to the program enable voltage Val. Since the source selection transistors SST are turned on, the voltage of the channels 1CH to 4CH is at a voltage level lower than the voltage level of the program enable voltage Val.

[0173] To increase the threshold voltage of the selected memory cells among the memory cells connected to the selected word line Sel_WL, a voltage Vpass is applied to the unselected word line Unsel_WL, and a programming voltage Vpgm is applied to the selected word line Sel_WL. Among the memory cells included in the selected plug Sel_PL, the memory cells connected to the selected word line Sel_WL are the selected memory cells.

[0174] A conduction voltage is applied to the source selection line, so that the source selection transistor SST conducts. As a result, the channels 1CH to 4CH of the selected plug Sel_PL are electrically connected to the source line SL. Consequently, the voltages of the channels 1CH to 4CH are lower than or equal to the programming enable voltage Val.

[0175] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming enable voltage Val applied to each of the channels 1CH to 4CH, the selected memory cells of the selected plug Sel_PL are programmed. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of each selected memory cell is equal to or higher than the reference voltage difference.

[0176] Since the selected memory cells of the plugs connected to different drain selection lines DSL1 and DSL2 are programmed simultaneously, programming disturbance in the Y direction, X direction, or XY direction (e.g., the diagonal direction between the X direction and the Y direction) can be reduced.

[0177] Figure 14A and Figure 14B is a table including voltages and transistor states during the programming operation according to the second embodiment of the present disclosure when all plugs are unselected plugs.

[0178] Referring to Figure 11 and Figure 14A In this example, the plug in contact with the first drain selection line DSL1 is the unselected plug Unsel_PL connected to the first bit line BL1 and the third bit line BL3, and the plug in contact with the second drain selection line DSL2 is the unselected plug Unsel_PL connected to the second bit line BL2 and the fourth bit line BL4. Each unselected plug Unsel_PL is a plug connected to a bit line to which a programming inhibition voltage is applied. The bit line to which the programming inhibition voltage is applied is the bit line of the page buffer connected to the input data "1".

[0179] The ground voltage GND is applied to the source line SL, and all source selection transistors SST are turned off. As a result, the unselected plug Unsel_PL is not connected to the source line SL. The pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage that can turn on the memory cell. The turn-on voltage Von is applied to the drain selection lines DSL1 and DSL2, and can be applied to the drain selection lines DSL1 and DSL2 simultaneously. Since the turn-on voltage Von is applied to the drain selection lines DSL1 and DSL2, the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on.

[0180] The precharge voltage Vpre is applied to the bit lines BL1 to BL4. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0181] Since all the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on, the precharge voltage Vpre applied to the bit lines BL1 to BL4 is applied to the channels 1CH to 4CH of the selected plug Sel_PL. Therefore, the channels 1CH to 4CH can be precharged to the precharge voltage Vpre simultaneously.

[0182] Refer to Figure 11 and Figure 14B , after the channels 1CH to 4CH are precharged as described in reference to Figure 14A , the program inhibit voltage Vinh is applied to the bit lines BL1 to BL4 according to the data of the page buffer connected to the bit lines BL1 to BL4. In this example, the data input to the page buffer connected to the bit lines BL1 to BL4 is "1". When the data "0" is the data for increasing the threshold voltage of the memory cell and the data "1" is the data for maintaining the threshold voltage of the memory cell in the previous state, the page buffer inputting the data "1" outputs the program inhibit voltage Vinh through the corresponding bit line. Therefore, as described in reference to Figure 14A , the plug applied with the program inhibit voltage Vinh is the unselected plug Unsel_PL.

[0183] Since the drain selection transistors DST connected to the drain selection lines DSL1 and DSL2 are turned on, the program inhibit voltage Vinh applied to the bit lines BL1 to BL4 is transmitted to the channels 1CH to 4CH of the unselected plug Unsel_PL. Therefore, the voltage of the channels 1CH to 4CH increases to the program inhibit voltage Vinh. Since the source selection transistor SST is turned on, the voltage of the channels 1CH to 4CH is at a voltage level lower than the voltage level of the program inhibit voltage Vinh.

[0184] To increase the threshold voltage of the selected memory cells among the memory cells connected to the selected word line Sel_WL, a voltage Vpass is applied to the unselected word line Unsel_WL, and a programming voltage Vpgm is applied to the selected word line Sel_WL. Among the memory cells included in the unselected plug Unsel_PL, the memory cells connected to the selected word line Sel_WL are unselected memory cells.

[0185] A conduction voltage is applied to the source selection line, so that the source selection transistor SST conducts. As a result, channels 1CH to 4CH are electrically connected to the source line SL. Consequently, the voltages of channels 1CH to 4CH are lower than or equal to the programming inhibition voltage Vinh.

[0186] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming inhibition voltage Vinh applied to each of channels 1CH to 4CH, the unselected memory cells of the unselected plug Unsel_PL are prohibited from being programmed. For example, the voltage difference between the gate and the channel of each unselected memory cell is lower than the reference voltage difference. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of each unselected memory cell is lower than the reference voltage difference.

[0187] Even when the voltages of channels 1CH to 4CH are lower than the programming inhibition voltage Vinh, the level of the programming inhibition voltage Vinh is high enough to prevent the threshold voltage of the unselected memory cells from increasing, and the programming inhibition voltage Vinh continues to be supplied to channels 1CH to 4CH through bit lines BL1 to BL4. Therefore, when a programming operation is performed on the selected memory cells connected to the selected word line Sel_WL, the memory cells connected to the selected word line Sel_WL among the memory cells included in the unselected plug Unsel_PL are prohibited from being programmed.

[0188] Figure 15 is a perspective view showing the structure of a memory block according to the third embodiment of the present disclosure.

[0189] Refer to Figure 15, the memory block according to the third embodiment includes four drain select lines, such as a first drain select line DSL1, a second drain select line DSL2, a third drain select line DSL3, and a fourth drain select line DSL4, also referred to as drain select lines DSL1 to DSL4. Each of the drain select lines DSL1 to DSL4 contacts plugs arranged along the first row R1 and the second row R2. For example, a first plug P1 arranged along the first row R1 and a fifth plug P5 arranged along the second row R2 contact the first drain select line DSL1. A second plug P2 arranged along the first row R1 and a sixth plug P6 arranged along the second row R2 contact the second drain select line DSL2. A third plug P3 arranged along the first row R1 and a seventh plug P7 arranged along the second row R2 contact the third drain select line DSL3. A fourth plug P4 arranged along the first row R1 and an eighth plug P8 arranged along the second row R2 contact the fourth drain select line DSL4.

[0190] The first plug P1 and the fifth plug P5 penetrate the first drain select line DSL1 and the word lines WL(n - 3) to WLn, the second plug P2 and the sixth plug P6 penetrate the second drain select line DSL2 and the word lines WL(n - 3) to WLn, the third plug P3 and the seventh plug P7 penetrate the third drain select line DSL3 and the word lines WL(n - 3) to WLn, and the fourth plug P4 and the eighth plug P8 penetrate the fourth drain select line DSL4 and the word lines WL(n - 3) to WLn.

[0191] In Figure 15 the remaining area of the memory block not shown, the plugs P1 to P8 penetrate the remaining word lines W1 to WL(n - 4) and the source select line.

[0192] The first row R1 of the first plug P1 and the first row R1 of the second plug P2 may be symmetric with respect to the division region DV between the first drain selection line DSL1 and the second drain selection line DSL2. The first row R1 of the second plug P2 and the first row R1 of the third plug P3 may be symmetric with respect to the division region DV between the second drain selection line DSL2 and the third drain selection line DSL3. The first row R1 of the third plug P3 and the first row R1 of the fourth plug P4 may be symmetric with respect to the division region DV between the third drain selection line DSL3 and the fourth drain selection line DSL4. The second row R2 of the fifth plug P5 and the second row R2 of the sixth plug P6 may be symmetric with respect to the division region DV between the first drain selection line DSL1 and the second drain selection line DSL2. The second row R2 of the sixth plug P6 and the second row R2 of the seventh plug P7 may be symmetric with respect to the division region DV between the second drain selection line DSL2 and the third drain selection line DSL3. The second row R2 of the seventh plug P7 and the second row R2 of the eighth plug P8 may be symmetric with respect to the division region DV between the third drain selection line DSL3 and the fourth drain selection line DSL4.

[0193] Plugs P1 to P8 may have the same structure. The planar structure or cross-section of each of plugs P1 to P8 is similar to the structure described with reference to Figure 5 the structure.

[0194] Multiple bit lines BL1 to BL4 are arranged on plugs P1 to P8. Figure 15 A part of the memory block is shown. The number of bit lines is not limited to Figure 15 the number of bit lines shown. For convenience of description, only four bit lines (e.g., bit lines BL1 to BL4) provided on plugs P1 to P4 are shown. Bit lines BL1 to BL4 extend individually along the Y direction and are spaced apart from each other along the X direction. Each of bit lines BL1 to BL4 contacts one plug. For example, the first bit line BL1 contacts one of the first plug P1, the second bit line BL2 contacts one of the second plug P2, the third bit line BL3 contacts one of the third plug P3, and the fourth bit line BL4 contacts one of the fourth plug P4.

[0195] In the described embodiment, although the number of separate drain selection lines is shown as 2 or 4, the embodiment can be applied to a memory device including three or more separate drain selection lines.

[0196] Figure 16 is a layout diagram showing the connection relationship between the memory block and the page buffer according to the third embodiment of the present disclosure.

[0197] Referring to Figure 15 and Figure 16, bit lines BL1 to BL4 are respectively connected to page buffers PB1 to PB4.

[0198] Describe plugs P1 to P4 that contact bit lines BL1 to BL4.

[0199] The first plug P1 contacts the first bit line BL1 through a contact CT. The second plug P2 contacts the second bit line BL2 through a contact CT. The third plug P3 contacts the third bit line BL3 through a contact CT. The fourth plug P4 contacts the fourth bit line BL4 through a contact CT.

[0200] When a conduction voltage is applied to the first drain select line DSL1, the first plug P1 is electrically connected to the first page buffer PB1 through the contact CT and the first bit line BL1. When a conduction voltage is applied to the second drain select line DSL2, the second plug P2 is electrically connected to the second page buffer PB2 through the contact CT and the second bit line BL2. When a conduction voltage is applied to the third drain select line DSL3, the third plug P3 is electrically connected to the third page buffer PB3 through the contact CT and the third bit line BL3. When a conduction voltage is applied to the fourth drain select line DSL4, the fourth plug P4 is electrically connected to the fourth page buffer PB4 through the contact CT and the fourth bit line BL4.

[0201] When conduction voltages are simultaneously applied to drain select lines DSL1 to DSL4, plugs P1 to P4 are simultaneously and respectively electrically connected to page buffers PB1 to PB4.

[0202] During a programming operation, even when plugs P1 to P4 are simultaneously selected, plugs P1 to P4 are electrically connected to different bit lines BL1 to BL4, so programming operations can be simultaneously performed on plugs P1 to P4.

[0203] Because, according to the data input to the page buffer, the plugs that contact drain select lines DSL1 to DSL4 can be selected plugs or unselected plugs, programming operations of various examples are described.

[0204] Figure 17A and Figure 17B are tables including voltages and transistor states during a programming operation according to a third embodiment of the present disclosure when at least one plug is not selected.

[0205] Refer to Figure 16 and Figure 17A, in this example, the plugs contacting the drain select lines DSL1 to DSL3 are respectively the selected plugs Sel_PL connected to the bit lines BL1 to BL3, and the plug contacting the fourth drain select line DSL4 is the unselected plug Unsel_PL connected to the fourth bit line BL4. Each selected plug Sel_PL is a plug connected to the bit line to which a programming enable voltage is applied. The bit line to which a programming enable voltage is applied is the bit line connected to the page buffer for the input data "0". The unselected plug Unsel_PL is a plug connected to the bit line to which a programming inhibit voltage is applied. The bit line to which a programming inhibit voltage is applied is the bit line connected to the page buffer for the input data "1".

[0206] The ground voltage GND is applied to the source line SL, and all source select transistors SST are turned off. As a result, the selected plug Sel_PL and the unselected plug Unsel_PL are not connected to the source line SL. A pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage capable of turning on the memory cell. A turn-on voltage Von is applied to the drain select lines DSL1 to DSL4, and can be applied to the drain select lines DSL1 to DSL4 simultaneously. Since the turn-on voltage Von is applied to the drain select lines DSL1 to DSL4, the drain select transistors DST connected to the drain select lines DSL1 to DSL4 are turned on.

[0207] A precharge voltage Vpre is applied to the bit lines BL1 to BL4. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0208] Because all the drain select transistors DST connected to the drain select lines DSL1 to DSL4 are turned on, the precharge voltage Vpre applied to the bit lines BL1 to BL4 is applied to the channels 1CH to 3CH of the selected plug Sel_PL and the fourth channel 4CH of the unselected plug Unsel_PL. Therefore, the channels 1CH to 4CH can be precharged to the precharge voltage Vpre simultaneously.

[0209] Refer to Figure 16 and Figure 17B , in the channels 1CH to 4CH as referred to Figure 17AAfter the described pre-charging, according to the data of the page buffers connected to bit lines BL1 to BL4, the programming enable voltage Val is applied to bit lines BL1 to BL3, and the programming inhibit voltage Vinh is applied to the fourth bit line BL4. In this example, the data input to the page buffers connected to bit lines BL1 to BL3 is "0", and the data input to the page buffer connected to the fourth bit line BL4 is "1". When the data "0" is the data for increasing the threshold voltage of the memory cell and the data "1" is the data for maintaining the threshold voltage of the memory cell in the previous state, the page buffer inputting the data "0" outputs the programming enable voltage Val through the corresponding bit line, and the page buffer inputting the data "1" outputs the programming inhibit voltage Vinh through the corresponding bit line. Therefore, as described with reference to Figure 17A the plug to which the programming enable voltage Val is applied is the selected plug Sel_PL, and the plug to which the programming inhibit voltage Vinh is applied is the unselected plug Unsel_PL. The programming inhibit voltage Vinh can be a positive voltage higher than the programming enable voltage Val.

[0210] Since the drain select transistors DST connected to the drain select lines DSL1 to DSL4 are turned on, the programming enable voltage Val applied to the bit lines BL1 to BL3 is transmitted to the channels 1CH to 3CH of the selected plug Sel_PL, and the programming inhibit voltage Vinh applied to the fourth bit line BL4 is transmitted to the fourth channel 4CH of the unselected plug Unsel_PL. Therefore, the voltages of the channels 1CH to 3CH are reduced to the programming enable voltage Val, and the voltage of the fourth channel 4CH is increased to the programming inhibit voltage Vinh. Since the source select transistors SST are turned on, the voltages of the channels 1CH to 3CH are at a voltage level lower than the voltage level of the programming enable voltage Val, and the voltage of the fourth channel 4CH is at a voltage level lower than the voltage level of the programming inhibit voltage Vinh.

[0211] To increase the threshold voltage of the selected memory cells among the memory cells connected to the selected word line Sel_WL, the voltage Vpass is applied to the unselected word line Unsel_WL, and the programming voltage Vpgm is applied to the selected word line Sel_WL. Among the memory cells included in the selected plug Sel_PL, the memory cells connected to the selected word line Sel_WL are the selected memory cells, and among the memory cells included in the unselected plug Unsel_PL, the memory cells connected to the selected word line Sel_WL are the unselected memory cells.

[0212] A conduction voltage is applied to the source selection line, so that the source selection transistor SST is turned on. Accordingly, the channels 1CH to 3CH of the selected plug Sel_PL and the fourth channel 4CH of the unselected plug Unsel_PL are electrically connected to the source line SL. As a result, the voltages of the channels 1CH to 3CH are less than or equal to the programming enable voltage Val, and the voltage of the fourth channel 4CH is less than or equal to the programming inhibit voltage Vinh.

[0213] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming enable voltage Val applied to each of the channels 1CH to 3CH, the selected memory cells of the selected plug Sel_PL are programmed. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of each selected memory cell is equal to or higher than the reference voltage difference.

[0214] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming inhibit voltage Vinh applied to the fourth channel 4CH, the unselected memory cells of the unselected plug Unsel_PL are prohibited from being programmed. For example, the voltage difference between the gate and the channel of the unselected memory cell is lower than the reference voltage difference.

[0215] Even when the voltage of the fourth channel 4CH is lower than the programming inhibit voltage Vinh, the level of the programming inhibit voltage Vinh is high enough to prevent the threshold voltage of the unselected memory cell from increasing, and the programming inhibit voltage Vinh continues to be supplied to the fourth channel 4CH through the fourth bit line BL4. Accordingly, the memory cells among the memory cells included in the unselected plug Unsel_PL that are coupled to the selected word line Sel_WL are prohibited from being programmed.

[0216] Figure 18A and Figure 18B is a table including voltages and transistor states during a programming operation according to the third embodiment of the present disclosure when all plugs are selected plugs.

[0217] Referring to Figure 16 and Figure 18A In this example, the plugs that contact the drain select lines DSL1 to DSL4 are the selected plugs Sel_PL coupled to the bit lines BL1 to BL4, respectively. Each selected plug Sel_PL is a plug coupled to the bit line to which the programming enable voltage is applied. The bit line to which the programming enable voltage is applied is the bit line of the page buffer coupled to the input data "0".

[0218] A ground voltage GND is applied to the source line SL, and all source selection transistors SST are turned off. As a result, the selected plug Sel_PL is not connected to the source line SL. A pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage capable of turning on the memory cells. A conduction voltage Von is applied to the drain selection lines DSL1 to DSL4 and can be applied to the drain selection lines DSL1 to DSL4 simultaneously. Since the conduction voltage Von is applied to the drain selection lines DSL1 to DSL4, all drain selection transistors DST connected to the drain selection lines DSL1 to DSL4 are turned on.

[0219] A precharge voltage Vpre is applied to the bit lines BL1 to BL4. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0220] Since all drain selection transistors DST connected to the drain selection lines DSL1 to DSL4 are turned on, the precharge voltage Vpre applied to the bit lines BL1 to BL4 is applied to the channels 1CH to 4CH of the selected plug Sel_PL. Thus, the channels 1CH to 4CH can be precharged to the precharge voltage Vpre simultaneously.

[0221] Refer to Figure 16 and Figure 18B , after the channels 1CH to 4CH are precharged as described in reference to Figure 18A , a program enable voltage Val is applied to the bit lines BL1 to BL4 according to the data of the page buffers connected to the bit lines BL1 to BL4. In this example, the data input to the page buffers connected to the bit lines BL1 to BL4 is "0". When the data "0" is data for increasing the threshold voltage of the memory cells and the data "1" is data for maintaining the threshold voltage of the memory cells in the previous state, the page buffer inputting the data "0" outputs the program enable voltage Val through the corresponding bit line. As described in reference to Figure 18A , the plug to which the program enable voltage Val is applied is the selected plug Sel_PL.

[0222] Since all drain selection transistors DST connected to the drain selection lines DSL1 to DSL4 are turned on, the program enable voltage Val applied to the bit lines BL1 to BL4 is applied to the channels 1CH to 4CH of the selected plug Sel_PL. Thus, the voltage of the channels 1CH to 4CH is reduced to the program enable voltage Val. Since the source selection transistors SST are turned on, the voltage of the channels 1CH to 4CH is at a voltage level lower than the voltage level of the program enable voltage Val.

[0223] To increase the threshold voltage of the selected memory cells among the memory cells connected to the selected word line Sel_WL, a voltage Vpass is applied to the unselected word line Unsel_WL, and a programming voltage Vpgm is applied to the selected word line Sel_WL. Among the memory cells included in the selected plug Sel_PL, the memory cells connected to the selected word line Sel_WL are the selected memory cells.

[0224] A conduction voltage is applied to the source selection line, so that the source selection transistor SST is turned on. Accordingly, the channels 1CH to 4CH of the selected plug Sel_PL can be electrically connected to the source line SL. As a result, the voltages of the channels 1CH to 4CH are lower than or equal to the programming enable voltage Val.

[0225] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming enable voltage Val applied to each of the channels 1CH to 4CH, the selected memory cells of the selected plug Sel_PL are programmed. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of each selected memory cell is equal to or higher than the reference voltage difference.

[0226] Since the selected memory cells of the plugs connected to the different drain selection lines DSL1 to DSL4 are programmed simultaneously, programming disturbance in the Y direction, X direction, or XY direction (for example, the diagonal direction between the X direction and the Y direction) can be reduced.

[0227] Figure 19A and Figure 19B is a table including voltages and transistor states during the programming operation according to the third embodiment of the present disclosure when all plugs are unselected plugs.

[0228] Referring to Figure 16 and Figure 19A In this example, the plugs in contact with the drain selection lines DSL1 to DSL4 are the unselected plugs Unsel_PL connected to the bit lines BL1 to BL4, respectively. Each unselected plug Unsel_PL is a plug connected to the bit line to which a programming inhibition voltage is applied. The bit line to which the programming inhibition voltage is applied is the bit line of the page buffer connected to the input data "1".

[0229] The ground voltage GND is applied to the source line SL, and all source selection transistors SST are turned off. As a result, the unselected plug Unsel_PL is not connected to the source line SL. The pass voltage Vpass is applied to the unselected word line Unsel_WL and the selected word line Sel_WL. The pass voltage Vpass is a positive voltage capable of turning on the memory cell. The turn-on voltage Von is applied to the drain selection lines DSL1 to DSL4 and can be applied to the drain selection lines DSL1 to DSL4 simultaneously. Since the turn-on voltage Von is applied to the drain selection lines DSL1 to DSL4, the drain selection transistors DST connected to the drain selection lines DSL1 to DSL4 are turned on.

[0230] The precharge voltage Vpre is applied to the bit lines BL1 to BL4. The precharge voltage Vpre can be a positive voltage higher than 0V.

[0231] Since all the drain selection transistors DST connected to the drain selection lines DSL1 to DSL4 are turned on, the precharge voltage Vpre applied to the bit lines BL1 to BL4 is applied to the channels 1CH to 4CH of the selected plug Sel_PL. Therefore, the channels 1CH to 4CH can be precharged to the precharge voltage Vpre simultaneously.

[0232] Refer to Figure 16 and Figure 19B , after the channels 1CH to 4CH are precharged as described in reference Figure 19A , the program inhibit voltage Vinh is applied to the bit lines BL1 to BL4 according to the data of the page buffers connected to the bit lines BL1 to BL4. In this example, the data input to the page buffers connected to the bit lines BL1 to BL4 is "1". When the data "0" is the data for increasing the threshold voltage of the memory cell and the data "1" is the data for maintaining the threshold voltage of the memory cell in the previous state, the page buffer inputting the data "1" outputs the program inhibit voltage Vinh through the corresponding bit line. Therefore, as described in reference Figure 19A , the plug applied with the program inhibit voltage Vinh is the unselected plug Unsel_PL.

[0233] Since all the drain selection transistors DST connected to the drain selection lines DSL1 to DSL4 are turned on, the program inhibit voltage Vinh applied to the bit lines BL1 to BL4 is transmitted to the channels 1CH to 4CH of the unselected plug Unsel_PL. Therefore, the voltage of the channels 1CH to 4CH increases to the program inhibit voltage Vinh. Since the source selection transistor SST is turned on, the voltage of the channels 1CH to 4CH is at a voltage level lower than the voltage level of the program inhibit voltage Vinh.

[0234] To increase the threshold voltage of the selected memory cells among the memory cells connected to the selected word line Sel_WL, a voltage Vpass is applied to the unselected word line Unsel_WL, and a programming voltage Vpgm is applied to the selected word line Sel_WL. Among the memory cells included in the unselected plug Unsel_PL, the memory cells connected to the selected word line Sel_WL are unselected memory cells.

[0235] A conduction voltage is applied to the source selection line, so the source selection transistor SST is turned on. As a result, channels 1CH to 4CH are electrically connected to the source line SL. Consequently, the voltages of channels 1CH to 4CH are lower than or equal to the programming inhibition voltage Vinh.

[0236] Due to the voltage difference between the programming voltage Vpgm applied to the selected word line Sel_WL and the programming inhibition voltage Vinh applied to each of channels 1CH to 4CH, the unselected memory cells of the unselected plug Unsel_PL are prohibited from being programmed. For example, the voltage difference between the gate and the channel of each unselected memory cell is lower than the reference voltage difference. For example, when the allowable programming voltage difference is the reference voltage difference, the voltage difference between the gate and the channel of each unselected memory cell is lower than the reference voltage difference.

[0237] Even when the voltages of channels 1CH to 4CH are lower than the programming inhibition voltage Vinh, the level of the programming inhibition voltage Vinh is high enough to prevent the threshold voltage of the unselected memory cells from increasing, and the programming inhibition voltage Vinh continues to be supplied to channels 1CH to 4CH through bit lines BL1 to BL4. Therefore, when performing a programming operation on the selected memory cells connected to the selected word line Sel_WL, the memory cells connected to the selected word line Sel_WL among the memory cells included in the unselected plug Unsel_PL are prohibited from being programmed.

[0238] Figure 20 FIG. is a diagram showing an embodiment of a memory card system including a memory device according to the present disclosure.

[0239] Refer to Figure 20 , the memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0240] The controller 3100 is coupled to the memory device 3200. The controller 3100 accesses the memory device 3200. For example, the controller 3100 is configured to control programming operations, read operations, erase operations, and background operations of the memory device 3200. The controller 3100 is configured to provide an interface between the memory device 3200 and a host. The controller 3100 runs firmware that controls the memory device 3200. In an embodiment, the controller 3100 may include components such as a RAM, a processor, a host interface, a memory interface, and an error correction circuit.

[0241] The controller 3100 communicates with an external device via the connector 3300. The controller 3100 communicates with an external device (e.g., a host) based on a specific communication standard or protocol. In an embodiment, the controller 3100 may be configured to communicate with an external device via at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory Express (NVMe). In an embodiment, the connector 3300 may be configured according to at least one of the above communication standards.

[0242] The memory device 3200 includes a plurality of memory cells and is configured, for example, in the same manner as the memory device 100 shown. Figure 1 The memory device 3200 is configured to perform the method of the programming operation described. For example, the method suppresses an increase in the threshold voltage of unselected memory cells. Figures 1 to 19B

[0243] The controller 3100 and the memory device 3200 are integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device and may form a memory card such as a PC Card (Personal Computer Memory Card International Association: PCMCIA), CompactFlash card (CF), SmartMedia card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, or eMMC), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0244] Figure 21 is a diagram illustrating an embodiment of a solid state drive (SSD) system including a memory device according to the present disclosure.

[0245] Reference Figure 21 As shown in Figure 21 , the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001 and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0246] The controller 4210 controls the plurality of memory devices 4221 to 422n in response to signals received from the host 4100. In an embodiment, the signals may include signals based on the interface between the host 4100 and the SSD 4200. For example, the signals may be configured or constructed according to any one of a variety of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory Express (NVMe).

[0247] Each of the plurality of memory devices 4221 to 422n includes a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n is configured, for example, in the same manner as the memory device 100 shown in Figure 1 . The plurality of memory devices 4221 to 422n communicate with the controller 4210 through channels CH1 to CHn. Each of the plurality of memory devices 4221 to 422n is configured to perform the method of the programming operation described in Figures 1 to 19B . For example, the method suppresses an increase in the threshold voltage of unselected memory cells.

[0248] The auxiliary power supply 4230 is connected to the host 4100 through the power connector 4002. A power voltage is supplied from the host 4100 to the auxiliary power supply 4230 and can be charged. When the power supply from the host 4100 is not smooth or continuous, the auxiliary power supply 4230 can provide a power voltage for the SSD 4200. In an embodiment, the auxiliary power supply 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the motherboard and can also provide auxiliary power to the SSD 4200.

[0249] The buffer memory 4240 serves as the buffer memory of the SSD 4200. For example, the buffer memory 4240 temporarily stores data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or temporarily stores metadata (e.g., mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include one or more volatile memories such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0250] The present disclosure describes embodiments that can suppress an increase in the threshold voltage of unselected memory cells, thus improving the reliability of the memory device.

[0251] The concepts have been described in connection with various embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered from a restrictive perspective, but from an illustrative perspective. Accordingly, the scope of the present disclosure should not be limited to the above embodiments. All changes within the meaning and equivalent scope of the claims should be included within its scope.

[0252] Cross-reference to Related Applications

[0253] This application claims the priority of Korean Patent Application No. 10-2023-0166541, filed with the Korean Intellectual Property Office on November 27, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method of operating a memory device, the method comprising the steps of: precharging a first channel of a first plug corresponding to a first selection line and a second channel of a second plug corresponding to a second selection line; applying one of a program enable voltage and a program inhibit voltage to the first channel; applying one of the program enable voltage and the program inhibit voltage to the second channel; as well as A memory cell selected from among memory cells included in the first plug and the second plug is programmed.

2. The method according to claim 1, wherein: The program inhibition voltage is higher than the program enable voltage.

3. The method according to claim 1, wherein: The step of precharging the first channel and the second channel comprises the following steps: applying a precharge voltage to a first bit line coupled to the first plug; applying the precharge voltage to a second bit line coupled to the second plug; applying a pass voltage to a word line commonly coupled to the first plug and the second plug; turning on a first selection transistor between the first channel and the first bit line; and A second selection transistor between the second channel and the second bit line is turned on.

4. The method according to claim 3, wherein: The precharge voltage is a voltage higher than 0V.

5. The method according to claim 3, wherein: The step of turning on the first selection transistor includes applying a turn-on voltage to the first selection line coupled to the gate of the first selection transistor, and Turning on the second selection transistor includes applying the turn-on voltage to the second selection line coupled to a gate of the second selection transistor.

6. The method according to claim 1, wherein: The step of applying one of the program enable voltage and the program inhibit voltage to the first channel comprises the following steps: inputting data into the first page buffer; and One of the program enable voltage and the program inhibit voltage is output by the first page buffer to a first bit line coupled to the first plug according to the data.

7. The method according to claim 1, wherein: The step of applying one of the program enable voltage and the program inhibit voltage to the second channel comprises the following steps: inputting data into the second page buffer; and One of the program enable voltage and the program inhibit voltage is outputted by the second page buffer to a second bit line coupled to the second plug according to the data.

8. The method according to claim 1, wherein: The step of programming the selected memory cell includes the following steps: applying a pass voltage to an unselected word line among word lines coupled to the first plug and the second plug; and A program voltage is applied to a selected word line among the word lines.

9. The method according to claim 1, further comprising the steps of: When a selected memory cell is included in the first plug and the second plug, the program enable voltage is applied to the first channel and the second channel.

10. The method according to claim 1, further comprising the steps of: When a selected memory cell is included in the first plug and is not included in the second plug, applying the program enable voltage to the first channel; and The program inhibit voltage is applied to the second channel.

11. The method according to claim 1, further comprising the steps of: When a selected memory cell is not included in the first plug and the second plug, the program inhibition voltage is applied to the first channel and the second channel.

12. A method of operating a memory device, the method comprising the steps of: precharging a first channel of a first plug and a second channel of a second plug, wherein the first plug and the second plug correspond to a first selection line; precharging a third channel of the third plug and a fourth channel of the fourth plug, wherein the third channel and the fourth channel correspond to a second selection line; applying one of a program enable voltage and a program inhibit voltage to each of the first channel, the second channel, the third channel, and the fourth channel; and A memory cell selected from among memory cells included in the first plug, the second plug, the third plug, and the fourth plug is programmed.

13. The method according to claim 12, wherein: The step of precharging the first channel, the second channel, the third channel and the fourth channel comprises the following steps: applying a precharge voltage to a first bit line coupled to the first plug; applying the precharge voltage to a second bit line coupled to the second plug; applying the precharge voltage to a third bit line coupled to the third plug; applying the precharge voltage to a fourth bit line coupled to the fourth plug; applying a pass voltage to a word line commonly coupled to the first plug, the second plug, the third plug, and the fourth plug; turning on a first selection transistor between the first channel and the first bit line and a second selection transistor between the second channel and the second bit line at the same time; and A third selection transistor between the third channel and the third bit line and a fourth selection transistor between the fourth channel and the fourth bit line are turned on at the same time.

14. The method according to claim 13, wherein: The step of turning on the first selection transistor and the second selection transistor at the same time includes applying a turn-on voltage to the first selection line commonly connected to the gate of the first selection transistor and the gate of the second selection transistor, and The step of turning on the third selection transistor and the fourth selection transistor at the same time includes applying the turn-on voltage to the second selection line commonly coupled to the gate of the third selection transistor and the gate of the fourth selection transistor.

15. The method according to claim 12, wherein: The step of applying one of the program enable voltage and the program inhibit voltage to each of the first channel, the second channel, the third channel, and the fourth channel includes the following steps: inputting data to each of a first page buffer, a second page buffer, a third page buffer, and a fourth page buffer coupled to the first plug, the second plug, the third plug, and the fourth plug through a first bit line, a second bit line, a third bit line, and a fourth bit line, respectively; and One of the program enable voltage and the program inhibit voltage is outputted by the first, second, third and fourth page buffers to the first, second, third and fourth bit lines, respectively, according to the data.

16. The method according to claim 12, wherein: The step of programming the selected memory cell includes the following steps: applying a pass voltage to an unselected word line among word lines commonly coupled to the first plug, the second plug, the third plug, and the fourth plug; and A program voltage is applied to a selected word line among the word lines.

17. The method according to claim 12, further comprising the steps of: When a selected memory cell is included in the first plug, the second plug, the third plug, and the fourth plug, a program voltage is applied to the first channel, the second channel, the third channel, and the fourth channel.

18. The method according to claim 12, further comprising the steps of: When a selected memory cell is not included in at least one of the first plug, the second plug, the third plug, and the fourth plug, applying a program voltage to a channel including a plug of a selected memory cell among the first plug, the second plug, the third plug, and the fourth plug; as well as The program inhibition voltage is applied to a channel excluding a plug of a selected memory cell among the first plug, the second plug, the third plug, and the fourth plug.

19. The method according to claim 12, further comprising the steps of: When a selected memory cell is not included in the first, second, third, and fourth plugs, the program inhibition voltage is applied to the first, second, third, and fourth channels.

20. A method of operating a memory device, the method comprising the steps of: precharging a first channel of a first plug corresponding to a first selection line, a second channel of a second plug corresponding to the first selection line, a third channel of a third plug corresponding to the second selection line, and a fourth channel of a fourth plug corresponding to the second selection line; applying a program enable voltage to the first channel of the first plug and the third channel of the third plug when the first plug and the third plug are selected plugs; applying a program inhibition voltage to the second channel of the second plug and the fourth channel of the fourth plug when the second plug and the fourth plug are unselected plugs; as well as Selected memory cells among memory cells included in the first plug and the third plug of a memory block are programmed.

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