Operation method of memory, memory and memory system

Abstract

The embodiment of the invention provides an operation method of a memory, the memory and a memory system. The operation method of the memory comprises the following steps: in a pre-pulse operation, applying a first voltage to a non-selected upper selection line coupled with an upper selection tube of a non-selected memory string so as to turn off the upper selection tube of the non-selected memory string, a second voltage is applied to a non-selected lower selection line coupled with a lower selection tube of the non-selected memory string so as to conduct the lower selection tube of the non-selected memory string; applying a pass voltage to the non-selected word line; and applying a third voltage to the dummy word lines coupled to the dummy memory cells in the at least one dummy memory cell group to turn off the corresponding dummy memory cells, wherein a stage in which the pass voltage is applied to the non-selected word line and a stage in which the third voltage is applied to the dummy word line to which the dummy memory cell in the at least one dummy memory cell group is coupled partially overlap in time.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and particularly to an operation method of a memory, a memory, and a memory system. Background Art

[0002] A three-dimensional memory generally includes stacked memory arrays and peripheral circuits. Among them, the peripheral circuits can apply a programming voltage or a read voltage to the memory arrays to realize reading and writing of stored information.

[0003] With the progress of semiconductor technologies, the number of stacked layers of three-dimensional memories is continuously increasing, and the control requirements of the peripheral circuits for the memory arrays are also increasing accordingly. Summary of the Invention

[0004] Embodiments of the present disclosure provide an operation method of a memory, a memory, and a memory system.

[0005] In a first aspect, embodiments of the present disclosure provide an operation method of a memory. The memory includes: a memory block, the memory block including a plurality of memory strings, each memory string including a top select transistor, a plurality of memory cells, and a bottom select transistor connected in series in sequence; the plurality of memory cells including at least two memory cell groups and dummy memory cell groups located between any two adjacent memory cell groups; a plurality of word lines, each word line being coupled to a corresponding memory cell; at least one dummy word line, each dummy word line being coupled to a corresponding dummy memory cell; a top select line, the top select line being coupled to a corresponding top select transistor; and a bottom select line, the bottom select line being coupled to a corresponding bottom select transistor. The operation method includes: in a pre-pulse operation, applying a first voltage to a non-selected top select line coupled to the top select transistor of a non-selected memory string to turn off the top select transistor of the non-selected memory string, and applying a second voltage to a non-selected bottom select line coupled to the bottom select transistor of the non-selected memory string to turn on the bottom select transistor of the non-selected memory string; applying a pass voltage to a non-selected word line; and applying a third voltage to a dummy word line coupled to a dummy memory cell in at least one of the dummy memory cell groups to turn off the corresponding dummy memory cell; wherein a stage of applying the pass voltage to the non-selected word line and a stage of applying the third voltage to the dummy word line coupled to the dummy memory cell in at least one of the dummy memory cell groups overlap in time.

[0006] In some embodiments, applying the pass voltage to the non-selected word line includes: in a first stage, the voltage on the non-selected word line ramps up to the pass voltage; in a second stage, the voltage on the non-selected word line stabilizes at the pass voltage; wherein the first stage and the process of applying the third voltage to the dummy word line coupled to the dummy memory cell in at least one of the dummy memory cell groups overlap in time.

[0007] In some embodiments, the method for operating the memory further includes: in the second stage, applying a fourth voltage to the at least one dummy word line to turn on the corresponding dummy memory cell.

[0008] In some embodiments, applying the third voltage to the dummy word line coupled to the dummy memory cell in at least one of the dummy memory cell groups includes: in the first stage, applying the third voltage to the dummy word line coupled to the dummy memory cell in the dummy memory cell group closest to the lower selection transistor, and applying the fourth voltage to the dummy word lines coupled to the dummy memory cells in other dummy memory cell groups.

[0009] In some embodiments, the plurality of memory cells include a first memory cell group, a second memory cell group, a third memory cell group, a first dummy memory cell group located between the first memory cell group and the second memory cell group, and a second dummy memory cell group located between the second memory cell group and the third memory cell group; applying the third voltage to the dummy word line coupled to the dummy memory cell in at least one of the dummy memory cell groups includes: in the first stage, applying the third voltage to the dummy word line coupled to the dummy memory cell in one of the first dummy memory cell group and the second dummy memory cell group, and applying the fourth voltage to the dummy word line coupled to the dummy memory cell in the other dummy memory cell group of the first dummy memory cell group and the second dummy memory cell group; or, in the first stage, applying the third voltage to the dummy word lines coupled to the dummy memory cells in the first dummy memory cell group and the second dummy memory cell group.

[0010] In some embodiments, the plurality of lower selection transistors at the same level in different memory strings in the memory block are connected to each other and coupled to the same lower selection line.

[0011] In some embodiments, the method for operating the memory further includes: in the pre-pulse operation, applying the second voltage to the selected upper selection line coupled to the upper selection transistor of the selected memory string.

[0012] In some embodiments, the method for operating the memory further includes: in the pre-pulse operation, applying a pass voltage or a fifth voltage to the selected word line.

[0013] In some embodiments, the pre-pulse operation is before the verification operation; or, the pre-pulse operation is before the read operation; or, the pre-pulse operation is before the programming operation.

[0014] In some embodiments, the method for operating the memory further includes: during the verification operation, applying the second voltage to the upper selection transistor of the selected memory string and applying the first voltage to the upper selection transistor of the non-selected memory string, and applying the second voltage to the lower selection transistors of both the selected memory string and the non-selected memory string; during the verification operation, applying a verification voltage to the selected word line, applying a pass voltage to the non-selected word line, and applying a fourth voltage to the dummy word lines to which the dummy memory cells of all the dummy memory cell groups are coupled.

[0015] In a second aspect, an embodiment of the present disclosure provides a memory, which includes a memory block. The memory block includes a plurality of memory strings, and each memory string includes an upper selection transistor, a plurality of memory cells, and a lower selection transistor connected in series in sequence; the plurality of memory cells include at least two memory cell groups and a dummy memory cell group located between any two adjacent memory cell groups; a plurality of word lines, each word line being coupled to a corresponding memory cell; at least one dummy word line, each dummy word line being coupled to a corresponding dummy memory cell; an upper selection line, the upper selection line being coupled to a corresponding upper selection transistor; a lower selection line, the lower selection line being coupled to a corresponding lower selection transistor; and a peripheral circuit, coupled to the plurality of word lines, the at least one dummy word line, the upper selection line, and the lower selection line, and configured to: during a pre-pulse operation, applying a first voltage to a non-selected upper selection line coupled to the upper selection transistor of the non-selected memory string to turn off the upper selection transistor of the non-selected memory string, and applying a second voltage to the lower selection line coupled to the lower selection transistor of the non-selected memory string to turn on the lower selection transistor of the non-selected memory string; applying a pass voltage to the non-selected word line; and applying a third voltage to the dummy word lines to which the dummy memory cells in at least one of the dummy memory cell groups are coupled to turn off the corresponding dummy memory cells; wherein the process of applying the pass voltage to the non-selected word line and the stage of applying the third voltage to the dummy word lines to which the dummy memory cells in at least one of the dummy memory cell groups are coupled to turn off the corresponding dummy memory cells overlap in time.

[0016] In some embodiments, the peripheral circuit is specifically configured to: in a first stage, the voltage on the non-selected word line ramps up to the pass voltage; in a second stage, the voltage on the non-selected word line stabilizes at the pass voltage; wherein the first stage and the process of applying the third voltage to the dummy word lines to which the dummy memory cells in at least one of the dummy memory cell groups are coupled overlap in time.

[0017] In some embodiments, the peripheral circuit is specifically configured to: in the second stage, applying a fourth voltage to the at least one dummy word line to turn on all the dummy memory cells.

[0018] In some embodiments, the peripheral circuit is specifically configured to: in the first stage, apply the third voltage to the dummy word lines coupled to the dummy memory cells in the dummy memory cell group closest to the lower selection transistor, and apply the fourth voltage to the dummy word lines coupled to the dummy memory cells in the other dummy memory cell groups.

[0019] In some embodiments, the plurality of memory cells include a first memory cell group, a second memory cell group, a third memory cell group, a first dummy memory cell group located between the first memory cell group and the second memory cell group, and a second dummy memory cell group located between the second memory cell group and the third memory cell group; the peripheral circuit is specifically configured to: in the first stage, apply the third voltage to the dummy word lines coupled to the dummy memory cells in one of the first dummy memory cell group and the second dummy memory cell group, and apply the fourth voltage to the dummy word lines coupled to the dummy memory cells in the other of the first dummy memory cell group and the second dummy memory cell group; or, in the first stage, apply the third voltage to the dummy word lines coupled to the dummy memory cells in the first dummy memory cell group and the second dummy memory cell group.

[0020] In some embodiments, the plurality of lower selection transistors at the same level in different memory strings in the memory block are connected to each other and coupled to the same lower selection line.

[0021] In some embodiments, the peripheral circuit is specifically configured to: in the pre-pulse operation, apply the second voltage to the selected upper selection line coupled to the upper selection transistor of the selected memory string.

[0022] In some embodiments, the peripheral circuit is specifically configured to: in the pre-pulse operation, apply a pass voltage or a fifth voltage to the selected word line.

[0023] In some embodiments, the peripheral circuit is specifically configured to: perform the pre-pulse operation before the verify operation; or, perform the pre-pulse operation before the read operation; or, perform the pre-pulse operation before the program operation.

[0024] In some embodiments, the peripheral circuit is specifically configured to: in the verify operation, apply the second voltage to the upper selection transistor of the selected memory string and apply the first voltage to the upper selection transistors of the non-selected memory strings, and apply the second voltage to the lower selection transistors of both the selected memory string and the non-selected memory strings; in the verify operation, apply a verify voltage to the selected word line and apply the fourth voltage to the non-selected word lines and the dummy word lines coupled to the dummy memory cells of all the dummy memory cell groups.

[0025] In some embodiments, the memory includes a NAND-type memory.

[0026] In a third aspect, an embodiment of the present disclosure provides a memory system, which includes: the memory as described in the above technical solution; and a controller coupled to the memory and configured to control the memory.

[0027] Embodiments of the present disclosure provide an operation method, a memory, and a memory system of a memory. The memory includes: a memory block, the memory block includes a plurality of memory strings, each memory string includes a top select transistor, a plurality of memory cells, and a bottom select transistor connected in series in sequence; the plurality of memory cells include at least two memory cell groups and dummy memory cell groups located between any two adjacent memory cell groups; a plurality of word lines, each word line is coupled to a corresponding memory cell; at least one dummy word line, each dummy word line is coupled to a corresponding dummy memory cell; a top select line, the top select line is coupled to a corresponding top select transistor; and a bottom select line, the bottom select line is coupled to a corresponding bottom select transistor; the operation method includes: in a pre-pulse operation, applying a turn-off first voltage to an unselected top select line coupled to the top select transistor of an unselected memory string to turn off the top select transistor of the unselected memory string, and applying a turn-on second voltage to an unselected bottom select line coupled to the bottom select transistor of the unselected memory string to turn on the bottom select transistor of the unselected memory string; applying a pass voltage to an unselected word line; and applying a turn-off third voltage to a dummy word line coupled to a dummy memory cell in at least one of the dummy memory cell groups to turn off the corresponding dummy memory cell; wherein, the stage of applying the pass voltage to the unselected word line and the stage of applying the turn-off third voltage to the dummy word line coupled to the dummy memory cell in at least one of the dummy memory cell groups overlap partially in time. In the embodiments of the present disclosure, in the pre-pulse operation, a first voltage is applied to the top select transistor of the unselected memory string, and the stage of applying the pass voltage to the unselected word line and the stage of applying the third voltage to the dummy word line coupled to the dummy memory cell overlap partially, so that the channel potential of the memory cell group located above the dummy memory cell coupled to the dummy word line to which the third voltage is applied is lifted, thereby shortening the programming time and improving the programming efficiency. And the embodiments of the present disclosure can be applied to a memory structure without a physical Bottom Select Gate CUT (BSG CUT), and shorten the programming time and improve the programming efficiency. Description of the Drawings

[0028] Figure 1 It is a schematic partial cross-sectional structure diagram of a memory in an example of an embodiment of the present disclosure;

[0029] Figure 2 The voltage waveform timing diagram of the programming operation of the memory and the channel potential diagram in the unselected memory string in the first example of the present disclosure;

[0030] Figure 3 The flowchart of the operation method of the memory in another example of the present disclosure;

[0031] Figure 4 The partial cross-sectional structure schematic diagram of the memory in another example of the present disclosure;

[0032] Figure 5 The circuit schematic diagram of a memory provided by an embodiment of the present disclosure;

[0033] Figure 6 The partial equivalent circuit diagram of the memory in another example of the present disclosure;

[0034] Figure 7 The voltage waveform timing diagram of the programming operation of the memory in another example of the present disclosure;

[0035] Figure 8 The partial circuit diagram of the memory string in yet another example of the present disclosure;

[0036] Figure 9 The voltage waveform timing diagram of the programming operation of the memory in yet another example of the present disclosure;

[0037] Figure 10 The structural block diagram of a memory provided by an embodiment of the present disclosure;

[0038] Figure 11 The block diagram of the memory including a memory cell array and a peripheral circuit provided by an embodiment of the present disclosure;

[0039] Figure 12 The block diagram of a memory system provided by an embodiment of the present disclosure;

[0040] Figure 13a The schematic diagram of a memory card provided by an embodiment of the present disclosure;

[0041] Figure 13b The schematic diagram of a solid state drive (SSD) provided by an embodiment of the present disclosure. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0044] In the drawings, for the sake of clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Throughout the drawings, the same reference numerals indicate the same elements.

[0045] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be denoted as a second element, component, region, layer, or section without departing from the teachings of the present disclosure. And when a second element, component, region, layer, or section is discussed, it does not imply that a first element, component, region, layer, or section necessarily exists in the present disclosure.

[0046] Spatial relationship terms such as "under," "below," "beneath," "underneath," "above," "over," etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to another element or feature. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0048] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0049] To increase the ramp-up speed of the drive voltage and the word line voltage, a physical bottom select gate tangent can be added in the process. Exemplarily, a three-dimensional memory includes a stacked memory array and peripheral circuits. The memory array includes a plurality of memory blocks (Blocks) arranged in an array. A memory block can be the smallest erasable unit of the three-dimensional memory. Each memory block includes a plurality of memory strings arranged vertically. Each memory string includes a bottom select gate structure and a top select gate structure. By forming one or more physical bottom select gate tangents in the bottom select gate, a memory block can be divided into a plurality of finger storage areas (Fingers). Each finger storage area includes a plurality of memory strings. After the subsequent gate replacement process, the top select gate structure and the bottom select gate structure can be converted into a top select gate (Top Selective Gate, TSG) and a bottom select gate (Bottom Selective Gate, BSG). At this time, each bottom select gate controls the corresponding finger storage area separately in units of finger storage areas.

[0050] Reference Figure 1 , Figure 1 is a schematic partial cross-sectional structure diagram of the memory in the first embodiment of the present disclosure. As Figure 1 shown, four rows of memory strings 101 are shown in the partial schematic diagram of the memory 100. Through the physical bottom select gate tangent scheme, the four rows of memory strings 101 are divided into two finger storage areas, namely Finger1 and Finger2. Each finger storage area includes two adjacent rows of memory strings 101. The finger storage areas in the memory can be physically isolated through the bottom select gate tangent 102, so as to realize separate control of each finger storage area through the bottom select gate of each finger storage area.

[0051] It should be noted thatFigure 1 The number of rows of memory strings given is only an exemplary demonstration and is not used to limit the number of rows of memory strings included in one finger storage area of the memory in the present disclosure. In practical applications, the number of rows of memory strings included in one finger storage area can be adjusted according to actual situations, such as 2, 4, 8, 16, etc.

[0052] Reference Figure 2 , Figure 2 is the voltage waveform timing diagram of the programming operation of the memory and the channel potential diagram in the unselected memory string in the first exemplary embodiment of the present disclosure.

[0053] In a specific example, each memory string of the 3D memory may include a plurality of stacked memory cell groups connected in series. Due to the limitations of the etching process, when the number of layers of the memory string increases, it is necessary to stack multiple times to form multiple stacks and perform multiple etching operations to form a memory string including a plurality of memory cell groups. In some embodiments, two adjacent memory cell groups are tightly connected through dummy memory cell groups to form a memory string. Here, each dummy memory cell in the dummy memory cell group can play a transitional role in the process and can be not used to store data. Exemplarily, the memory string to be programmed is located in the selected finger storage area in the memory block, and the other finger storage areas in the memory block except the selected finger storage area are unselected finger storage areas. Each memory string includes two memory cell groups connected in series up and down, namely the upper memory cell group and the lower memory cell group, and each memory cell group includes a plurality of memory cells. In some embodiments, a dummy memory cell group is further included between the upper memory cell group and the lower memory cell group, and the dummy memory cell group includes a plurality of dummy memory cells, and the dummy memory cells are coupled to dummy word lines (for example, Inter Deck Plug Dummy (IDPDUM) dummy word lines). Each memory string further includes an upper selection transistor, and the corresponding memory string in the finger storage area can be selected through the upper selection transistor; each finger storage area includes a lower selection transistor, and the corresponding finger storage area can be selected through the lower selection transistor.

[0054] Continue to refer to Figure 2 , in the pre-pulse stage, a conduction voltage is applied to the upper selection transistor of the selected memory string in the selected finger storage area, where the conduction voltage can be greater than the threshold voltage of the upper selection transistor; a turn-off voltage is applied to the upper selection transistor of the memory string in the unselected finger storage area, where the turn-off voltage can be 0V; a turn-off voltage is applied to the lower selection transistor of the unselected finger storage area; a conduction voltage is applied to the selected lower selection transistor of the selected finger storage area. The upper selection transistor and the lower selection transistor of the unselected finger storage area are turned off, so that the channel of the unselected finger storage area is in a floating state, and a pass voltage is applied to the unselected word line, and the pass voltage V passIt can be the turn-on voltage of the memory cell. As the voltage on the unselected word line rises from 0V to the pass voltage, a potential will be coupled in the channel of the memory string in the unselected finger memory area, thereby increasing the slew rate of the drive voltage and shortening the programming time period (tPROG). It should be noted that Figure 2 In the example shown, the physical bottom select gate tangent scheme is used. In the pre-pulse stage, by applying corresponding turn-off voltages to the unselected upper select transistor and the unselected lower select transistor of the memory string in the unselected finger memory area, the channel potential of the memory string in the unselected finger memory area can be increased. There is no requirement for what voltage to apply to the word line or the dummy word line coupled to the memory cell in each memory string. Therefore, the description of the word line voltage and the dummy word line voltage in the example shown Figure 2 is omitted here.

[0055] Refer to Figure 3 , Figure 3 which is a flowchart of an operation method of a memory in another example of the present disclosure embodiment.

[0056] As Figure 3 shown, the present disclosure embodiment provides an operation method of a memory. The memory includes: a memory block, the memory block includes a plurality of memory strings, each memory string includes an upper select transistor, a plurality of memory cells and a lower select transistor connected in series in sequence; the plurality of memory cells include at least two memory cell groups and a dummy memory cell group located between any two adjacent memory cell groups; a plurality of word lines, each word line is coupled to a corresponding memory cell; at least one dummy word line, each dummy word line is coupled to a corresponding dummy memory cell; an upper select line, the upper select line is coupled to a corresponding upper select transistor; and a lower select line, the lower select line is coupled to a corresponding lower select transistor. The operation method of the memory includes: Step 301, in the pre-pulse operation, applying a first voltage to the unselected upper select line coupled to the upper select transistor of the unselected memory string to turn off the upper select transistor of the unselected memory string, and applying a second voltage to the unselected lower select line coupled to the lower select transistor of the unselected memory string to turn on the lower select transistor of the unselected memory string; Step 302, applying a pass voltage to the unselected word line; and Step 303, applying a third voltage to the dummy word line coupled to the dummy memory cell in at least one dummy memory cell group to turn off the corresponding dummy memory cell; wherein, the stage of applying the pass voltage to the unselected word line and the stage of applying the third voltage to the dummy word line coupled to the dummy memory cell in at least one dummy memory cell group overlap partially in time.

[0057] In an embodiment of the present disclosure, a memory cell array in a memory block may be provided in the form of an array of memory strings (e.g., NAND memory strings). In some embodiments, each of the memory strings may extend vertically, and each memory string may include a plurality of memory cells connected in series. Each memory cell or dummy memory cell may be a floating-type memory cell having a floating gate transistor or a charge trapping-type memory cell having a charge trapping transistor. The upper select transistor and the lower select transistor may be conventional MOS transistors or charge trapping-type MOS transistors, and the present disclosure does not make specific limitations thereon.

[0058] Reference Figure 4 and Figure 5 , Figure 4 is a schematic diagram of a partial cross-sectional structure of a memory in another example of an embodiment of the present disclosure. Figure 5 is a schematic circuit diagram of a memory provided by an embodiment of the present disclosure.

[0059] As Figure 4 shown, by way of example, a memory block in the memory may include four rows of memory strings, namely String1, String2, String3, and String4. Reference Figure 5 , the memory 500 includes a memory cell array 510 and a peripheral circuit 520 coupled to the memory cell array. The memory cell array 510 includes a plurality of memory strings 501. Each memory string 501 may include a lower select transistor 503 at its source end and an upper select transistor 502 at its drain end. The lower select transistor 503 and the upper select transistor 502 may be configured to activate a selected memory string 501 during read and program operations. During a pre-pulse operation, one or more memory strings 501 may be selected through an upper select line (which may also be referred to as a string select line (SSL)) 504, such as selecting a row of memory strings 501 in the memory block.

[0060] Reference Figure 6 , Figure 6 is a partial circuit diagram of a memory string in another example of an embodiment of the present disclosure.

[0061] As Figure 6As shown, the memory string 600 includes two serially connected memory cell groups and a dummy memory cell group 603 located between the two memory cell groups. Specifically, the memory string 600 includes a first memory cell group 601 and a second memory cell group 602. Among them, the first memory cell group 601 can also be referred to as the upper memory cell group (Upper Deck), and the second memory cell group 602 can also be referred to as the lower memory cell group (Lower Deck). The dummy memory cell group 603 includes one or more dummy memory cells 604, and the dummy word line to which the dummy memory cell 604 is coupled is an interlayer plug dummy word line. Among them, the first memory cell group 601 is adjacent to the upper selection transistor 605, and the second memory cell group 602 is adjacent to the lower selection transistor 606.

[0062] Reference Figure 7 , Figure 7 is a voltage waveform timing diagram of the programming operation of the memory in another example of the embodiments of the present disclosure.

[0063] Combined with Figures 4 to 7 , in the pre-pulse operation stage, a pass voltage V pass can be applied to the unselected word lines. For example, a pass voltage V pass is applied to the unselected word lines corresponding to the memory cells in the upper memory cell group and the unselected word lines corresponding to the memory cells in the lower memory cell group. The pass voltage V pass can be greater than the threshold voltage of the corresponding memory cell. Exemplarily, the pass voltage V pass can be 5V to 7V, and the threshold voltage of the corresponding memory cell can be 2V to 3V. At the same time, a first voltage V 1 can be applied to the upper selection transistor of the unselected memory string, a second voltage V 2 can be applied to the lower selection transistor of the unselected memory string, and a third voltage V 3 is applied to the dummy word line DWL to which the dummy memory cells in at least one dummy memory cell group are coupled; among them, the first voltage V 1 and the third voltage V 3 can be 0V, and the second voltage V 2 can be greater than the threshold voltage of the upper selection transistor.

[0064] In the pre-pulse operation, a first voltage V 1 is applied to the unselected word line, and in the stage where a pass voltage V pass is applied to the unselected word line and a third voltage V 3The stages are partially overlapped in time. Thus, in the unselected memory string, a complete turn-off is achieved between the upper select transistor of the unselected memory string and the dummy memory cell corresponding to the dummy word line to which the third voltage is applied, and a part of the channel in the unselected memory string is in a floating state. At this time, a pass voltage V is applied to the unselected word line pass , and as the voltage on the unselected word line rises from 0V to the pass voltage V pass , an electric potential will be coupled out in the channel of the unselected memory string. Specifically, a first electric potential will be coupled out in the channel of the upper memory cell group of the unselected memory string. In the embodiment of the present disclosure, since the third voltage is applied to the dummy word line coupled to the dummy memory cell above the lower memory cell group of the unselected memory string, a second electric potential will also be coupled out in the channel of the lower memory cell group of the unselected memory string. The first electric potential is higher than the second electric potential. Thus, the relatively high electric potential coupled out in the channel of the upper memory cell group of the unselected memory string can increase the slew rate of the word line voltage, thereby improving the programming time.

[0065] In the embodiment of the present disclosure, the voltage timings applied to the word line, the dummy word line, the upper select transistor, and the lower select transistor can be controlled by a timing controller, so that a relatively high electric potential is coupled out in the channel of the memory cell group above the dummy memory cell corresponding to the dummy word line to which the third voltage is applied, that is, the electric potential in the channel is boosted to a certain height. The boosting of the channel electric potential can increase the slew rate of the word line voltage. When programming the memory cell above the dummy memory cell corresponding to the dummy word line to which the third voltage is applied, the word line voltage can be applied to the selected word line corresponding to the memory cell. At this time, the programming speed can be significantly increased, and the programming time can be significantly shortened.

[0066] In the embodiment of the present disclosure, the stage of applying the pass voltage V pass to the unselected word line and the stage of applying the third voltage V 3 to the dummy word line coupled to the dummy memory cell in at least one dummy memory cell group are partially overlapped in time, including: applying the third voltage V 3 to the dummy word line coupled to a part of the dummy memory cells in at least one dummy memory cell group, or applying the third voltage V 3 to the dummy word line coupled to all the dummy memory cells in at least one dummy memory cell group, and the stage is partially overlapped with the stage of applying the pass voltage V pass to the unselected word line.

[0067] Embodiments of the present disclosure can better reduce costs while shortening the programming time cycle, and have good operability. Moreover, with the continuous development of memories, when the volume of the memory is continuously reduced, the width of the channel structure is also continuously decreased, and more and more channel structures are included in the memory blocks of the same area, this operation method can be applied to the memory structure without BSG CUT, that is, the operation method provided by the embodiments of the present disclosure can replace part of the functions of BSG CUT, so that the channel potential of the memory cell group located above the dummy memory cells coupled to the dummy word lines to which the third voltage is applied is lifted, thereby shortening the programming time and improving the programming efficiency.

[0068] It should be noted that the above selected word lines and unselected word lines are for facilitating the distinction of different operations corresponding during the programming process, and do not mean that there are two different types of word lines. The selected word line can be any one of the coupled word lines in the memory array, and the selected word line corresponding to different programming processes can be the same word line or different word lines. The word line that needs to be prohibited from programming is the unselected word line in the current programming process. The same applies to the selected memory string and the unselected memory string.

[0069] In the embodiments of the present disclosure, applying a pass voltage to the unselected word line includes: in the first stage, the voltage on the unselected word line ramps up to the pass voltage; in the second stage, the voltage on the unselected word line stabilizes at the pass voltage; wherein, the first stage overlaps in time with the stage of applying a third voltage to the dummy word lines coupled to the dummy memory cells in at least one group of dummy memory cells.

[0070] Continuing to refer to Figure 6 , applying a pass voltage to the unselected word line includes two stages, namely the first stage and the second stage. Among them, the time between t1 and t2 is the first stage, and after t2 is the second stage. In the first stage, the unselected word line is charged to the pass voltage V pass , and in the second stage, the voltage of the unselected word line remains at V pass . Moreover, in the first stage, a third voltage V 3 is applied to the dummy word lines coupled to the dummy memory cells in at least one group of dummy memory cells. It should be noted that for the dummy memory cells corresponding to the dummy word lines to which the third voltage V 3 is applied in the first stage, a third voltage V 3 can also be applied to the dummy word lines to which they are coupled before the first stage.

[0071] In the embodiments of the present disclosure, the stage of applying a pass voltage V pass to the unselected word line and the stage of applying a third voltage V 3The stages, which are partially overlapped in time, include: in the first stage, applying a pass voltage V to the unselected word lines pass and applying a third voltage V to the dummy word lines coupled to the dummy memory cells in at least one group of dummy memory cells 3 .

[0072] As Figure 6 shown, in the embodiments of the present disclosure, the operation method of the memory further includes: in the second stage, applying a fourth voltage V to at least one dummy word line 4 to turn on the corresponding dummy memory cell.

[0073] In the embodiments of the present disclosure, the fourth voltage V 4 may be greater than the threshold voltage of the corresponding dummy memory cell.

[0074] In the embodiments of the present disclosure, applying a third voltage to the dummy word lines coupled to the dummy memory cells in at least one group of dummy memory cells includes: in the first stage, applying a third voltage to the dummy word lines coupled to the dummy memory cells in the group of dummy memory cells closest to the lower selection transistor, and applying a fourth voltage to the dummy word lines coupled to the dummy memory cells in other groups of dummy memory cells.

[0075] In the embodiments of the present disclosure, in the first stage, a third voltage V may be applied to all the dummy word lines coupled to the dummy memory cells in the group of dummy memory cells closest to the lower selection transistor 3 , or a third voltage V may be applied to some of the dummy word lines coupled to the dummy memory cells in the group of dummy memory cells closest to the lower selection transistor 3 .

[0076] In the embodiments of the present disclosure, a third voltage may be applied to the dummy word line corresponding to the dummy memory cell in the group of dummy memory cells closest to the lower selection transistor in the unselected memory string, so that a channel potential is coupled out above the dummy memory cell. As the number of memory cell groups in the memory string increases, the channel potential coupled out in the unselected memory string will gradually tend to cover the entire channel, thereby making the effect of improving the slope rate of the word line voltage more obvious, and the improvement of the programming efficiency is also more obvious. Here, for the understanding of the slope rate of the word line voltage, reference can be made to Figure 7 , Figure 7 where the time between t1 and t2 is the slope time of the word line voltage. Among them, the smaller the difference between t2 and t1, the shorter the slope time of the word line voltage, and the faster the slope rate of the word line voltage.

[0077] In the embodiments of the present disclosure, multiple memory cells of each memory string include a first memory cell group, a second memory cell group, a third memory cell group, a first dummy memory cell group located between the first memory cell group and the second memory cell group, and a second dummy memory cell group located between the second memory cell group and the third memory cell group; applying a third voltage to the dummy word lines coupled to the dummy memory cells in at least one dummy memory cell group includes: in a first stage, applying the third voltage to the dummy word lines coupled to the dummy memory cells in one of the first dummy memory cell group and the second dummy memory cell group, and applying a fourth voltage to the dummy word lines coupled to the dummy memory cells in the other of the first dummy memory cell group and the second dummy memory cell group; or, in the first stage, applying the third voltage to the dummy word lines coupled to the dummy memory cells in the first dummy memory cell group and the second dummy memory cell group.

[0078] Reference Figure 8 , Figure 8 is a partial circuit diagram of a memory string in another example of the embodiments of the present disclosure.

[0079] As Figure 8 shown, the memory string 800 includes three memory cell groups and dummy memory cell groups. Specifically, the memory string includes a first memory cell group 801, a second memory cell group 802, and a third memory cell group 803. Among them, the first memory cell group 801 can also be referred to as the upper memory cell group (Upper Deck), the second memory cell group 802 can also be referred to as the middle memory cell group (Middle Deck), and the third memory cell group 803 can also be referred to as the lower memory cell group (Lower Deck). The dummy memory cell groups include a first dummy memory cell group 804 located between the first memory cell group 801 and the second memory cell group 802, and a second dummy memory cell group 805 located between the second memory cell group 802 and the third memory cell group 803. Among them, the first memory cell group 801 is adjacent to the upper selection transistor 806, and the third memory cell group 803 is adjacent to the lower selection transistor 807.

[0080] Reference Figure 9 , Figure 9 is a voltage waveform timing diagram of the programming operation of the memory in another example of the embodiments of the present disclosure.

[0081] Combined with Figure 8 and Figure 9 , in the first stage (between time t1 and time t2), the pass voltages V pass can be respectively applied to the non-selected word lines coupled to the first memory cells, the non-selected word lines coupled to the second memory cells, and the non-selected word lines coupled to the third memory cells of the memory string, and a first voltage V1 , a second voltage V is applied to the lower selection transistor of the non-selected memory string 2 , a third voltage V is applied to the dummy word line coupled to the dummy memory cells in the second dummy memory cell group between the second memory cell group and the third memory cell group 3 , and a fourth voltage V is applied to the dummy word lines coupled to all the dummy memory cells in the first dummy memory cell group between the first memory cell group and the second memory cell group 4 , then the channel potentials of the first memory cell group, the second memory cell group, and the first dummy memory cell group of the non-selected memory string are lifted. Among them, in the first stage, the third voltage V can be applied to the dummy word lines coupled to all the dummy memory cells in the second dummy memory cell group 3 , or the third voltage V can be applied to the dummy word lines coupled to some of the dummy memory cells in the second dummy memory cell group 3 .

[0082] In another embodiment of the present disclosure, in the first stage, a third voltage is applied to the dummy word line coupled to the dummy memory cell in the first dummy memory cell group, and a fourth voltage is applied to the dummy word line coupled to the dummy memory cell in the second dummy memory cell group, then the channel potential of the first memory cell group of the non-selected memory string is lifted. Among them, in the first stage, the third voltage can be applied to the dummy word lines coupled to all the dummy memory cells in the first dummy memory cell group, or the third voltage can be applied to the dummy word lines coupled to some of the dummy memory cells in the first dummy memory cell group.

[0083] In another embodiment of the present disclosure, in the first stage, the third voltage is applied to both the dummy word line coupled to the dummy memory cell in the first dummy memory cell group and the dummy word line coupled to the dummy memory cell in the second dummy memory cell group, then the channel potential of the first memory cell group of the non-selected memory string is lifted. Similarly, in the first stage, the third voltage can be applied to the dummy word lines coupled to all the dummy memory cells in the first dummy memory cell group and the second dummy memory cell group; or the third voltage can be applied to the dummy word lines coupled to some of the dummy memory cells in the first dummy memory cell group and the third voltage can be applied to the dummy word lines coupled to some of the dummy memory cells in the second dummy memory cell group; or the third voltage can be applied to the dummy word lines coupled to all the dummy memory cells in the first dummy memory cell group and the third voltage can be applied to the dummy word lines coupled to some of the dummy memory cells in the second dummy memory cell group; or the third voltage can be applied to the dummy word lines coupled to some of the dummy memory cells in the first dummy memory cell group and the third voltage can be applied to the dummy word lines coupled to all the dummy memory cells in the second dummy memory cell group.

[0084] Reference Figure 8, in the embodiments of the present disclosure, in the first stage, compared with the case of applying a third voltage to the dummy word line coupled to the dummy memory cells in the dummy memory cell group that is the second closest to the lower selection transistor (for example, the first dummy memory cell group 804), and applying a fourth voltage to the dummy word lines coupled to the dummy memory cells in other dummy memory cell groups (for example, the second dummy memory cell group 805); when applying a third voltage to the dummy word line coupled to the dummy memory cells in the dummy memory cell group that is the closest to the lower selection transistor (for example, the second dummy memory cell group 805), and applying a fourth voltage to the dummy word lines coupled to the dummy memory cells in other dummy memory cell groups (for example, the first dummy memory cell group 804), the channel potential of the unselected memory string can be lifted to a greater extent. That is, the programming speed can be better improved.

[0085] In the embodiments of the present disclosure, the description of the memory string including two memory cell groups or three memory cell groups is only an example. In some other embodiments, the memory string may include more than three memory cell groups, and the present disclosure does not limit this.

[0086] In the embodiments of the present disclosure, different memory strings in the same memory block are electrically isolated from each other through different upper selection transistors respectively. Multiple lower selection transistors at the same level in different memory strings in the memory block are connected to each other and coupled to the same lower selection line.

[0087] Reference Figure 5 and Figure 8 , in the embodiments of the present disclosure, the gate of the upper selection transistor of each memory string is connected to the upper selection line, the source of the upper selection transistor is connected to the drain of the adjacent memory cell below the upper selection transistor, and the drain of the upper selection transistor is connected to the bit line (BitLine, BL) 506. That is, at a certain moment, the upper selection transistors of different memory strings can obtain different voltages. The gates of the lower selection transistors of multiple memory strings in the same memory block are connected to the same lower selection line (which can also be called the ground selection line (Ground SelectLine, GSL)) 505, the drain of the lower selection transistor is connected to the source of the adjacent memory cell above the lower selection transistor, and the source of the lower selection transistor is connected to the source line. At a certain moment, the lower selection transistors of different memory strings in the same memory block can obtain the same voltage.

[0088] In the embodiments of the present disclosure, the operation method of the memory further includes: in the pre-pulse operation, applying a second voltage to the selected upper selection line coupled to the upper selection transistor of the selected memory string. In other words, in the pre-pulse operation, a second voltage can be applied to the upper selection transistor of a certain memory string, so as to turn on the upper selection transistor of the memory string and realize the selection of the memory string.

[0089] In the embodiments of the present disclosure, the operation method of the memory further includes: in the pre-pulse operation, applying a passing voltage V to the selected word linepass or a fifth voltage V 5 . Among them, the fifth voltage V 5 can be a turn-off voltage.

[0090] In the embodiments of the present disclosure, the pre-pulse operation is before the verification operation; or, the pre-pulse operation is before the read operation; or, the pre-pulse operation is before the programming operation.

[0091] Specifically, in the operation method of the memory, the pre-pulse operation can be respectively performed before any one or more of the verification operation, the read operation, and the programming operation. The pre-pulse operation can also be respectively performed before one or more verification operations, read operations, and programming operations. In one example, the pre-pulse operation is between the current programming operation and the current verification operation. In another example, the pre-pulse operation is between the current verification operation and the next programming operation. In the embodiments of the present disclosure, the pre-pulse operation can improve the speed of the verification operation, read operation, or programming operation performed after it, thereby shortening the entire operation time period.

[0092] In the embodiments of the present disclosure, the operation method of the memory further includes: in the verification operation, applying a second voltage to the upper selection transistor of the selected memory string and applying a first voltage to the upper selection transistor of the non-selected memory string, and applying a second voltage to the lower selection transistors of both the selected memory string and the non-selected memory string; in the verification operation, applying a verification voltage to the selected word line, applying a pass voltage to the non-selected word line, and applying a fourth voltage to the dummy word lines coupled to the dummy memory cells of all the dummy memory cell groups.

[0093] In the embodiments of the present disclosure, in the verification operation, a verification voltage is applied to the selected word line to verify the threshold voltage of the memory cell to confirm that the memory cell is in the corresponding storage state. In the embodiments of the present disclosure, the pass voltage and the verification voltage can be determined according to the actual application situation. Among them, the verification voltage can be less than the pass voltage, and the fourth voltage can be equal to the pass voltage.

[0094] Reference Figure 10 , Figure 10 is a structural block diagram of a memory provided by the embodiments of the present disclosure.

[0095] Such as Figure 10As shown, an embodiment of the present disclosure also provides a memory 1000, which includes: a storage cell array 1100, the storage cell array 1100 includes a plurality of storage blocks 1001, the storage block 1001 includes a plurality of storage strings, and each storage string includes an upper selection transistor, a plurality of storage cells, and a lower selection transistor connected in series in sequence; the plurality of storage cells includes at least two storage cell groups 1003 and dummy storage cell groups 1004 located between any two adjacent storage cell groups 1003; a plurality of word lines, each word line is coupled to a corresponding storage cell; at least one dummy word line, each dummy word line is coupled to a corresponding dummy storage cell; an upper selection line, the upper selection line is coupled to a corresponding upper selection transistor; a lower selection line, the lower selection line is coupled to a corresponding lower selection transistor; and a peripheral circuit 1002, which is coupled to the plurality of word lines, at least one dummy word line, the upper selection line, and the lower selection line, and the peripheral circuit is configured to: in a pre-pulse operation, apply a first voltage to an unselected upper selection line coupled to the upper selection transistor of the unselected storage string to turn off the upper selection transistor of the unselected storage string, and apply a second voltage to an unselected lower selection line coupled to the lower selection transistor of the unselected storage string to turn on the lower selection transistor of the unselected storage string; apply a pass voltage to the unselected word lines; and apply a third voltage to the dummy word lines coupled to the dummy storage cells in at least one dummy storage cell group to turn off the corresponding dummy storage cells; wherein, the process of applying the pass voltage to the unselected word lines and the stage of applying the third voltage to the dummy word lines coupled to the dummy storage cells in at least one dummy storage cell group to turn off the corresponding dummy storage cells are partially overlapped in time.

[0096] In an embodiment of the present disclosure, the peripheral circuit can be coupled to the storage cell array through bit lines, word lines, source lines, upper selection lines, and lower selection lines. The bit lines and the upper selection lines can intersect on a horizontal plane, so as to uniquely select the storage string where the storage cell to be programmed is located. The peripheral circuit can include any suitable analog, digital, and mixed-signal circuits to implement applying voltage signals and / or current signals to each target storage cell and sensing voltage signals and / or current signals from each target storage cell to facilitate the operation of the storage cell array. The peripheral circuit includes a page buffer / sense amplifier, a column decoder / bit line driver, a row decoder / word line driver, a voltage generator, a control logic unit, a register, an interface, and a data bus. The peripheral circuit can also include various types of circuits and electronic components formed using metal-oxide-semiconductor (MOS) technology.

[0097] In an embodiment of the present disclosure, the peripheral circuit is specifically configured to: in a first stage, the voltage on the unselected word line ramps up to the pass voltage; in a second stage, the voltage on the unselected word line stabilizes at the pass voltage; wherein the first stage overlaps in time with the process of applying a third voltage to the dummy word line coupled to the dummy memory cell in at least one dummy memory cell group.

[0098] In an embodiment of the present disclosure, the peripheral circuit is specifically configured to: in the second stage, apply a fourth voltage to at least one dummy word line to turn on all the dummy memory cells.

[0099] In an embodiment of the present disclosure, the peripheral circuit is specifically configured to: in the first stage, apply a third voltage to the dummy word line coupled to the dummy memory cell in the dummy memory cell group closest to the lower selection transistor, and apply a fourth voltage to the dummy word lines coupled to the dummy memory cells in other dummy memory cell groups.

[0100] In an embodiment of the present disclosure, the multiple memory cells include a first memory cell group, a second memory cell group, a third memory cell group, a first dummy memory cell group located between the first memory cell group and the second memory cell group, and a second dummy memory cell group located between the second memory cell group and the third memory cell group; the peripheral circuit is specifically configured to: in the first stage, apply a third voltage to the dummy word line coupled to the dummy memory cell in one of the first dummy memory cell group and the second dummy memory cell group, and apply a fourth voltage to the dummy word line coupled to the dummy memory cell in the other of the first dummy memory cell group and the second dummy memory cell group; or, in the first stage, apply a third voltage to the dummy word lines coupled to the dummy memory cells in the first dummy memory cell group and the second dummy memory cell group.

[0101] In an embodiment of the present disclosure, the multiple lower selection transistors at the same level in different memory strings in the memory block are connected to each other and coupled to the same lower selection line.

[0102] In an embodiment of the present disclosure, the peripheral circuit is specifically configured to: in a pre-pulse operation, apply a second voltage to the selected upper selection line coupled to the upper selection transistor of the selected memory string.

[0103] In an embodiment of the present disclosure, the peripheral circuit is specifically configured to: in a pre-pulse operation, apply a pass voltage or a fifth voltage to the selected word line.

[0104] In an embodiment of the present disclosure, the peripheral circuit is specifically configured to: perform a pre-pulse operation before a verification operation; or, perform a pre-pulse operation before a read operation; or, perform a pre-pulse operation before a programming operation.

[0105] In the embodiments of the present disclosure, the peripheral circuit is specifically configured to: in a verification operation, apply a second voltage to the upper selection transistor of the selected memory string and apply a first voltage to the upper selection transistor of the non-selected memory string, and apply a second voltage to the lower selection transistors of both the selected memory string and the non-selected memory string; in the verification operation, apply a verification voltage to the selected word line, apply a pass voltage to the non-selected word line, and apply a fourth voltage to the dummy word lines coupled to the dummy memory cells of all the dummy memory cell groups.

[0106] In the embodiments of the present disclosure, the memory includes a NAND-type memory.

[0107] Reference Figure 11 , Figure 11 is a block diagram of a memory including a memory cell array and a peripheral circuit provided by the embodiments of the present disclosure.

[0108] As Figure 11 shown, the peripheral circuit includes a page buffer / sense amplifier 1101, a column decoder / bit line driver 1102, a row decoder / word line driver 1103, a voltage generator 1104, a control logic unit 1105, a register 1106, an interface 1107, and a data bus 1108. It should be understood that in some embodiments, additional peripheral circuits not shown in Figure 11 may also be included.

[0109] The page buffer / sense amplifier 1101 may be configured to read data from the memory cell array 1109 and program (write) data to the memory cell array 1109 according to control signals from the control logic unit 1105. In one example, the page buffer / sense amplifier 1101 may store a page of programming data (write data) to be programmed into a page of the memory cell array. In another example, the page buffer / sense amplifier 1101 may perform a verification operation to ensure that data has been correctly programmed into the memory cells coupled to the selected word line. In yet another example, the page buffer / sense amplifier 1101 may also sense a low-power signal from the bit line representing the data bits stored in the memory cells and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 1102 may be configured to be controlled by the control logic unit and select one or more NAND memory strings by applying bit line voltages generated from the voltage generator.

[0110] The row decoder / word line driver 1103 can be configured to be controlled by the control logic unit 1105, and to select or deselect the memory blocks of the memory cell array and the word lines of the memory blocks. The row decoder / word line driver 1103 can also be configured to drive the word lines using the word line voltages generated from the voltage generator 1104. As described in detail below, the row decoder / word line driver 1103 is configured to perform an erase operation on the memory cells coupled to the selected word line(s). The voltage generator 1104 can be configured to be controlled by the control logic unit 1105, and to generate the word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 1109.

[0111] The control logic unit 1105 can be coupled to each of the peripheral circuits described above, and is configured to control the operations of each peripheral circuit. The register 1106 can be coupled to the control logic unit 1105, and includes status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit. The interface 1107 can be coupled to the control logic unit 1105, and acts as a control buffer to buffer the control commands received from the host ( Figure 11 not shown in the figure) and relay them to the control logic unit 1105, and to buffer the status information received from the control logic unit 1105 and relay it to the host. The interface 1107 can also be coupled to the column decoder / bit line driver 1102 via the data bus 1108, and acts as a data I / O interface and data buffer to buffer data and relay it to or from the memory cell array 1109.

[0112] Reference Figure 12 , Figure 12 is a block diagram of a memory system provided by an embodiment of the present disclosure.

[0113] As Figure 12 shown, an embodiment of the present disclosure provides a memory system 1200, which includes: a memory 1201 as described in the above technical solution; and a controller 1202 coupled to the memory 1201 and configured to control the memory 1201.

[0114] In the embodiments of the present disclosure, the controller 1202 may be coupled to the memory 1201 through multiple interfaces, and may control operations such as reading, erasing, and programming of the memory 1201. The memory system further includes a host 1203, and the host 1203 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)). The host 1203 may be configured to send data to the memory 1201. Alternatively, the host 1203 may be configured to receive data from the memory 1201.

[0115] In the embodiments of the present disclosure, the memory system 1200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage.

[0116] In some embodiments, the controller 1202 may be designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, or a Universal Serial Bus (USB) flash drive, or to be used in an electronic device such as a personal calculator, a digital camera, or a mobile phone. In other embodiments, the controller 1202 may also be designed to operate in a high-duty-cycle environment, such as a Solid State Drive (SSD) or an embedded multimedia card (eMMC), and the SSD or eMMC may be used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0117] In some embodiments, the controller 1202 may manage the data in the memory 1201 and communicate with the host. Exemplarily, the controller 1202 may be configured to control operations such as reading, erasing, and programming of the memory 1201; may also be configured to manage various functions regarding the data stored in or to be stored in the memory 1201, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc.; may also be configured to process error correction codes (ECCs) regarding the data read from or written to the memory 1201.

[0118] In some other embodiments, the controller 1202 may also perform any other suitable functions, such as formatting the memory 1201, or communicating with external devices according to a specific communication protocol. Exemplarily, the controller 1202 may communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, or Firewire protocol, etc.

[0119] Reference Figure 13a and Figure 13b , Figure 13a FIG. is a schematic diagram of a memory card provided by an embodiment of the present disclosure. Figure 13b FIG. is a schematic diagram of a solid state drive (SSD) provided by an embodiment of the present disclosure.

[0120] In some embodiments, the memory controller 1301 and a single memory 1302 may be integrated into the memory card 1300. The memory card 1300 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1300 may also include a memory card connector 1303 that couples the memory card 1300 to a host (e.g., Figure 12 the host 1203 in

[0121] In some other embodiments, the memory controller 1301 and multiple memories 1302 may be integrated into a solid state drive (SSD) 1310. The solid state drive 1310 may also include a solid state drive connector 1304 that couples the solid state drive 1310 to a host (e.g., Figure 12 the host 1203 in

[0122] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0123] The above is only the preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Any equivalent structural transformation made by using the content of the specification and drawings of the present disclosure under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields is included in the patent protection scope of the present disclosure.

Claims

1. A method for operating a memory, characterized in that, the memory includes: memory blocks, each memory block including a plurality of memory strings, each memory string including a top select transistor, a plurality of memory cells, and a bottom select transistor connected in series in sequence; the plurality of memory cells including at least two memory cell groups and dummy memory cell groups located between any two adjacent memory cell groups; a plurality of word lines, each word line being coupled to a corresponding one of the memory cells; at least one dummy word line, each dummy word line being coupled to a corresponding one of the dummy memory cells; a top select line, the top select line being coupled to a corresponding top select transistor; and a bottom select line, the bottom select line being coupled to a corresponding bottom select transistor; the operating method includes: In a pre-pulse operation, applying a first voltage to a non-selected top select line coupled to the top select transistor of a non-selected memory string to turn off the top select transistor of the non-selected memory string, and applying a second voltage to a non-selected bottom select line coupled to the bottom select transistor of the non-selected memory string to turn on the bottom select transistor of the non-selected memory string; applying a pass voltage to the non-selected word lines; and applying a third voltage to a dummy word line coupled to a dummy memory cell in at least one of the dummy memory cell groups to turn off the corresponding dummy memory cell; wherein, the stage of applying the pass voltage to the non-selected word lines and the stage of applying the third voltage to the dummy word line coupled to the dummy memory cell in at least one of the dummy memory cell groups overlap in time.

2. The method for operating a memory according to claim 1, characterized in that, the applying a pass voltage to the non-selected word lines includes: In a first stage, the voltage on the non-selected word line ramps up to the pass voltage; In a second stage, the voltage on the non-selected word line stabilizes at the pass voltage; wherein, the first stage and the process of applying the third voltage to the dummy word line coupled to the dummy memory cell in at least one of the dummy memory cell groups overlap in time.

3. The method for operating a memory according to claim 2, characterized in that, the operating method further includes: In the second stage, applying a fourth voltage to the at least one dummy word line to turn on the corresponding dummy memory cell.

4. The method for operating a memory according to claim 3, characterized in that, the applying the third voltage to the dummy word line coupled to the dummy memory cell in at least one of the dummy memory cell groups includes: In the first stage, applying the third voltage to the dummy word line coupled to the dummy memory cell in the dummy memory cell group closest to the bottom select transistor, and applying the fourth voltage to the dummy word lines coupled to the dummy memory cells in other dummy memory cell groups.

5. The method for operating a memory according to claim 3, characterized in that, The multiple memory cells include a first memory cell group, a second memory cell group, a third memory cell group, a first dummy memory cell group located between the first memory cell group and the second memory cell group, and a second dummy memory cell group located between the second memory cell group and the third memory cell group; Applying the third voltage to the dummy word lines coupled to the dummy memory cells in at least one of the dummy memory cell groups includes: In the first stage, applying the third voltage to the dummy word lines coupled to the dummy memory cells in one of the first dummy memory cell group and the second dummy memory cell group, and applying the fourth voltage to the dummy word lines coupled to the dummy memory cells in the other of the first dummy memory cell group and the second dummy memory cell group; Or, In the first stage, applying the third voltage to the dummy word lines coupled to the dummy memory cells in the first dummy memory cell group and the second dummy memory cell group.

6. The method for operating a memory according to claim 1, wherein, The multiple lower selection transistors at the same level in different memory strings in the memory block are connected to each other and coupled to the same lower selection line.

7. The method for operating a memory according to claim 1, wherein, The operating method further includes: In the pre-pulse operation, applying the second voltage to the selected upper selection line coupled to the upper selection transistor of the selected memory string.

8. The method for operating a memory according to claim 1, wherein, The operating method further includes: In the pre-pulse operation, applying a pass voltage or a fifth voltage to the selected word line.

9. The method for operating a memory according to claim 1, wherein, The pre-pulse operation is before the verification operation; or, The pre-pulse operation is before the read operation; or, The pre-pulse operation is before the programming operation.

10. The method for operating a memory according to claim 9, wherein, The operating method further includes: In the verification operation, applying the second voltage to the upper selection transistor of the selected memory string and applying the first voltage to the upper selection transistors of the non-selected memory strings, and applying the second voltage to the lower selection transistors of both the selected memory string and the non-selected memory strings; In the verification operation, applying a verification voltage to the selected word line, applying a pass voltage to the non-selected word lines, and applying the fourth voltage to the dummy word lines coupled to the dummy memory cells of all the dummy memory cell groups.

11. A memory, wherein, includes: A memory block, the memory block includes multiple memory strings, each memory string includes an upper selection transistor, multiple memory cells and a lower selection transistor connected in series in sequence; the multiple memory cells include at least two memory cell groups and dummy memory cell groups located between any two adjacent memory cell groups; Multiple word lines, each word line is coupled to a corresponding memory cell; At least one dummy word line, each of the dummy word lines being coupled to a corresponding dummy memory cell; An upper selection line, the upper selection line being coupled to a corresponding upper selection transistor; A lower selection line, the lower selection line being coupled to a corresponding lower selection transistor; and A peripheral circuit, coupled to the plurality of word lines, the at least one dummy word line, the upper selection line, and the lower selection line, and configured to: In a pre-pulse operation, apply a first voltage to an unselected upper selection line coupled to an upper selection transistor of an unselected memory string to turn off the upper selection transistor of the unselected memory string, and apply a second voltage to an unselected lower selection line coupled to a lower selection transistor of the unselected memory string to turn on the lower selection transistor of the unselected memory string; Apply a pass voltage to an unselected word line; And Apply a third voltage to a dummy word line to which a dummy memory cell in at least one of the dummy memory cell groups is coupled to turn off the corresponding dummy memory cell; Wherein, a process of applying the pass voltage to the unselected word line and a stage of applying the third voltage to a dummy word line to which a dummy memory cell in at least one of the dummy memory cell groups is coupled to turn off the corresponding dummy memory cell overlap in time.

12. The memory according to claim 11, wherein, The peripheral circuit is specifically configured to: In a first stage, the voltage on the unselected word line ramps up to the pass voltage; In a second stage, the voltage on the unselected word line stabilizes at the pass voltage; Wherein, the first stage and a process of applying the third voltage to a dummy word line to which a dummy memory cell in at least one of the dummy memory cell groups is connected overlap in time.

13. The memory according to claim 12, wherein, The peripheral circuit is specifically configured to: In the second stage, apply a fourth voltage to the at least one dummy word line to turn on all of the dummy memory cells.

14. The memory according to claim 13, wherein, The peripheral circuit is specifically configured to: In the first stage, apply the third voltage to a dummy word line to which a dummy memory cell in the dummy memory cell group closest to the lower selection transistor is coupled, and apply the fourth voltage to a dummy word line to which a dummy memory cell in other dummy memory cell groups is coupled.

15. The memory according to claim 13, wherein, The plurality of memory cells include a first memory cell group, a second memory cell group, a third memory cell group, a first dummy memory cell group located between the first memory cell group and the second memory cell group, and a second dummy memory cell group located between the second memory cell group and the third memory cell group; the peripheral circuit is specifically configured to: In the first stage, a third voltage is applied to a dummy word line coupled to a dummy memory cell in one of the first dummy memory cell group and the second dummy memory cell group, and a fourth voltage is applied to a dummy word line coupled to a dummy memory cell in the other dummy memory cell group of the first dummy memory cell group and the second dummy memory cell group; Or, In the first stage, a third voltage is applied to a dummy word line coupled to a dummy memory cell in the first dummy memory cell group and the second dummy memory cell group.

16. The memory according to claim 11, wherein, A plurality of lower select transistors at the same level in different memory strings in the memory block are connected to each other and coupled to the same lower select line.

17. The memory according to claim 11, wherein, The peripheral circuit is specifically configured to: In the pre-pulse operation, a second voltage is applied to a selected upper select line coupled to an upper select transistor of a selected memory string.

18. The memory according to claim 11, wherein, The peripheral circuit is specifically configured to: In the pre-pulse operation, a pass voltage or a fifth voltage is applied to a selected word line.

19. The memory according to claim 11, wherein, The peripheral circuit is specifically configured to: Execute the pre-pulse operation before the verify operation; Or, Execute the pre-pulse operation before the read operation; or, Execute the pre-pulse operation before the program operation.

20. The memory according to claim 11, wherein, The peripheral circuit is specifically configured to: In the verify operation, a second voltage is applied to an upper select transistor of a selected memory string and a first voltage is applied to an upper select transistor of a non-selected memory string, and a second voltage is applied to lower select transistors of both the selected memory string and the non-selected memory string; In the verify operation, a verify voltage is applied to a selected word line and a fourth voltage is applied to a non-selected word line and a dummy word line coupled to a dummy memory cell of all the dummy memory cell groups.

21. The memory according to claim 11, wherein, The memory includes a NAND type memory.

22. A memory system, wherein, The memory system includes: A memory according to any one of claims 11 to 21; and A controller coupled to the memory and configured to control the memory.

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