Method, device and equipment for detecting read-write duration of DRAM (Dynamic Random Access Memory) and computer readable medium

Abstract

The invention provides a DRAM (Dynamic Random Access Memory) read-write duration detection method, device and equipment and a computer readable medium. The method comprises the following steps: allocating a buffer area with a preset capacity of a target address for read-write speed detection; performing read-write operations of preset times, and recording the starting and ending time of each read-write operation; and determining read-write durations according to the starting and ending time, and screening the read-write durations. According to the embodiment, the read-write speed is detected at the target address of the preset capacity of the buffer area, so that the read-write speed can be detected under the situation of different addresses and different capacities, and the detection result is more targeted. According to the method, the read-write duration of each operation is obtained by performing multiple read-write operations, and then the read-write durations are screened, so that the detection accuracy is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and more particularly to a method, apparatus, device, and computer-readable medium for detecting read / write duration of a DRAM. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a computer memory technology used for temporarily storing and accessing data. DRAM has the advantages of high-density storage and low cost, and has become the main type of memory commonly used in computer systems. However, compared with Static Random Access Memory (SRAM), it has the shortcoming of slower read / write speed.

[0003] In the process of continuously improving and upgrading DRAM, improving the read / write speed is one of the key focuses, so the detection of the read / write speed becomes particularly important. Summary of the Invention

[0004] This section of the present invention is used to briefly introduce concepts that will be described in detail in the subsequent Detailed Description section. This section of the present invention is not intended to identify the key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0005] Some embodiments of the present invention propose a method, apparatus, device, and computer-readable medium for detecting read / write duration of a DRAM to solve the technical problems mentioned in the above Background Art section.

[0006] In a first aspect, some embodiments of the present invention provide a method for detecting read / write duration of a DRAM, the method comprising: allocating a buffer with a preset capacity at a target address for read / write speed detection; performing read / write operations a preset number of times and recording the start and end times of each read / write operation; determining the read / write duration based on the start and end times, and screening the read / write duration.

[0007] In a second aspect, some embodiments of the present invention provide a device for detecting read / write duration of a DRAM, the device comprising: an allocation unit configured to allocate a buffer with a preset capacity at a target address for read / write speed detection; a recording unit configured to perform read / write operations a preset number of times and record the start and end times of each read / write operation; a screening unit configured to determine the read / write duration based on the start and end times and screen the read / write duration.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, which includes: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any implementation manner of the first aspect.

[0009] In a fourth aspect, an embodiment of the present application provides a computer-readable medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in any implementation manner of the first aspect is implemented.

[0010] In a fifth aspect, some embodiments of the present invention provide a computer program product, including a computer program, and when the computer program is executed by a processor, the method described in any implementation manner of the above first aspect is implemented.

[0011] The above embodiments of the present invention have the following beneficial effects: Through the read / write duration detection method of the DRAM of the present invention, by detecting the read / write speed at the target address with a preset capacity in the buffer, it is possible to detect the read / write speed in different address and different capacity scenarios, making the detection result more targeted.

[0012] By performing multiple read / write operations, obtaining the read / write duration of each operation, and screening the above read / write durations, the accuracy of the detection is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the specific implementation manners of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific implementation manners or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 is a flowchart of some embodiments of the read / write duration detection method of the DRAM according to the present invention;

[0015] Figure 2 is a structural schematic diagram of some embodiments of the read / write duration detection device of the DRAM according to the present invention;

[0016] Figure 3 is a structural schematic diagram of an electronic device suitable for implementing some embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0018] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0019] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined. In addition, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0020] The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0021] First, please refer to Figure 1 , which shows a flow 100 of some embodiments of the read / write duration detection method of a DRAM according to the present invention. The read / write duration detection method of the DRAM includes the following steps:

[0022] Step 101, allocate a buffer with a preset capacity for the target address for read / write speed detection.

[0023] In some embodiments, the execution subject of the method may be an electronic device. The electronic device may be hardware or software. When the electronic device is hardware, it may be implemented as a distributed cluster composed of multiple servers or terminal devices, or as a single server or a single terminal device. When the electronic device is embodied as software, it may be installed in the above-listed hardware devices. It may be implemented as, for example, multiple software or software modules for providing distributed services, or as a single software or software module. Specific limitations are not made here.

[0024] The electronic device may divide the buffer of the DRAM into multiple intervals with a preset capacity. Detect the read and write speeds of the addresses and target addresses within the selected interval. The test data can be traversed to the above target address.

[0025] It should be noted that the above preset capacity can be adjusted according to the actual situation or detection requirements. For example, 1M or 10M, so as to obtain the read and write speeds of the target address under different capacity scenarios.

[0026] Step 102, perform read and write operations a preset number of times, and record the start and end times of each read and write operation.

[0027] In some embodiments, the staff can set the above preset number of times, such as 100 times or 1000 times. The electronic device records the start and end times of each read and write operation. As an example, it can be connected to the DRAM through an ATE (Automatic Test Equipment) device, an MCU (Microcontroller Unit), or an FPGA (Field Programmable Gate Array) to record the start and end times of the read and write operations.

[0028] Step 103, determine the read and write duration according to the start and end times, and screen the read and write duration.

[0029] In some embodiments and some optional implementation manners, during the screening process, the following steps may be adopted:

[0030] First, set sequence numbers for the obtained multiple read and write durations according to the acquisition time sequence to obtain a sequence number set. For example, sort the multiple read and write durations in the order of acquisition. For example, 100 read and write durations are obtained and sorted in sequence as 1 - 100 to obtain a sequence number set.

[0031] First, set sequence numbers for the obtained multiple read and write durations according to the acquisition time sequence to obtain a sequence number set. For example, sort the multiple read and write durations in the order of acquisition. For example, 100 read and write durations are obtained and sorted in sequence as 1 - 100 to obtain a sequence number set.

[0032] Second, generate a corresponding relationship curve between the above serial number set and the above multiple read / write durations. Specifically, the hundreds of serial numbers in the above serial number set can be used as the abscissa, and the above hundreds of read / write durations can be used as the ordinate to establish a coordinate system, and then a corresponding relationship curve of serial number - read / write duration can be generated.

[0033] Third, perform a fitting process on the above corresponding relationship curve to obtain a fitting curve. It should be noted that the sum of the squares of the differences between the values of the above multiple read / write durations in the corresponding relationship curve and the values of the points corresponding to the multiple read / write durations in the fitting curve is the smallest. For example, the sum of the squares of the differences between the values of the above 100 read / write durations in the corresponding relationship curve and the values of the points corresponding to the serial numbers corresponding to these values in the fitting curve is the smallest, and at this time, the fitting effect is the best.

[0034] Fourth, determine the difference between the value of each read / write duration in the above multiple read / write durations in the corresponding relationship curve and the value of the point corresponding to this read / write duration in the above fitting curve, and obtain a difference set. Specifically, determine the difference between the value of each read / write duration in the corresponding relationship curve and the value of the ordinate of the point corresponding to the serial number corresponding to this value in the fitting curve. Then a difference set of 100 differences is obtained.

[0035] Fifth, sort the differences in the above difference set according to the numerical magnitudes of the differences. Then a difference set of 100 differences arranged in numerical order can be obtained.

[0036] Sixth, perform a deletion operation on the differences in the above difference set according to a preset numerical deletion rate. Those skilled in the art can determine the preset numerical deletion rate according to the actual situation. For example, this deletion rate can be 10%, and multiple differences among the above 100 differences can be deleted at this deletion rate.

[0037] Seventh, use the data corresponding to the differences in the above difference set after deletion as valid data.

[0038] Eighth, use the above valid data as detection data for read / write operations.

[0039] Ninth, determine the read / write duration corresponding to the difference deleted in the seventh step, and judge whether this read / write duration exceeds a preset threshold. If it exceeds, then after marking the acquisition timing corresponding to this read / write duration, give feedback, and use it as special detection data to reflect the read / write function of the corresponding target address. Thus, the detection process becomes more targeted.

[0040] The above preset threshold can be determined by those skilled in the art according to design requirements or actual situations.

[0041] The above preset threshold can also be obtained by analyzing the reading and writing duration through an artificial intelligence chip. Among them, the machine learning model carried by the above artificial intelligence chip is obtained by training with a training sample set.

[0042] As an example, the machine learning model can be obtained by performing the following training steps based on the training sample set: inputting the sample reading and writing durations of at least one training sample in the training sample set into the initial machine learning model respectively to obtain the corresponding preset thresholds; comparing the preset thresholds corresponding to the reading and writing durations of each sample in the above at least one training sample with the corresponding sample preset thresholds; determining the prediction accuracy of the above initial machine learning model according to the comparison results; determining whether the above prediction accuracy is greater than a preset accuracy threshold; in response to determining that the above accuracy is greater than the above preset accuracy threshold, taking the above initial machine learning model as the trained machine learning model; in response to determining that the above accuracy is not greater than the above preset accuracy threshold, adjusting the parameters of the above initial machine learning model, and using the unused training samples to form a training sample set, taking the adjusted initial machine learning model as the initial machine learning model, and performing the above training steps again. It can be understood that after the above training, the machine learning model can be used to represent the corresponding relationship between the reading and writing duration and the preset threshold. The above-mentioned machine learning model can be a convolutional neural network model.

[0043] As an example, the above machine learning model can include a reading and writing duration and a corresponding relationship table. Among them, the corresponding relationship table can be a corresponding relationship table based on the corresponding relationship between a large number of reading and writing durations and preset thresholds by those skilled in the art. In this way, the reading and writing duration is compared with the multiple reading and writing durations in the corresponding relationship table in sequence. If a certain reading and writing duration in the corresponding relationship table is the same as or similar to the reading and writing duration, the preset threshold corresponding to the reading and writing duration in the corresponding relationship table is used as the preset threshold indicated by the reading and writing duration. Thus, the preset threshold can be determined for the reading and writing duration.

[0044] As another example, the above initial machine learning model can be an untrained deep learning model or an incompletely trained deep learning model. Each layer of the initial deep learning model can be set with initial parameters, and the parameters can be continuously adjusted during the training process of the deep learning model. The initial deep learning model can be various types of untrained or incompletely trained artificial neural networks or a model obtained by combining multiple untrained or incompletely trained artificial neural networks. For example, the initial deep learning model can be an untrained convolutional neural network, or an untrained recurrent neural network, or a model obtained by combining an untrained convolutional neural network, an untrained recurrent neural network, and an untrained fully connected layer.

[0045] For further referenceFigure 2 , as an implementation of the method shown in Figure 1 , some embodiments of the present invention provide a read / write duration detection device for DRAM. These device embodiments correspond to Figure 1 those method embodiments shown, and the device can be specifically applied to various electronic devices.

[0046] As shown in Figure 2 , the read / write duration detection device 200 for DRAM in some embodiments includes: a distribution unit 201, a recording unit 202, and a screening unit 203. Among them, the distribution unit 201 is configured to allocate a buffer with a preset capacity for the target address for read / write speed detection. The recording unit 202 is configured to perform read / write operations for a preset number of times and record the start and end times of each read / write operation. The screening unit 203 is configured to determine the read / write duration according to the start and end times and screen the read / write duration.

[0047] It can be understood that the various units described in the device 200 correspond to the respective steps in the method described with reference to Figure 1 . Therefore, the operations, features, and beneficial effects described above for the method also apply to the device 200 and the units included therein, and will not be repeated here.

[0048] Next, refer to Figure 3 , which shows a schematic structural diagram of an electronic device 300 suitable for implementing some embodiments of the present invention. Figure 3 The electronic device shown is only an example and should not bring any limitations to the functions and usage scopes of the embodiments of the present invention.

[0049] As shown in Figure 3 , the electronic device 300 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 302 or the program loaded from the storage device 308 into the random access memory (RAM) 303. In the RAM 303, various programs and data required for the operation of the electronic device 300 are also stored. The processing device 301, the ROM 302, and the RAM 303 are connected to each other through a bus 304. The input / output (I / O) interface 305 is also connected to the bus 304.

[0050] Typically, the following devices can be connected to the I / O interface 305: input devices 306 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 308 including, for example, magnetic tapes, hard disks, etc.; and a communication device 309. The communication device 309 can allow the electronic device 300 to communicate with other devices wirelessly or wireline to exchange data. Although Figure 3 the electronic device 300 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices can be implemented or had. Figure 3 Each block shown in can represent one device or, as needed, multiple devices.

[0051] Specifically, according to some embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, some embodiments of the present invention include a computer program product that includes a computer program carried on a computer-readable medium, and the computer program contains program codes for performing the methods shown in the flowcharts. In such some embodiments, the computer program can be downloaded and installed from a network through the communication device 309, or installed from the storage device 308, or installed from the ROM 302. When the computer program is executed by the processing device 301, the above functions defined in the methods of some embodiments of the present invention are executed.

[0052] It should be noted that the computer-readable medium described in some embodiments of the present invention can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0053] In some embodiments of the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device. In some embodiments of the present invention, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above.

[0054] A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0055] In some embodiments, the client and the server can communicate using any currently known or future-developed network protocol such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet), and end-to-end networks (e.g., ad hoc end-to-end networks), as well as any currently known or future-developed networks.

[0056] The above computer-readable medium may be included in the above electronic device; or it may exist separately without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device is caused to: allocate a buffer with a preset capacity of the target address for read / write speed detection; perform read / write operations a preset number of times, and record the start and end times of each read / write operation; determine the read / write duration according to the start and end times, and screen the read / write duration.

[0057] Computer program code for performing the operations of some embodiments of the present invention may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0058] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur in a different order than noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0059] The units described in some embodiments of the present invention may be implemented in software or in hardware. The described units may also be provided in a processor. For example, it may be described as: a processor includes an allocation unit, a recording unit, and a screening unit. Among them, the names of these units do not constitute a limitation to the unit itself in some cases. For example, the allocation unit may also be described as "the unit that allocates a buffer with a preset capacity of the target address for read / write speed detection".

[0060] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, by way of non-limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), system on a chip (SOC), complex programmable logic devices (CPLD), and so on.

[0061] Some embodiments of the present invention also provide a computer program product, including a computer program which, when executed by a processor, implements any one of the above-mentioned DRAM read / write duration detection methods.

[0062] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting the read and write duration of a DRAM, characterized in that: The method comprises: Allocating a buffer of preset capacity at the target address for reading and writing speed detection; Perform a preset number of read and write operations and record the start and end time of each read and write operation; The reading and writing durations are determined according to the start and end times, and the reading and writing durations are screened.

2. The DRAM read and write duration detection method according to claim 1, characterized in that: Determining the read and write duration according to the start and end time, and screening the read and write duration, including: The obtained multiple read and write durations are used to obtain the timing setting sequence numbers to obtain a sequence number set; Generate a corresponding relationship curve between the sequence number set and the plurality of read and write durations; Perform fitting processing on the corresponding relationship curve to obtain a fitting curve.

3. The DRAM read and write duration detection method according to claim 2, characterized in that: Determining the reading and writing duration according to the start and end time, and screening the reading and writing duration, further comprising: Determine the difference between the value of each read / write time in the corresponding relationship curve and the value of the point corresponding to the data in the fitting curve to obtain a difference value set; Sorting the differences in the difference set according to the numerical values ​​of the differences; Performing a elimination operation on the differences in the difference set according to a preset numerical elimination rate; The read and write durations corresponding to the differences in the difference set after elimination are taken as valid data.

4. The DRAM read and write duration detection method according to claim 3, characterized in that: Determining the reading and writing duration according to the start and end time, and screening the reading and writing duration, further comprising: Determine whether the read / write duration corresponding to the eliminated difference exceeds a preset threshold; If so, the read and write duration marks are acquired and then feedback is given.

5. The DRAM read and write duration detection method according to claim 4, characterized in that: The preset threshold is obtained by analyzing the read and write time by an artificial intelligence chip, wherein the machine learning model carried by the artificial intelligence chip is obtained by training with a training sample set.

6. The DRAM read and write duration detection method according to claim 5, characterized in that: The training sample set includes sample read and write duration and sample preset threshold, and the machine learning model is trained with the sample read and write duration as input and the sample preset threshold as expected output.

7. A DRAM read and write duration detection device, characterized in that: include: an allocation unit configured to allocate a buffer of a preset capacity of a target address for reading and writing speed detection; a recording unit configured to perform a preset number of read and write operations and record the start and end time of each read and write operation; The screening unit is configured to determine the read and write duration according to the start and end time, and screen the read and write duration.

8. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon, When the one or more programs are executed by the one or more processors, the one or more processors can implement the DRAM read and write duration detection method as described in any one of claims 1 to 6.

9. A computer-readable medium, characterized in that A computer program is stored thereon, wherein when the program is executed by a processor, the method for detecting the read and write duration of a DRAM as described in any one of claims 1 to 6 can be implemented.

10. A computer program product, characterized in that It includes a computer program, which, when executed by a processor, can implement the DRAM read and write duration detection method as described in any one of claims 1 to 6.

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