Preparation method of high-voltage semiconductor device structure
By ion implantation on the side walls and bottom of the trench to form a drift region and then filling in the insulator, the problem of ion implantation dose loss in the drift region in the prior art is solved, and a uniformly distributed drift region and high-precision doping concentration control are achieved.
Patent Information
- Application Number
- CN202311584713.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-24
- Publication Date
- 2025-05-27
AI Technical Summary
In the prior art, ion implantation in the drift zone requires thick photoresist to block, and during the ion implantation process, it is necessary to penetrate the thick oxide layer with shallow trench isolation structure, resulting in actual dose loss, making it difficult to ensure the ion doping concentration of the drift zone.
After the trench etching, an ion implantation process is performed to form a drift zone on the side walls and bottom of the trench, and then the trench insulation is filled. By controlling the energy and dose of ion implantation, the drift zone completely covers the bottom and side walls of the shallow trench isolation structure.
The formation of a uniformly distributed drift zone under the shallow trench isolation structure is achieved, reducing the photoresist thickness requirement, avoiding the actual implant dose loss, and improving the precise control of the doping concentration in the drift zone.
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Figure CN120048730A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to a method for preparing a high-voltage semiconductor device structure. Background Art
[0002] In order for a high-voltage (HV) device to withstand a relatively high voltage without breakdown, its device structure is adjusted compared to a traditional low-voltage (LV) CMOS device. It is necessary to reduce the voltage when the high voltage at the drain reaches the channel. Usually, a drift region is set. The main function of this drift region is to lengthen the distance between the gate and the drain, so as to increase the breakdown voltage from the drain to the gate. When a shallow trench isolation structure (STI) is pre-formed in the device, the implantation depth of the drift region is required to be greater than the depth of the shallow trench isolation structure.
[0003] The traditional method for forming the drift region is realized by high-energy ion implantation after the formation of the shallow trench isolation structure. This process requires high-energy ion implantation, so a relatively thick photoresist is needed for blocking, and the process is difficult. Moreover, during the ion implantation process, due to the need to penetrate the relatively thick oxide layer of the shallow trench isolation structure, it will cause a loss of the actual ion implantation dose, making it difficult to ensure the final ion doping concentration of the drift region.
[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention
[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for preparing a high-voltage semiconductor device structure, which is used to solve the problems in the prior art that a relatively thick photoresist is required for blocking the ion implantation of the drift region, and during the ion implantation process, due to the need to penetrate the relatively thick oxide layer of the shallow trench isolation structure, it will cause a loss of the actual ion implantation dose.
[0006] To achieve the above object and other related objects, the present invention provides a method for preparing a high-voltage semiconductor device structure. The preparation method includes: providing a substrate, forming spaced-apart trenches on the substrate; forming a protective liner on the surface of the trenches; forming a mask layer on the substrate, setting an implantation window for defining the drift region in the mask layer, and performing ion implantation on the sidewalls and bottom of the trenches through the implantation window to form a drift region on the sidewalls and bottom of the trenches; after the ion implantation, filling the trenches with an insulating material to form a shallow trench isolation structure.
[0007] Optionally, forming the spaced trenches on the substrate includes: depositing a hard mask layer on the substrate; forming a photolithography pattern on the hard mask layer, the photolithography pattern having a photolithography window corresponding to the trench; etching the hard mask layer based on the photolithography window to form an etching window in the hard mask layer; etching trenches in the substrate based on the etching window.
[0008] Optionally, the high-voltage semiconductor device structure is an NMOS device, and the ions for ion implantation on the sidewalls and bottom of the trench are N-type ions to form an N-type drift region; or the high-voltage semiconductor device structure is a PMOS device, and the ions for ion implantation on the sidewalls and bottom of the trench are P-type ions to form a P-type drift region.
[0009] Optionally, by controlling the implantation energy and implantation dose of ion implantation, the drift region completely covers the bottom and sidewalls of the shallow trench isolation structure.
[0010] Optionally, the cross-sectional shape of the trench is an inverted trapezoid, and the depth of the trench is 2500 Å to 3500 Å.
[0011] Optionally, the protective liner includes a silicon dioxide layer, and the silicon dioxide layer is formed on the trench surface by a thermal oxidation process.
[0012] Optionally, the energy range for ion implantation on the sidewalls and bottom of the trench is 50 KeV to 150 KeV, and the dose range is 4E12 to 1E13 cm -2 。
[0013] Optionally, ion implantation on the sidewalls and bottom of the trench includes inclined implantation, and the angle between the inclined implantation direction and the vertical direction is 10° to 50°.
[0014] Optionally, the trench includes two adjacent and spaced first trenches. A drift region is formed on the sidewalls and bottom of the first trenches. There is a gap between the drift regions of the two first trenches. A gate structure is arranged above the gap. A source region and a drain region are respectively arranged on the two outer sides of the two first trenches, and the source region and the drain region are respectively connected to the corresponding drift regions.
[0015] Optionally, a plurality of second trenches arranged at intervals are further arranged outside the first trenches. Before filling the trench with an insulator, it further includes: performing ion implantation between two adjacent second trenches through an ion implantation process to form a body region, and the conductivity type of the body region is opposite to that of the drift region.
[0016] Optionally, before forming the spaced trenches on the substrate, it further includes the steps of: forming an implantation blocking layer on the substrate, and the implantation blocking layer has a pre-implantation window at the position corresponding to the trench; performing ion implantation on the substrate based on the pre-implantation window, and the implantation depth is deeper than the bottom of the trench to form a pre-implantation region in the region adjacent to the bottom of the trench.
[0017] Optionally, before forming the mask layer on the substrate, the method further includes the steps of: conformally depositing a dielectric layer on the surface of the trench, where when the sidewall of the trench has an inclination angle with respect to the vertical direction, the sidewall of the dielectric layer also has an inclination angle with respect to the vertical direction; etching the inner wall of the dielectric layer through a photolithography process and an anisotropic etching process to make the sidewall of the dielectric layer parallel to the vertical direction.
[0018] As described above, the method for manufacturing the high-voltage semiconductor device structure of the present invention has the following beneficial effects:
[0019] After trench etching in the present invention, an ion implantation process is performed to form a drift region on the sidewalls and bottom of the trench, and then the trench insulator is filled. Therefore, the present invention only requires a relatively low ion implantation energy to form a uniformly distributed drift region under the shallow trench isolation structure, which can greatly reduce the thickness of the required photoresist. At the same time, when performing ion implantation, it is not necessary to penetrate the insulator filled in the shallow trench isolation structure, and there is no problem of actual implantation dose loss, which can greatly improve the precise control of the doping concentration of the drift region. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The accompanying drawings included are used to provide a further understanding of the embodiments of the present application, which form a part of the specification, are used to illustrate the implementation manners of the present application, and together with the textual description, explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application.
[0021] Figures 1 to 16 It shows a schematic structural diagram presented by each step of the method for manufacturing the high-voltage semiconductor device structure according to the embodiment of the present invention.
[0022] Description of Component Labels
[0023] 101 Substrate
[0024] 102 Silicon dioxide thin film
[0025] 103 Silicon nitride thin film
[0026] 104 Photolithography pattern
[0027] 105 First trench
[0028] 106 Second trench
[0029] 107 Protection pad
[0030] 108 First mask layer
[0031] 109 Drift region
[0032] 110 Second mask layer
[0033] 111 Body region
[0034] 112 Insulator
[0035] 113 Gate Structure
[0036] 114 Source Region
[0037] 115 Drain Region
[0038] 201 Injection Barrier Layer
[0039] 202 Pre-Injection Window
[0040] 203 Pre-Injection Region
[0041] 301 Dielectric Layer Detailed Implementation Manner
[0042] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0043] It should be emphasized that the term "including / comprising" when used herein refers to the presence of features, whole, steps or components, but does not exclude the presence or addition of one or more other features, whole, steps or components.
[0044] Features described and / or illustrated for one implementation manner can be used in the same or similar manner in one or more other implementation manners, combined with features in other implementation manners, or replace features in other implementation manners.
[0045] When detailing the embodiments of the present invention, for the sake of convenience of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.
[0046] For the sake of convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more layers in between.
[0047] In the context of the present application, the structure in which the first feature described is "above" the second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0048] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0049] The traditional method of forming the drift region is achieved by high-energy ion implantation after the formation of the shallow trench isolation structure. This process requires high-energy ion implantation, so a relatively thick photoresist is needed for blocking, and the process is difficult. Moreover, during the ion implantation process, since it is necessary to penetrate the relatively thick oxide layer of the shallow trench isolation structure, it will cause a loss of the actual dose of ion implantation, making it difficult to ensure the ion doping concentration of the final drift region.
[0050] To solve the above problems, as Figures 1 to 16 shown, this embodiment provides a method for fabricating a high-voltage semiconductor device structure, and the fabrication method includes the following steps:
[0051] As Figures 1 to 5 shown, first, perform step 1), provide a substrate 101, and form trenches arranged at intervals on the substrate 101.
[0052] In some embodiments, the substrate 101 may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a group III-V compound (such as gallium nitride, gallium arsenide, etc.), and is not limited to the examples listed above. Element doping may also be pre-set in the substrate 101 to adjust the substrate 101 to the desired resistivity. Various doping regions, such as bulk doping regions, may also be provided in the substrate 101.
[0053] In a specific example, forming trenches arranged at intervals on the substrate 101 includes the following steps:
[0054] As Figure 2 shown, perform step 1-1), deposit a hard mask layer on the substrate 101. Specifically, a silicon dioxide thin film 102 and a silicon nitride thin film 103 may be sequentially deposited on the substrate 101 through a chemical vapor deposition process, such as a plasma-enhanced chemical vapor deposition process (PECVD), etc., to form a hard mask layer.
[0055] As Figure 3As shown, perform step 1-2), and form a photolithography pattern 104 on the hard mask layer. The photolithography pattern 104 has a photolithography window corresponding to the trench.
[0056] As Figure 4 shown, perform step 1-3), and etch the hard mask layer based on the photolithography window to form an etch window in the hard mask layer.
[0057] As Figure 5 shown, perform step 1-4), and etch a trench in the substrate 101 based on the etch window.
[0058] In one embodiment, the cross-sectional shape of the trench can be an inverted trapezoid, and the angle between the side wall and the bottom of the trench can be, for example, 95° to 105°. It should be noted that when the cross-section of the trench is an inverted trapezoid, doping of the corresponding trench side wall can also be achieved through a vertical ion implantation process, or the difficulty of doping the trench side wall during the inclined ion implantation process can be reduced.
[0059] In some embodiments, the depth of the trench is 2500 Å to 3500 Å. For example, the depth of the trench can be 3000 Å.
[0060] In one embodiment, the trench includes two adjacent and spaced-apart first trenches 105. A drift region 109 is formed on the side wall and the bottom of the first trench 105. There is a gap between the drift regions 109 of the two first trenches 105. A gate structure 113 is disposed above the gap. Source regions 114 and drain regions 115 are respectively disposed on the two outer sides of the two first trenches 105. The source regions 114 and the drain regions 115 are respectively connected to the corresponding drift regions 109.
[0061] In one embodiment, a plurality of second trenches 106 arranged at intervals are further disposed outside the first trench 105. As Figure 5 shown, the second trench 106 and the first trench 105 can be formed simultaneously in the same photolithography process and etch process.
[0062] As Figure 6 shown, then perform step 2), and form a protective pad 107 on the surface of the trench.
[0063] In one embodiment, the protective liner 107 includes a silicon dioxide layer, which can be formed on the surface of the trench by a thermal oxidation process. The thickness of the silicon dioxide can be 20 angstroms to 60 angstroms. The silicon dioxide layer serves as the protective liner 107. On the one hand, it can repair the defects introduced on the trench surface during the aforementioned etching process through oxidation, improving the quality of the trench surface. On the other hand, the protective substrate can protect the surfaces of the trench and the substrate 101 during the subsequent ion implantation process, avoiding the defects caused to the substrate 101 and the trench surface during the ion implantation process. Further, by forming the protective liner 107 through a thermal oxidation process, the corners of the trench can be made rounded, reducing the influence of device tip discharge.
[0064] As Figures 7 to 8 shown, then step 3) is carried out. A first mask layer 108 (such as a photoresist mask) is formed on the substrate 101. An implantation window for defining the drift region 109 is set in the first mask layer 108. The implantation window exposes the sidewalls and the bottom of the first trench 105. Ion implantation is performed on the sidewalls and the bottom of the first trench 105 through the implantation window to form a drift region 109 on the sidewalls and the bottom of the first trench 105.
[0065] In one embodiment, the high-voltage semiconductor device structure is an NMOS device, and the ions for ion implanting the sidewalls and the bottom of the first trench 105 are N-type ions to form an N-type drift region 109.
[0066] In another embodiment, the high-voltage semiconductor device structure is a PMOS device, and the ions for ion implanting the sidewalls and the bottom of the first trench 105 are P-type ions to form a P-type drift region 109.
[0067] In one embodiment, by controlling the implantation energy and implantation dose of the ion implantation, the drift region 109 completely covers the bottom and the sidewalls of the shallow trench isolation structure.
[0068] In one embodiment, the energy range for ion implanting the sidewalls and the bottom of the first trench 105 is 50 KeV to 150 KeV, and the dose range is 4E12 to 1E13 cm -2 2.
[0069] In one embodiment, the ion implantation of the sidewalls and bottom of the first trench 105 includes inclined implantation, and the angle between the inclined implantation direction and the vertical direction is 10° to 50°. For example, a first implantation can be performed with an ion implantation angle of 10° to 50° with respect to the sidewall of the first trench 105, and then the substrate 101 is rotated 180°, and the ion implantation angle is kept unchanged for a second implantation to form a drift region 109 with a uniform depth on the bottom and opposite sidewalls of the first trench 105, without the need for secondary adjustment of the ion implantation angle, reducing the difficulty and cost of the ion implantation process. Of course, the substrate 101 can also be kept stationary, and the drift region 109 on the bottom and opposite sidewalls of the first trench 105 can be achieved by adjusting the ion implantation direction angle.
[0070] Furthermore, the depth of the drift region 109 at the bottom and sidewalls of the shallow trench isolation structure can be made uniform by controlling the implantation energy, implantation dose, and / or implantation angle of the ion implantation, so that the resistivity of each part of the drift region 109 is basically the same, improving the uniformity of the electric field.
[0071] As Figures 9 to 10 shown, before filling the insulating material 112 in the trench, it further includes: providing a second mask layer 110 (such as a photoresist mask), and performing ion implantation between two adjacent second trenches 106 through an ion implantation process to form a body region 111, and the conductivity type of the body region 111 is opposite to that of the drift region 109.
[0072] The body region 111 of the present invention is also formed by an ion implantation process before filling the insulating material 112 of the shallow trench structure, so as to reduce the implantation energy and dose required for implanting the body region 111, without the need to prepare a thick photoresist to protect the drift region 109 and the source region 114 and drain region 115, and can also minimize the impact of the implantation of the body region 111 on the drift region 109 and the source region 114 and drain region 115, thereby greatly improving the stability of the device process and performance.
[0073] As Figure 11 shown, finally, step 4) is performed. After the ion implantation, an insulating material 112 is filled in the trenches (both in the first trench 105 and the second trench 106) to form a shallow trench isolation structure.
[0074] In one embodiment, the insulating material 112, such as silicon dioxide, can be filled in the first trench 105 and the second trench 106 simultaneously by processes such as high-density plasma chemical vapor deposition (HDP) and chemical vapor deposition (CVD), and planarization can be achieved by processes such as chemical mechanical polishing (CMP) or etch-back.
[0075] As Figure 12As shown, finally, above the gap between the drift regions 109 of the two first trenches 105, a gate structure 113 is provided. Source regions 114 and drain regions 115 are respectively disposed on the two outer sides of the two first trenches 105. The source regions 114 and the drain regions 115 are respectively connected to the corresponding drift regions 109 to form corresponding MOS device structures.
[0076] As Figures 13 to 14 shown, in some embodiments, before forming the spaced-apart trenches on the substrate, the following steps are further included:
[0077] As Figure 13 shown, an implantation blocking layer 201 is formed on the substrate 101. The implantation blocking layer 201 has pre-implantation windows 202 at positions corresponding to the trenches.
[0078] As Figure 14 shown, based on the pre-implantation windows 202, the substrate 101 is subjected to ion implantation, and the implantation depth is deeper than the bottom of the trenches, so as to form a pre-implantation region 203 in the region adjacent to the bottom of the trenches. The implanted ion type of the pre-implantation region 203 is the same as that of the drift region. The pre-implantation region 203 can supplement the concentration of the drift region in the corner region at the bottom of the trenches, thereby effectively reducing the on-resistance of the device.
[0079] As Figures 15 to 16 shown, in some embodiments, before forming the mask layer on the substrate, the following steps are further included:
[0080] As Figure 15 shown, a conformal dielectric layer 301 is deposited on the surface of the trenches 105. The dielectric layer can be, for example, silicon dioxide, etc. When the sidewalls of the trenches 105 have an inclination angle with respect to the vertical direction, the sidewalls of the dielectric layer 301 have an inclination angle with respect to the vertical direction.
[0081] As Figure 16 shown, the inner wall of the dielectric layer 301 is etched through a photolithography process and an anisotropic etching process, so that the sidewalls of the dielectric layer are parallel to the vertical direction.
[0082] In this example, the conformal dielectric layer is anisotropically etched to form sidewalls perpendicular to the bottom of the trenches. When performing ion implantation subsequently, because after anisotropic etching, the distance from the bottom corners and the bottom edges of the trenches to the inner sidewall surface of the formed rectangle is smaller than other places, the depth at which the finally formed ions reach is formed along with the inner surface in the substrate, so as to ensure that the ion implantation can be deeper at the lower corners and the bottom of the trenches. Therefore, the closer the outer sidewalls of the trenches are to the inner sidewalls of the dielectric layer, the farther the highest concentration region of the finally formed ion implantation can be from the boundary of the trenches. That is, it can make the sharp corners of the trenches be surrounded by the drift regions as much as possible, preventing tip discharge and easy breakdown at sharp points.
[0083] As described above, the method for preparing the high-voltage semiconductor device structure of the present invention has the following beneficial effects:
[0084] After the trench etching in the present invention, an ion implantation process is carried out to form the drift region 109 on the sidewalls and the bottom of the trench, and then the trench insulator 112 is filled. Therefore, the present invention only needs a relatively low ion implantation energy to form a uniformly distributed drift region 109 under the shallow trench isolation structure, which can greatly reduce the thickness of the required photoresist. At the same time, when ion implanting, it is not necessary to pass through the insulator 112 filled in the shallow trench isolation structure, and there is no problem of actual implantation dose loss, which can greatly improve the precise control of the doping concentration of the drift region 109.
[0085] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0086] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a high-voltage semiconductor device structure, characterized in that, the preparation method includes: providing a substrate, and forming trenches arranged at intervals on the substrate; forming a protective liner on the surface of the trenches; forming a mask layer on the substrate, setting an implantation window for defining a drift region in the mask layer, and performing ion implantation on the sidewalls and bottom of the trenches through the implantation window to form a drift region on the sidewalls and bottom of the trenches; after ion implantation, filling the trenches with an insulating material to form a shallow trench isolation structure.
2. The method for preparing a high-voltage semiconductor device structure according to claim 1, characterized in that, forming trenches arranged at intervals on the substrate includes: depositing a hard mask layer on the substrate; forming a photolithography pattern on the hard mask layer, the photolithography pattern having a photolithography window corresponding to the trenches; etching the hard mask layer based on the photolithography window to form an etching window in the hard mask layer; etching trenches in the substrate based on the etching window.
3. The method for preparing a high-voltage semiconductor device structure according to claim 1, characterized in that: the high-voltage semiconductor device structure is an NMOS device, and the ions for performing ion implantation on the sidewalls and bottom of the trenches are N-type ions to form an N-type drift region; or the high-voltage semiconductor device structure is a PMOS device, and the ions for performing ion implantation on the sidewalls and bottom of the trenches are P-type ions to form a P-type drift region.
4. The method for preparing a high-voltage semiconductor device structure according to claim 1, characterized in that: by controlling the implantation energy and implantation dose of ion implantation, the drift region completely covers the bottom and sidewalls of the shallow trench isolation structure.
5. The method for preparing a high-voltage semiconductor device structure according to claim 1, characterized in that: the cross-sectional shape of the trenches is an inverted trapezoid, and the depth of the trenches is 2500 Å to 3500 Å.
6. The method for preparing a high-voltage semiconductor device structure according to claim 1, characterized in that: the protective liner includes a silicon dioxide layer, and the silicon dioxide layer is formed on the surface of the trenches by a thermal oxidation process.
7. The method for preparing a high-voltage semiconductor device structure according to claim 1, characterized in that: the energy range for performing ion implantation on the sidewalls and bottom of the trenches is, and the dose range is.
8. The method for preparing a high-voltage semiconductor device structure according to claim 1, characterized in that: performing ion implantation on the sidewalls and bottom of the trenches includes inclined implantation, and the angle between the direction of the inclined implantation and the vertical direction is 10° to 50°.
9. The method for preparing a high-voltage semiconductor device structure according to claim 1, characterized in that: the trenches include two adjacent and spaced-apart first trenches, a drift region is formed on the sidewalls and bottom of the first trenches, there is a gap between the drift regions of the two first trenches, a gate structure is arranged above the gap, a source region and a drain region are respectively arranged on the two outer sides of the two first trenches, and the source region and the drain region are respectively connected to the corresponding drift regions.
10. The manufacturing method of the high-voltage semiconductor device structure according to claim 9, characterized in that: A plurality of second trenches arranged at intervals are further provided outside the first trench. Before filling the trenches with an insulating material, it further includes: performing ion implantation between two adjacent second trenches through an ion implantation process to form a body region, and the conductivity type of the body region is opposite to that of the drift region.
11. The manufacturing method of the high-voltage semiconductor device structure according to claim 1, characterized in that, Before forming trenches arranged at intervals on the substrate, it further includes the steps of: forming an implantation blocking layer on the substrate, and the implantation blocking layer has a pre-implantation window at the position corresponding to the trench; performing ion implantation on the substrate based on the pre-implantation window, and the implantation depth is deeper than the bottom of the trench to form a pre-implantation region in the region adjacent to the bottom of the trench.
12. The manufacturing method of the high-voltage semiconductor device structure according to claim 1 or 11, characterized in that, Before forming a mask layer on the substrate, it further includes the steps of: conformally depositing a dielectric layer on the surface of the trench. When the side wall of the trench has an inclination angle with the vertical direction, the side wall of the dielectric layer has the inclination angle with the vertical direction; etching the inner wall of the dielectric layer through a photolithography process and an anisotropic etching process to make the side wall of the dielectric layer parallel to the vertical direction.