Manufacturing method of cobalt silicide and manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a cobalt silicide and a manufacturing method of a semiconductor device, and the method comprises the steps: carrying out the rapid heat treatment of a silicon substrate deposited with metal cobalt at a first temperature, removing unreacted cobalt, carrying out the rapid heat treatment at a second temperature, and then depositing at least one dielectric material layer, and first laser peak annealing is carried out on any proper node after deposition of partial or all dielectric material layers is completed, so that de-crystallization points in the cobalt silicide are re-activated and crystallized, and therefore, under the condition that the influence on the original device manufacturing process is small, the performance of the device can be improved. The performance of the device is improved by adding one or more first laser spike annealing.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a method for manufacturing cobalt silicide and a method for manufacturing a semiconductor device. Background Art

[0002] When the feature size of the semiconductor process is reduced to below deep sub-micron, the size width of the source and drain active regions of the transistor continuously decreases, resulting in an increasing series resistance of the active region of the device, thereby affecting the speed of the circuit. In order to reduce the series resistance and contact resistance of the active region, after the source and drain ion implantation is completed, a salicide process is introduced. This salicide process adds related process steps of metal silicidation on the basis of the standard CMOS process technology. The metal silicides commonly used in this technology include titanium silicide, cobalt silicide, nickel silicide, etc.

[0003] Since in the process nodes of 65 nanometers and below, titanium silicide and nickel silicide have disadvantages such as low thermal stability and high resistivity. Especially in the case of a higher temperature process in the back-end process, it is more difficult to adopt. For example, nickel silicide is prone to piping defects in the high-temperature process. Therefore, cobalt silicide is selected to replace titanium silicide and nickel silicide. Specifically, after the source and drain ion implantation and annealing activation are completed, metallic cobalt (Co) is deposited and two rapid thermal processes are carried out. The first rapid thermal process causes the metallic cobalt to react with silicon to generate a high-resistance phase of cobalt silicide Co 2 Si, and the second thermal annealing process can cause the high-resistance Co 2 Si phase to transform into a low-resistance CoSi phase or CoSi 2 phase.

[0004] The inventors have found that in the above process, since the crystal phase transformation temperature of cobalt silicide is high, that is, the temperature of the second thermal annealing process is relatively high. Therefore, the high temperature of the second thermal annealing process will increase the recrystallized cobalt silicide, that is, it will cause the resistance of the cobalt silicide with an easily transformed resistance phase to increase, and the number of high-resistance scatter points will increase. The resistance of the cobalt silicide after the second thermal annealing process increases relative to the ideal situation. At the same time, the ordered lattice in the silicon substrate masked by the silicide barrier layer is also damaged, resulting in an increase in the resistance at the silicide barrier layer, which is not conducive to improving the device performance. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for manufacturing cobalt silicide and a method for manufacturing a semiconductor device, which can further reduce the resistance of cobalt silicide and is conducive to improving the device performance.

[0006] To achieve the above purpose, the present invention provides a method for manufacturing cobalt silicide, which includes:

[0007] Provide a silicon substrate and deposit cobalt metal on the silicon substrate;

[0008] Perform rapid thermal processing at a first temperature to cause the cobalt metal to react with the silicon substrate to form cobalt silicide;

[0009] Remove the unreacted cobalt metal;

[0010] Perform rapid thermal processing at a second temperature to transform the high-resistance phase of the cobalt silicide into a low-resistance phase, where the second temperature is higher than the first temperature;

[0011] Deposit at least one dielectric material layer, and at least one process node after depositing some or all of the dielectric material layers, perform first laser spike annealing to reactivate and crystallize the recrystallization points in the cobalt silicide.

[0012] Optionally, the range of the first temperature is 400°C to 600°C, and / or the range of the second temperature is 700°C to 900°C.

[0013] Optionally, before depositing cobalt metal, the manufacturing method further includes:

[0014] Form a gate;

[0015] Form source / drain trenches on both sides of the gate;

[0016] Epitaxially grow a germanium-silicon source / drain in the source / drain trenches.

[0017] Optionally, the dielectric material layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material with a dielectric constant lower than that of silicon oxide.

[0018] Optionally, when multiple layers of the dielectric material layer are deposited, the thickness of each layer of the dielectric material layer is The total thickness of the dielectric material layer deposited on the cobalt silicide is

[0019] Optionally, the temperature range of the first laser spike annealing is 1100°C to 1200°C.

[0020] Based on the same inventive concept, the present invention also provides a manufacturing method of a semiconductor device, which includes: providing a silicon substrate and using the manufacturing method of cobalt silicide as described in the present invention to form the cobalt silicide required for the semiconductor device and at least one dielectric material layer stacked on the cobalt silicide.

[0021] Optionally, before forming the cobalt silicide required for the semiconductor device, the manufacturing method of the semiconductor device further includes:

[0022] Form a gate on the silicon substrate, and perform source-drain ion implantation on the silicon substrate on both sides of the gate to form source-drain regions;

[0023] Perform spike thermal annealing first and then second laser spike annealing to activate the ions implanted in the source-drain regions;

[0024] Deposit a silicide blocking layer, and open the silicide blocking layer on at least one of the source-drain regions and the gate through photolithography and etching processes to expose the silicon in the region where cobalt silicide is to be formed;

[0025] Wherein, the cobalt silicide is formed on the region of the silicon substrate where cobalt silicide is to be formed.

[0026] Optionally, deposit a multi-layer dielectric material layer on the cobalt silicide, and the first deposited dielectric material layer is a contact hole etch stop layer, the second deposited dielectric material layer is a bottom interlayer dielectric layer for forming contact plugs, the intermediate dielectric material layers deposited thereafter are inter-metal dielectric layers between adjacent two metal interconnect layers in the back-end metal interconnect process, and the topmost deposited dielectric material layer is a passivation layer on the top metal interconnect structure; The manufacturing method of the semiconductor device further includes:

[0027] After depositing the bottom interlayer dielectric layer, etch the bottom interlayer dielectric layer and the contact hole etch stop layer on the gate and the source-drain regions to form contact holes exposing the cobalt silicide;

[0028] Fill the corresponding metal into the contact holes to form contact plugs in electrical contact with the cobalt silicide;

[0029] Adopt a single damascene process or a dual damascene process for the back-end metal interconnect process, deposit the corresponding inter-metal dielectric layer, and form a multi-layer metal interconnect structure having at least two metal interconnect lines in the deposited inter-metal dielectric layer. Any two metal interconnect lines are electrically connected through a conductive via, and the bottom of the bottom metal interconnect line of the multi-layer metal interconnect structure is electrically in contact with the contact plug;

[0030] Deposit the passivation layer, and remove the passivation layer in the corresponding region through photolithography and etching processes to expose a part of the top surface of the top metal interconnect structure to form a bonding pad.

[0031] Optionally, perform first laser spike annealing at at least one process node after depositing the contact hole etch stop layer and before forming the bonding pad to reactivate and crystallize the recrystallization points in the cobalt silicide.

[0032] Compared with the prior art, in the technical solution of the present invention, after performing rapid thermal processing on a silicon substrate deposited with metallic cobalt at a first temperature to remove unreacted cobalt, and performing rapid thermal processing at a second temperature, at least one dielectric material layer is deposited, and at any suitable node after the deposition of some or all of the dielectric material layers is completed, a first laser spike annealing is performed to reactivate and crystallize the recrystallization points in the cobalt silicide, thereby being able to improve device performance by adding one or more first laser spike annealing processes while ensuring a minimal impact on the original device manufacturing process. Description of the Drawings

[0033] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0034] Figure 1 is a schematic flowchart of a method for manufacturing cobalt silicide according to an embodiment of the present invention.

[0035] Figure 2 is a schematic cross-sectional view of a device structure in a method for manufacturing cobalt silicide according to an embodiment of the present invention.

[0036] Figure 3 is a schematic cross-sectional view of a device structure in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Embodiments

[0037] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, well-known technical features have not been described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout the drawings indicate the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0038] The technical solution proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0039] Please refer to Figure 1 , an embodiment of the present invention provides a method for manufacturing cobalt silicide, which includes:

[0040] S11, providing a silicon substrate and depositing metallic cobalt on the silicon substrate;

[0041] S12, performing rapid thermal processing at a first temperature to cause the metallic cobalt to react with the silicon substrate to form cobalt silicide;

[0042] S13, removing the unreacted metallic cobalt;

[0043] S14, performing rapid thermal processing at a second temperature to transform the high-resistance phase of the cobalt silicide into a low-resistance phase, where the second temperature is higher than the first temperature;

[0044] S15, depositing at least one dielectric material layer, and performing first laser spike annealing at at least one process node after depositing some or all of the dielectric material layers, so that the recrystallization points in the cobalt silicide are reactivated and crystallized.

[0045] Please refer to Figure 2 in (A). In step S11, the provided silicon substrate 100 can be a bare silicon substrate or a substrate processed by a corresponding CMOS process, for example, structures such as gates and source-drain regions have been formed (only a partial cross-sectional view of the substrate and the deposited metal silicon structure at some positions is shown in the figure). As an example, a gate (not shown) is formed on the silicon substrate 100 through a gate process; sidewalls (not shown) are formed on the sidewalls of the gate through a sidewall process; source-drain trenches (not shown) are formed in the silicon substrate 100 on both sides of the gate through an etching process; and, through a selective epitaxial growth process, germanium-silicon source-drains (not shown) are epitaxially grown in the source-drain trenches.

[0046] Please refer to Figure 2 in (A). In step S11, after preparing the silicon substrate 100 on which cobalt silicide is to be formed, metallic cobalt (Co) 101 is deposited on the silicon substrate 100 by any suitable process such as sputtering deposition. The exposed silicon top surface of the silicon substrate 100 (which can be a partial top surface of regions such as germanium-silicon source-drains) is in direct contact with the metallic cobalt (Co) 101. The deposition thickness of the metallic cobalt 101 is generally greater than the thickness required for the subsequent formation of cobalt silicide.

[0047] Please refer to Figure 2 (B) in [reference document]. In step S12, perform any suitable rapid thermal processing (RTP), such as rapid thermal annealing, on the silicon substrate 100 at a first temperature, causing the metal cobalt (Co) 101 to react with the silicon in contact therewith to form cobalt silicide 101a. Optionally, the range of the first temperature is 400°C to 600°C, for example, about 480°C, and the formed cobalt silicide 101a is a high-resistance phase, and its composition is mainly high-resistance Co 2 Si phase. At this time, there will be remaining unreacted metal cobalt 101' on the cobalt silicide 101a.

[0048] Please refer to Figure 2 (B) and (C) in [reference document]. In step S13, remove the unreacted metal cobalt 101' by any suitable process such as wet etching or dry etching.

[0049] Please continue to refer to Figure 2 (C) in [reference document]. In step S14, perform a second rapid thermal processing (RTP), such as rapid thermal annealing, at a second temperature, which is higher than the first temperature, so that the high-resistance phase cobalt silicide 101a is converted into a low-resistance phase cobalt silicide 101b. Optionally, the range of the second temperature is 700°C to 900°C, for example, about 800°C, and the main component of the formed cobalt silicide 101b is low-resistance CoSi phase or CoSi 2 phase. Moreover, the second temperature is relatively high, and this high temperature increases the recrystallization point (also known as the recrystallization scatter point) in the cobalt silicide 101b (i.e., the cobalt silicide 101b recrystallizes at some positions), resulting in the resistance of the cobalt silicide 101b not being able to be further reduced (i.e., the resistance of the cobalt silicide 101b becomes larger compared to the resistance of the ideal low-resistance phase cobalt silicide).

[0050] Please refer to Figure 2 (D) in [reference document]. In step S15, deposit at least one layer of dielectric material layer 102 on the cobalt silicide 101b, for example, deposit n (n≥1 and n is an integer) layers of dielectric material layers 1021 to 102n. The materials of adjacent two layers in the dielectric material layers 1021 to 102n can be the same or different, and the thicknesses can be the same or different. Each layer of dielectric material layer is a film layer required for the device manufacturing process after the formation of the cobalt silicide 101b.

[0051] Optionally, each layer of dielectric material layer 1021 to 102n can be selected from silicon oxide, silicon nitride, silicon oxynitride, or a low-k material with a dielectric constant lower than that of silicon oxide. Thus, the stacked structure formed by all the dielectric material layers 102 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material with a dielectric constant lower than that of silicon oxide.

[0052] Optionally, the thickness of each of the dielectric material layers 1021 to 102n of the dielectric material layer is The total thickness of the dielectric material layers 1021 to 102n deposited on the cobalt silicide 101b is

[0053] Please refer to Figure 2 (E) in, perform the first laser spike annealing (LSA) at any suitable one or more process nodes in step S15, that is, perform the first laser spike annealing (LSA) at any one process node or multiple process nodes after depositing the dielectric material layer 1021 and before depositing the dielectric material layers 1021 to 102n. For example, perform it only once after depositing the dielectric material layers 1021 to 102n, or perform the first laser spike annealing (LSA) once after any one layer or two or more consecutive layers of the dielectric material layers 1021 to 102n, that is, intersperse the first laser spike annealing between the depositions of the dielectric material layers of different layers, so as to obtain a more uniform recrystallization activation effect through multiple first laser spike annealings.

[0054] Optionally, the temperature range of any first laser spike annealing is 1100 °C to 1200 °C. Exemplarily, the temperature of any first laser spike annealing is about 1100 °C.

[0055] The manufacturing method of the cobalt silicide in this embodiment, on the basis of the conventional process of forming cobalt silicide, further deposits the corresponding dielectric material layer, and uses laser spike annealing to activate the recrystallization points of the cobalt silicide, so that these scattered points recrystallize, thereby reducing the resistance of the cobalt silicide, improving the DC performance, and having little impact on the original process, and is applicable to the manufacturing of any device that needs to improve the DC performance.

[0056] For example, the manufacturing method of the cobalt silicide in this embodiment can be used for the manufacturing of CMOS devices. After experiencing source / drain ion implantation of CMOS devices, depositing metallic cobalt and performing rapid thermal processing at the first temperature and the second temperature to form cobalt silicide on the source / drain regions, and removing the unreacted cobalt, perform the first laser spike annealing at any one or more process nodes after depositing the contact hole etch stop layer and the bottom interlayer dielectric layer in the back-end process (for example, intersperse the first laser spike annealing between the depositions of different interlayer dielectric layers), and one or more first laser spike annealings can be performed in the entire back-end process, and the first laser spike annealing can be performed intermittently or continuously, so that the recrystallization points in the previously formed cobalt silicide are reactivated and crystallized, thereby being able to reduce the resistance of the cobalt silicide while ensuring a minimal impact on the original device manufacturing process, and further improving the device performance (for example, increasing the DC performance of the device by 7%).

[0057] Based on this, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, which includes: providing a silicon substrate, and using the method for manufacturing cobalt silicide as described in the present invention to form cobalt silicide required for the semiconductor device and at least one dielectric material layer stacked on the cobalt silicide.

[0058] As an example, the step of providing a silicon substrate includes:

[0059] First, please refer to Figure 3 in (A), provide a bare silicon substrate 200. The material of the bare silicon substrate 200 can be any suitable silicon substrate material such as silicon (Si), silicon germanium (GeSi), silicon carbide (SiC), or silicon on insulator (SOI). Through any suitable device isolation process such as shallow trench isolation process or local field oxidation isolation process, a shallow trench isolation structure 201 can be formed in the bare silicon substrate 200, thereby defining corresponding nMOS regions and pMOS regions. And before or after forming the shallow trench isolation structure 201, corresponding n-type wells (not shown) or p-type wells (not shown) can also be formed in the bare silicon substrate 200 of the nMOS region or pMOS region through corresponding ion implantation processes;

[0060] Then, please refer to Figure 3 in (A), through any suitable process such as thermal oxidation or chemical vapor deposition, a gate oxide layer 202 is synchronously formed on the bare silicon substrate 200 of the nMOS region and pMOS region, and further polysilicon is deposited on the gate oxide layer 202 and gate lithography and etching are performed, thereby synchronously forming corresponding polysilicon gates 203 on the nMOS region and pMOS region;

[0061] Next, please refer to Figure 3 in (A), sidewalls 204 are formed on the sidewalls of the polysilicon gates 203 through a sidewall process.

[0062] After that, please refer to Figure 3 in (A), first, a photoresist is coated and lithography processes such as developing the photoresist are performed with the mask plate for forming the source and drain of the nMOS device (i.e., the nMOS S / D mask) to form a patterned photoresist 300. Further, using the patterned photoresist 300, the polysilicon gate 203 and the sidewall 204 of the nMOS region as masks, the bare silicon substrate 200 of the nMOS region is subjected to source and drain ion implantation with n-type ions such as P (phosphorus) or As (arsenic) (i.e., n-type ion implantation is performed on the nMOS region) to form n-type source and drain implantation regions 205n in the bare silicon substrate 200 on both sides of the polysilicon gate 203 of the nMOS region. Next, please refer to Figure 3(B) in it, the patterned photoresist 300 is removed through a suitable photoresist stripping process, and then a photoresist is coated and lithography processes such as developing the photoresist are performed by means of a mask plate for forming the source and drain of the pMOS device (i.e., the pMOS S / D mask) to form a patterned photoresist 301. Further, using the patterned photoresist 301, the polysilicon gate 203 and the sidewall 204 in the pMOS region as masks, at least one p-type ion such as B (boron), BF 2 (boron fluoride), Ga (gallium), In (indium), etc. is used to perform source and drain ion implantation on the bare silicon substrate 200 in the pMOS region (i.e., p-type ion implantation on the pMOS region) to form p-type source and drain implantation regions 205p in the bare silicon substrate 200 on both sides of the polysilicon gate 203 in the pMOS region. In the above steps, the pMOS region is first masked and n-type ion implantation is performed, and then the nMOS region is masked and p-type ion implantation is performed. In other embodiments, the nMOS region can also be masked first and p-type ion implantation is performed, and then the pMOS region is masked and n-type ion implantation is performed. In some embodiments, when the critical dimension (CD) of the device is small to a certain extent, in order to improve the carrier migration rate and increase the speed of the device, the formation of the structures at the source and drain of the pMOS region and the nMOS region can also adopt the source and drain embedded SiC strain technology (applied to the nMOS region) and the source and drain embedded SiGe strain technology (applied to the pMOS region) to adapt to the application scenario when the CD is small, and metal cobalt is deposited on the surface layer of the SiGe source and drain in the pMOS region or the SiC source and drain in the nMOS region, and other salicide formation processes are performed, which is the same as the method in the above embodiment and will not be elaborated in detail here.

[0063] After the n-type source and drain implantation regions 205n and the p-type source and drain implantation regions 205p are formed, spike thermal annealing (S / D spike anneal) is first performed, and then the above-mentioned laser spike annealing (LSA) is performed to activate the n-type ions in the n-type source and drain implantation regions 205n and the p-type ions in the p-type source and drain implantation regions 205p.

[0064] Then, please refer to Figure 3In (C), through processes such as deposition, photolithography, etching, and photoresist stripping of a silicide area block (SAB) material (such as silicon oxide, silicon nitride, or silicon oxynitride), a silicide blocking layer 206 is formed. The silicide blocking layer 206 exposes at least a part of the top surface of each polysilicon gate 203, at least a part of the top surface of the n-type source / drain injection region 205n, and at least a part of the top surface of the p-type source / drain injection region 205p. The area masked by the silicide blocking layer 206 is the area where cobalt silicide does not need to be formed. Subsequently, while forming cobalt silicide on the n-type source / drain injection region 205n and the p-type source / drain injection region 205p, cobalt silicide is also formed on the top surface of each polysilicon gate 203. In other embodiments of the present invention, according to device performance and design requirements, in addition to masking surfaces such as the sidewalls of the sidewall 204, the remaining silicide blocking layer 206 after etching also masks the top surface of the polysilicon gate 203. Thus, when forming cobalt silicide on the n-type source / drain injection region 205n and the p-type source / drain injection region 205p subsequently, cobalt silicide is not formed on the top surface of the polysilicon gate 203 at the same time.

[0065] After forming the silicide blocking layer 206, please refer to Figure 3 In (C), under the masking effect of the silicide blocking layer 206, pre-amorphization ion implantation (i.e., PAI implantation) is performed on the nMOS region, the pMOS region, and the polysilicon gate 203 together. The ions for PAI implantation are usually elements such as Ge and C, thereby forming the required silicon substrate. Among them, by using the ions implanted by PAI, the atoms in the lattices of the n-type source / drain injection region 205n, the p-type source / drain injection region 205p, and the polysilicon gate 203 can be displaced, causing the crystal to transform into an amorphous state, thereby reducing the subsequent CoSi phase transition temperature.

[0066] Next, steps S11 to S14 in the manufacturing method of cobalt silicide of the present invention are implemented. Specifically, (1) please refer to Figure 3 In (D), step S11 is executed to deposit metallic cobalt 207 on the silicide blocking layer 206 and the exposed top surfaces of the n-type source / drain injection region 205n, the p-type source / drain injection region 205p, and the polysilicon gate 203; (2) please refer to Figure 3 In (E), step S12 is executed to perform rapid thermal processing (RTP) at a first temperature to form a high-resistance phase of cobalt silicide 208; (3) please refer to Figure 3 In (E), step S13 is executed to perform rapid thermal processing (RTP) at a second temperature to convert the high-resistance phase of the cobalt silicide 208 into a low-resistance phase. During this heat treatment process, the amorphous layer generated by PAI implantation can reduce the CoSi phase transition temperature; (4) please refer to Figure 3In (E), perform step S14 to remove the unreacted Co by any suitable process such as wet etching or dry etching.

[0067] After that, perform the back-end process, and in this back-end process, perform step S15 in the method for manufacturing cobalt silicide of the present invention. Exemplarily, please refer to Figure 3 In (F), the back-end process includes the following steps:

[0068] (1) Deposit materials such as silicon oxide to form the first dielectric material layer and serve as the contact hole etch stop layer 2091. (2) Deposit a low-k dielectric constant material with a dielectric constant lower than that of silicon oxide to form the second dielectric material layer and serve as the bottom interlayer dielectric layer 2092. (3) Through contact hole lithography, etching, and metal (such as tungsten or copper) filling, form a plurality of contact plugs 210 that penetrate the bottom interlayer dielectric layer 2092 and the contact hole etch stop layer 2091. These contact plugs 210 include contact plugs 210 respectively formed on the top surfaces of the n-type source / drain injection region 205n, the p-type source / drain injection region 205p, and the polysilicon gate 203, and the bottoms of the contact plugs 210 at these positions are in electrical contact with the top surfaces of the cobalt silicide 208 formed on the top surfaces of the n-type source / drain injection region 205n, the p-type source / drain injection region 205p, and the polysilicon gate 203. (4) Deposit a dielectric material layer as the intermetal dielectric layer 2093, and perform lithography, trench etching, and metal (such as copper) filling on the intermetal dielectric layer 2093 to form the bottom metal interconnect line 211, and the bottom metal interconnect line 211 is in electrical contact with the top of each contact plug 210. (5) Adopt a dual damascene process to deposit the corresponding dielectric material layer as the intermetal dielectric layer 2094, and after depositing each layer of the intermetal dielectric layer 2094, perform lithography, via and trench etching, and metal (such as copper) filling on each layer of the intermetal dielectric layer 2094 to form at least one layer of the intermetal dielectric layer 2094 and the metal interconnect structure formed in these intermetal dielectric layers 2094. Each layer of the metal interconnect structure includes a metal interconnect line (metal) 213 and a conductive via (via) 212 that electrically connects the metal interconnect line 213 of this layer and the lower metal interconnect line 213. These metal interconnect structures and the bottom metal interconnect line 211 form a multi-layer metal interconnect structure. In other embodiments of the present invention, a single damascene process can also be used to replace the dual damascene process of this embodiment to form the corresponding metal interconnect structure. (6) Deposit the top dielectric material layer and serve as the passivation layer 2095, and through lithography and etching processes, remove the passivation layer 2095 in the corresponding region to expose a part of the top surface of the top metal interconnect structure and form a solder pad 214.

[0069] It should be noted that at least one process node in the back-end process after step (1) in the above process is completed, the first laser spike annealing in step S15 can be performed to reactivate and crystallize the recrystallization points in the cobalt silicide. That is, from after the deposition of the contact hole etch stop layer 2091 to at least one process node in the process of forming the pad 214, the first laser spike annealing is performed to reactivate and crystallize the recrystallization points in the cobalt silicide. At the same time, the damaged crystal lattice or recrystallization points in the silicon substrate originally masked by the silicide barrier layer are also reactivated, thereby reducing the resistance of the cobalt silicide and the resistance in the silicon substrate originally masked by the silicide barrier layer, which is beneficial to the improvement of device performance. This first laser spike annealing can be performed only once in the entire back-end process, or can be performed multiple times. And the multiple first laser spike annealings can be performed continuously, or can be interspersed between the depositions of different dielectric material layers, so as to obtain a more uniform effect.

[0070] In addition, since in this embodiment, in the back-end process, the first laser spike annealing is added after depositing some or all of the dielectric material layers, the impact on the original process of the back-end process is small, and it also accommodates the demand gap for the formation of cobalt silicide and the heat treatment temperature for the transformation of cobalt silicide from a high-resistance phase to a low-resistance phase in the nMOS region and the pMOS region, avoiding problems such as poor consistency and morphology of cobalt silicide and too high resistance of cobalt silicide caused by this demand gap in the prior art, and finally improving the device resistance and performance. It is found through testing that, under the condition that other process conditions are the same, just adding a first laser spike annealing at a suitable process node in the back-end process relative to the prior art, the DC performance of the device can be improved by about 7%.

[0071] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing cobalt silicide, characterized in that, comprising: providing a silicon substrate and depositing metallic cobalt on the silicon substrate; performing rapid thermal processing at a first temperature to cause the metallic cobalt to react with the silicon substrate to form cobalt silicide; removing unreacted metallic cobalt; performing rapid thermal processing at a second temperature to transform the high-resistance phase of the cobalt silicide into a low-resistance phase, where the second temperature is higher than the first temperature; depositing at least one dielectric material layer, and performing first laser spike annealing at at least one process node after depositing a part or all of the dielectric material layers, to reactivate and crystallize the recrystallization points in the cobalt silicide.

2. The method for manufacturing cobalt silicide according to claim 1, characterized in that, the range of the first temperature is 400°C to 600°C, and / or the range of the second temperature is 700°C to 900°C.

3. The method for manufacturing cobalt silicide according to claim 1 or 2, characterized in that, before depositing metallic cobalt, further comprising: forming a gate; forming source / drain trenches on both sides of the gate; epitaxially growing silicon germanium source / drain in the source / drain trenches.

4. The method for manufacturing cobalt silicide according to claim 1, characterized in that, the dielectric material layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material with a dielectric constant lower than that of silicon oxide.

5. The method for manufacturing cobalt silicide according to claim 1, characterized in that, When multiple layers of the dielectric material layer are deposited, the thickness of each layer of the dielectric material layer is The total thickness of the dielectric material layer deposited on the cobalt silicide is 6. The method for manufacturing cobalt silicide according to any one of claims 1-5, characterized in that, the temperature range of the first laser spike annealing is 1100°C to 1200°C.

7. A method for manufacturing a semiconductor device, characterized in that, comprising: providing a silicon substrate and using the method for manufacturing cobalt silicide according to any one of claims 1-6 to form the cobalt silicide required for the semiconductor device and at least one dielectric material layer stacked on the cobalt silicide.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, before forming the cobalt silicide required for the semiconductor device, further comprising: forming a gate on the silicon substrate and performing source / drain ion implantation on the silicon substrate on both sides of the gate to form source / drain regions; performing spike thermal annealing first and then second laser spike annealing to activate the ions implanted in the source / drain regions; depositing a silicide blocking layer and opening the silicide blocking layer on at least one of the source / drain regions and the gate through photolithography and etching processes to expose the silicon in the region where cobalt silicide is to be formed; wherein, the cobalt silicide is formed on the region of the silicon substrate where cobalt silicide is to be formed.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Deposit a multi-layer dielectric material layer on the cobalt silicide, and the first deposited dielectric material layer is a contact hole etch stop layer, the second deposited dielectric material layer is a bottom interlayer dielectric layer for forming a contact plug, and the dielectric material layers of the intermediate layers deposited thereafter are inter-metal dielectric layers between two adjacent metal interconnect layers in the back-end metal interconnect process, and the topmost deposited dielectric material layer is a passivation layer on the top metal interconnect structure; the manufacturing method of the semiconductor device further includes: After depositing the bottom interlayer dielectric layer, etch the bottom interlayer dielectric layer and the contact hole etch stop layer on the gate and the source / drain regions to form a contact hole exposing the cobalt silicide; Fill a corresponding metal into the contact hole to form a contact plug in electrical contact with the cobalt silicide; Perform a back-end metal interconnect process using a single damascene process or a dual damascene process, deposit a corresponding inter-metal dielectric layer, and form a multi-layer metal interconnect structure having at least two metal interconnect lines in the deposited inter-metal dielectric layer. Any two metal interconnect lines are electrically connected through a conductive via, and the bottom of the bottom metal interconnect line of the multi-layer metal interconnect structure is in electrical contact with the contact plug; Deposit the passivation layer, and through photolithography and etching processes, remove the passivation layer in a corresponding region to expose a part of the top surface of the top metal interconnect structure to form a bonding pad.

10. The manufacturing method of the semiconductor device according to claim 9, wherein, At least one process node during the process from after depositing the contact hole etch stop layer to forming the bonding pad, perform a first laser spike annealing to reactivate and crystallize the recrystallization points in the cobalt silicide.

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