Electronic device

Abstract

The invention discloses an electronic device. The electronic device comprises a transparent core substrate and a first buffer layer. The transparent core substrate includes a through hole, wherein the transparent core substrate includes a first transparent core layer and a second transparent core layer. The first transparent core layer includes first sub-perforations. The second transparent core layer is bonded to the first transparent core layer, and the second transparent core layer includes a second sub-perforation, where the first sub-perforation overlaps the second sub-perforation to form a perforation. The first buffer layer is disposed in at least a portion of the through hole.

Description

Technical Field

[0001] The invention relates to an electronic device, and in particular to an electronic device comprising a transparent core substrate. Background Art

[0002] As the performance of semiconductor chips continues to improve, semiconductor packaging technology is becoming more and more important. The core substrate, carrier or circuit board commonly used in semiconductor packaging will increase in density with the increase in the number of chips to be packaged. However, as the density of the redistribution layer increases or the number of layers increases, the core substrate or carrier is prone to warping during the manufacturing process, making it impossible to carry out subsequent processes or causing product defects. Summary of the invention

[0003] The object of the present invention is to provide an electronic device to reduce warping during the manufacturing process and improve product yield.

[0004] The present invention provides an electronic device, which includes a transparent core substrate and a first buffer layer. The transparent core substrate includes a perforation, wherein the transparent core substrate includes a first transparent core layer and a second transparent core layer. The first transparent core layer includes a first sub-perforation. The second transparent core layer is bonded to the first transparent core layer, and the second transparent core layer includes a second sub-perforation, wherein the first sub-perforation overlaps with the second sub-perforation to form a perforation. The first buffer layer is disposed in at least a portion of the perforation.

[0005] In the electronic device of the present invention, by stacking multiple transparent core layers, the rigidity of the transparent core substrate can be improved, and the difference between the maximum aperture and the minimum aperture of the perforation can be reduced. In this way, the transparent core substrate can be used as a core substrate, so that the warping can be reduced during the formation of the redistribution layer, thereby improving the yield of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 5 FIG. 1 is a schematic cross-sectional view of a method for manufacturing an electronic device according to a first embodiment of the present invention at different steps.

[0007] Figure 6 FIG. 1 is a cross-sectional schematic diagram of an electronic device according to a first variation of the first embodiment of the present invention.

[0008] Figure 7 FIG. 1 is a cross-sectional schematic diagram of an electronic device according to a second variation of the first embodiment of the present invention.

[0009] Figure 8 FIG. 1 is a cross-sectional schematic diagram of an electronic device according to a third variation of the first embodiment of the present invention.

[0010] Fig. 9 FIG. 4 is a cross-sectional schematic diagram of an electronic device according to a fourth variation of the first embodiment of the present invention.

[0011] Fig.10 FIG. 4 is a cross-sectional diagram of an electronic device according to a second embodiment of the present invention.

[0012] Figures 11 to 16 FIG. 1 is a schematic cross-sectional view of a method for manufacturing an electronic device according to a third embodiment of the present invention at different steps.

[0013] Fig.17 Schematic top views of grooves according to some embodiments of the present invention are shown.

[0014] Fig.18 FIG. 4 is a cross-sectional view of an electronic device according to a fourth embodiment of the present invention.

[0015] Fig.19 FIG. 5 is a schematic cross-sectional view of an electronic device according to a fifth embodiment of the present invention.

[0016] Explanation of reference numerals: 1, 1a, 1b, 1c, 1d, 2, 3, 4, 5-electronic device; 12-transparent core substrate; 12a, 12b-transparent core layer; 14, 68, 72, 78e-buffer layer; 14a, 14b-part; 16, 36, 78f, 78g-rewiring layer; 18-intermediary layer; 20, 32, 70-carrier; 22, 34-release layer; 24, 76-alignment mark; 26, 78b-conductive Through hole; 26a, 26b-sub-conductive through hole; 28, 30-track; 38, 40, 82-bonding pad; 42, 44, 60, 62, 74-electronic unit; 46-optical fiber; 48-circuit board; 50-passive component; 52, 54-polymer layer; 56a, 56b-conductive material; 58-transparent substrate; 64, 86-protective layer; 66a, 66b-groove; 66aR-arc edge; 66aS1, 66aS2, 66 aS3-straight edge; 68a-buffer material; 78-circuit board; 78a-core substrate; 78S1-upper surface; 78S2-lower surface; 80-adhesive layer; P1, P2, 78c, 78d, 84-pads; A-pitch; B-radius of curvature; BH1, BH2-blind hole; CL1, CL2, CL3-conductive layer; d-shortest distance; d1, d2-distance; H-hole; IN1, IN2-insulating layer; ND-normal Direction; P1, P2, 78c, 78d, 84-pads; PD-electronic component; R1-overlapping area; S1, S2, S3, S4-surface; T-thickness; TH, TH5, TH6, TH7, TH8-perforations; TH1, TH2, TH3, TH4-sub-perforations; VP-virtual point; W-maximum width; W1-maximum aperture; W2-minimum aperture; W3-aperture; WO-overlapping width; X-direction; θ-angle. DETAILED DESCRIPTION

[0017] The present invention is described in detail in conjunction with specific embodiments and drawings. In order to make the content of the present invention clearer and easier to understand, the drawings of the present invention may be simplified schematic diagrams, and the elements therein may not be drawn to scale. Moreover, the number and size of each element in the drawings are only for illustration and are not intended to limit the scope of the present invention.

[0018] Certain words are used throughout the present specification and the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names, and the present invention does not intend to distinguish between components that have the same function but different names. In the present specification and claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to...".

[0019] The ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify the elements of the claims, do not themselves mean or represent any previous ordinal numbers of the claimed elements, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of the ordinal numbers is only used to clearly distinguish a claimed element with a certain name from another claimed element with the same name.

[0020] In addition, when an element or a film layer is referred to as being connected to another element or another film layer, it should be understood that the element or film layer is directly physically or electrically connected to the other element or film layer, or the two may be physically or electrically connected through other elements or film layers (indirectly). But on the contrary, when an element or a film layer is referred to as being "directly connected to" another element or film layer, it should be understood that the two are not physically or electrically connected through other elements or film layers. The term "connection" may include means of "direct contact" or "indirect contact". In addition, the terms "electrically connected" or "coupled" include any direct and indirect electrical connection means.

[0021] In the present invention, when an element is referred to as being “disposed on” another element, there is no limitation on the process steps or order of forming the element and the other element.

[0022] In the present invention, the terms "about", "substantially", "roughly" or "the same" generally indicate a range within 20%, within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "substantially", "roughly" or "the same", the meanings of "about", "substantially", "roughly" or "the same" may still be implied.

[0023] The term “between value A and value B” is to be interpreted as including value A and value B or a situation containing at least one of value A and value B, and including other values ​​between value A and value B.

[0024] In the present invention, the depth, thickness, length, width and aperture may be measured by an optical microscope (OM), an electron microscope (such as a scanning electron microscope (SEM)), or other methods, but is not limited thereto.

[0025] In the present invention, the definition of roughness judgment can be observed by SEM. On the concave-convex surface, it can be seen that the peaks and valleys of the surface undulations have a distance difference of 0.15 micrometers (μm) to 1 μm. The measurement of roughness judgment can include using SEM, transmission electron microscope (TEM), etc., to observe the surface undulations at the same appropriate magnification, and by taking a sample of unit length (for example, 10 μm) to compare the undulations, which is its roughness range. Here, "appropriate magnification" means that at least one surface can see at least 10 undulating peaks in the field of view of this magnification. Roughness (Rz) or average roughness (Ra).

[0026] It should be understood that the following embodiments can replace, reorganize, or mix features in multiple different embodiments to complete other embodiments without departing from the spirit of the present invention. The features between the embodiments can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present invention belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0028] The electronic device of the present invention may be, for example, a semiconductor device, and may be applicable to any device. The electronic device may, for example, include a display device, a light-emitting device, a sensing device, an antenna device, a touch device, a splicing device, a packaging device or other suitable electronic devices, but is not limited thereto. The electronic device may, for example, be a bendable, stretchable, foldable, rollable and / or flexible electronic device, but is not limited thereto. The display device may, for example, be applied to a notebook computer, a public display, a splicing display, a car display, a touch display, a television, a monitor, a smart phone, a tablet computer, a light source module, a lighting device, a military equipment or, for example, an electronic device applied to the above products, but is not limited thereto. The sensing device may, for example, be a sensing device for detecting capacitance changes, light, heat energy or ultrasound, but is not limited thereto. The sensing device may, for example, include a biosensor, a touch sensor, a fingerprint sensor, other suitable sensors or a combination of sensors of the above types. The display device may include, for example, liquid crystal molecules, light emitting diodes, fluorescent materials, phosphor materials, other suitable display media, or combinations thereof, but is not limited thereto. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (miniLED), a micro-millimeter light emitting diode (micro LED) or a quantum dot light emitting diode (quantum dot, QD, which may be, for example, QLED, QDLED) or other suitable materials or any combination of the above materials, but is not limited thereto. The antenna device may be, for example, a liquid crystal antenna, a variable capacitance diode (varactor diode) antenna or other types of antenna types, but is not limited thereto. The splicing device may include, for example, a spliced ​​display device or a spliced ​​antenna device, but is not limited thereto. In addition, the appearance of the electronic device may be, for example, a rectangular, circular, polygonal, a shape with curved edges, a curved surface (curved) or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, a shelf system, etc. The electronic device may include an electronic unit, wherein the electronic unit may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, etc. It should be noted that the electronic device of the present invention may be various combinations of the above devices, but is not limited thereto.The method for manufacturing the electronic device of the present invention may be applied, for example, to a wafer-level package (WLP) process or a panel-level package (PLP) process, wherein the wafer-level package or panel-level package process may include a chip-first process or a chip-last process, but is not limited thereto. The electronic device of the present invention may be applied, for example, to a power module, a semiconductor packaging device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device, or a splicing device, but is not limited thereto. The electronic device may include a system on a chip (SoC), a system in a package (SiP), an antenna in package (AiP), or various combinations of the above devices, but is not limited thereto.

[0029] Figures 1 to 5 FIG. 1 is a schematic cross-sectional view of a method for manufacturing an electronic device according to a first embodiment of the present invention at different steps, wherein Figure 5 FIG. 1 is a cross-sectional view of an electronic device according to a first embodiment of the present invention. The method for manufacturing an electronic device of the present invention may include the following steps, and the method for manufacturing the present invention is not limited to the following steps, and other steps may be performed before, after or during any of the steps shown. Figures 1 to 5As shown, the manufacturing method of the electronic device 1 may include forming a transparent core substrate 12 and a buffer layer 14 and forming a redistribution layer 16, wherein the transparent core substrate 12 includes at least one through-hole TH, and the buffer layer 14 is disposed in at least a portion of the through-hole TH. The transparent core substrate 12 includes a transparent core layer 12a and a transparent core layer 12b, wherein the transparent core layer 12a includes at least one sub-through-hole TH1, the transparent core layer 12b includes at least one sub-through-hole TH2, and the transparent core layer 12b may be bonded to the transparent core layer 12a so that the sub-through-hole TH1 overlaps with the sub-through-hole TH2 to form the through-hole TH. The redistribution layer 16 is formed on the surface of the transparent core layer 12a away from the transparent core layer 12b. It should be noted that by using the transparent core substrate 12 as the core substrate, the warping can be reduced in the process of forming the redistribution layer 16, thereby improving the yield of manufacturing the electronic device 1. For example, the transparent core layer 12a and the transparent core layer 12b may include a glass substrate, a silicon-containing transparent material, an optical layer, an acrylic plate, or a combination thereof or other transparent materials, and have a certain stiffness and insulation. In other words, the rigidity of the transparent core substrate 12 is greater than the rigidity of the redistribution layer 16, for example, the rigidity of the transparent core substrate 12 is greater than the rigidity of the insulating layer of the redistribution layer 16, so that when the transparent core substrate 12 is used to carry the redistribution layer 16, the warping can be slowed down, but not limited to this. Alternatively, the dielectric loss of the transparent core substrate 12 is less than the dielectric loss of the insulating layer of the redistribution layer 16, so that when the transparent core substrate 12 is used to carry the redistribution layer 16, the electrical characteristics of the electronic device 1 can be improved, but not limited to this.

[0030] Specifically, the manufacturing method of the electronic device 1 of this embodiment is to use Figures 1 to 5 Details are given below. Figure 1 and Figure 2 As shown, the step of forming the transparent core substrate 12 and the buffer layer 14 may include sequentially performing the step of forming the transparent core substrate 12 and the step of forming the buffer layer 14. The step of forming the transparent core substrate 12 in this embodiment may include separately forming a transparent core layer 12a and a transparent core layer 12b and bonding the transparent core layer 12b to the transparent core layer 12a through an intermediate layer 18 to form the transparent core substrate 12.

[0031] In detail, Figure 1 As shown, first, the transparent core layer 12a and the transparent core layer 12b can be separated and formed. Figure 1In the method of forming a transparent core layer 12a, a transparent substrate may be provided, and a patterning process is performed from two surfaces of the transparent substrate opposite to each other to form a transparent core layer 12a having a sub-perforation TH1, wherein the sub-perforation TH1 penetrates the transparent core layer 12a. The transparent substrate may be, for example, glass. In this case, the patterning process may, for example, include a modification process for the position where the sub-perforation TH1 is to be formed and an etching process, a lithography and etching process or other suitable processes are performed on the modified transparent substrate. The modification process may, for example, include irradiating a laser, and the etching process may, for example, include a wet etching process using an etching liquid, so that different parts of the transparent substrate may have a significant etching selectivity ratio to the etching liquid, thereby forming the sub-perforation TH1. In other words, the transparent substrate may allow laser penetration, but is not limited thereto. In some embodiments, the formation of the sub-perforation TH1 may be performed by etching both sides of the transparent substrate sequentially or simultaneously, but is not limited thereto. The "modification" referred to in the present invention is to adjust the bonding strength of the local area of ​​the transparent core layer 12a and the transparent core layer 12b by laser or other suitable process methods, or to weaken the structural strength of the local area. According to some embodiments, the etching solution may include an acidic or alkaline liquid, wherein the acidic etching solution includes hydrofluoric acid, and the alkaline etching solution includes sodium hydroxide, but is not limited thereto. According to some embodiments, the average roughness of the sub-perforation TH1 or the groove 66a may be between 0.1 micrometers (μm) and 1 μm, so as to improve the bonding strength of the subsequent film layer therewith, but is not limited thereto.

[0032] It should be noted that the sub-perforation TH1 can be formed by etching a single surface or by etching from surfaces S1 and S2 of the transparent core layer 12a that are opposite to each other. For example, when the sub-perforation TH1 is formed by etching from surfaces S1 and S2 of the transparent core layer 12a that are opposite to each other, the sub-perforation TH1 can be connected by two holes H, and the holes H can be respectively etched from surfaces S1 and S2. By adjusting the modification process and etching process parameters, the sub-perforation TH1 can have a more uniform aperture, that is, the difference between the maximum aperture W1 and the minimum aperture W2 of the sub-perforation TH1 can be reduced. For example, a ratio of maximum aperture W1 / minimum aperture W2 can be between 1.01 and 2 or between 1.1 and 1.6. Figure 1In the embodiment, the aperture of the hole H adjacent to the surface S1 may become smaller as the distance from the surface S1 increases. Similarly, the aperture of the hole H adjacent to the surface S2 may become smaller as the distance from the surface S2 increases, but is not limited thereto. For example, the acute angle θ between the side wall of the hole H adjacent to the surface S1 and the normal direction ND of the surface S1 may be less than or equal to 20 degrees. Similarly, the acute angle θ between the side wall of the hole H adjacent to the surface S2 and the normal direction ND may be less than or equal to 20 degrees. The angle θ between the hole H adjacent to the surface S1 and the hole H adjacent to the surface S2 may be the same or different from each other. In some embodiments, the hole H may also have a roughly consistent aperture with different depths. In some embodiments, in a cross-sectional view, the sub-perforation TH1 may be an hourglass shape, a rectangle, a trapezoid, an inverted trapezoid, or other suitable shapes.

[0033] like Figure 1 As shown, the thickness T of the transparent core layer 12a of the present embodiment, that is, the depth of the sub-throughhole TH1, may be, for example, greater than or equal to 200 μm and less than or equal to 500 μm. In this case, the maximum aperture W1 of the sub-throughhole TH1 may be, for example, greater than or equal to 30 μm and less than or equal to 60 μm. The minimum aperture W2 of the sub-throughhole TH1 may be, for example, greater than or equal to 15 μm and less than or equal to 30 μm. The size of the sub-throughhole TH1 of the present invention is not limited to the above.

[0034] In some embodiments, since the step of forming the second transparent core layer 12b may be the same as the step of forming the transparent core layer 12a, the sub-perforation TH2 may be the same as or similar to the sub-perforation TH1, or may be formed by connecting two holes H, and the maximum aperture and minimum aperture of the sub-perforation TH2 and the thickness of the transparent core layer 12b may be the same as or similar to the maximum aperture W1 and minimum aperture W2 of the sub-perforation TH1 and the thickness T of the transparent core layer 12a. According to some embodiments, the absolute value of the difference between the maximum aperture of the sub-perforation TH2 and the maximum aperture W1 of the sub-perforation TH1 as a percentage (%) of the maximum aperture W1 of the sub-perforation TH1 may be less than or equal to 15%, the absolute value of the difference between the minimum aperture of the sub-perforation TH2 and the minimum aperture W2 of the sub-perforation TH1 as a percentage (%) of the minimum aperture W2 of the sub-perforation TH1 may be less than or equal to 15%, and the absolute value of the difference between the thickness of the transparent core layer 12b and the thickness T of the transparent core layer 12a as a percentage (%) of the thickness T of the transparent core layer 12a may be less than or equal to 15%. Through the above design, stress imbalance can be avoided or stability in the manufacturing process can be improved, but the present invention is not limited thereto.

[0035] like Figure 1As shown, after forming the transparent core layer 12a and the transparent core layer 12b, the transparent core layer 12a (or the transparent core layer 12b) may be selectively disposed on the carrier 20. In some embodiments, before disposing the transparent core layer 12a, a release layer 22 may be selectively formed on the carrier 20 to facilitate the subsequent separation of the formed transparent core substrate 12 from the carrier 20.

[0036] like Figure 2 As shown, a lamination process may then be performed, wherein the transparent core layer 12b is bonded or bonded to the transparent core layer 12a through the intermediate layer 18 to form a transparent core substrate 12, wherein the sub-perforation TH1 may overlap with the sub-perforation TH2 to form a perforation TH, and the intermediate layer 18 may be disposed between the transparent core layer 12a and the transparent core layer 12b. It should be noted that by stacking the transparent core layer 12b and the transparent core layer 12a, the difference between the maximum aperture and the minimum aperture of the perforation TH may be reduced while improving the rigidity of the transparent core substrate 12. In some embodiments, the number of transparent core layers forming the transparent core substrate 12 may not be limited to two layers, but may be three or more layers. In this case, the aperture consistency of the sub-perforations of each transparent core layer may be improved by reducing the thickness of each transparent core layer, but is not limited thereto. The transparent core substrate 12 may, for example, allow laser penetration.

[0037] In one embodiment, the intermediary layer 18 may be formed on the surface of the transparent core layer 12a or the transparent core layer 12b before the transparent core layer 12b is bonded to the transparent core layer 12a. The lamination process may, for example, include an annealing process, wherein the temperature of the annealing process may, for example, be greater than or equal to 150°C and less than or equal to 600°C. In this case, the intermediary layer 18 can withstand a temperature greater than or equal to 150°C. In some embodiments, the lamination process may selectively include a pressing process for the transparent core layer 12b and the transparent core layer 12a, but is not limited thereto.

[0038] The intermediary layer 18 may include, for example, an inorganic material or an organic material. The inorganic material may include a material that is isotropic with glass, so that after the annealing process, the material of the intermediary layer 18 may be the same as or similar to the material of the transparent core layer 12a and the transparent core layer 12b. The inorganic material may include, for example, silicon dioxide, tetraethoxysilane (TEOS), a silicon-containing material, a glass-like material, or other suitable materials. In this case, the thickness of the intermediary layer 18 may be, for example, greater than or equal to 1 nanometer (nm) and less than or equal to 20nm (i.e., 1nm≤thickness of the intermediary layer 18≤20nm). The organic material may include a material that is heterogeneous with glass, such as an adhesive or other suitable material. In this case, after the annealing process, the material of the intermediary layer 18 may be different from the material of the transparent core layer 12a and the transparent core layer 12b, and the thickness of the intermediary layer 18 may be, for example, greater than or equal to 1μm and less than or equal to 10μm (i.e., 1μm≤thickness of the intermediary layer 18≤10μm). The intermediary layer 18 may be, for example, viscous and transparent. It should be noted that "transparent" in this article may refer to a light transmittance of the element being greater than or equal to 90%, but is not limited thereto. The refractive index of the intermediate layer 18 may be different from the refractive index of the transparent core layer 12a. For example, the refractive index of the intermediate layer 18 is less than the refractive index of the transparent core layer 12a.

[0039] In some embodiments, the intermediate layer 18 may have a dissipation factor (Df), and the dissipation factor is greater than or equal to 0.001 and less than or equal to 0.01 (ie, 0.001≤Df≤0.01) at an operating frequency greater than or equal to 10 MHz, thereby reducing the impact of the intermediate layer 18 on signal transmission.

[0040] In addition, if Figure 1 and Figure 2 As shown, before the transparent core layer 12b is bonded to the transparent core layer 12a, an alignment mark 24 may be provided or formed on the carrier 20 to help align the sub-perforation TH2 of the transparent core layer 12b with the sub-perforation TH1 of the transparent core layer 12a. According to some embodiments, when the carrier 20 is used in the manufacturing process of the electronic device 1, the rigidity of the carrier 20 is greater than that of the transparent core layer 12a or the transparent core layer 12b, so that the carrier 20 can resist deformation, which helps the reliability of the electronic device 1. The carrier 20 may include a wafer, a steel plate, a glass substrate, or any substrate material suitable for carrying objects. According to some embodiments, along the normal direction ND, the thickness of the carrier 20 is greater than at least one of the transparent core layer 12a or the transparent core layer 12b. Along the perpendicular normal direction ND, the width of the carrier 20 is greater than at least one of the transparent core layer 12a or the transparent core layer 12b. Through the above design, it is helpful to improve the stability of the electronic device 1 during the manufacturing process, but it is not limited to this.

[0041] It should be noted that the sub-perforation TH1 and the sub-perforation TH2 may have an overlapping area R1, and the overlapping area R1 includes an overlapping width WO, and the overlapping width WO may be greater than or equal to 0.5 times the maximum aperture W1 of the sub-perforation TH1 and less than or equal to the maximum aperture W1 of the sub-perforation TH1 (that is, 0.5 times the maximum aperture W1 ≤ overlapping width WO ≤ maximum aperture W1). The overlapping area R1 may refer to the area where the portion of the sub-perforation TH1 closest to the sub-perforation TH2 and the portion of the sub-perforation TH2 closest to the sub-perforation TH1 overlap in the normal direction ND of the surface S3 of the transparent core substrate 12. For example, the portion of the sub-perforation TH1 closest to the sub-perforation TH2 may be the portion of the hole H of the sub-perforation TH1 adjacent to the sub-perforation TH2 having the maximum aperture W1, and the portion of the sub-perforation TH2 closest to the sub-perforation TH1 is the portion of the hole H of the sub-perforation TH2 adjacent to the sub-perforation TH1 having the maximum aperture W1, but is not limited to this. Figure 2 By designing the overlap width WO of the sub-throughhole TH1 and the sub-throughhole TH2 to be within the above range, it is helpful to reduce the possibility of disconnection of the conductive via 26 subsequently formed in the throughhole TH, but the invention is not limited thereto.

[0042] like Figure 3 As shown, after forming the transparent core substrate 12, the carrier 20 can be removed through the release layer 22, and the buffer layer 14 can be formed on the transparent core substrate 12, so that the buffer layer 14 can be disposed in at least a portion of the through hole TH. For example, the buffer layer 14 can be formed in the sub-through hole TH1 and the sub-through hole TH2 and on the surface S3 and the surface S4 of the transparent core substrate 12. The method of forming the buffer layer 14 may include a deposition process or other suitable processes. The deposition process may, for example, include coating, evaporation, atomic layer deposition or other physical deposition processes or chemical deposition processes. The material of the buffer layer 14 may include, for example, organic materials or inorganic materials such as polyimide (PI), poly-p-xylylene (also known as Parylene), benzocyclobutene (BCB), epoxy, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, etc.

[0043] exist Figure 3In the embodiment, the buffer layer 14 may cover the sidewalls in the through hole TH and the surface of the transparent core substrate 12 outside the through hole TH, but is not limited thereto. The thickness of the buffer layer 14 may be, for example, greater than or equal to 0.01 μm and less than or equal to 10 μm (i.e., 0.01 μm ≤ the thickness of the buffer layer 14 ≤ 10 μm). For example, when the thickness of the buffer layer 14 gradually becomes thinner from the surface to the surface away from the surface, the buffer layer 14 usually covering the minimum aperture W2 of the through hole TH has the minimum thickness, but is not limited thereto. The ratio of the thickness of the buffer layer 14 to the aperture of the sub-through hole TH1 may be, for example, greater than or equal to 0.02 and less than or equal to 0.2 (i.e., 0.02 ≤ the ratio of the thickness of the buffer layer 14 to the aperture of the sub-through hole TH1 ≤ 0.2), for example, the ratio of the minimum thickness of the buffer layer 14 at the minimum aperture W2 to the minimum aperture W2 of the sub-through hole TH1 may be, for example, greater than or equal to 0.02 and less than or equal to 0.2. The toughness of the buffer layer 14 may be greater than or equal to 0.1 kJ / m2. 2 ) and less than or equal to 100 kJ / m 2 (i.e., 0.1 kJ / m 2 ≤Toughness of buffer layer 14≤100kJ / m 2 ). In the present invention, the toughness of the film layer can be obtained by integrating the area under the stress-strain curve, and the stress-strain curve can be obtained by performing a tensile test on the film layer using a universal testing machine (UTM).

[0044] like Figure 3 As shown, after the buffer layer 14 is formed, a conductive through hole 26 can be formed in the through hole TH. In the present embodiment, forming the conductive through hole 26 can also include forming a trace 28 and a trace 30 on the surface S3 and the surface S4 of the transparent core substrate 12 outside the through hole TH, respectively. In other words, the conductive through hole 26, the trace 28 and the trace 30 can be formed by the same conductive layer CL1 or include the same conductive material, but are not limited thereto. The step of forming the conductive layer CL1 can, for example, include a metallization process, wherein the metallization process can, for example, include evaporation, sputtering, electroplating, chemical plating, deposition or other suitable processes. It should be noted that, since the difference between the maximum aperture and the minimum aperture of the through hole TH can be reduced, the difference between the maximum aperture and the minimum aperture of the conductive through hole 26 formed in the through hole TH can also be reduced, thereby reducing the occurrence of cracks or disconnections caused by stress or external force on the conductive through hole 26. According to some embodiments, the conductive layer CL1 may include a single layer or a composite layer. For example, when the conductive layer CL1 is a composite layer, it may include a first sublayer and a second sublayer, and the first sublayer is arranged between the second sublayer and the transparent core substrate 12. The first sublayer may be, for example, a seed layer, which can enhance the bonding force between the second sublayer and the transparent core substrate 12 or enhance the conductivity of the conductive layer CL1, but is not limited thereto.

[0045] like Figure 4 As shown, after forming the conductive vias 26, the transparent core substrate 12 may be selectively disposed on another carrier 32, with the surface S3 (or surface S4) of the transparent core substrate 12 facing upward, and a redistribution layer 16 may be formed on the surface S3 (or surface S4) of the transparent core substrate 12. In some embodiments, a release layer 34 may be selectively formed on the carrier 20 to facilitate subsequent separation of the transparent core substrate 12 from the carrier 32.

[0046] In the present embodiment, the formation of the redistribution layer 16 is performed after the transparent core substrate 12 and the buffer layer 14 are formed, but not limited thereto. The step of forming the redistribution layer 16 may include providing at least one insulating layer and at least one conductive layer stacked, for example, including processes such as yellow light, etching, surface treatment, laser, electroplating, etc. The surface treatment may include roughening the surface of the insulating layer or the conductive layer to improve its bonding ability. The redistribution layer 16 may be electrically connected to each chip or electronic unit through a bonding pad or other bonding element. The redistribution layer 16 may include at least one conductive layer and at least one insulating layer, or reroute the circuit and / or further increase the circuit fan-out area, or different electronic units may be electrically connected to each other through a redistribution structure. Alternatively, the redistribution layer may be a substrate used as an electrical interface wiring between one connection and another connection. The purpose of the redistribution layer is to expand the connection to a wider spacing or to reroute the connection to another connection with a different spacing. For example, the insulating layer may include polyimide (PI), photosensitive polyimide (PSPI), build-up layer material (ABF), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide nitride (SiOxNy) or other suitable dielectric materials. The conductive layer may include a conductive material, and the conductive material may include, for example, copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), nitride, carbide or other conductive materials or any combination thereof, but is not limited thereto. According to some embodiments, the redistribution layer 16 may include an electronic unit, that is, the electronic unit may be embedded or formed in the redistribution layer 16.

[0047] exist Figure 4 In the embodiment of the present invention, the conductive layer of the redistribution layer 16 may include a portion of the conductive layer CL1 and at least one conductive layer CL2, and Figure 4The insulating layer IN1 is used to illustrate a combination of multiple insulating layers, but the present invention is not limited thereto. Each insulating layer may have at least one through hole, so that the conductive layer CL1 and the conductive layer CL2 are electrically connected in the stacking direction. Figure 4 It is shown that there is no connection between the conductive layer CL1 and the conductive layer CL2, but the conductive layer CL1 can still be electrically connected to the conductive layer CL2 at other positions, so that the redistribution layer 16 achieves the purpose of vertical electrical connection. In addition, the conductive layer CL2 farthest from the transparent core substrate 12 may include a plurality of pads P1 for bonding with an electronic unit, a circuit board or other suitable components. In some embodiments, when the conductive layer CL1 is not disposed outside the through hole TH of the transparent core substrate 12, the redistribution layer 16 may also not include the conductive layer CL1. In some embodiments, the thickness of a single insulating layer of the redistribution layer 16 may be, for example, greater than or equal to 5 microns (μm) and less than or equal to 25 μm (i.e., 5 μm≤thickness of the insulating layer≤25 μm), and the thickness of a single insulating layer of the redistribution layer 16 may be greater than the thickness of the buffer layer 14. According to some embodiments, the conductive layer CL2 may include a single layer or a composite layer. For example, when the conductive layer CL2 is a composite layer, it may include a first sublayer and a second sublayer, and the first sublayer is arranged between the second sublayer and the insulating layer IN1. The first sublayer may be, for example, a seed layer, which can enhance the bonding force between the second sublayer and the insulating layer IN1 or enhance the conductivity of the redistribution layer 16, but is not limited thereto.

[0048] like Figure 5 As shown, after forming the redistribution layer 16, the carrier 32 can be removed, and the transparent core substrate 12 can be turned upside down so that the surface S3 of the transparent core substrate 12 formed with the redistribution layer 16 is placed downward on another carrier (not shown). Then, another redistribution layer 36 is formed on the surface S4 of the transparent core substrate 12 away from the transparent core layer 12b. The method of forming the redistribution layer 36 can be similar to or the same as the method of forming the redistribution layer 16, so it is not described in detail here.

[0049] The redistribution layer 36 may also include at least one insulating layer and at least one conductive layer, and the number of insulating layers and conductive layers may be adjusted to be the same as or different from the number of insulating layers and conductive layers of the redistribution layer 16 according to requirements. Figure 5 In the redistribution layer 36, the conductive layer may include a portion of the conductive layer CL1 and at least one conductive layer CL3, and Figure 5 A single insulating layer IN2 is used to illustrate a combination of multiple insulating layers, but the present invention is not limited thereto. Each insulating layer may have at least one through hole, so that the conductive layer CL1 and the conductive layer CL3 are electrically connected in the stacking direction. Figure 5Although there is no connection between the conductive layer CL1 and the conductive layer CL3, the conductive layer CL1 can still be electrically connected to the conductive layer CL3 at other locations, so that the redistribution layer 36 can achieve the purpose of vertical electrical connection. In some embodiments, the thickness of the single insulating layer of the redistribution layer 16 and / or the redistribution layer 36 can be greater than the thickness of the buffer layer 14. Figure 5 In the embodiment, the conductive layer CL2 of the redistribution layer 36 which is farthest from the transparent core substrate 12 may also include a plurality of pads P2 for connecting with an electronic unit, a circuit board or other suitable components. In some embodiments, when the conductive layer CL1 is not disposed outside the through hole TH of the transparent core substrate 12, the redistribution layer 36 may also not include the conductive layer CL1.

[0050] It should be noted that in the step of forming the redistribution layer 16 and / or the step of forming the redistribution layer 36, the transparent core substrate 12 is subjected to uneven stress due to the different densities of the conductive layers on the surface S3 and the surface S4 of the transparent core substrate 12. Since the transparent core substrate 12 of the present embodiment may have a certain rigidity due to, for example, including glass, the warping may be reduced in the step of forming the redistribution layer 16 and / or in the process of forming the redistribution layer 36, thereby improving the yield of manufacturing the electronic device 1.

[0051] After forming the redistribution layer 36, a bonding pad 38 may be formed on the pad P2 of the redistribution layer 36. Subsequently, the carrier is removed, and a bonding pad 40 is formed on the pad P1 of the redistribution layer 16, thereby forming the electronic device 1. The bonding pad 38 and the bonding pad 40 may, for example, include solder balls, nickel, gold, copper, gallium or other suitable conductive materials, and the bonding pad 38 may be electrically connected to the corresponding bonding pad 40 through the redistribution layer 36, the conductive via 26 and the redistribution layer 16. According to some embodiments, the bonding pad may include a portion of the pad P1 to achieve hybrid bonding. Figure 5 As shown, the upper side of the electronic device 1 can be bonded to other suitable components through the bonding pads 38, and the lower side can be bonded to other suitable components through the bonding pads 40, so that the electronic device 1 can be used as a rewiring substrate, for example, to carry at least one electronic unit or other component and electrically connect it to other circuits, or to electrically connect multiple electronic units to each other. According to some embodiments, along a direction perpendicular to the normal direction ND, the distance d1 between adjacent pads P1 is different from the distance d2 between adjacent pads P2.

[0052] like Figure 5As shown, the electronic device 1 may include at least a transparent core substrate 12 and a buffer layer 14, wherein the transparent core substrate 12 may include a perforation TH, and include a transparent core layer 12a including a sub-perforation TH1 and a transparent core layer 12b including a sub-perforation TH2. The transparent core layer 12b may be bonded to the transparent core layer 12, and the sub-perforation TH1 may overlap with the sub-perforation TH2 to form a perforation TH. The buffer layer 14 may be disposed in at least a portion of the perforation TH. By stacking the transparent core layer 12a and the transparent core layer 12b, the transparent core substrate 12 of the electronic device 1 may have a perforation TH with a certain uniformity of aperture under a certain rigidity. According to some embodiments, the buffer layer 14 may be disposed on the surface of the transparent core substrate 12 and extend into at least a portion of the perforation TH.

[0053] exist Figure 5 In the embodiment, a conductive through hole 26 may be provided in the through hole TH of the transparent core substrate 12, and a redistribution layer 16 and a redistribution layer 36 may be provided on the surface S3 and the surface S4, respectively, so that the transparent core substrate 12 may be provided between the redistribution layer 16 and the redistribution layer 36, and the redistribution layer 16 may be electrically connected to the redistribution layer 36 through the conductive through hole 26. It is worth noting that, since the pad density of the redistribution layer 16 and / or the redistribution layer 36 increases or the line density of the conductive layer of the redistribution layer 16 and the redistribution layer 36 is different from each other, the transparent core substrate 12 located between the redistribution layer 16 and the redistribution layer 36 will be subjected to uneven stress. In particular, when the computing power of the electronic unit to be connected increases, the pad density of the electronic unit will increase, so that the pad density of the redistribution layer 36 (or the redistribution layer 16) needs to be increased. In the electronic device 1 of the present embodiment, the transparent core substrate 12 may have a higher rigidity than the BT resin and the rigidity of the insulating layer of the redistribution layer 16 and the redistribution layer 36, so that the warping of the electronic device 1 during the manufacturing process or when it is further arranged on other components or other components are arranged thereon can be reduced, thereby improving the product yield. In addition, since the aperture uniformity of the through hole TH of the transparent core substrate 12 can be improved through the above-mentioned method for manufacturing the electronic device 1, the conductive through hole 26 arranged in the through hole TH can be reduced from being damaged by external force.

[0054] The electronic device and the manufacturing method thereof are not limited to the above-mentioned embodiments, and may have different embodiments or variant embodiments. To simplify the description, the same reference numerals as those in the first embodiment are used to mark the same elements in different embodiments or variant embodiments of the present invention. To clearly describe different embodiments or variant embodiments, the present invention will focus on the differences between different embodiments or variant embodiments, and will not repeat the repeated parts.

[0055] Please refer to Figure 6, which is a cross-sectional schematic diagram of an electronic device according to a first variation of the first embodiment of the present invention. Figure 6 As shown, the buffer layer 14 of the electronic device 1a of this variation embodiment may not cover the sidewalls of the through hole TH adjacent to the intermediary layer 18. For example, the sidewalls of the hole H of the sub-through hole TH1 adjacent to the sub-through hole TH2 and the sidewalls of the hole H of the sub-through hole TH2 adjacent to the sub-through hole TH1 may not have the buffer layer 14 disposed thereon, so that the buffer layer 14 may include a portion 14a disposed on the transparent core layer 12a and a portion 14b disposed on the transparent core layer 12b, and the portion 14a and the portion 14b may be separated from each other. In some embodiments, Figure 6 The portion 14a and the portion 14b of the buffer layer 14 can be applied to any of the following embodiments. The other parts of the electronic device 1a and the manufacturing method thereof can be the same as Figures 1 to 5 The embodiments of the present invention are described in detail herein.

[0056] Please refer to Figure 7 , which is a cross-sectional schematic diagram of an electronic device according to a second variation of the first embodiment of the present invention. Figure 7 As shown, the sub-perforation TH1 and the sub-perforation TH2 of the electronic device 1b of this variation embodiment may have approximately the same aperture W3. In other words, the sidewall of the sub-perforation TH1 and the sidewall of the sub-perforation TH2 may be parallel to the normal direction ND of the surface S3, so that in a cross-sectional view, the sub-perforation TH1 may be rectangular. In some embodiments, the sub-perforation TH1 and the sub-perforation TH2 may have an overlapping area R1, and the overlapping area R1 includes an overlapping width WO, and the overlapping width WO is greater than or equal to 0.5 times the aperture W3 and less than or equal to the aperture W3 (that is, 0.5 times the aperture W3 ≤ overlapping width WO ≤ aperture W3). The other parts of the electronic device 1b and its manufacturing method may be the same as Figures 1 to 5 Embodiments or Figure 6 In addition, according to some embodiments, the transparent core substrate 12 may have an arc-shaped corner to reduce the risk of cracking of the film layer coated on the transparent core substrate 12, but the present invention is not limited thereto. In some embodiments, Figure 7 The range of the overlapping width WO of the overlapping region R1 and / or the arc-shaped corner of the transparent core substrate 12 may be applicable to any of the above or below embodiments.

[0057] Please refer to Figure 8 , which is a cross-sectional schematic diagram of an electronic device according to a third variation of the first embodiment of the present invention. Figure 8 As shown, the electronic device 1c of this variation embodiment may further include a polymer layer disposed in the through hole TH, wherein the polymer layer may be disposed between the buffer layer 14 and the transparent core substrate 12. Figure 8In the embodiment, the electronic device 1c may include a polymer layer 52 and a polymer layer 54, which are disposed on the sidewalls of the sub-throughhole TH1 and the sidewalls of the sub-throughhole TH2, respectively. The polymer layer 52 and the polymer layer 54 may respectively have a sub-throughhole TH3 and a sub-throughhole TH4 with approximately the same aperture, so as to help to uniformize the aperture of the conductive via 26 formed in the sub-throughhole TH1 and the sub-throughhole TH2, thereby reducing the cracks or damages generated by the conductive via 26 when impacted. In some embodiments, Figure 8 The polymer layer may be applicable to any of the above or below embodiments.

[0058] In some embodiments, the method for manufacturing the electronic device 1c may further include forming a polymer layer 52 in the sub-perforation TH1 between forming the transparent core layer 12a and bonding the transparent core layer 12b to the transparent core layer 12a, and forming a sub-perforation TH3 in the polymer layer 52 through a drilling process. Similarly, the sub-perforation TH4 of the polymer 54 may also be formed between forming the transparent core layer 12b and bonding the transparent core layer 12b to the transparent core layer 12a by the same method as that of forming the sub-perforation TH3, which will not be described in detail herein. The other parts of the electronic device 1c and the other steps of the manufacturing method may be the same as those of Figures 1 to 5 Embodiments or Figure 6 or Figure 7 The present invention has been described in detail herein, and therefore no further details are given here.

[0059] Please refer to Fig. 9 , which is a cross-sectional schematic diagram of an electronic device according to a fourth variation of the first embodiment of the present invention. Fig. 9 As shown, the transparent core substrate 12 of the electronic device 1d of this variation embodiment may further include at least one blind hole disposed in the transparent core layer 12a or the transparent core layer 12b to reduce the stress non-uniformity of the electronic device 1d, thereby reducing the warping of the electronic device 1d. Fig. 9In the embodiment, the transparent core substrate 12 may include a blind hole BH1 and a blind hole BH2. In other words, the blind hole BH1 may be, for example, a sub-perforation of the transparent core layer 12a, and the blind hole BH1 does not overlap with the sub-perforation of the transparent core layer 12b in a top view. Similarly, the blind hole BH2 may be a sub-perforation TH2 of the transparent core layer 12b, and the blind hole BH2 does not overlap with the sub-perforation TH1 of the transparent core layer 12a in a top view. In this case, the electronic device 1e may also include a conductive material 56a and a conductive material 56b, which are respectively disposed in the blind hole BH1 and the blind hole BH2. The top view herein may, for example, view the electronic device along a normal direction ND perpendicular to the surface S3 of the transparent core substrate 12. In some embodiments, the conductive material 56a and the conductive material 56b may be formed by the conductive layer CL1, but are not limited thereto. It is worth noting that, since the blind hole BH1 is disposed in the transparent core layer 12a but not in the transparent core layer 12b, when the portion of the redistribution layer 16 corresponding to the blind hole BH1 generates a greater tensile stress than the portion of the redistribution layer 36 corresponding to the blind hole BH1, the blind hole BH1 and the conductive material 56a can be disposed to alleviate the stress unevenness between the redistribution layer 16 and the redistribution layer 36. Similarly, the blind hole BH2 and the conductive material 56b can also alleviate the stress unevenness between the redistribution layer 16 and the redistribution layer 36. In some embodiments, Fig. 9 The blind holes BH1 and BH2 may be applicable to any of the above or below embodiments.

[0060] In some embodiments, the conductive via 26 and the buffer layer 14 may not fill the through hole TH. In other words, the conductive via 26 may selectively have a through hole TH5 to help relieve the stress generated by the conductive via 26. In this case, the conductive material 56a and the conductive material 56b may also each have a through hole TH6, but the present invention is not limited thereto. The other parts of the electronic device 1d and its manufacturing method may be the same as Figures 1 to 5 Embodiments or Figures 6 to 8 Any variation of the embodiment is not described here. In some embodiments, Fig. 9 The through hole TH5 and the through hole TH6 may be applicable to any of the above or below embodiments.

[0061] Please refer to Fig.10 , which is a cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention. Fig.10As shown, the electronic device 2 of this embodiment is a device structure using the electronic device 1. In the manufacturing method of the electronic device 2 provided in this embodiment, after forming the bonding pad 38 and the bonding pad 40, at least one electronic unit may be arranged on the electronic device 1, for example, an electronic unit 42 and an electronic unit 44 are arranged, so that the electronic unit 42 and the electronic unit 44 can be bonded to the redistribution layer 36 through the bonding pad 38. The functions of the electronic unit 42 and the electronic unit 44 can be adjusted according to the needs. The electronic unit 42 and / or the electronic unit 44 may include a chip, a chip packaging structure, a chip assembly structure or other types of component structures. The chip may have an active surface and a back surface, wherein the surface of the chip with the bonding pad may be, for example, an active surface for bonding with the bonding pad 38. For example, the electronic unit 42 may be, for example, a control chip, and the electronic unit 44 may be, for example, a photonic integrated circuit. The electronic unit 44 may, for example, include an assembly structure of a photoelectric conversion element, an optical waveguide, a signal processing element, a micro-electromechanical element and / or other suitable elements. In this case, the electronic device 2 may further selectively include an optical fiber 46 assembled on the electronic unit 44 , so that the electronic unit 44 can receive the optical signal through the optical fiber 46 .

[0062] In some embodiments, after the electronic unit 42 and the electronic unit 44 are arranged, the side of the electronic device 1 away from the electronic unit 42 can be bonded to the circuit board 48 through the bonding pad 40, thereby forming the electronic device 2. In some embodiments, a passive component 50 can be selectively arranged on the circuit board 48. The passive component 50 can include, for example, a resistor, a capacitor, an inductor, or other suitable components. In some embodiments, Fig.10 The electronic device 1 in the embodiment can be replaced by Figures 6 to 9 The electronic device may be any one of the electronic devices of any of the following embodiments, but is not limited thereto.

[0063] Please refer to Figures 11 to 16 , which is a schematic cross-sectional view of a method for manufacturing an electronic device according to a third embodiment of the present invention at different steps, wherein Fig.16 FIG. 2 is a cross-sectional view of an electronic device according to a third embodiment of the present invention. Figures 11 to 16 As shown, the manufacturing method of the electronic device 3 of this embodiment is Figures 1 to 5 The main difference between the manufacturing method of the embodiment is that the step of forming the redistribution layer 16 in the embodiment is performed before forming the transparent core substrate 12 and the buffer layer 14. The manufacturing method of the electronic device 3 in the embodiment is described in detail as follows. Fig.11As shown, first, a carrier 20 is provided, and a transparent substrate 58 is disposed on the carrier 20. In some embodiments, a release layer may be selectively formed on the carrier 20, but is not limited thereto. Then, a redistribution layer 36 is formed on the transparent substrate 58, and a bonding pad 38 is formed on the redistribution layer 36. The step of forming the redistribution layer 36 may include forming at least one insulating layer and at least one conductive layer. The difference between the redistribution layer 36 of this embodiment and the above-mentioned embodiment is that the conductive layer may include multiple conductive layers CL3 but does not include the conductive layer CL1, but is not limited thereto. Since the other parts of the redistribution layer 36 and the methods of forming the insulating layer and forming the conductive layer may be the same as those in the above-mentioned embodiment, reference may be made to the above text and will not be repeated here. In some embodiments, the layout structure of the redistribution layer 36 may be adjusted according to demand.

[0064] like Fig.11 As shown, after forming the redistribution layer 36, the electronic unit 60 and the electronic unit 62 may be arranged on the redistribution layer 36, wherein the electronic unit 60 and the electronic unit 62 may be bonded to the redistribution layer 36 through the bonding pad 38. Then, a protective layer 64 is formed on the redistribution layer 36. The protective layer 64 may, for example, include a packaging material. For example, the step of forming the protective layer 64 may include performing a molding process. The protective layer 64 may be formed on the carrier 20, the redistribution layer 36, the electronic unit 60, and the electronic unit 62, and extend to the sidewalls of the redistribution layer 36 and the carrier 20, but is not limited thereto. The protective layer 64 may at least surround the electronic unit 60 and the electronic unit 62. In the present invention, an element "surrounding" another element may refer to the element contacting at least one side of the other element in a cross-sectional view, for example, the protective layer 64 may at least contact the side of the electronic unit 60 and the electronic unit 62. In some embodiments, the protection layer 64 on the back side of the electronic unit 60 and the electronic unit 62 away from the redistribution layer 36 may be further removed by a thinning process, but is not limited thereto. In some embodiments, the protection layer 64 may not extend onto the sidewall of the carrier 20 .

[0065] The functions of the electronic unit 60 and the electronic unit 62 can be adjusted according to the requirements. The electronic unit 60 and / or the electronic unit 62 can include, for example, a chip, a chip packaging structure, a chip assembly structure, or other types of component structures. For example, the electronic unit can include a stacked RAM and / or DRAM chip assembly structure, but is not limited thereto. In some embodiments, the electronic unit 60 and the electronic unit 62 can be configured as follows: Fig.10 The electronic unit 42 and / or the electronic unit 44 may be, but are not limited to, these.

[0066] After forming the protective layer 64, the steps of forming the transparent core substrate 12 and the buffer layer 14 may be performed, as described in detail below. Fig.12As shown, after forming the protective layer 64, the carrier 20 is removed, and the transparent substrate 58 is turned upside down so that the surface away from the redistribution layer 36 faces upward. Then, the transparent substrate 58 is subjected to a patterning process to form a transparent core layer 12a having a sub-through hole TH1, wherein the sub-through hole TH1 can expose a portion of the wiring of the redistribution layer 36. The patterning process can be, for example, the same as the above embodiment, and thus will not be described in detail herein.

[0067] Then, a buffer material 68a is formed on the surface of the transparent core layer 12a away from the redistribution layer 36, in the sub-through hole TH1 of the transparent core layer 12a, and on the exposed wiring of the redistribution layer 36. Next, the buffer material 68a on part of the wiring of the redistribution layer 36 is removed to expose the wiring of the redistribution layer 36.

[0068] In some embodiments, the step of forming the transparent core layer 12a may further selectively include forming a groove 66a on the surface of the transparent core layer 12a away from the redistribution layer 36, wherein the groove 66a does not penetrate the transparent core layer 12a. In this case, the step of forming the buffer material 68a may further include forming the buffer material 68a in the sidewall and bottom of the groove 66a. The buffer material 68a may, for example, include the same or similar material as the buffer layer 14 of the above embodiment, and may have the same or similar thickness, and therefore will not be described in detail herein.

[0069] like Fig.13 As shown, then, a sub-conductive through hole 26a may be formed in the sub-through hole TH1, and the buffer material 68a located outside the sub-through hole TH1 and the groove 66a is removed to form a buffer layer 68 in the sub-through hole TH1. Since the step of forming the redistribution layer 36 is performed before forming the transparent core substrate 12, the conductive layer of the redistribution layer 36 may be different from the conductive layer forming the sub-conductive through hole 26a. The step of forming the sub-conductive through hole 26a may, for example, include a metallization process, wherein the metallization process may, for example, include evaporation, sputtering, electroplating, chemical plating, deposition or other suitable processes. The sub-conductive through hole 26a may include a conductive material, such as tantalum, titanium, ruthenium, tungsten, copper or other suitable materials. It should be noted that since the buffer material 68a is provided on the surface of the transparent core layer 12a outside the sub-through hole TH1 during the metallization process, the conductive material formed on the surface of the transparent core layer 12a can reduce the influence of the transparent core layer 12a on the transparent core layer 12a.

[0070] In some embodiments, when a groove 66a is formed on the surface of the transparent core layer 12a, a buffer layer 68 is also formed in the groove 66a. It should be noted that in the step of forming the sub-conductive via 26a, the groove 66a can be shielded by a photoresist layer so that the buffer material 68a in the groove 66a is not removed, thereby forming the buffer layer 68, and no conductive material is disposed in the groove 66a. In one embodiment, the sub-conductive via 26b may be filled with or not filled with the sub-through hole TH1.

[0071] like Fig.14 As shown, another transparent substrate may be disposed on another carrier 70, and the transparent substrate may be patterned to form a transparent core layer 12b having a sub-throughhole TH2. Then, another sub-conductive via 26b and another buffer layer 72 are formed in the sub-throughhole TH2, wherein the buffer layer 72 is located between the sidewall of the sub-throughhole TH2 and the sub-conductive via 26b. The method for forming the buffer layer 72 may be the same as the method for forming the buffer layer 68, and the method for forming the sub-conductive via 26b may be the same as the method for forming the sub-conductive via 26a, and therefore will not be described in detail herein. In one embodiment, the sub-conductive via 26b may fill or not fill the sub-throughhole TH2. In some embodiments, a release layer may be selectively formed on the carrier 70, but is not limited thereto.

[0072] In some embodiments, when the transparent core layer 12a is formed with a groove 66a, the step of forming the transparent core layer 12b may further include forming another groove 66b on the surface of the transparent core layer 12b away from the carrier 70, wherein the groove 66b does not penetrate the transparent core layer 12b. In this case, the step of forming the buffer layer 72 may further form the buffer layer 72 in the sidewall and bottom of the groove 66a. After forming the sub-conductive via 26b, an electronic unit 74 may be selectively disposed in the groove 66b. It should be noted that the steps of forming the transparent core layer 12b, the buffer layer 72, the sub-conductive via 26b and the groove 66b and disposing the electronic unit 74 are the same as those in the embodiment of the present invention. Fig.13 The steps shown do not affect each other, so the steps of forming the transparent core layer 12b, the buffer layer 72, the sub-conductive vias 26b and the grooves 66b and setting the electronic unit 74 can be performed in Fig.13 before or after or with the step Fig.13 steps are performed simultaneously.

[0073] According to design requirements, the top view profiles of the grooves 66a and 66b may be rectangular, polygonal or other suitable shapes, and the top view profile of the through hole TH may be circular, elliptical, rectangular, polygonal or other suitable shapes. Fig.17 , which is a schematic top view of the grooves of some embodiments of the present invention. Fig.17Taking the groove 66a as an example, but not limited thereto. The top view contour of the groove 66b may be similar to or the same as that of the groove 66a, which will not be elaborated here. For example, the top view contour of the groove 66a or the groove 66b includes adjacent straight edges 66aS1 and 66aS2 that are not parallel to each other. The straight edge 66aS1 is nearly parallel to the straight edge 66aS3. And adjacent ones of these straight edges are connected by, for example, an arc edge 66aR, but not limited thereto. In some embodiments, the radius of curvature B of the arc edge 66aR may be between 0.01 millimeter (mm) and 5 millimeters. In some embodiments, as Fig.17 shown, the extension lines of the straight edge 66aS1 and the straight edge 66aS2 of the top view contour of the groove 66a may intersect at a virtual point VP. The virtual point VP is at the shortest distance d from the arc edge 66aR. The groove 66a may have a maximum width W in a direction X. The ratio of the shortest distance d to the maximum width W satisfies the following relationship:

[0074] 0 < d / W ≤ 0.1 (for example, 0 < d / W ≤ 0.06),

[0075] When the shortest distance d is small, the arc edge 66aR of the groove 66a may be closer to a right angle. According to some embodiments, the electronic device may include a plurality of grooves 66a. There may be a spacing A between two adjacent grooves 66a. The ratio of the spacing A to the radius of curvature B (spacing A / radius of curvature B) may be greater than 0.5, or greater than 0.7. Through the above design, the risk of rupture due to too small a pitch between the grooves 66a can be reduced, but not limited thereto. According to some embodiments, the groove 66b may also have the same or a similar structure as the groove 66a, as Fig.17 shown, but not limited thereto.

[0076] In some embodiments, the electronic unit 74 may also be disposed in the groove 66a. In this case, during the step of forming the redistribution layer 36, a circuit for electrically connecting the electronic unit 74 may be formed. And after forming the groove 66a, vias may be further formed in the transparent core layer 12a at the bottom of the groove 66a. And during the step of forming the sub-conductive via 26a, conductive vias are formed in the vias to electrically connect the electronic unit 74 to the redistribution layer 36, but the present invention is not limited thereto.

[0077] As Fig.15As shown, after forming the sub-conductive through hole 26a and forming the sub-conductive through hole 26b (or setting the electronic unit 74), the transparent core layer 12b can be turned upside down, and the transparent core layer 12b can be bonded to the surface of the transparent core layer 12a away from the redistribution layer 36 through the intermediate layer 18 to form the transparent core substrate 12. In addition, the sub-through hole TH2 can overlap the corresponding sub-through hole TH1 in the top view to form the through hole TH, and the sub-conductive through hole 26b can overlap the corresponding sub-conductive through hole 26a in the top view to form the conductive through hole 26.

[0078] In some embodiments, before the transparent core layer 12b is bonded to the transparent core layer 12a, an alignment mark 76 may be formed on the surface of the protective layer 64 adjacent to the transparent core layer 12a to help align the sub-perforation TH2 of the transparent core layer 12b with the sub-perforation TH1 of the transparent core layer 12a. The alignment mark 76 may be, for example, a groove of the protective layer 64 or other suitable mark.

[0079] In some embodiments, when the transparent core layer 12a is formed with a groove 66a, and the transparent core layer 12b is formed with a groove 66b, the step of bonding the transparent core layer 12b to the transparent core layer 12a may further include disposing the groove 66b provided with the electronic unit 74 on the groove 66a, wherein the groove 66b may correspond to the groove 66a in a top view to form a receiving space 66 for accommodating the electronic unit 74 disposed in the groove 66b. For example, the height of the electronic unit 74 may be greater than the depth of the groove 66b and the depth of the groove 66a, and less than the sum of the depth of the groove 66b and the depth of the groove 66a, so as to avoid collision during the lamination step of stacking the transparent core layer 12b and the transparent core layer 12a.

[0080] like Fig.16 As shown, after forming the transparent core substrate 12, a redistribution layer 16 may be formed on the surface S3 of the transparent core substrate 12 away from the redistribution layer 36, and then a bonding pad 40 may be formed on the redistribution layer 16, thereby forming the electronic device 3. Since the step of forming the redistribution layer 16 is performed after forming the sub-conductive via 26b, the conductive layer CL2 of the redistribution layer 16 may be different from the conductive layer forming the sub-conductive via 26b. In some embodiments, before the step of forming the redistribution layer 16, a through hole TH7 may be formed in the portion of the transparent core layer 12b located at the bottom of the groove 66b, so that the conductive layer CL2 of the redistribution layer 16 may extend into the through hole TH7 to be electrically connected to the electronic unit 74.

[0081] like Fig.16As shown, in the electronic device 3 of the present embodiment, the buffer layer 68 and the buffer layer 72 may be respectively disposed in the sub-perforation TH1 and the sub-perforation TH2, and not extend outside the perforation TH, but are not limited thereto. In addition, it is worth mentioning that when the transparent core layer 12a has a groove 66a, and the transparent core layer 12b has a groove 66b facing the groove 66a, the electronic unit 74 may be disposed in the groove 66a and the groove 66b, thereby reducing the signal transmission distance between the electronic unit 74 and the electronic unit 60 and / or the electronic unit 62, and improving the computing performance of the electronic device 3. The electronic unit 74 may adjust its function according to demand. The electronic unit 74 may, for example, include a chip, which may, for example, include active components and / or passive components. In some embodiments, Fig.16 The electronic device 3 may also not include the groove 66a, the groove 66b and the electronic unit 74. The other parts of the electronic device 3 and the manufacturing method thereof may adopt Figures 1 to 10 Any one of the embodiments of the present invention is not described in detail here.

[0082] Please refer to Fig.18 , which is a cross-sectional schematic diagram of an electronic device according to a fourth embodiment of the present invention. Fig.18 As shown, the manufacturing method of the electronic device 4 of this embodiment can also be used to bond the electronic device 3 to the circuit carrier 78 through the bonding pad 40 after the electronic device 3 is formed. In some embodiments, the circuit carrier 78 may include a core substrate 78a and a plurality of conductive through holes 78b, wherein the core substrate 78a may have a plurality of through holes TH8, and the conductive through holes 78b may be respectively arranged in the corresponding through holes TH8 and pass through the core substrate 78a. The circuit carrier 78 may also include a pad 78c and a pad 78d, which are respectively arranged on the upper surface 78S1 and the lower surface 78S2 of the core substrate 78a. In some embodiments, Fig.18 The circuit board 78 can be used Figure 3 A transparent core substrate 12 is formed with a conductive layer CL1. Alternatively, Fig.18 The core substrate 78a may include BT resin or other suitable core substrate materials. In some embodiments, the circuit carrier 78 may further include another buffer layer 78e disposed in the through hole TH8 and located between the conductive through hole 78b and the core substrate 78a, but is not limited thereto. In some embodiments, Fig.18 The circuit board 78 can be replaced by Figures 5 to 9 Any one of the electronic devices.

[0083] In some embodiments, after the electronic device 3 is bonded to the circuit carrier 78, an adhesive layer 80 may be disposed between the electronic device 3 and the circuit carrier 78 to help improve the adhesion between the electronic device 3 and the circuit carrier 78. In some embodiments, the circuit carrier 78 may also be bonded to the circuit board 48 via a bonding pad 82. The adhesive layer 80 may include, for example, bottom filler or other suitable materials.

[0084] Please refer to Fig.19 , which is a cross-sectional schematic diagram of an electronic device according to a fifth embodiment of the present invention. Fig.19 As shown, the electronic device 5 of this embodiment is Fig.18 The main difference between the electronic device 4 and the electronic device 5 is that the electronic device 5 may not include the redistribution layer 16, and the side of the transparent core substrate 12 away from the redistribution layer 36 may be bonded to the circuit carrier 78. Specifically, the electronic device 5 may include a pad 84, which is disposed on the side of the transparent core substrate 12 away from the redistribution layer 36 and is electrically connected to the corresponding conductive via 26, so that the conductive via 26 can be bonded and electrically connected to the circuit carrier 78 through the bonding pad 40. In some embodiments, the pad 84 may be selectively replaced by Fig.18 The redistribution layer 16 is provided.

[0085] exist Fig.19 In the embodiment of the present invention, the circuit board 78 may further include a redistribution layer 78f and a redistribution layer 78g, which are respectively disposed on the upper and lower sides of the core substrate 78a. The redistribution layer 78f can be used to bond with the pad 84 and electrically connect. The redistribution layer 78g can be used to bond with other components. In some embodiments, Fig.19 The circuit board 78 can be used Figures 5 to 9 Any one of the electronic devices of the present invention. Other components include, but are not limited to, circuit boards or other electronic components. According to some embodiments, the circuit board 78 may not include a redistribution layer.

[0086] In some embodiments, the electronic device 5 may further include a protective layer 86 and at least one electronic component PD. The protective layer 86 is disposed on the protective layer 64, the adhesive layer 80 and the circuit carrier 78 to protect the electronic unit 60, the electronic unit 62, the transparent core substrate 12 and the circuit carrier 78. The protective layer 86 may, for example, include packaging materials, but is not limited thereto. The electronic component PD may include resistors, capacitors, inductors, combinations of the above or other surface components. The electronic component PD may be bonded to the circuit carrier 78 via a bonding pad. Specifically, the electronic component PD may be bonded to the redistribution layer 78f via a bonding pad. According to some embodiments, the electronic component PD may not overlap the electronic unit 60 or the electronic unit 62. According to some embodiments, the electronic component PD may selectively overlap at least one of the electronic unit 60 or the electronic unit 62. Other parts of the electronic device 5 and its manufacturing method may be adopted Figures 1 to 18Any one of the embodiments of the present invention is not described in detail here.

[0087] In summary, in the electronic device and the manufacturing method thereof of the present invention, the rigidity of the transparent core substrate can be improved by stacking multiple transparent core layers, and the difference between the maximum aperture and the minimum aperture of the perforation can be reduced. In this way, the transparent core substrate can be used as a core substrate, so that the warping can be reduced in the process of forming the redistribution layer, thereby improving the yield of the electronic device. In addition, since the difference between the maximum aperture and the minimum aperture of the perforation can be reduced, the difference between the maximum aperture and the minimum aperture of the conductive via formed in the perforation can also be reduced, thereby reducing the occurrence of cracks or disconnections caused by stress or external force on the conductive via.

[0088] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An electronic device, characterized in that: include: A transparent core substrate including a through hole, wherein the transparent core substrate comprises: a first transparent core layer, comprising a first sub-perforation; as well as a second transparent core layer bonded to the first transparent core layer, wherein the second transparent core layer comprises a second sub-perforation, wherein the first sub-perforation overlaps with the second sub-perforation to form the perforation; and A first buffer layer is disposed in at least a portion of the through hole.

2. The electronic device according to claim 1, wherein: The first sub-perforation has an aperture, and the first sub-perforation and the second sub-perforation have an overlapping area, the overlapping area includes an overlapping width, and the overlapping width is greater than or equal to 0.5 times the aperture and less than or equal to the aperture.

3. The electronic device according to claim 1, wherein: The invention also includes an intermediate layer, which is disposed between the first transparent core layer and the second transparent core layer, and the thickness of the intermediate layer is greater than or equal to 1 nanometer and less than or equal to 20 nanometers.

4. The electronic device as claimed in claim 3, characterized in that: The interposer has a dissipation factor, and the dissipation factor is greater than or equal to 0.001 and less than or equal to 0.01 when the operating frequency is greater than or equal to 10 MHz.

5. The electronic device as claimed in claim 3, characterized in that: The refractive index of the intermediate layer is different from the refractive index of the first transparent core layer.

6. The electronic device as claimed in claim 1, wherein: It also includes a conductive through hole, a first redistribution layer and a second redistribution layer, and the conductive through hole is arranged in the through hole, wherein the transparent core substrate is arranged between the first redistribution layer and the second redistribution layer, and the first redistribution layer is electrically connected to the second redistribution layer through the conductive through hole.

7. The electronic device as claimed in claim 1, characterized in that: The first buffer layer is disposed in the first sub-through hole, and the electronic device further includes a second buffer layer disposed in the second sub-through hole.

8. The electronic device as claimed in claim 1, wherein: The first transparent core layer has a first groove, and the second transparent core layer has a second groove facing the first groove, wherein the electronic device further includes an electronic unit disposed in the first groove and the second groove.

9. The electronic device as claimed in claim 1, wherein: The invention also includes a polymer layer disposed in the through hole, wherein the polymer layer is disposed between the first buffer layer and the transparent core substrate.

10. The electronic device according to claim 1, wherein: The first transparent core layer and the second transparent core layer include glass substrates.

Images