Semiconductor device and doherty amplifier circuit

Abstract

The invention provides a semiconductor device and a Doherty amplifier circuit. The semiconductor device includes: a package (30) including a base and an output lead; a first semiconductor chip (40a) including a main amplifier that amplifies the first signal and a first output pad that outputs the amplified first signal; a second semiconductor chip (40b) including a first peak amplifier that amplifies a second signal and a second output pad that outputs the amplified second signal; a third semiconductor chip (40c) including a second peak amplifier that amplifies a third signal and a third output pad that outputs the amplified third signal; the first end of the first impedance converter is electrically connected to the first output bonding pad and the output lead, and the second end of the first impedance converter is electrically connected to the second output bonding pad and the third output bonding pad; a first matching circuit that matches the impedance of the first output pad and the impedance of the first terminal with each other; and a second matching circuit matching the impedance of the second output pad and the impedance of the second terminal with each other.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a Doherty amplifier circuit. Background Art

[0002] There is known an N-way (N is 3 or more) Doherty amplifier circuit that uses a main amplifier and two or more peak amplifiers (for example, Patent Documents 1 and 2). In the N-way Doherty amplifier circuit, there are provided an impedance converter that electrically connects the output terminal of the main amplifier to the output terminal of the first peak amplifier and an impedance converter that electrically connects the output terminal of the main amplifier to the output terminal of the second peak amplifier.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: U.S. Patent No. 8,022,760 Specification

[0006] Patent Document 2: U.S. Patent No. 10,601,375 Specification

[0007] However, it is difficult to implement a matching circuit that matches the impedance between the main amplifier and the impedance converter and a matching circuit that matches the impedance between the first peak amplifier and the impedance converter. Summary of the Invention

[0008] The present disclosure has been made in view of the above problems, and an object thereof is to implement a matching circuit for an N-way Doherty amplifier circuit.

[0009] One embodiment of the present disclosure is a semiconductor device including: a package including a base and output leads; a first semiconductor chip mounted on the base, including a main amplifier that amplifies a first signal obtained by distributing an input signal and a first output pad that outputs the amplified first signal; a second semiconductor chip mounted on the base, including a first peak amplifier that amplifies a second signal obtained by distributing the input signal and a second output pad that outputs the amplified second signal; a third semiconductor chip mounted on the base, including a second peak amplifier that amplifies a third signal obtained by distributing the input signal and a third output pad that outputs the amplified third signal; a first impedance converter mounted on the base, having a first end electrically connected to the first output pad and the output leads and a second end electrically connected to the second output pad and the third output pad; a first matching circuit mounted on the base, matching the impedance between the first output pad and the first end; and a second matching circuit mounted on the base, matching the impedance between the second output pad and the second end.

[0010] Advantages of the Invention

[0011] According to the present disclosure, a matching circuit for an N-way Doherty amplifier circuit can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a block diagram of the Doherty amplifier circuit of Embodiment 1.

[0013] Figure 2 It is a graph showing the drain efficiency corresponding to the input power of each amplifier in Embodiment 1.

[0014] Figure 3 It is a circuit diagram of the Doherty amplifier circuit of Embodiment 1.

[0015] Figure 4 It is a circuit diagram of the subsequent stage of the transistor in Embodiment 1.

[0016] Figure 5 It is a top view of the semiconductor device in Embodiment 1.

[0017] Figure 6 It is Figure 5 A - A cross-sectional view.

[0018] Figure 7 It is a top view of a part of the semiconductor device in Embodiment 1.

[0019] Figure 8 It is Figure 7 The equivalent circuit diagram.

[0020] Figure 9 It is a top view of a part of the semiconductor device in Comparative Example 1.

[0021] Figure 10 It is Figure 9 The equivalent circuit diagram.

[0022] Figure 11 It is a top view of a part of the semiconductor device in Comparative Example 2.

[0023] Figure 12 It is Figure 11 The equivalent circuit diagram.

[0024] Figure 13 It is a top view of a part of the semiconductor device in Comparative Example 3.

[0025] Figure 14 It is Figure 13 The equivalent circuit diagram.

[0026] Figure 15 It is a top view of the circuit board in Comparative Example 1.

[0027] Figure 16It is a top view of the circuit board of Example 1.

[0028] Figure 17 It is a top view of a semiconductor device showing another example of the impedance converter of Example 1.

[0029] Figure 18 It is a circuit diagram showing another example of the impedance converter of Example 1.

[0030] Figure 19 It is a top view of another example 1 of the matching circuit of Example 1.

[0031] Figure 20 It is Figure 19 the equivalent circuit diagram of.

[0032] Figure 21 It is a top view of another example 2 of the matching circuit of Example 1.

[0033] Figure 22 It is Figure 21 the equivalent circuit diagram of.

[0034] Figure 23 It is a top view of another example 3 of the matching circuit of Example 1.

[0035] Figure 24 It is Figure 23 the equivalent circuit diagram of.

[0036] Figure 25 It is a top view of another example 4 of the matching circuit of Example 1.

[0037] Figure 26 It is Figure 25 the equivalent circuit diagram of.

[0038] Explanation of reference numerals

[0039] 10a: Main amplifier; 10b, 10c: Peak amplifiers; 12a, 12b, 12c, 14a, 14b, 14c: Matching circuits; 15a, 15b, 15c: Paths; 16: Divider; 18: Combiner; 20, 21, 25a, 25b, 25c: Impedance transformers; 20a, 20b, 21a, 21b: Terminals; 23, 24: Phase adjusters; 30: Package; 31: Base; 32: Housing; 34a, 34b, 34c, 35: Leads; 36: Cover; 39: Circuit board; 40a, 40b, 40c: Semiconductor chips; 41: Semiconductor substrate; 42, 43: Bond pads; 44, 48, 52, 53, 56, 57, 63, 63a, 63b, 63c, 67, 68: Electrodes; 45, 60: Circuit components; 46: Dielectric substrate; 47, 58a, 58b, 58c, 58d, 58e, 58f, 58g, 62a, 62b: Circuit patterns; 50, 50a, 50b: High-dielectric components; 51: High-dielectric substrate; 55a, 55b, 55c, 55d, 65: Capacitive components; 71, 72, 73, 73a, 74, 75a, 75b, 75c, 76, 77a, 77c, 77d, 78a, 78b, 79, 79a, 79b, 79c: Bonding wires; 80, 81: Directions; 100: Doherty amplifier circuit; 102, 104: Semiconductor devices. Detailed implementation manners

[0040] [Description of the embodiments of the present disclosure]

[0041] First, the content of the embodiments of the present disclosure will be listed and described.

[0042] (1) An embodiment of the present disclosure is a semiconductor device, comprising: a package having a base and output leads; a first semiconductor chip mounted on the base, having a main amplifier that amplifies a first signal obtained by distributing an input signal and a first output pad that outputs the amplified first signal; a second semiconductor chip mounted on the base, having a first peak amplifier that amplifies a second signal obtained by distributing the input signal and a second output pad that outputs the amplified second signal; a third semiconductor chip mounted on the base, having a second peak amplifier that amplifies a third signal obtained by distributing the input signal and a third output pad that outputs the amplified third signal; a first impedance converter mounted on the base, with its first end electrically connected to the first output pad and the output lead, and its second end electrically connected to the second output pad and the third output pad; a first matching circuit mounted on the base to match the impedance between the first output pad and the first end; and a second matching circuit mounted on the base to match the impedance between the second output pad and the second end. Thus, a first matching circuit and a second matching circuit for an N-way Doherty amplifier circuit with a low characteristic impedance can be realized.

[0043] (2) In the above (1), it may also comprise: a second impedance converter mounted on the base, with its third end electrically connected to the second end of the first impedance converter and its fourth end electrically connected to the third output pad; and a third matching circuit to match the impedance between the third output pad and the fourth end. Thus, a third matching circuit and a second matching circuit with a low characteristic impedance can be realized.

[0044] (3) In the above (1) or (2), it may be that the first end is electrically connected to the first output pad via a first bonding wire, and the first end is electrically connected to the output lead via a second bonding wire. Thus, the first bonding wire can be used as part of the first matching circuit.

[0045] (4) In the above (3), it may be that the second end is electrically connected to the second output pad via a third bonding wire. Thus, the third bonding wire can be used as part of the second matching circuit.

[0046] (5) In the above (2), it may be that the first end is electrically connected to the first output pad via a first bonding wire, the second end is electrically connected to the output lead via a second bonding wire, the second end and the third end are electrically connected to the second output pad via a third bonding wire, and the fourth end is electrically connected to the third output pad via a fourth bonding wire. Thus, the first bonding wire, the third bonding wire, and the fourth bonding wire can be used as parts of the first matching circuit, the second matching circuit, and the third matching circuit, respectively.

[0047] (6) In any one of the above (1) to (5), it may also be provided with a circuit component, the circuit component including: a dielectric substrate mounted on the base; and a circuit pattern provided on the dielectric substrate, and the first impedance converter includes the circuit pattern. Thus, the characteristic impedance and electrical length of the first impedance converter can be achieved with high precision.

[0048] (7) In any one of the above (1) to (5), it may also be provided with: a first capacitor mounted on the base, the first end of which is electrically connected to the base; a second capacitor mounted on the base, the first end of which is electrically connected to the base; and a fifth bonding wire for electrically connecting the second end of the first capacitor and the second end of the second capacitor, and the first impedance converter includes the first capacitor, the second capacitor, and the fifth bonding wire. Thus, the first impedance converter can be formed.

[0049] (8) In any one of the above (1) to (7), it may also be that the first impedance converter shifts the phase of the center frequency of the operating band by 90° between the first end and the second end. Thus, the first impedance converter can transform the impedance on the real axis of the Smith chart into an impedance on the real axis.

[0050] (9) In the above (8), it may also be that the first matching circuit shifts the phase of the center frequency by 90° between the signal source of the main amplifier and the first end, and the second matching circuit shifts the phase of the center frequency by 90° between the signal source of the first peak amplifier and the second end. Thus, the impedance converter including the first matching circuit and the second matching circuit can transform the impedance on the real axis of the Smith chart into a different impedance on the real axis.

[0051] (10) In the above (2) or (5), it may also be that the first impedance converter shifts the phase of the center frequency of the operating band by 90° between the first end and the second end, the second impedance converter shifts the phase of the center frequency of the operating band by 90° between the third end and the fourth end, the first matching circuit shifts the phase of the center frequency by 90° between the signal source of the main amplifier and the first end, the second matching circuit shifts the phase of the center frequency by 90° between the signal source of the first peak amplifier and the second end and the third end, and the third matching circuit shifts the phase of the center frequency by 90° between the signal source of the second peak amplifier and the fourth end. Thus, the impedance converter including the first impedance converter, the second impedance converter, the first matching circuit, and the second matching circuit can transform the impedance on the real axis of the Smith chart into an impedance on the real axis.

[0052] (11) In any one of the above (1) to (10), it is also possible that the input power for turning on the first peak amplifier is greater than the input power for turning on the main amplifier, and the input power for turning on the second peak amplifier is greater than the input power for turning on the first peak amplifier. Thus, a Doherty amplifier circuit can be realized.

[0053] (12) In any one of the above (1) to (11), it is also possible that at the first end, the angle formed by the flow direction of the amplified first signal and the flow direction of the amplified second signal is 70° or more and 110° or less. Thus, miniaturization can be achieved.

[0054] (13) One embodiment of the present disclosure is a Doherty amplifier circuit, comprising: the semiconductor device according to any one of the above (1) to (12); and a distributor that distributes the input signal into the first signal, the second signal, and the third signal. Thus, a Doherty amplifier circuit can be realized.

[0055] [Details of the Embodiment of the Present Disclosure]

[0056] Hereinafter, with reference to the drawings, specific examples of the semiconductor device and the Doherty amplifier circuit according to the embodiment of the present disclosure will be described. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0057] [Example 1]

[0058] As a Doherty amplifier circuit, a high-output high-frequency amplifier circuit for a mobile communication base station will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. Figure 1 is a block diagram of the Doherty amplifier circuit of Example 1. Figure 1 The illustration of the bias circuit for supplying bias voltages to the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c is omitted.

[0059] As shown in Figure 1 , in the Doherty amplifier circuit 100, three paths 15a to 15c are provided in parallel between the distributor 16 and the combiner 18. The high-frequency signal is input as an input signal Sin to the input terminal Tin. The distributor 16 distributes the input signal Sin input to the input terminal Tin into a signal S1 (first signal), a signal S2 (second signal), and a signal S3 (third signal). The distributor 16 is, for example, a Wilkinson-type distributor. Thus, the Doherty amplifier circuit 100 is a three-way amplifier circuit. It can also be an N-way Doherty amplifier circuit having N paths 15a to 15c with three or more paths.

[0060] Signals S1 to S3 pass through paths 15a to 15c respectively. Path 15a includes: a phase adjuster 23, a matching circuit 12a, a main amplifier 10a, and a matching circuit 14a (first matching circuit). Path 15b includes: a phase adjuster 24, a matching circuit 12b (second matching circuit), a peak amplifier 10b, and a matching circuit 14b. Path 15c includes: a matching circuit 12c (third matching circuit), a peak amplifier 10c, and a matching circuit 14c.

[0061] The phase adjuster 23 and the phase adjuster 24 adjust the phases between paths 15a to 15c. The matching circuits 12a to 12c match the impedances when looking from the distributor 16 to the matching circuits 12a to 12c respectively with the impedances when looking from the matching circuits 12a to 12c to the main amplifier 10a, the peak amplifier 10b (first peak amplifier), and 10c (second peak amplifier) respectively.

[0062] The main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c amplify signals S1 to S3 respectively, and output the amplified signals S4 to S6 respectively. The matching circuits 14a to 14c match the impedances when looking from the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c to the matching circuits 14a to 14c respectively with the impedances when looking from the matching circuits 14a to 14c to the nodes N1 to N3 respectively.

[0063] The synthesizer 18 includes impedance transformers 20 to 22. An impedance transformer 20 (first impedance transformer) is connected between node N1 and node N2. An impedance transformer 21 (second impedance transformer) is connected between node N2 and node N3. An impedance transformer 22 is connected between node N1 and the output terminal Tout. The synthesizer 18 synthesizes signals S4 to S6, and outputs the synthesized signal as the output signal Sout to the output terminal Tout.

[0064] The main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c are, for example, FETs (Field Effect Transistor), such as GaN HEMTs (Gallium Nitride High Electron Mobility Transistor) or LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0065] Figure 2 It is a diagram showing the drain efficiency corresponding to the input power of each amplifier in Embodiment 1. AsFigure 2 As shown, when the input power Pin increases, the main amplifier 10a starts to operate. At the power P1 where the drain efficiency of the main amplifier 10a is maximized, the peak amplifiers 10b and 10c do not operate. When the input power Pin is greater than the power P1, not only does the main amplifier 10a operate, but the peak amplifier 10b also starts to operate. At the power P2 where the drain efficiency of the peak amplifier 10b is maximized, the peak amplifier 10c does not operate. When the input power Pin is greater than the power P2, not only do the main amplifier 10a and the peak amplifier 10b operate, but the peak amplifier 10c also starts to operate. Then, at the power P3, the drain efficiency of the peak amplifier 10c is maximized. Thus, the input power at which the peak amplifier 10b conducts is greater than the input power at which the main amplifier 10a conducts, and the input power at which the peak amplifier 10c conducts is greater than the input power at which the peak amplifier 10b conducts. The main amplifier 10a is, for example, a class A or AB amplifier, and the peak amplifiers 10b and 10c are, for example, class C amplifiers.

[0066] The conditions for causing the Doherty amplifier circuit 100 to operate as Figure 2 shown are as follows.

[0067] Condition 1: At the power P1, the output power of the main amplifier 10a saturates, and the peak amplifiers 10b and 10c do not operate.

[0068] Condition 2: At the power P2, the output powers of the main amplifier 10a and the peak amplifier 10b saturate, and the peak amplifier 10c does not operate.

[0069] Condition 3: At the power P3, the output powers of the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c saturate.

[0070] Condition 4: The main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c do not become over-saturated.

[0071] Condition 5: When the peak amplifiers 10b and 10c do not operate, the impedance seen from the node N1 looking at the peak amplifiers 10b and 10c is the open-circuit impedance, and when the peak amplifier 10c does not operate, the impedance seen from the node N2 looking at the peak amplifier 10c is the open-circuit impedance.

[0072] [Explanation of Circuit Structure]

[0073] An explanation will be given of the circuit structure that satisfies the above Conditions 1 to 5. Figure 3 is a circuit diagram of the Doherty amplifier circuit of Embodiment 1. The illustration of the matching circuits 12a to 12c is omitted.

[0074] As Figure 3As shown, the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c are transistors Q1 to Q3. The sources S of the transistors Q1 to Q3 are grounded. The signals S1 to S3 are respectively input to the gates G of the transistors Q1 to Q3. The signals S4 to S6 are respectively output from the drains D of the transistors Q1 to Q3. Impedance converters 25a to 25c are respectively connected between the drains D of the transistors Q1 to Q3 and the nodes N1 to N3.

[0075] Figure 4 is the circuit diagram of the subsequent stage of the transistor in Embodiment 1. As Figure 4 shown, Figure 3 the transistors Q1 to Q3 in do not include the drain-source capacitance Cds, the drain inductance Ld, and the drain resistance Rd. At the subsequent stage of the signal source Id, the drain-source capacitance Cds is shunt-connected, and the drain inductance Ld and the drain resistance Rd are series-connected. The drain resistance Rd is connected to the pads 43 of the semiconductor chips 40a to 40c described later. Matching circuits 14a to 14c are respectively provided between the pads 43 and the nodes N1 to N3. Figure 3 The impedance converters 25a to 25c of include: the drain-source capacitance Cds, the drain inductance Ld, the drain resistance Rd, and the respective matching circuits 14a to 14c.

[0076] When the transistors Q1 to Q3 are at the saturation power, the load impedance Zopt (referred to as output matching) at which the output power reaches the maximum and the load impedance Zmod (referred to as efficiency matching) at which the efficiency reaches the maximum are approximately located on the real axis in the Smith chart. That is, the reactance components of the load impedance Zopt and the load impedance Zmod are approximately 0. For example, if it is assumed that the center frequency of the operating frequency band is 2 GHz, the maximum output power of each of the transistors Q1 to Q3 is 200 W, and the maximum output power of the output signal Sout is 600 W for a Doherty amplifier circuit, then Zopt is about 2 Ω, and Zmod is Zopt × M (M is about 1 to 5).

[0077] The impedance transformers 20 to 22 and 25a to 25c shift the phase by 90° at the center frequency of the operating frequency band. Thereby, the impedance located on the approximate real axis of the Smith chart is transformed into an impedance at a different position on the approximate real axis of the Smith chart. The characteristic impedances of the impedance transformers 20 to 22 and 25a to 25c are set according to the impedances before and after the transformation. For example, in a two-way Doherty amplifier circuit, it is only necessary to shift the phase by 180° between the impedance transformer 25b and the impedance transformer 20. Since there is no node to which the peak amplifier 10c is to be connected, the impedance transformer 25b and the impedance transformer 20 may not be divided. On the other hand, in an N (N is 3 or more)-way Doherty amplifier circuit, there is a node N2 that is electrically connected to the peak amplifier 10c between the impedance transformer 20 and the impedance transformer 25b. Therefore, the impedance transformer 25b and the impedance transformer 20 that shift the phase by 90° respectively are divided, and the node N2 is provided between the impedance transformer 25b and the impedance transformer 20.

[0078] As Figure 3 shown, the impedance transformers 25a to 25c transform the impedances Z1a to Z1c when looking at the impedance transformers 25a to 25c from the signal sources Id of the transistors Q1 to Q3 into the impedances Z2a to Z2c when looking at the nodes N1 to N3 from the impedance transformers 25a to 25c, respectively. The impedance transformer 20 transforms the impedance Z3b when looking at the impedance transformer 20 from the node N2 into the impedance Z3a when looking at the node N1 from the impedance transformer 20. The impedance transformer 21 transforms the impedance Z2c when looking at the impedance transformer 21 from the node N3 into the impedance Z3c when looking at the node N2 from the impedance transformer 21. The impedance transformer 22 transforms the impedance Z4 when looking at the impedance transformer 22 from the node N1 into the load impedance Z0 when looking at the output terminal Tout from the impedance transformer 22.

[0079] For example, the case where the saturation powers of the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c are the same will be described. At the power P3, the output powers of the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c are set to the maximum power Pmax. At this time, the following matters are assumed. At the power P2, the output power of the main amplifier 10a is Pmax / 2, and the output power of the peak amplifier 10b is Pmax / 4. At the power P1, the output power of the main amplifier 10a is Pmax / 3. In addition to the above, the input power Pin and the output powers of the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c at each of the powers P1 to P3 may be set as appropriate. It is assumed that the load impedance Z0 is 50 Ω and the impedance Z4 is 16.7 Ω. The load impedance Z0 and the impedance Z4 may be set as appropriate. It is assumed that the structures of the matching circuits 14a to 14c are the same. The structures of the matching circuits 14a to 14c may be set as appropriate.

[0080] At power P1, the impedance when looking at impedance converter 20 from node N1 is almost infinite. Therefore, impedance Z2a is the same as impedance Z4, which is 16.7 Ω. Impedance converter 25a converts impedance Z2a of 16.7 Ω into impedance Z1a of Zmod. Thus, main amplifier 10a operates in an efficiency-matched manner.

[0081] At power P2, impedance Z4 of 16.7 Ω is divided into impedance Z2a of 25 Ω and impedance Z3a of 50 Ω. Impedance converter 20 converts impedance Z3a of 50 Ω into impedance Z3b of 12.5 Ω. The impedance when looking at impedance converter 21 from node N2 is almost infinite. Therefore, impedance Z2b is the same as impedance Z3b, which is 12.5 Ω. At power P2, the powers of main amplifier 10a and peak amplifier 10b are Pmax / 2 and Pmax / 4 respectively. Therefore, since main amplifier 10a and peak amplifier 10b are set to output matching, impedance Z1a and impedance Z1b are 2×Zopt and 4×Zopt respectively. Impedance converter 25a converts impedance Z2a of 25 Ω into impedance Z1a of 2×Zopt. Impedance converter 25b converts impedance Z2b of 12.5 Ω into impedance Z1b of 4×Zopt. Thus, main amplifier 10a and peak amplifier 10b operate in an output-matched manner.

[0082] At power P3, impedance Z4 of 16.7 Ω is divided into impedance Z2a of 50 Ω and impedance Z3a of 25 Ω. The characteristic impedance of impedance converter 20 is 25 Ω, and impedance converter 20 converts impedance Z3a of 25 Ω into impedance Z3b of 25 Ω. Impedance Z3b of 25 Ω is divided into impedance Z2b of 50 Ω and impedance Z2c of 50 Ω. The characteristic impedance of impedance converter 21 is 50 Ω, and impedance converter 21 converts impedance Z3c of 50 Ω into impedance Z2c of 50 Ω. In this way, impedances Z2a to Z2c are all 50 Ω. Impedance converters 25a to 25c respectively convert impedances Z2a to Z2c of 50 Ω so that impedances Z1a to Z1c are all Zopt. Thus, main amplifier 10a, peak amplifier 10b, and peak amplifier 10c operate in an output-matched manner.

[0083] As described above, the Doherty amplifier circuit 100 can be made to operate as shown by using impedance converters 20 to 22 and 25a to 25c. Figure 2 Phase adjuster 23 and phase adjuster 24 make the phases of signals S4 to S6 at node N1 consistent. Phase adjuster 23, for example, shifts the phase of signal S1 by approximately 180°. Phase adjuster 24 shifts the phase of signal S2 by approximately 90°.

[0084] A description is given of the semiconductor device used in Example 1. In Figure 1 the main amplifier 10a, the peak amplifier 10b, the peak amplifier 10c, the matching circuits 12a to 12c, the matching circuits 14a to 14c, the impedance converter 20, and the impedance converter 21 are provided in the semiconductor device 100.

[0085] When the input power Pin is the powers P1, P2, and P3, for broadbanding evenly, the characteristic impedance of the impedance converters 25a to 25c is about √(Zopt × Zmod). When Zopt is about 2 Ω, the characteristic impedance of the impedance converters 25a to 25c is 2 Ω to 4 Ω. In the matching circuits 14a to 14c, the remaining part with the drain-source capacitance Cds removed from the impedance converters 25a to 25c is achieved. For example, the matching circuits 14a to 14c are lines with a characteristic impedance of 2 Ω to 4 Ω and a phase of about 30° to 50°. Figure 4 The remaining part with the drain-source capacitance Cds removed from the impedance converters 25a to 25c is achieved. For example, the matching circuits 14a to 14c are lines with a characteristic impedance of 2 Ω to 4 Ω and a phase of about 30° to 50°.

[0086] [Description of the semiconductor device]

[0087] A description is given of the semiconductor device that realizes such matching circuits 14a to 14c. Figure 5 is a top view of the semiconductor device of Example 1. Figure 6 is Figure 5 the A-A cross-sectional view of. In Figure 5 the cover 36 is not shown. The thickness direction of the base 31 is set as the Z direction, the direction from the lead 34a to the lead 35 is set as the X direction, and the direction orthogonal to the X direction and the Z direction is set as the Y direction.

[0088] As Figure 5 and Figure 6 shown, in the semiconductor device 102 of Example 1, the package 30 has at least a conductive base 31, a frame 32, and a cover 36 on the upper surface. The base 31 is, for example, a conductive substrate such as a laminated substrate of copper and molybdenum. The base 31 is provided with a reference potential such as a ground potential. The frame 32 and the cover 36 are dielectric layers made of, for example, a resin such as glass epoxy or ceramic. On the base 31, semiconductor chips 40a to 40c, a circuit component 45, a high dielectric component 50, a circuit component 60, and a capacitive component 65 are mounted. The frame 32 is provided on the base 31 so as to surround the semiconductor chips 40a to 40c, the circuit component 45, the high dielectric component 50, the circuit component 60, and the capacitive component 65. The cover 36 is joined to the upper surface of the frame 32 by an insulating adhesive (not shown) such as resin. The frame 32 and the cover 36 seal the semiconductor chips 40a to 40c in the void.

[0089] The planar shape of the housing 32 is substantially rectangular. On one side in the X direction of the housing 32, input leads 34a to 34c are provided. On the + side in the X direction of the housing 32, an output lead 35 is provided. The leads 34a to 34c and 35 are, for example, metal layers or metal plates such as copper. Signals S1 to S3 are respectively input to the leads 34a to 34c, and an output signal Sout is output from the lead 35.

[0090] Corresponding to the path 15a, leads 34a, a capacitive component 65, a semiconductor chip 40a (first semiconductor chip), a circuit component 45, and a high-dielectric component 50 are arranged in the X direction. Corresponding to the path 15b, leads 34b, a capacitive component 65, a semiconductor chip 40b (second semiconductor chip), a circuit component 45, and a high-dielectric component 50 are arranged in the X direction. Corresponding to the path 15c, leads 34c, a capacitive component 65, a semiconductor chip 40c (third semiconductor chip), a circuit component 45, and a high-dielectric component 50 are arranged in the X direction. The circuit component 60 is mounted between the high-dielectric component 50 and the housing 32 so as to extend in the Y direction.

[0091] Each of the semiconductor chips 40a to 40c includes: a semiconductor substrate 41, a pad 42 provided on the upper surface of the semiconductor substrate 41, a pad 43, and an electrode 44 provided on the lower surface of the semiconductor substrate 41. The pad 42, the pad 43, and the electrode 44 are a gate electrode, a drain electrode, and a source electrode respectively, and the pad 42 is an input pad. The pads 43 of the semiconductor chips 40a, 40b, and 40c are a first output pad, a second output pad, and a third output pad respectively. On the semiconductor substrate 41, Figure 3 the transistors Q1 to Q3 shown are provided. When the transistors Q1 to Q3 are GaN HEMTs, the semiconductor substrate 41 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. When the transistors Q1 to Q3 are LDMOSs, the semiconductor substrate 41 is, for example, a silicon (Si) substrate. The pad 42, the pad 43, and the electrode 44 are, for example, metal layers such as gold layers.

[0092] The capacitive component 65 includes: a dielectric substrate 66, an electrode 67 provided on the upper surface of the dielectric substrate 66, and an electrode 68 provided on the lower surface of the dielectric substrate 66. A capacitor is formed by the electrode 67 and the electrode 68 with the dielectric substrate 66 interposed therebetween. The dielectric substrate 66 is, for example, an alumina substrate or a barium titanate substrate. The electrode 67 and the electrode 68 are, for example, metal layers such as gold layers.

[0093] The line component 45 includes a dielectric substrate 46, a line pattern 47 provided on the upper surface of the dielectric substrate 46, and an electrode 48 provided on the lower surface of the dielectric substrate 46. The line pattern 47 and the electrode 48 form a transmission line. The dielectric substrate 46 is, for example, an alumina substrate. The line pattern 47 and the electrode 48 are, for example, metal layers such as a gold layer.

[0094] The high dielectric component 50 includes a high dielectric substrate 51, an electrode 52 provided on the upper surface of the high dielectric substrate 51, and an electrode 53 provided on the lower surface of the high dielectric substrate 51. The electrode 52 and the electrode 53 sandwiching the high dielectric substrate 51 form a capacitor. The high dielectric substrate 51 is, for example, a barium titanate substrate, and has a larger relative dielectric constant than an alumina substrate. The electrode 52 and the electrode 53 are, for example, metal layers such as gold layers.

[0095] The line component 60 includes a dielectric substrate 61, a line pattern 62a and a line pattern 62b provided on the upper surface of the dielectric substrate 61, and an electrode 63 provided on the lower surface of the dielectric substrate 61. The line pattern 62a and the electrode 63 form a transmission line TL01. The line pattern 62b and the electrode 63 form a transmission line TL02. The transmission line TL01 and the transmission line TL02 correspond to the impedance converter 20 and the impedance converter 21, respectively. The width of the transmission line TL01 in the X direction is greater than the width of the transmission line TL02 in the X direction. Therefore, the characteristic impedance of the transmission line TL01 is lower than the characteristic impedance of the transmission line TL02. The two ends of the transmission line TL01 in the Y direction correspond to the end 20a (first end) and the end 20b (second end) of the impedance converter 20, respectively. The two ends of the transmission line TL02 in the Y direction correspond to the end 21a (third end) and the end 21b (fourth end) of the impedance converter 21, respectively. The electrodes 44 , 48 , 53 , 63 , and 68 are bonded to the base 31 via a conductive bonding layer 38 such as solder or metal paste.

[0096] The bonding wire 71 electrically connects the leads 34a to 34c to the electrode 67. The bonding wire 72 electrically connects the electrode 67 to the pad 42. The bonding wire 73 electrically connects the pad 43 to the line pattern 47. The bonding wire 74 electrically connects the line pattern 47 to the electrode 52. The bonding wire 75a electrically connects the electrode 52 of the path 15a to the end 20a of the line pattern 62a. The bonding wire 75b electrically connects the electrode 52 of the path 15b to the end 20b of the line pattern 62a and the end 21a of the line pattern 62b. The bonding wire 75c electrically connects the electrode 52 of the path 15c to the end 21b of the line pattern 62b. The bonding wire 76 electrically connects the end of the line pattern 62a to the lead 35. The bonding wires 71 to 76 are metal wires such as gold wires or aluminum wires.

[0097] The bonding wires 71 and 72 function as inductors, and the capacitive component 65 functions as a capacitor. Thus, the bonding wires 71, 72, and the capacitive component 65 correspond to the matching circuits 12a to 12c of the T-type LCL circuit.

[0098] Next, regarding the matching circuits 14a to 14c, the matching circuit 14a will be described as an example. The structures of the matching circuits 14b and 14c are the same as that of the matching circuit 14a. Figure 7 It is a top view of a part of the semiconductor device of Embodiment 1. Figure 8 It is Figure 7 the equivalent circuit diagram of. As Figure 7 and Figure 8 shown, inside the semiconductor chip 40a, a drain-source capacitance is electrically connected between the pad 43 and a reference potential such as a ground potential. Figure 4 The influence of the drain inductance Ld and the drain resistance Rd of

[0099] is small, so the influence of the drain inductance Ld and the drain resistance Rd is ignored. An inductor L1 and a transmission line TL1 are connected in series between the pad 43 and the lead 35. The inductor L1 and the transmission line TL1 form the matching circuit 14a. The terminal 20a of the impedance converter 20 is connected to the node N1 between the transmission line TL1 and the lead 35.

[0100] The inductor L1 may be formed only by bonding wires. In the case of forming the inductor L1 by bonding wires, the bonding wires are set long to increase the inductance of the inductor L1. In this case, when a large current flows through the bonding wires, the bonding wires may melt. Therefore, the line component 45 is provided to shorten the lengths of the bonding wires 73 and 74.

[0101] To reduce Figure 3 the characteristic impedance (for example, 2 Ω to 4 Ω) of the impedance converters 25a to 25c, the characteristic impedance of the transmission line TL1 is reduced. For example, the characteristic impedance can be adjusted by adjusting the width of the electrode 52 in the Y direction and the thickness of the high-dielectric substrate 51. The phase can be adjusted by adjusting the width of the electrode 52 in the X direction.

[0102] As described above, the characteristic impedance of the matching circuits 14a to 14c can be reduced. As a method for reducing the characteristic impedance of the matching circuits 14a to 14c, Comparative Examples 1 to 3 will be described.

[0103] [Comparative Example 1]

[0104] Figure 9 A top view of a part of the semiconductor device of Comparative Example 1. Figure 10 is Figure 9 equivalent circuit diagram. As Figure 9 shown, in Comparative Example 1, a bonding wire 79 connecting the pad 43 and the lead 35 is provided. As Figure 10 shown, an inductor L0 is connected between the pad 43 and the lead 35. The matching circuit 14a and the impedance transformer 20 are provided on the circuit board 39 on which the package 30 is to be mounted. The inductor L0 corresponds to the bonding wire 79.

[0105] As shown in Comparative Example 1, when the matching circuits 14a to 14c are provided on the circuit board 39 on which the semiconductor device 102 is mounted, if a transmission line with a low characteristic impedance is to be provided on the circuit board, the width of the line becomes large. This is because the dielectric constant of the dielectric substrate of the circuit board 39 is low and the dielectric substrate is thick. As an example, the width of the line is about 40 mm. As a result, the circuit board becomes large. When the characteristic impedance of the matching circuit 14a (10 Ω as an example) is increased, the matching circuit 14a becomes narrowband. If a wide line is used, the width of the line connecting the matching circuits 14a to 14c and the impedance transformer 20 also becomes large. If a shunt capacitor is used instead of a line, resonance occurs due to the inductance of the via holes of the circuit board 39 for shunt connection. The characteristic impedances of the impedance transformer 20 and the impedance transformer 21 do not have to be as low as the characteristic impedances of the matching circuits 14a to 14c. However, when the impedance transformer 20 and the impedance transformer 21 are provided on the circuit board 39, problems such as those in Comparative Example 2 and Comparative Example 3 below occur.

[0106] [Comparative Example 2]

[0107] Figure 11 A top view of a part of the semiconductor device of Comparative Example 2. Figure 12 is Figure 11 equivalent circuit diagram. As Figure 11 shown, in Comparative Example 2, a capacitive component 55d is mounted on the base 31. A bonding wire 73a connecting the pad 43 and the electrode 56 of the capacitive component 55d and a bonding wire 79a connecting the pad 43 and the lead 35 are provided.

[0108] As Figure 12 shown, a shunt-connected inductor L2 and a capacitor C2 connected in series with the inductor L2 are provided. An inductor L0a is provided between the pad 43 and the lead 35. The inductor L2 is an inductor for compensating the drain-source capacitance Cds. The inductance of the inductor L2 is 1 / ((2 × π × f0) 2×Cds). f0 is the center frequency of the operating frequency band. The capacitor C2 blocks DC. The matching circuit 14a and the impedance converter 20 are provided on the circuit board 39. The inductor L2 and the inductor L0a correspond to the bonding wire 73a and the bonding wire 79a, respectively. The capacitor C2 corresponds to the capacitive component 55d.

[0109] In Comparative Example 2, the drain-source capacitance Cds is compensated by providing the inductor L2. Therefore, it is only necessary to provide the impedance converter 25a that shifts the phase by 90° after the pad 43. However, since the bonding wire 79a passes over the capacitive component 55d, the inductance of the inductor L0a is larger than the inductance of the inductor L0 in Comparative Example 1. When the inductance of the inductor L0a is large, it is difficult to design an impedance converter with a desired characteristic impedance and a 90° phase shift using the matching circuit 14a having a capacitor and an inductor and the inductor L0a, and it is difficult to achieve broadband operation.

[0110] [Comparative Example 3]

[0111] Figure 13 is a top view of a part of the semiconductor device of Comparative Example 3. Figure 14 is Figure 13 the equivalent circuit diagram of. As Figure 13 shown, in Comparative Example 3, the high-dielectric component 50b is mounted on the base 31. The bonding wire 79b that connects the pad 43 and the electrode 52 of the high-dielectric component 50b and the bonding wire 79c that connects the electrode 52 and the lead 35 are provided.

[0112] As Figure 14 shown, an inductor L0b, a transmission line TL0a, and an inductor L0c are connected in series between the pad 43 and the lead 35. The inductor L0b, the transmission line TL0a, and the inductor L0c form the matching circuit 14a. The impedance converter 20 is provided on the circuit board 39. The inductor L0b and the inductor L0c correspond to the bonding wire 79b and the bonding wire 79c, respectively. The transmission line TL0a corresponds to the high-dielectric component 50b.

[0113] In Comparative Example 3, the matching circuit 14a is provided inside the package 30. As a result, a matching circuit 14a with a low characteristic impedance can be realized. However, the parasitic capacitance of the lead 35 is large. Therefore, the high-frequency characteristics of the lead 35 deviate significantly from those of an ideal transmission line. Thus, it is difficult to design an impedance converter with a desired characteristic impedance and a 90° phase shift using the matching circuit 14a and the lead 35, and it is difficult to achieve broadband operation.

[0114] As an example, when the center frequency f0 is set to 2 GHz, the characteristic impedances of the impedance transformers 20, 21, and 22 are 3.9 Ω, 7.9 Ω, and 11.4 Ω, respectively. The characteristic impedance of the matching circuits 14a to 14c is 2.63 Ω, and the phase stagger angle is 37.2°. An example of the case where the impedance transformers 20, 21, and 22 are provided on the circuit board 39 as in Comparative Example 1 will be described.

[0115] Figure 15 is a top view of the circuit board of Comparative Example 1. As Figure 15 shown, packages 30a to 30c are mounted on the circuit board 39. A main amplifier 10a, a peak amplifier 10b, and a peak amplifier 10c are respectively mounted in the packages 30a to 30c. Line patterns 58a to 58g are provided on the circuit board 39. The line pattern 58a is a line with a characteristic impedance of 50 Ω. The line pattern 58b corresponds to the impedance transformer 22. The line patterns 58c and 58d respectively correspond to the impedance transformers 20 and 21. The line patterns 58e to 58g respectively correspond to the matching circuits 14a to 14c. For example, if the center frequency is assumed to be 2 GHz, and the relative dielectric constant and thickness of the circuit board 39 are assumed to be 3.5 and 500 μm, respectively, the length of the 1 / 4 wavelength line is approximately 20 mm. The widths of the line patterns with characteristic impedances of 2.63 Ω, 3.9 Ω, 7.8 Ω, and 11.4 Ω are 35 mm, 25 mm, 12 mm, and 7.8 mm, respectively. When these line patterns 58a to 58g are provided on the circuit board 39, the width D1 in the Y direction is approximately 107 mm. Thus, the circuit board 39 becomes large-sized.

[0116] [Description of Example 1]

[0117] Figure 16 is a top view of the circuit board of Example 1. In Example 1, not only the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c, but also the matching circuits 14a to 14c, the impedance transformer 20, and the impedance transformer 21 are mounted in the package 30. Therefore, only the line patterns 58a and 58b need to be provided on the circuit board 39, and the line patterns 58c to 58g can be omitted. Therefore, the width D2 in the Y direction is the width of the package 30, which is smaller than the width D1 of Comparative Example 1.

[0118] As described above, according to Example 1, as Figure 5 and Figure 7As shown, an impedance converter 20, a matching circuit 14a, and a matching circuit 14b are mounted on a base 31. An end 20a of the impedance converter 20 is electrically connected to a pad 43 of a semiconductor chip 40a via the matching circuit 14a and is also electrically connected to a lead 35. An end 20b of the impedance converter 20 is electrically connected to a semiconductor chip 40b and is also electrically connected to a pad 43 of a semiconductor chip 40c via an impedance converter 21. The matching circuit 14a matches the impedance between the pad 43 of the semiconductor chip 40a and the end 20a. The matching circuit 14b matches the impedance between the pad 43 of the semiconductor chip 40b and the end 20b.

[0119] In this way, by mounting the impedance converter 20, the matching circuit 14a, and the matching circuit 14b on the base 31, matching circuits 14a and 14b with low characteristic impedance can be realized. Thus, impedance converters 25a and 25b can shift the phase between the signal source of the transistor Q1 and the node N1 and the phase between the signal source of the transistor Q2 and the node N2 by 90°. Thus, an N-way Doherty amplifier circuit 100 can be realized. In addition, the circuit board 39 can be miniaturized.

[0120] The impedance converter 21 is mounted on the base 31. An end 21a of the impedance converter 21 is electrically connected to an end 20b of the impedance converter 20 and is short-circuited to be at the same potential. An end 21b of the impedance converter 21 is electrically connected to a pad 43 of the semiconductor chip 40c. The matching circuit 14c matches the impedance between the pad 43 of the semiconductor chip 40c and the end 21b.

[0121] In this way, by mounting the impedance converter 21 and the matching circuit 14c on the base 31, a matching circuit 14c with low characteristic impedance can be realized. Thus, the impedance converter 25c can shift the phase between the signal source of the transistor Q3 and the node N3 by 90°. Thus, an N-way Doherty amplifier circuit 100 can be realized. It is also possible that the impedance converter 21 may not be provided.

[0122] An end 20a of the impedance converter 20 is electrically connected to a pad 43 of the semiconductor chip 40a via bonding wires 73, 74, and 75a (first bonding wires). An end 20a of the impedance converter 20 is electrically connected to a lead 35 via a bonding wire 76 (second bonding wire). Thus, the bonding wires 73, 74, and 75a can be used as part of the matching circuit 14a. The node N1 can be electrically connected to the outside of the package 30 via the bonding wire 76.

[0123] The terminal 20b of the impedance converter 20 is electrically connected to the pad 43 of the semiconductor chip 40b via the bonding wire 73, the bonding wire 74, and the bonding wire 75b (the third bonding wire). The terminal 21b of the impedance converter 21 is electrically connected to the pad 43 of the semiconductor chip 40c via the bonding wire 73, the bonding wire 74, and the bonding wire 75c (the fourth bonding wire). Thus, the bonding wire 73, the bonding wire 74, and the bonding wire 75b can be used as part of the matching circuit 14b. The bonding wire 73, the bonding wire 74, and the bonding wire 75c can be used as part of the matching circuit 14c.

[0124] The impedance converter 20 includes a line pattern 62a provided in the line component 60, and the impedance converter 21 includes a line pattern 62b provided in the line component 60. Thus, the impedance converters 20 and 21 can be formed using the transmission line TL01 and the transmission line TL02. The characteristic impedance and the electrical length of the impedance converters 20 and 21 can be realized with high precision by using the line pattern 62a and the line pattern 62b.

[0125] The impedance converter 20 shifts the phase of the center frequency f0 of the operating frequency band by 90° between the terminal 20a and the terminal 20b, and the impedance converter 21 shifts the phase of the center frequency f0 of the operating frequency band by 90° between the terminal 21a and the terminal 21b. Thus, the impedance converters 20 and 21 can transform the impedance on the real axis of the Smith chart into different impedances on the real axis.

[0126] The matching circuit 14a shifts the phase of the center frequency f0 by 90° between the signal source of the main amplifier 10a and the terminal 20a. The matching circuit 14b shifts the phase of the center frequency f0 by 90° between the signal source of the peak amplifier 10b and the terminal 20b. The matching circuit 14c shifts the phase of the center frequency f0 by 90° between the signal source of the peak amplifier 10c and the terminal 20b. Thus, the impedance converters 25a to 25c each including the matching circuits 14a to 14c can transform the impedance on the real axis of the Smith chart into different impedances on the real axis.

[0127] As Figure 5As shown, at the end 20a, the angle θ formed by the flow direction 80 of the signal S4 and the flow direction 81 of the signal S5 is approximately 90°. As a result, the impedance transformer 20 can be extended along the Y direction between the semiconductor chip 40a, the semiconductor chip 40b and the frame 32, and the package 30 can be miniaturized. At the end 20b, the angle formed by the flow direction of the signal S5 and the flow direction of the signal S6 is also approximately 90°, similar to the angle θ. As a result, the impedance transformer 21 can be extended along the Y direction between the semiconductor chip 40b, the semiconductor chip 40c and the frame 32, and the package 30 can be miniaturized. The angle θ may not be 90°, for example, it may be set to be greater than 70° and less than 110°, or it may be set to be greater than 80° and less than 100°.

[0128] The phase of the center frequency f0 may be shifted by 90°, which may not be strictly 90°. For example, the phase shift may be greater than 70° and less than 110°, or greater than 85° and less than 95°. In addition, the impedance on the real axis may not be strictly located on the real axis (i.e., the reactance component is 0). The absolute value of the reactance component of the impedance may be less than 1.0 times the resistance component, or less than 0.2 times.

[0129] [Another example of the impedance converters 20 and 21]

[0130] Figure 17 FIG. 2 is a top view of a semiconductor device showing another example of the impedance converter of the first embodiment. Figure 17 As shown, in the semiconductor device 104, the circuit component 60a includes electrodes 63a to 63c on the dielectric substrate 61. The electrode 63a and the electrode 63b are electrically connected by a bonding wire 78a. The electrode 63b and the electrode 63c are electrically connected by a bonding wire 78b. The electrode 63a is connected to a bonding wire 75a and a bonding wire 76. The electrode 63b and the electrode 63c are connected to a bonding wire 75b and a bonding wire 75c, respectively.

[0131] Figure 18 : is a circuit diagram showing another example of the impedance converter of the first embodiment. An inductor L01 is connected between the node N1 and the node N2, and an inductor L02 is connected between the node N2 and the node N3. Capacitors C01, C02, and C03 are connected in a branch manner to the nodes N1 to N3, respectively. Capacitor C01, capacitor C02, and inductor L01 form an impedance converter 20, and capacitor C02, capacitor C03, and inductor L02 form an impedance converter 21. Capacitors C01, C02, and C03 correspond to electrodes 63a to 63c and base 31 across a dielectric substrate 61, respectively. Inductor L01 and inductor L02 correspond to bonding wire 78a and bonding wire 78b, respectively.

[0132] The target characteristic impedances of impedance transformers 20 and 21 are set to Z01 and Z02 respectively, the capacitances of capacitors C01 to C03 are set to C01 to C03 respectively, and the inductances of inductors L01 and L02 are set to L01 and L02 respectively. At this time, it is set that L01 = Z01 / (2×π×f0), L02 = Z02 / (2×π×f0), C01 = (2×π×f0) / Z01, C02 = (2×π×f0) / Z01 + (2×π×f0) / Z02, C03 = (2×π×f0) / Z02. Thus, the characteristic impedances Z01 and Z02 of impedance transformers 20 and 21 can be set to the target values.

[0133] As Figure 17 and Figure 18 shown, impedance transformer 20 may also include capacitor C01 (first capacitor), capacitor C02 (second capacitor), and bonding wire 78a (fifth bonding wire). The first ends of capacitor C01 and capacitor C02 are electrically connected to base 31. Bonding wire 78a electrically connects the second end of capacitor C01 and the second end of capacitor C02. Impedance transformer 21 may also include capacitor C02, capacitor C03, and bonding wire 78b. The first ends of capacitor C02 and capacitor C03 are electrically connected to base 31. Bonding wire 78b electrically connects the second end of capacitor C02 and the second end of capacitor C03. Thus, impedance transformers 20 and 21 can be formed. An example of disposing electrodes 63a to 63c on one dielectric substrate 61 has been described, but electrodes 63a to 63c may also be disposed on different dielectric substrates 61.

[0134] [Another example 1 of matching circuits 14a to 14c]

[0135] As matching circuits 14a to 14c, matching circuit 14a is taken as an example for description, but matching circuits 14b and 14c can also be formed in the same way. The same applies to another examples 2 to 4 of matching circuits 14a to 14c described later. Figure 19 is a top view showing another example 1 of the matching circuit of Embodiment 1. Figure 20 is Figure 19 's equivalent circuit diagram. As Figure 19 shown, in another example 1 of matching circuit 14a, a capacitive component 55a is mounted on base 31. There are provided a bonding wire 77a that electrically connects pad 43 and the electrode 57 of capacitive component 55a and a bonding wire 75a that electrically connects electrode 57 and terminal 20a.

[0136] As Figure 20As shown, there is an inductor L1a connecting the pad 43 and the node N1, and a capacitor C1a shunt-connected between the inductor L1a and the node N1. The inductor L1a corresponds to the bonding wire 77a. The capacitor C1a corresponds to the capacitive component 55a.

[0137] If the capacitance of the capacitor C1a is set to be the same as the drain-source capacitance Cds and the inductance of the inductor L1a is set to 1 / ((2×π×f0) 2 ×Cds), then the impedance converter 25a shifts the phase of the center frequency f0 by 90°. The characteristic impedance of the impedance converter 25a is 1 / (2×π×f0×Cds). In another example 1 of the matching circuits 14a to 14c, although the characteristic impedance cannot be freely set, the number of components mounted on the base 31 can be reduced.

[0138] [Another example 2 of the matching circuits 14a to 14c]

[0139] Figure 21 is a top view showing another example 2 of the matching circuit of Embodiment 1. Figure 22 is Figure 21 the equivalent circuit diagram. As Figure 21 shown, in another example 2 of the matching circuit 14a, a capacitive component 55d and a capacitive component 55b are mounted on the base 31. There are provided a bonding wire 73a electrically connecting the pad 43 and the electrode 57 of the capacitive component 55d, a bonding wire 77b electrically connecting the pad 43 and the electrode 57 of the capacitive component 55b, and a bonding wire 75a electrically connecting the electrode 57 of the capacitive component 55b and the terminal 20a.

[0140] As Figure 22 shown, an inductor L2 is shunt-connected. A capacitor C2 is connected in series with the inductor L2. There is an inductor L1b connecting the pad 43 and the node N1, and a capacitor C1b shunt-connected between the inductor L1b and the node N1. The inductor L2 and the inductor L1b correspond to the bonding wire 73a and the bonding wire 77b respectively. The capacitor C2 and the capacitor C1b correspond to the capacitive component 55d and the capacitive component 55b respectively.

[0141] The inductance of the inductor L2 is greater than 1 / ((2×π×f0) 2 ×Cds). Thus, the inductor L2 does not completely compensate the drain-source capacitance Cds. Let the uncompensated capacitance component be ΔCds. The capacitor C2 is a DC-blocking capacitor, and its capacitance is large enough not to affect the inductor L2 at the center frequency f0. The inductance of the inductor L1b is 1 / ((2×π×f0) 2×(Cds - ΔCds)), the capacitance of capacitor C1b is Cds - ΔCds. Thus, impedance transformer 25a shifts the phase of the center frequency f0 by 90°. The characteristic impedance of impedance transformer 25a is 1 / (2×π×f0×(Cds - ΔCds)). In this way, by selecting the value of ΔCds, the characteristic impedance of impedance transformer 25a can be arbitrarily set compared to another Example 1.

[0142] Instead of inductor L2 and capacitor C2, capacitor C2 can be provided without providing an inductor. In this case, the capacitance of capacitor C2 is set to ΔCds. The inductance of inductor L1b is 1 / ((2×π×f0) 2 ×(Cds + ΔCds)), the capacitance of capacitor C1b is Cds + ΔCds. Thus, impedance transformer 25a shifts the phase of the center frequency f0 by 90°. The characteristic impedance of impedance transformer 25a is 1 / (2×π×f0×(Cds + ΔCds)). In this case, the characteristic impedance of impedance transformer 25a can also be arbitrarily set.

[0143] [Another Example 3 of Matching Circuits 14a to 14c]

[0144] Figure 23 is a top view showing another Example 3 of the matching circuit of Example 1. Figure 24 is Figure 23 the equivalent circuit diagram. As Figure 23 shown, in another Example 3 of matching circuit 14a, a capacitive component 55d and a high-dielectric component 50a are mounted on a base 31. Bonding wires 73a for electrically connecting pad 43 to electrode 57 of capacitive component 55d, bonding wire 77c for electrically connecting pad 43 to electrode 52 of high-dielectric component 50a, and bonding wire 75a for electrically connecting electrode 52 of high-dielectric component 50a to terminal 20a are provided.

[0145] As Figure 24 shown, an inductor L2 is shunt-connected, and capacitor C2 is connected in series with inductor L2. An inductor L1c and a transmission line TL1a are connected in series between pad 43 and node N1. Inductor L2 and inductor L1c correspond to bonding wire 73a and bonding wire 77c respectively. Capacitor C2 corresponds to capacitive component 55d. Transmission line TL1a corresponds to high-dielectric component 50a.

[0146] The inductance of inductor L2 is 1 / ((2×π×f0) 2 ×Cds). Thus, inductor L2 compensates for the drain-source capacitance Cds. As long as inductor L1c and transmission line TL1a are used to shift the phase of the center frequency f0 by 90°. The characteristic impedance and the shifted phase of transmission line TL1a can be the same asFigure 7 and Figure 8 The high-dielectric component 50 is set in the same manner. Thus, the drain-source capacitance Cds is compensated, and therefore, it is only necessary to make the phase shifted by the transmission line TL1a be around 90°, and it is easy to design the high-dielectric component 50a.

[0147] [Another example 4 of the matching circuits 14a to 14c]

[0148] Figure 25 FIG. is a top view showing another example 4 of the matching circuit of Embodiment 1. Figure 26 is Figure 25 the equivalent circuit diagram of. As Figure 25 shown, in another example 4 of the matching circuit 14a, a capacitive component 55d and a capacitive component 55c are mounted on the base 31. Bonding wires 73a for electrically connecting the pad 43 to the electrode 57 of the capacitive component 55d, bonding wires 77d for electrically connecting the pad 43 to the electrode 52 of the capacitive component 55c, and a bonding wire 75a for electrically connecting the electrode 52 of the capacitive component 55c to the terminal 20a are provided.

[0149] As Figure 26 shown, a shunt-connected inductor L2 is provided, and a capacitor C2 is connected in series with the inductor L2. An inductor L1d and an inductor L3 are connected in series between the pad 43 and the node N1. A capacitor C1c is shunt-connected to the node between the inductor L1d and the inductor L3. The inductor L2, the inductor L1d, and the inductor L3 respectively correspond to the bonding wires 73a, 77d, and 75a. The capacitor C2 and the capacitor C1c respectively correspond to the capacitive component 55d and the capacitive component 55c.

[0150] The inductance of the inductor L2 is 1 / ((2 × π × f0) 2 × Cds). Thus, the inductor L2 compensates the drain-source capacitance Cds. It is only necessary to use the inductor L1d, the inductor L3, and the capacitor C1c to shift the phase of the center frequency f0 by 90°. For example, when the characteristic impedance of the impedance transformer 25a is set to Z0, the inductances of the inductor L1d and the inductor L3 are set to Z0 / (2 × π × f0), and the capacitance of the capacitor C1c is set to 1 / (2 × π × f0 × Z0). Thus, the drain-source capacitance Cds is compensated, and therefore, it is easy to design the inductor L1d, the inductor L3, and the capacitor C1c.

[0151] In Embodiment 1, an example in which the semiconductor substrates 41 of the semiconductor chips 40a to 40c are separated has been described, but at least two of the semiconductor substrates 41 of the semiconductor chips 40a to 40c may be made common and integrated.

[0152] The description has been given by taking a three-way Doherty amplifier circuit as an example. However, in the case of an N-way Doherty amplifier circuit, it is only necessary to provide N semiconductor chips, N matching circuits, and N-1 impedance transformers.

[0153] The description has been given for the case where the saturation powers of the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c are the same. However, the saturation powers of the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c may also be different. For example, the saturation powers of the peak amplifier 10b and the peak amplifier 10c may be twice that of the main amplifier 10a.

[0154] It should be noted that the embodiments disclosed herein are illustrative in all aspects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: A package having a base and output leads; A first semiconductor chip is mounted on the base and includes a main amplifier for amplifying a first signal obtained by distributing an input signal and a first output pad for outputting the amplified first signal; A second semiconductor chip is mounted on the base and includes a first peak amplifier for amplifying a second signal obtained by dividing the input signal and a second output pad for outputting the amplified second signal; A third semiconductor chip is mounted on the base and includes a second peak amplifier for amplifying a third signal obtained by dividing the input signal and a third output pad for outputting the amplified third signal; A first impedance converter, mounted on the base, with a first end electrically connected to the first output pad and the output lead, and a second end electrically connected to the second output pad and the third output pad; A first matching circuit, mounted on the base, matches the impedance of the first output pad with that of the first end; and The second matching circuit is mounted on the base to match the impedance of the second output pad with that of the second end.

2. The semiconductor device according to claim 1, wherein have: A second impedance converter is mounted on the base, a third end of the second impedance converter is electrically connected to the second end of the first impedance converter, and a fourth end of the second impedance converter is electrically connected to the third output pad; and The third matching circuit matches the impedance of the third output pad with that of the fourth end.

3. The semiconductor device according to claim 1 or 2, wherein: The first end is electrically connected to the first output pad via a first bonding wire, The first end is electrically connected to the output lead via a second bonding wire.

4. The semiconductor device according to claim 3, wherein: The second end is electrically connected to the second output pad via a third bonding wire.

5. The semiconductor device according to claim 2, wherein: The first end is electrically connected to the first output pad via a first bonding wire, The second end is electrically connected to the output lead via a second bonding wire, The second end and the third end are electrically connected to the second output pad via a third bonding wire, The fourth end is electrically connected to the third output pad via a fourth bonding wire.

6. The semiconductor device according to claim 1 or 2, wherein: A circuit component is provided, wherein the circuit component comprises: a dielectric substrate mounted on the base; and a circuit pattern provided on the dielectric substrate. The first impedance converter includes the line pattern.

7. The semiconductor device according to claim 1 or 2, wherein: have: A first capacitor, mounted on the base, with a first end electrically connected to the base; A second capacitor is mounted on the base, and a first end of the second capacitor is electrically connected to the base; as well as a fifth bonding wire electrically connecting the second end of the first capacitor to the second end of the second capacitor, The first impedance converter includes the first capacitor, the second capacitor, and the fifth bonding wire.

8. The semiconductor device according to claim 1 or 2, wherein: The first impedance converter shifts the phase of the center frequency of the operating frequency band by 90° between the first end and the second end.

9. The semiconductor device according to claim 8, wherein: The first matching circuit shifts the phase of the center frequency by 90° between the signal source of the main amplifier and the first end. The second matching circuit shifts the phase of the center frequency by 90° between the signal source of the first peak amplifier and the second end.

10. The semiconductor device according to claim 2 or 5, wherein: The first impedance converter shifts the phase of the center frequency of the operating frequency band by 90° between the first end and the second end. The second impedance transformer shifts the phase of the center frequency of the operating frequency band by 90° between the third end and the fourth end. The first matching circuit shifts the phase of the center frequency by 90° between the signal source of the main amplifier and the first end. The second matching circuit shifts the phase of the center frequency by 90° between the signal source of the first peak amplifier and the second end and the third end. The third matching circuit shifts the phase of the center frequency by 90° between the signal source of the second peak amplifier and the fourth end.

11. The semiconductor device according to claim 1 or 2, wherein: The input power for turning on the first peak amplifier is greater than the input power for turning on the main amplifier, The input power at which the second peak amplifier is turned on is greater than the input power at which the first peak amplifier is turned on.

12. The semiconductor device according to claim 1 or 2, wherein: At the first end, an angle formed by a flow direction of the amplified first signal and a flow direction of the amplified second signal is greater than or equal to 70° and less than or equal to 110°.

13. A Doherty amplifier circuit, comprising: The semiconductor device according to claim 1 or 2; and A distributor distributes the input signal into the first signal, the second signal, and the third signal.

Images