Power amplifier circuit

Abstract

The invention relates to a power amplifier circuit. The invention particularly relates to a power amplifier circuit comprising a transistor package and a substrate. The transistor package is disposed on the substrate. The power amplifier circuit includes a transistor package including at least one power transistor, and for each power transistor, the transistor package has an output lead electrically connected to an output terminal of the power transistor. The power amplifier circuit further includes a substrate on which the transistor package is disposed, where, for each output lead, the substrate includes a conductive track to which the output leads are fixedly attached. According to the invention, a conductive track comprising a cavity is formed for a conductive track of at least one output lead, the conductive track comprising the cavity comprising a cavity in which a shunt capacitor is disposed. The shunt capacitor has a first terminal connected to the conductive track and a grounded second terminal configured to be grounded during operation.

Description

Technical Field

[0001] The present invention relates to a power amplifier circuit. In particular, the present invention relates to a power amplifier circuit including a transistor package and a substrate on which the transistor package is disposed. The transistor package includes at least one power transistor, and for each power transistor, the transistor package has an output lead electrically connected to the output terminal of the power transistor. For each output lead, the substrate includes a conductive track to which the output lead is fixedly attached.

[0002] The present invention relates to a radiofrequency (RF) power amplifier circuit that delivers a maximum output power in the range of 10 watts to 1000 watts at an operating frequency in the range of 0.5 GHz to 10 GHz. Background Art

[0003] Power amplifier circuits of the above type are known in the art. Power transistors are typically configured to output maximum power when presenting a relatively low impedance at their output terminals. Hereinafter, this impedance is referred to as the optimum load impedance. These impedances are typically much lower than the impedance of the load to which power is to be delivered.

[0004] To overcome the impedance difference, the power amplifier circuit includes an impedance matching network disposed between the output terminal of the power transistor and the load. The impedance matching network may include one or more stages. For example, the impedance matching network may include a first stage that matches an optimum load impedance of, for example, 2 ohms to 10 ohms and a second stage that matches a load impedance of 10 ohms to 50 ohms. Alternatively, a single stage that directly matches 2 ohms to 50 ohms may be used.

[0005] The bandwidth over which the impedance matching stage provides an acceptable match decreases with the impedance ratio achieved by such a matching stage. Thus, in the above example, the combination of the first and second stages typically provides a better bandwidth than a solution with a single matching stage. On the other hand, increasing the number of impedance matching stages generally increases the losses between the power transistor and the load.

[0006] A particular example of a matching network is a quarter-wavelength transformer. This matching network uses a transmission line having a specific characteristic impedance and an electrical length of 90 degrees at the frequency of interest. For these matching networks, the ratio between the impedance Zin entering the network and the impedance Z1 presented at the output is Zin = Z0 2 / Z1. Where Z0 is the characteristic impedance of the transmission line, which can be approximated as Z0 = (L / C) 1 / 2 . Where L and C are the inductance and capacitance per unit length of the transmission line.

[0007] Using the quarter-wavelength transformer in the above example, for a single-stage solution, it is necessary to be equal to (2 × 50)1 / 2 a characteristic impedance of = 10 ohms, while for a two-stage solution, it needs to be equal to (2×10) 1 / 2 = 4.5 ohms and (10×50) 1 / 2 = 22.4 ohms of characteristic impedance.

[0008] It can be inferred from this example that the transmission line directly following the output of the power transistor requires a relatively low characteristic impedance, especially when the impedance ratio is relatively large, such as in a multi-stage network required for broadband applications. The low characteristic impedance transmission line is usually very wide because such a line needs to have a relatively large capacitance per unit length and a relatively low inductance per unit length. For a compact solution, there may not be enough available area on the substrate to set up these wide transmission lines.

[0009] Known methods for solving the problem of relatively wide transmission lines include using shunt capacitors, thereby effectively increasing the capacitance of the transmission line per unit length without actually increasing the width of the transmission line to the width required without shunt capacitors. To ensure a symmetric current distribution, the shunt capacitors are usually set at the opposite edges of the transmission line.

[0010] Generally, a transistor package includes multiple power transistors. Each of these transistors requires a corresponding matching network. In addition, there is a continuous demand for transistor packages with reduced occupied area. Therefore, the leads for power transistors in current packages are relatively wide and arranged closely, thus preventing or restricting the setting options for shunt capacitors. Therefore, for these applications, it is difficult to apply the above method of shunt capacitors to obtain broadband performance. Summary of the Invention

[0011] The object of the present invention is to provide a power amplifier circuit applicable to broadband applications to at least partially alleviate the above problems.

[0012] According to the present invention, the above object is achieved by using the power amplifier circuit as described in claim 1, and the power amplifier circuit is characterized in that the conductive track for at least one output lead forms a conductive track including a cavity, and the conductive track including the cavity includes a cavity in which a shunt capacitor is provided.

[0013] The applicant has recognized that in an RF power amplifier circuit, current usually flows at the edges of the conductive track. According to the present invention, a cavity is provided in the internal region of the conductive track, and a shunt capacitor is provided in the cavity. Due to the central positioning of the shunt capacitor, a single shunt capacitor can be used without deteriorating the symmetry of the current distribution inside the conductive track and without increasing the occupied area of the combination of the conductive track and the shunt capacitor.

[0014] Each conductive track including a cavity may include a first track portion, a second track portion, and a pair of spaced-apart third track portions. Among them, the first track portion is fixedly connected to the corresponding output lead, and each third track portion connects the first track portion to the second track portion, where the cavity is disposed between the third track portion, the first track portion, and the second track portion. The first track portion, the second track portion, and the pair of third track portions are preferably formed by track portions, and each track portion has a constant width. For example, the first track portion, the second track portion, and the pair of third track portions may be formed by microstrip lines.

[0015] The shunt capacitor may include a first terminal and a second ground terminal, where the first terminal is preferably directly connected to the first track portion or the second track portion. In the direct connection, one of the terminals of the shunt capacitor, which is usually a surface mount device (SMD), is attached (e.g., welded) to the first track portion or the second track portion. The second terminal of the shunt capacitor is usually connected to a ground via-hole that extends through at least a portion of the substrate. In some embodiments, the substrate has a ground plane on its back surface. Then, the ground via-hole can extend from the front surface of the substrate where the transistor package is mounted to the ground plane at the back surface.

[0016] At least one conductive track including a cavity may include a first end and a second end disposed opposite to each other. The first end is fixedly connected to the corresponding output lead, and the second end is connected to the first terminal of a series capacitor, where the second terminal of the series capacitor is connected to a shunt inductor. The electrical behavior associated with the combination of the at least one conductive track including a cavity and the shunt inductor between the output terminal of the corresponding power transistor and the second terminal of the corresponding series capacitor preferably corresponds to the electrical behavior of a band-pass filter having a passband that includes the operating frequency of the power amplifier circuit.

[0017] For at least one conductive track including a cavity, the combination of the electrical connection between the output of the power transistor and the non-ground terminal of the shunt capacitor, the shunt capacitor itself, and the transmission line between the non-ground terminal of the shunt capacitor and the second end of the at least one conductive track has a low-pass characteristic, while the combination of the series capacitor and the shunt inductor for the at least one conductive track has a high-pass characteristic. Combined, the low-pass and high-pass characteristics produce a band-pass characteristic.

[0018] The power amplifier circuit may be a Doherty amplifier. In this case, the first power transistor among the at least one power transistor forms the main amplifier of the Doherty amplifier, and the second power transistor among the at least one power transistor forms the peak amplifier of the Doherty amplifier. In addition, the power amplifier circuit includes a Doherty combiner for combining the signals from the main amplifier and the peak amplifier at a combining node. The Doherty combiner includes a main branch and a peak branch. The main branch is between the output terminal of the main amplifier and the combining node, and the peak branch is between the output terminal of the peak amplifier and the combining node. The conductive track for the main amplifier is included in the main branch, and the conductive track for the peak amplifier is included in the peak branch.

[0019] The main branch may be configured to provide a first effective impedance seen at the output terminal of the first power transistor in a power back-off state where the second power transistor is turned off. The main branch may also be configured to provide a second effective impedance seen at the output terminal of the first power transistor in a saturated output power state where the first power transistor and the second power transistor output saturated power. Here, the first effective impedance is greater than the second effective impedance.

[0020] The peak branch may be configured to provide a third effective impedance seen at the output terminal of the second power transistor in the saturated output power state. For a symmetric Doherty amplifier, the first power transistor and the second power transistor have substantially the same maximum output power, and the second effective impedance and the third effective impedance may be substantially the same.

[0021] At a frequency within the operating frequency range, the electrical length between the output terminal of the first power transistor and the combining node is preferably equal to m×180 + 90 degrees, and at a frequency within the operating frequency range, the electrical length between the output terminal of the second power transistor and the combining node is preferably equal to n×180 degrees, where m and n are integers equal to or greater than zero. In one example, m <= n. For example, m = 0 and n = 1.

[0022] Generally, the main branch has an impedance inversion function. Since the second power transistor outputs current in the saturated output power state, the impedance at the combining node seen from the main branch away from the first power transistor is greater than the impedance in the power back-off state. This behavior is opposite to the behavior required to achieve high efficiency in both the power back-off state and the saturated output power state. For this reason, the main branch has an impedance transformation function, which means that when the impedance presented at one end of the main branch increases, the impedance seen at the other end decreases. This behavior can generally be seen using a quarter-wavelength transformer or its electrical equivalent.

[0023] The conductive track for the main amplifier can be configured as the conductive track including a cavity as described above, and the conductive track can include a first end and an opposite second end, the first end being connected to the output lead for the first power transistor and the second end being connected to the combining node. The main branch can also include a main-branch series capacitor, wherein the second end of the conductive track including a cavity for the main branch is connected to the combining node through the main-branch series capacitor, the first terminal of the main-branch series capacitor is connected to the second end of the conductive track including a cavity for the main branch, and the second terminal of the main-branch series capacitor is connected to the combining node. The latter connection can be a direct connection, wherein the second terminal of the main-branch series capacitor at least partially forms the combining node, or the connection can be an indirect connection, wherein an offset line is provided between the second terminal of the main-branch series capacitor and the combining node. In addition, the main branch can also include a main-branch shunt inductor, and the main-branch shunt inductor is connected to the second terminal of the main-branch series capacitor. The main-branch shunt inductor preferably includes a first terminal connected to the second terminal of the main-branch series capacitor and a second terminal preferably grounded through a first direct current (DC) blocking capacitor or through a via hole.

[0024] The electrical behavior of the main branch between the output terminal of the first power transistor and the second terminal of the main-branch series capacitor can correspond to the electrical behavior of a band-pass filter having a passband that includes the operating frequency of the power amplifier circuit.

[0025] The conductive track for the peak amplifier can be configured as the conductive track including a cavity as described above, and the conductive track can include a first end and an opposite second end, the first end being connected to the output lead for the second power transistor and the second end being connected to the combining node. The peak branch can include a peak-branch series capacitor, wherein the second end of the conductive track including a cavity for the peak branch is connected to the combining node through the peak-branch series capacitor, the first terminal of the peak-branch series capacitor is connected to the second end of the conductive track including a cavity for the peak branch, and the second terminal of the peak-branch series capacitor is connected to the combining node. The latter connection can be a direct connection, wherein the second terminal of the peak-branch series capacitor at least partially forms the combining node, or the connection can be an indirect connection, wherein an offset line is provided between the second terminal of the peak-branch series capacitor and the combining node. The peak branch can also include a peak-branch shunt inductor, and the peak-branch shunt inductor is connected to the second terminal of the peak-branch series capacitor. The peak-branch shunt inductor preferably includes a first terminal connected to the second terminal of the peak-branch series capacitor and a second terminal preferably grounded through a second DC blocking capacitor or through a via hole.

[0026] The electrical behavior of the peak branch between the output terminal of the second power transistor and the second terminal of the peak branch series capacitor can correspond to the electrical behavior of a bandpass filter having a passband that includes the operating frequency of the power amplifier circuit or an operating frequency.

[0027] The peak branch can also include an offset transmission line connected between the second terminal of the peak branch series capacitor and the combining node.

[0028] The output lead for the first power transistor and the output lead for the second power transistor can be disposed adjacent to each other in a first direction and can be spaced apart from each other by a distance of 2 mm to 10 mm in the first direction.

[0029] Each power transistor in at least one power transistor can be a field effect transistor, where each field effect transistor preferably includes a gallium nitride-based field effect transistor or a silicon-based laterally diffused metal oxide semiconductor transistor.

[0030] The substrate can include an upper metal layer, one or more dielectric layers, and a lower metal layer, with one or more conductive traces implemented in the upper metal layer, where the substrate includes one or more vias for connecting the upper metal layer to the lower metal layer. The second terminals of one or more shunt capacitors for one or more conductive traces including cavities can be electrically connected and / or fixedly connected to one or more vias.

[0031] The substrate can include a metal sheet, preferably made of copper, located at the position on the substrate where the transistor package is disposed. The metal sheet can provide a low thermal resistance path and / or an electrical ground path for at least one power transistor. Description of the Drawings

[0032] Next, the present invention will be described in more detail with reference to the accompanying drawings, in which like reference numerals indicate the same or similar components, and in the drawings:

[0033] Figure 1 A schematic top view of an embodiment of a power amplifier circuit according to the present invention is shown;

[0034] Figure 2 Shown is Figure 1 A partial cross-sectional view of the embodiment in

[0035] Figure 3 Shown corresponding to Figure 1 The equivalent circuit of the embodiment in

[0036] Figure 4 A general Doherty amplifier is shown;

[0037] Figure 5shows an embodiment of a general Doherty amplifier according to the present invention; and Figure 4 and

[0038] Figure 6 shows an equivalent circuit corresponding to the Doherty amplifier in Figure 5 . DETAILED DESCRIPTION

[0039] Figure 1 shows a schematic top view of an embodiment of a power amplifier circuit 100 according to the present invention. The circuit 100 includes a transistor package 10 shown as partially opened. The transistor package 10 includes a substrate 11, such as a flange, a block, etc., on which a semiconductor die 12 is mounted. In Figure 1 , a power transistor embodied as a field effect transistor 13 is integrated on the semiconductor 12. The field effect transistor 13 includes a gate bar 14 serving as an input terminal, and a plurality of gate fingers 14A extending from the gate bar 14. The field effect transistor 13 also includes a drain bar 15 serving as an output terminal, and a plurality of drain fingers 15A extending from the drain bar 15. The source of the field effect transistor 13 is not shown, but can be formed using a through hole extending through the semiconductor 12, which is grounded to the back of the transistor package 10. Instead of using a through hole, the semiconductor die 12 may include a conductive substrate. Instead of using a through hole or a conductive substrate to achieve the source connection, the source of the field effect transistor 13 can be connected to an external ground terminal using a dedicated lead of the transistor package 10, and the field effect transistor 13 can be connected to the dedicated lead using one or more bonding wires.

[0040] The transistor package 10 includes an input lead 16 and an output lead 17. The gate bar 14 is connected to the input lead 16 by a bonding wire 16A, and the drain bar 15 is connected to the output lead 17 by a bonding wire 17A.

[0041] As Figure 2 shown, the transistor package 10 is mounted on a substrate 20. The latter substrate may be a printed circuit board and generally includes one or more dielectric layers 21 and one or more conductive layers, such as metal layers 22A, 22B. One or more conductive layers are respectively disposed on the back and front of the substrate 20, and optionally disposed between the dielectric layers. Tracks and / or other structures can be implemented in these metal layers. Connections between tracks and / or structures in different metal layers can be achieved using through holes 23.

[0042] The substrate 20 includes a cavity, and the transistor package 10 is partially disposed in the cavity. The substrate 20 further includes a copper metal sheet 24 that contacts the back surface of the transistor package 10. The metal sheet 22 realizes the ground connection of the field effect transistor 13, for example, by using the conductive back surface of the transistor package 10 that is connected to the source of the field effect transistor 13. The metal sheet also provides a heat path for removing the heat generated by the field effect transistor 13.

[0043] A conductive track 25 including a cavity is disposed on the front surface of the substrate 20. As Figure 1 shown, the conductive track including the cavity includes a first track portion 25A, a second track portion 25B, and a pair of third track portions 25C. Each track portion is formed by a microstrip line having a constant width. In this regard, it should be noted that a ground plane 26 is provided on the back surface of the substrate 20.

[0044] The cavity is defined by the region between the track portions 25A, 25B, 25C. Inside this cavity, a surface mount device (SMD) capacitor 27 is mounted. More specifically, the first terminal 27A of the SMD capacitor 27 is fixedly connected to the first portion 25A, for example, using a solder layer, and the second terminal 27B of the SMD capacitor 27 is connected to the via hole 23, for example, using a solder layer, where the via hole 23 extends through the substrate 20 and connects the second terminal 27B of the SMD capacitor 27 to the ground plane 26.

[0045] As Figure 1 shown, the first end of the conductive track including the cavity is connected to the output lead 17. The second end of the conductive track including the cavity is connected to the first terminal 30A of the series capacitor 30, and the series capacitor 30 is also embodied as an SMD here. The second terminal 30B of the series capacitor 30 is connected to a shunt inductor, and the shunt inductor is embodied as a section of transmission line 31 in Figure 1 . To provide an RF ground at the end of the transmission line 31, the end of the transmission line 31 is connected to the ground through an SMD capacitor 32. The first terminal 32A of the SMD capacitor is connected to the transmission line 31, and the second terminal 32B of the SMD capacitor is connected to the ground via hole 33.

[0046] The second terminal 30B of the series capacitor 30 is connected to the transmission line 34. The end of the latter transmission line is connected to the output end of the circuit 100 or at least partially forms the output end of the circuit 100.

[0047] Figure 3A circuit is shown that depicts the behavior of a portion of circuit 100. In this circuit, the field effect transistor 13 is referred to as transistor Q1, which has an output capacitance Cd and is provided with a direct current (DC) bias through a bias inductor Lb. An inductor Ld is used to model the bond wire (17A). Additionally, the combination of the first trace portion 25A, the second trace portion 25B, the third trace portion 25C, and the shunt capacitor 27 is modeled using inductors L1, L2, and a shunt capacitor C1. The series capacitor 30 is modeled as capacitor C2 and the transmission line 31 is modeled by an inductor L3. The SMD capacitor 32 connected at the end of the transmission line 31 is modeled as capacitor C3. It should be noted that the operating frequency is much higher than the series resonance frequency of C3 and L3. Therefore, at the operating frequency, the effect of capacitor C3 as seen at the combining node C on the combined impedance of the transmission line 31 and capacitor C3 can be ignored. Finally, the transmission line 34 is modeled using a characteristic impedance Z1 and an electrical length EL1. Here, the transmission line 34 may or may not correspond to a quarter wavelength transformer.

[0048] The components Ld, L1, L2, and C1 form a low-pass network N1, while the components C2, L3, and C3 form a high-pass network. The networks together form a band-pass network or filter that provides a compact and broadband impedance match between the load connected to the output O of the power amplifier circuit 100 and the field effect transistor Q1.

[0049] Figure 4 A general Doherty amplifier 200 is shown, which includes a Doherty splitter 210, a main amplifier 220, a peak amplifier 230, and a Doherty combiner 240. The Doherty splitter 210 splits an input RF signal into a main portion and a peak portion. It includes at least one of the delay elements 211, 212. The Doherty splitter 210 typically imparts a phase difference between the main portion and the peak portion that is generally substantially equal to 90 degrees at the operating frequency.

[0050] The main portion and the peak portion of the input RF signal are amplified by the main amplifier 220 and the peak amplifier 230, respectively. Typically, the main amplifier 220 is biased in class AB or class B, while the peak amplifier 230 is biased in class C. Under power back-off conditions, only the main amplifier 220 amplifies the signal, while under saturated power conditions, both the main amplifier 220 and the peak amplifier 230 amplify the signal.

[0051] At the combining node C, the Doherty combiner 240 combines the signals amplified by the main amplifier 220 and the peak amplifier 230. To this end, the Doherty combiner 240 includes one or more delay elements 241, 242. The Doherty combiner 240 is configured to present a first impedance at the output of the main amplifier 220 under power back-off conditions, and a second impedance at the output of the main amplifier 220 under saturated power conditions, and a third impedance at the output of the peak amplifier 230 under saturated power conditions.

[0052] The second impedance and the third impedance cause the main amplifier 220 and the peak amplifier 230 to present their optimum load impedances for maximum power efficiency.

[0053] The Doherty combiner 240 is configured such that under power back-off conditions, the impedance seen at the combining node C towards the peak amplifier 230 corresponds to an RF open circuit.

[0054] In at least some embodiments, the delay element 241 includes an impedance transformer, such as embodied as a quarter-wavelength transformer or its electrical equivalent.

[0055] The combined phase delay imparted by the Doherty splitter 210, the main amplifier 220, the peak amplifier 230, and the Doherty combiner 240 ensures that the signals amplified by the main amplifier 220 and the peak amplifier 230 add in-phase at the combining node C.

[0056] The combining node C is connected to the load impedance ZL, optionally via an impedance matching network, which is embodied as a quarter-wavelength transformer 250 in Figure 4 .

[0057] In the context of the present invention, the Doherty combiner 240 includes a main branch and a peak branch, the main branch being between the output terminal of the main amplifier 220 and the combining node C, and the peak branch being between the output terminal of the peak amplifier 230 and the combining node C. At frequencies within the operating frequency range, the electrical length between the output terminal of the main amplifier 220 and the combining node C is equal to m×180 + 90 degrees, and at frequencies within the operating frequency range or an operating frequency range, the electrical length between the output terminal of the peak amplifier 230 and the combining node C is equal to n×180 degrees, where m and n are integers equal to or greater than zero.

[0058] According to the present invention, the conductive tracks including cavities, an embodiment of which is shown in Figure 1 are part of the main branch and / or the peak branch. This provides a compact and broadband solution. Figure 5 An example of such a Doherty amplifier is shown in

[0059] In Figure 5 , the Doherty amplifier 300 includes a transistor package 310 that includes a first power transistor serving as a main amplifier and a second transistor serving as a peak amplifier. Each power transistor has a separate output lead 311, 312 associated therewith.

[0060] The output leads 311, 312 are spaced a distance d apart, where d is in the range between 2 mm and 10 mm.

[0061] In Figure 5 , the dashed rectangle 380 indicates the portion of the Doherty amplifier 300 corresponding to the main amplifier and the main branch, and the dashed rectangle 381 indicates the portion of the Doherty amplifier 300 corresponding to the peak amplifier and the peak branch. As shown, the dashed rectangle 380 has components substantially the same as the Figure 1 components shown. For example, the main branch 380 includes a cavity-containing conductive track having a shunt SMD capacitor 380A, a series SMD capacitor 380B, and a shunt inductor 380C grounded using an SMD capacitor 380D. On the other hand, the dashed rectangle 381 indicates that the peak amplifier is connected to the combining node C using two transmission line segments 382, 383 having different characteristic impedances and / or electrical lengths. The transmission line segments 382, 383 are connected by a series SMD capacitor 384, which for the remainder of this discussion will be considered a DC blocking capacitor having negligible impedance at RF frequencies.

[0062] The transmission line segment 382 has a lower characteristic impedance than the transmission line segment 383. Under power back-off conditions, the transmission line segment 382 presents a reactive impedance at its end remote from the peak amplifier, such as an RF short when looking towards the peak amplifier. The transmission line segment 383, which may include a quarter-wavelength transformer, transforms this reactive impedance into an RF open seen at the combining node C.

[0063] Under saturated power conditions, the transmission line segments 382, 383 provide a given impedance at the output of the peak amplifier so that the peak amplifier can output saturated power. For a symmetric Doherty amplifier, this impedance is the same as the impedance provided at the main amplifier output terminals when operating under saturated power conditions. The characteristic impedance of the transmission line segment 383 can be such that under saturated power conditions, the transmission line segment 383 provides little or no impedance transformation.

[0064] In some embodiments, at saturation power conditions, the impedance presented by the main branch at the output of the main amplifier equals Zlow, and at power back-off conditions, the impedance presented by the main branch at the output of the main amplifier equals Zhigh. In some embodiments, Zlow can be equal to 1 / 2×Zhigh.

[0065] Figure 6 A circuit representing a Doherty amplifier 300 is shown. As shown, a transmission line segment such as a quarter-wavelength transformer 390 can be disposed between the output O and the combining node C. The quarter-wavelength transformer 390 can be configured to transform the impedance ZL of a load connected to the output O to a lower value.

[0066] From Figure 6 it can be observed that the main branch includes components identical to the Figure 3 components shown. The second power transistor Q2, which serves as a peak amplifier, has an output capacitance Cd2, and a DC bias is provided to the second power transistor Q2 through a bias inductor Lb2. The power transistor Q2 is connected to the combining node C through a first transmission line segment 382 modeled as a line segment having a characteristic impedance Z2 and an electrical length EL2, a series SMD capacitor 384 modeled as a capacitor C4, and a second transmission line segment 383 modeled as a line segment having a characteristic impedance Z3 and an electrical length EL3. Figure 5 The transmission line segment 390 in

[0067] Above, the present invention has been explained using detailed embodiments of the present invention. However, the present invention is not limited to these embodiments. Instead, various modifications are possible without departing from the scope of the present invention as defined by the appended claims and their equivalents.

Claims

1. A power amplifier circuit (100; 300), comprising: A transistor package (10; 310) comprising at least one power transistor (13; Q1, Q2) and having, for each power transistor, an output lead (17; 311, 312) electrically connected to an output terminal of the power transistor; and a substrate (20) on which the transistor package is arranged, wherein, for each output lead, the substrate comprises a conductive track to which the output lead is fixedly attached; Characterized in that the conductive track for at least one output lead forms a conductive track (25) including a cavity, the conductive track including a cavity including a cavity in which a shunt capacitor (27; 380A) is arranged, the shunt capacitor (27; 380A) having a first terminal (27A) and a grounded second terminal (27B), the first terminal being connected to the conductive track (25), the grounded second terminal (27B) being configured to be grounded during operation.

2. The power amplifier circuit according to claim 1, wherein: The conductive track including the cavity includes a first track portion (25A), a second track portion (25B) and a pair of spaced apart third track portions (25C), wherein the first track portion is fixedly connected to a corresponding output lead, each third track portion connects the first track portion to the second track portion, wherein the cavity is disposed between the third track portions, the first track portion and the second track portion; Wherein, the first terminal is directly connected to the first rail portion or the second rail portion.

3. The power amplifier circuit according to claim 2, wherein: The first rail portion, the second rail portion, and the pair of third rail portions are formed of rail portions each having a constant width.

4. The power amplifier circuit according to claim 3, wherein: The first track portion, the second track portion, and the pair of third track portions are formed of microstrip lines.

5. The power amplifier circuit according to claim 1, wherein: At least one conductive track including a cavity includes a first end and an oppositely disposed second end, wherein the first end is fixedly connected to a corresponding output lead and the second end is connected to a first terminal (30A) of a series capacitor (30), wherein a second terminal (30B) of the series capacitor is connected to a shunt inductor (31).

6. The power amplifier circuit according to claim 5, wherein: The electrical behavior associated with the at least one cavity-including conductive track between an output terminal of a corresponding power transistor and the second terminal of the series capacitor corresponds to that of a bandpass filter having a passband containing an operating frequency of the power amplifier circuit.

7. The power amplifier circuit according to claim 1, wherein: The power amplifier circuit is a Doherty amplifier, wherein a first power transistor (Q1) of the at least one power transistor forms a main amplifier (220) of the Doherty amplifier, and a second power transistor (Q2) of the at least one power transistor forms a peak amplifier (230) of the Doherty amplifier; The power amplifier circuit comprises a Doherty combiner (210), the Doherty combiner is used to combine the signals from the main amplifier and the peak amplifier at a combining node (C), the Doherty combiner comprises a main branch and a peak branch, the main branch is between the output terminal of the main amplifier and the combining node, and the peak branch is between the output terminal of the peak amplifier and the combining node; wherein a conductive track for the main amplifier is comprised in the main branch, and wherein a conductive track for the peak amplifier is comprised in the peak branch.

8. The power amplifier circuit according to claim 7, wherein: The main branch is configured as: providing a first effective impedance seen at an output terminal of the first power transistor in a power back-off state in which the second power transistor is turned off; as well as providing a second effective impedance seen at an output terminal of the first power transistor in a saturated output power state in which the first power transistor and the second power transistor output saturated power; Wherein, the first effective impedance is greater than the second effective impedance.

9. The power amplifier circuit according to claim 8, wherein: The peak branch is configured as: In the saturated output power state, a third effective impedance seen at the output terminal of the second power transistor is provided.

10. The power amplifier circuit according to claim 7, wherein: At a frequency within the operating frequency range, the electrical length between the output terminal of the first power transistor and the combining node is equal to m×180+90 degrees, and wherein, at a frequency within an operating frequency range or within the operating frequency range, the electrical length between the output terminal of the second power transistor and the combining node is equal to n×180 degrees, wherein m and n are integers equal to or greater than zero.

11. The power amplifier circuit according to claim 7, wherein: The conductive track for the main amplifier is configured as a conductive track (25) comprising a cavity as defined in any one of claims 1 to 5 and comprises a first end and an opposite second end, the first end being connected to an output lead (311) for the first power transistor and the second end being connected to the combining node.

12. The power amplifier circuit according to claim 11, wherein: The main branch comprises a main branch series capacitor (380B), wherein the second end of the conductive track including the cavity for the main branch is connected to the combining node through the main branch series capacitor, the first terminal of the main branch series capacitor is connected to the second end of the conductive track including the cavity for the main branch, and the second terminal of the main branch series capacitor is connected to the combining node.

13. The power amplifier circuit according to claim 12, wherein: The main branch further comprises a main branch shunt inductor (380C), the main branch shunt inductor being connected to the second terminal of the main branch series capacitor, wherein the main branch shunt inductor preferably comprises a first terminal connected to the second terminal of the main branch series capacitor and a second terminal preferably connected to ground via a first DC blocking capacitor (380D) or via a through hole; Therein, the electrical behavior of the main branch between the output terminal of the first power transistor and the second terminal of the main branch series capacitor corresponds to the electrical behavior of a bandpass filter having a passband including the operating frequency of the power amplifier circuit.

14. The power amplifier circuit according to claim 7, wherein: The conductive track for the peaking amplifier is configured as a conductive track comprising a cavity as defined in claim 1 and comprises a first end connected to an output lead for the second power transistor and an opposite second end connected to the combining node.

15. The power amplifier circuit according to claim 14, wherein: The peak branch comprises a peak branch series capacitor, wherein the second end of the conductive track including the cavity for the peak branch is connected to the combining node via the peak branch series capacitor, a first terminal of the peak branch series capacitor is connected to the second end of the conductive track including the cavity for the peak branch, and a second terminal of the peak branch series capacitor is connected to the combining node.

16. The power amplifier circuit according to claim 15, wherein: The peak branch further comprises a peak branch shunt inductor connected to the second terminal of the peak branch series capacitor, wherein the peak branch shunt inductor preferably comprises a first terminal connected to the second terminal of the peak branch series capacitor and a second terminal preferably connected to ground via a second DC blocking capacitor; wherein the electrical behavior of the peaking branch between the output terminal of the second power transistor and the second terminal of the peaking branch series capacitor corresponds to the electrical behavior of a bandpass filter having a passband that includes the operating frequency of the power amplifier circuit; The peak branch further includes an offset transmission line, and the offset transmission line is connected between the second terminal of the peak branch series capacitor and the combining node.

17. The power amplifier circuit according to claim 7, wherein: The output lead for the first power transistor and the output lead for the second power transistor are disposed adjacent to each other in a first direction and are spaced apart from each other by a distance (d) of 2 mm to 10 mm in the first direction.

18. The power amplifier circuit according to claim 1, wherein: Each of the at least one power transistor is a field effect transistor, wherein each field effect transistor preferably comprises a gallium nitride based field effect transistor or a silicon based laterally diffused metal oxide semiconductor transistor.

19. The power amplifier circuit according to claim 1, wherein: The substrate (20) comprises an upper metal layer (22B), one or more dielectric layers (21) and a lower metal layer (22A), wherein one or more conductive tracks are implemented in the upper metal layer (22B), and the substrate comprises one or more through holes (23) for connecting the upper metal layer to the lower metal layer; Wherein, second terminals of one or more shunt capacitors for the one or more conductive tracks comprising the cavity are electrically and / or fixedly connected to the one or more through-holes.

20. The power amplifier circuit according to any one of claims 1 to 19, wherein: The substrate comprises a metal sheet (24), preferably made of copper, located at a position on the substrate where the transistor package is arranged.

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