A signal preprocessing circuit
Through the combination of the primary multiplexer, secondary multiplexer and signal processing module in the signal preprocessing circuit, the problem of difficulty in flexible processing before the signal input chip pin is solved, and the circuit area saving and signal processing flexibility is achieved, and it is suitable for signal preprocessing in electronic circuits.
Patent Information
- Application Number
- CN202510517818.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2045-04-24
AI Technical Summary
It is difficult to flexibly pre-process the existing signal input chip pins before the existing signal input chip pins, resulting in an increase in circuit area and cost. The existing circuit needs to be designed for specific scenarios and increase the R&D cycle, which is not conducive to product miniaturization.
The signal preprocessing circuit of at least one first-level multiplexer, at least one second-level multiplexer, a signal processing module and several source receiving terminals is adopted to realize flexible signal processing by setting the on or off state of the gate port and output to the subsequent chip module.
Save circuit area, improve the multiplexing of signal processing modules, realize low-pass, high-pass, band-pass filtering and logic operations of signals, and improve the flexibility and efficiency of signal processing.
Smart Images
Figure CN120049864B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and particularly relates to a signal preprocessing circuit. Background Art
[0002] With the development of electronic technology, a large number of chips are applicable to electronic circuits to implement the processing of input signals. In order to obtain high-quality signals and improve the signal processing effect, it is necessary to preprocess the signals before inputting them into the chip pins. Usually, before using a chip to process signals, the input signals are filtered, and commonly a digital filter is used to achieve this. However, the setting method of the digital filter is relatively single, and it can only filter the signals input from a fixed signal input terminal; if a digital filter is set for each signal input terminal, the circuit area and cost are unacceptable. Similarly, in some scenarios, before the signal is input into the chip pin, it is necessary to perform logical operations on the input signal, and the existing circuits need to be designed for specific scenarios, which increases the R & D cycle and is not conducive to the miniaturization of products. Aiming at the problem of inflexible preprocessing methods before the signal is input into the pin, there is an urgent need for a signal preprocessing circuit to solve the above technical problems. Summary of the Invention
[0003] In order to solve the problem that it is difficult to flexibly preprocess the signal before it is input into the chip pin, the present application provides the following technical solutions:
[0004] Provide a signal preprocessing circuit, including: at least one first-level multiplexer, at least one second-level multiplexer, a signal processing module, and several signal source receiving ends.
[0005] Any one of the at least one first-level multiplexer has: a first-level signal selection port and a first-level signal output port.
[0006] Any one of the at least one second-level multiplexer has: a second-level signal selection port and a second-level signal output port.
[0007] The signal processing module has: a module input port and a module output port.
[0008] Any one of the several signal source receiving ends is correspondingly connected to the first-level signal selection port of any one of the at least one first-level multiplexer, any one of the first-level signal output ports is correspondingly connected to the module input port, and the module output port is correspondingly connected to the second-level signal selection port of any one of the at least one second-level multiplexer.
[0009] By setting the on or off state of the first-level signal selection port and the second-level signal selection port, the signal obtained by any one of the several signal source receiving ends is processed by the signal processing module and then transmitted to a preset second-level signal output port.
[0010] Further, the signal processing module includes at least one signal processing unit.
[0011] Any one of the at least one signal processing unit has a signal processing input port and a signal processing output port.
[0012] The signal processing input ports serve as the module input ports in a one-to-one correspondence, and the signal processing output ports serve as the module output ports in a one-to-one correspondence.
[0013] The signal processing unit processes the signal obtained from the corresponding signal processing input port and outputs it from the corresponding signal processing output port.
[0014] Further, the secondary multiplexer further includes a source input port, and the source input port is connected to a plurality of source receiving ends in a one-to-one correspondence.
[0015] Further, the circuit further includes at least one tertiary multiplexer.
[0016] Any one of the at least one tertiary multiplexer has: a tertiary signal input port and a tertiary signal gating port.
[0017] The tertiary signal input ports are connected to the secondary signal output ports in a one-to-one correspondence.
[0018] The tertiary signal gating port outputs the signal transmitted by the secondary signal gating port that is set to be conductive among the secondary signal gating ports of the corresponding connected secondary multiplexer.
[0019] Further, the number of tertiary multiplexers is equal to the number of secondary multiplexers.
[0020] Further, the circuit further includes: a channel selection module.
[0021] The channel selection module is connected to the primary multiplexer, the secondary multiplexer, and the tertiary multiplexer, and is used to set the on or off states of the primary signal gating port, the secondary signal gating port, and the tertiary signal gating port.
[0022] Further, the signal processing module includes a first signal processing unit.
[0023] The first signal processing unit has at least two first unit signal input ports and a first unit signal output port.
[0024] At least two of the first unit signal input ports serve as the module input ports in a one-to-one correspondence.
[0025] The first unit signal output port serves as the module output port.
[0026] Further, the first signal processing unit is a logic operation unit.
[0027] The logic operation unit includes one or a combination of at least two of the following: basic logic gates, arithmetic units, numerical comparators, selectors, distributors, parity checkers, shift operation units, encoders, decoders, and numerical converters.
[0028] Furthermore, the signal processing module includes: a second signal processing unit and a third signal processing unit.
[0029] The second signal processing unit has a second unit signal output port, and the third signal processing unit has a third unit signal output port.
[0030] The first-level multiplexer also has a processing signal receiving port.
[0031] The second unit signal output port is connected to the processing signal receiving port of the first-level multiplexer connected to the third unit signal processing unit.
[0032] The third unit signal output port is connected to the processing signal receiving port of the first-level multiplexer connected to the second unit signal processing unit.
[0033] Furthermore, the second signal processing unit is a low-pass filter, and the third signal processing unit is a high-pass filter.
[0034] By setting the conduction or cutoff of the selection ports of the signal preprocessing circuit described in the embodiments of the present application, a group of signal processing modules are used to process the input signals of any signal source and output them to the corresponding subsequent chip modules. This saves circuit area and improves the multiplexing degree of the signal processing modules. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0036] Figure 1 It is a schematic diagram of a signal preprocessing circuit module provided by an embodiment of the present application;
[0037] Figure 2 It is a schematic diagram of a signal preprocessing module provided by an embodiment of the present application;
[0038] Figure 3 It is a schematic diagram of a signal and processing circuit module including a three-level multiplexer provided by an embodiment of the present application;
[0039] Figure 4 It is another schematic diagram of a signal preprocessing circuit provided by an embodiment of the present application;
[0040] Figure 5 It is a schematic diagram of a signal preprocessing circuit including a source input port provided by an embodiment of the present application;
[0041] Figure 6 It is a schematic diagram of a signal preprocessing circuit including second and third signal processing units provided by an embodiment of the present application;
[0042] Figure 7 It is a schematic diagram of a signal and processing circuit including a first signal processing unit provided by an embodiment of the present application. Detailed implementation manners
[0043] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only a part rather than all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts fall within the scope of protection of the present application.
[0044] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which this disclosure belongs. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The numbers in the accompanying drawings of the specification only represent the distinction of each functional component or module, and do not represent the logical relationship between the components or modules. The terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0045] Next, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structures and functions, and repeated descriptions thereof will be omitted.
[0046] In view of the problem that it is difficult to flexibly perform signal preprocessing before the signal enters the chip pin, the present application provides the following embodiments.
[0047] In some embodiments, as Figure 1 As shown, a signal pre-processing circuit is provided before the chip pin. It includes: at least one first-level multiplexer 100, at least one second-level multiplexer 200, a signal processing module 300 and several signal source receiving terminals S n , where n is a natural number used to distinguish several signal source and receiver terminals.
[0048] Any one of the at least one first-level multiplexers 100 has: a first-level signal selection port 100 si And the first level signal output port 100 so .
[0049] Any secondary multiplexer 200 in at least one secondary multiplexer has: a secondary signal selection port 200 si And secondary signal output port 200 so .
[0050] The signal processing module 300 has: a module input port 300 i And module output port 300 o .
[0051] Any one of several source receiving terminals S n With any one of the first-level multiplexer signal selection port 100 si One-to-one connection, any level one signal output port 100 so With module input port 300 i One-to-one connection, module output port 300 o With any secondary multiplexer secondary signal strobe port 200 si One-to-one connection.
[0052] By setting the first level signal to select port 100 si And the secondary signal strobe port 200 si The on or off state of any of the multiple signal source receiving terminals S n The acquired signal is processed by the signal processing module 300 and then transmitted to the preset secondary signal output port 200. so .
[0053] Schematically, the above-mentioned signal source receiving end is the signal input pin of the chip.
[0054] Specifically, if Figure 2 As shown, the signal processing module 300 includes at least one signal processing unit 310 .
[0055] Any signal processing unit 310 in at least one signal processing unit has: a signal processing input port 310i and a signal processing output port 310 o .
[0056] The signal processing input port 310 i correspondingly serves as the module input port 300 i , and the signal processing output port 310 o correspondingly serves as the module output port 300 o .
[0057] The signal processing unit 310 processes the signal obtained by the corresponding signal processing input port 310 i , and outputs it through the corresponding signal processing output port 310 o .
[0058] Optionally, the secondary multiplexer 200 further includes a source input port, and the source input port is connected to a plurality of source receiving ends S n in one-to-one correspondence.
[0059] Preferably, as Figure 3 shown, the circuit further includes at least one tertiary multiplexer 400.
[0060] Any one of the at least one tertiary multiplexer 400 has: a tertiary signal input port 400 si and a tertiary signal gating port 400 so .
[0061] The tertiary signal input port 400 si is connected to the secondary signal output port 200 so in one-to-one correspondence.
[0062] The tertiary signal gating port 400 so outputs the signal transmitted by the secondary signal gating port 200 that is set to be conductive among the secondary signal gating ports of the corresponding secondary multiplexer 200 si .
[0063] The number of tertiary multiplexers is equal to the number of secondary multiplexers.
[0064] Preferably, the tertiary signal gating port 400 so is connected to the module. The selected path transmits the signal from the preset source receiving end to the corresponding module for processing.
[0065] Preferably, the circuit further includes: a channel selection module.
[0066] The channel selection module generates control signals for controlling the conduction of corresponding multiplexer channels. Schematically, a multiplexer has four channels. Control signal 00 indicates selecting the first channel, control signal 01 indicates selecting the second channel, control signal 10 indicates selecting the third channel, and control signal 11 indicates selecting the fourth channel.
[0067] The channel selection module is connected to a first-level multiplexer, a second-level multiplexer, and a third-level multiplexer (not shown in the figure) for setting the conduction or cutoff states of the first-level signal selection port, the second-level signal selection port, and the third-level signal selection port.
[0068] In some other embodiments, as Figure 7 shown, the signal processing module 300 includes a first signal processing unit 310a.
[0069] The first signal processing unit 310a has at least two first unit signal input ports 310a i , and a first unit signal output port 310a o .
[0070] At least two first unit signal input ports 310a i correspondingly serve as module input ports 300 i .
[0071] The first unit signal output port 310a o serves as module output port 300 o .
[0072] Specifically, the first signal processing unit is a logic operation unit.
[0073] The logic operation unit includes: one or a combination of at least two of basic logic gates, arithmetic units, numerical comparators, selectors, distributors, parity checkers, shift operation units, encoders, decoders, and numerical converters.
[0074] Schematically, the basic logic gates include at least one of: AND gates, OR gates, NAND gates, NOR gates, XOR gates, and XNOR gates.
[0075] The arithmetic units include at least one of: half adders, full adders, half subtractors, full subtractors, and carry generators.
[0076] The numerical comparators include at least one of: one-bit comparators and multi-bit comparators.
[0077] The encoder includes at least: a priority encoder.
[0078] The decoder includes at least: a binary decoder.
[0079] In some other embodiments, asFigure 6 As shown, the signal processing module 300 includes: a second signal processing unit 310b and a third signal processing unit 310c.
[0080] The second signal processing unit 310b has a second unit signal output port 310b o and the third signal processing unit has a third unit signal output port 310c o .
[0081] The first-level multiplexer 100 also has a processing signal receiving port 100 pi .
[0082] The second unit signal output port 310b o is connected to the processing signal receiving port 100 of the first-level multiplexer 100 connected to the third signal processing unit 310c pi .
[0083] The third unit signal output port 310c o is connected to the processing signal receiving port 100 of the first-level multiplexer 100 connected to the second signal processing unit 310b pi .
[0084] Optionally, the second signal processing unit 310b is a low-pass filter and the third signal processing unit 310c is a high-pass filter.
[0085] By setting the conduction or cutoff of the selected ports of the signal preprocessing circuit described in the embodiments of the present application, a group of signal processing modules are used to process the input signals of any signal source and output them to the corresponding subsequent chip modules, enabling low-pass, high-pass, and band-pass filtering of signals and logical operations on signals, saving circuit area, and improving the multiplexing degree of the signal processing module.
[0086] Embodiment 1
[0087] A signal preprocessing circuit, as Figure 4 shown, includes four first-level multiplexers 100, four second-level multiplexers 200, four third-level multiplexers 400, a signal processing module 300, and four signal source receiving ends.
[0088] The signal source receiving ends are respectively: a first signal source receiving end S1, a second signal source receiving end S2, a third signal source receiving end S3, and a fourth signal source receiving end S4.
[0089] Any one of the first-level multiplexers 100 respectively has four first-level signal selection ports 100 si , and a first-level signal output port 100 so .
[0090] Each secondary multiplexer 200 respectively has four secondary signal gating ports 200 si , and one secondary signal output port 200 so .
[0091] Each tertiary multiplexer 400 respectively has a number of tertiary signal gating ports 400 so , and one tertiary signal input port 400 si .
[0092] The signal processing module 300 has four module input ports 300 i and four module output ports 300 o .
[0093] The signal processing module 300 includes four signal processing units 310.
[0094] Each signal processing unit 310 has: a signal processing input port 310 i and a signal processing output port 310 o .
[0095] The signal processing input port 310 i corresponds one-to-one to the module input port 300 i , and the signal processing output port 310 o corresponds one-to-one to the module output port 300 o .
[0096] The signal processing unit 310 processes the signal obtained by the corresponding signal processing input port 310 i , and outputs it through the corresponding signal processing output port 310 o .
[0097] Optionally, each signal processing unit 310 is one of a low-pass filter, a high-pass filter, a band-pass filter, and a special filter.
[0098] Preferably, the above filters are digital filters.
[0099] Any signal source receiving end is connected in one-to-one correspondence with a primary signal gating port 100 of any primary multiplexer si , and any primary signal output port 100 so is connected in one-to-one correspondence with the module input port 300 i , and any module output port 300 o is connected in one-to-one correspondence with a secondary signal gating port 200 of any secondary multiplexer si . The secondary signal output port 200 so is connected in one-to-one correspondence with the tertiary signal input port 400 si .
[0100] The circuit further includes a channel selection module ( Figure 4 not shown in the figure). Through the channel selection module, Figure 4 in the figure, the first primary signal selection port 100 of the second primary multiplexer from top to bottom si is set to be conductive, the second secondary signal selection port 200 of the third secondary multiplexer 200 from top to bottom si is set to be conductive, and the first tertiary signal selection port 400 of the third tertiary multiplexer 400 from top to bottom so is set to be conductive.
[0101] The signal input from the first signal source receiving end S1 passes through the second primary multiplexer 100 from top to bottom, is processed by the second signal processing unit 310 from top to bottom in the signal processing module 300, and then is output from the secondary signal output port 200 of the third secondary multiplexer 200 from top to bottom so and transmitted to the first tertiary signal selection port 400 of the third tertiary multiplexer 400 from top to bottom so , as shown by the arrow path in the figure. The first tertiary signal selection port 400 of the third tertiary multiplexer 400 from top to bottom Figure 4 is connected to module 31 for module 31 to process the signal. so
[0102] In this embodiment, by changing the settings of the channel selection module, other signal paths can also be selected. For example: the second primary signal selection port 100 of the first primary multiplexer from top to bottom si is set to be conductive, the first secondary signal selection port 200 of the second secondary multiplexer from top to bottom si is set to be conductive, and the first tertiary signal selection port 400 of the second tertiary multiplexer from top to bottom si is set to be conductive. so
[0103] The signal input from the second signal source receiving end S2 passes through the first multiplexer from top to bottom, is processed by the first signal processing unit from top to bottom in the signal processing module, and then is transmitted from the first secondary signal selection port of the second secondary multiplexer from top to bottom to the first tertiary signal selection port 400 of the second tertiary multiplexer from top to bottom so and transmitted to module 21 to process the signal.
[0104] Multiple signal path settings can also be performed simultaneously for the corresponding modules to process signals simultaneously.
[0105] Embodiment 2
[0106] A signal preprocessing circuit, as shown in Figure 5As shown, it includes two first-level multiplexers 100, four second-level multiplexers 200, four third-level multiplexers 400, a signal processing module 300, and four source receiving ends.
[0107] The source receiving ends are respectively: the first source receiving end S1, the second source receiving end S2, the third source receiving end S3, and the fourth source receiving end S4.
[0108] Any one of the first-level multiplexers 100 respectively has four first-level signal selection ports 100 si , and a first-level signal output port 100 so .
[0109] Any one of the second-level multiplexers 200 respectively has two second-level signal selection ports 200 si , and a second-level signal output port 200 so . Figure 5 The first second-level multiplexer 200 from top to bottom in it also has two source input ports 200 ssi , which are respectively connected to the first source receiving end S1 and the second source receiving end S2.
[0110] Any one of the third-level multiplexers 400 respectively has a number of third-level signal selection ports 400 so , and a third-level signal input port 400 si .
[0111] The signal processing module 300 has two module input ports 300 i and two module output ports 300 o .
[0112] The signal processing module 300 includes two signal processing units 310.
[0113] Any one of the signal processing units 310 has: a signal processing input port 310 i and a signal processing output port 310 o .
[0114] The signal processing input port 310 i corresponds one by one to be used as the module input port 300 i , and the signal processing output port 310 o corresponds one by one to be used as the module output port 300 o .
[0115] The signal processing unit 310 processes the signal obtained by the corresponding signal processing input port 310 i , and outputs it from the corresponding signal processing output port 310 o .
[0116] Optionally, each signal processing unit 310 is one of a low-pass filter, a high-pass filter, a band-pass filter, and a special filter.
[0117] Preferably, the above filters are digital filters.
[0118] Any source receiving end is connected in one-to-one correspondence with a first-stage signal selection port 100 of any one of the first-stage multiplexers si Any one of the first-stage signal output ports 100 so is connected in one-to-one correspondence with the module input port 300 i Any module output port 300 o is connected in one-to-one correspondence with a second-stage signal selection port 200 of any one of the second-stage multiplexers si The second-stage signal output port 200 so is connected in one-to-one correspondence with the third-stage signal input port 400 si in one-to-one correspondence.
[0119] The circuit further includes a channel selection module ( Figure 5 not shown in the figure). Through the channel selection module, Figure 5 in the figure, the third first-stage signal selection port 100 of the second first-stage multiplexer from top to bottom si is set to be conductive, and the second second-stage signal selection port 200 of the third second-stage multiplexer 200 from top to bottom si is set to be conductive, and the first third-stage signal selection port 400 of the third third-stage multiplexer 400 from top to bottom so is set to be conductive.
[0120] The signal input from the third source receiving end S3 passes through the third first-stage multiplexer 100 from top to bottom, is processed by the second signal processing unit 310 from top to bottom in the signal processing module 300, and then passes through the second-stage signal output port 200 of the third second-stage multiplexer 200 from top to bottom so and is transmitted to the first third-stage signal selection port 400 of the third third-stage multiplexer 400 from top to bottom so , as Figure 5 shown by the solid arrow path in the figure. The first third-stage signal selection port 400 of the third third-stage multiplexer 400 from top to bottom so is connected to module 31 for module 31 to process the signal.
[0121] Through the channel selection module, Figure 5 in the figure, the first source input port 200 of the first second-stage multiplexer 200 from top to bottom ssi is set to be conductive, and the first third-stage signal selection port 400 of the first third-stage multiplexer 400 from top to bottom soSet to conduct. The first three-stage signal selection port 400 of the first three-stage multiplexer 400 from top to bottom so is connected to Module 11, and the signal received by the first signal source receiving end S1 is transmitted to Module 11 for processing, such as Figure 5 shown by the dashed arrow in the figure.
[0122] The setting method of the channel selection module is as described in Embodiment 1, and will not be elaborated here.
[0123] Embodiment 3
[0124] A signal preprocessing circuit, as Figure 6 shown, includes two first-stage multiplexers 100, four second-stage multiplexers 200, four third-stage multiplexers 400, a signal processing module 300, and four signal source receiving ends.
[0125] The signal source receiving ends are respectively: the first signal source receiving end S1, the second signal source receiving end S2, the third signal source receiving end S3, and the fourth signal source receiving end S4.
[0126] Any one of the first-stage multiplexers 100 respectively has four first-stage signal selection ports 100 si , and one first-stage signal output port 100 so .
[0127] Any one of the second-stage multiplexers 200 respectively has two second-stage signal selection ports 200 si , and one second-stage signal output port 200 so .
[0128] Any one of the third-stage multiplexers 400 respectively has several third-stage signal selection ports 400 so , and one third-stage signal input port 400 si .
[0129] The signal processing module 300 has two module input ports 300 i and two module output ports 300 o .
[0130] The signal processing module 300 includes a second signal processing unit 310b and a third signal processing unit 310c.
[0131] The second signal processing unit has: a second signal unit input port 310b i and a second unit signal output port 310b o .
[0132] The third signal processing unit has: a third signal unit input port 310c i and a third unit signal output port 310c o。
[0133] The second signal processing unit 310b is a low-pass filter, and the third signal processing unit 310c is a high-pass filter.
[0134] Preferably, the above filters are digital filters.
[0135] Any one of the first-level multiplexers also has a signal reception port 100 for processing signals sri 。
[0136] The second unit signal output port 310b o is connected to the signal reception port 100 for processing signals of the first-level multiplexer connected to the third unit signal processing unit sri ;
[0137] The third unit signal output port 310c o is connected to the signal reception port 100 for processing signals of the first-level multiplexer connected to the second unit signal processing unit sri ;
[0138] The second signal unit input port 310b i serves as a module input port 300 i , and the third signal unit input port 310c i serves as another module input port 300 i 。
[0139] The signal processing input port 310 i serves as a module input port 300 one by one i , and the signal processing output port 310 o serves as a module output port 300 one by one o 。
[0140] The signal processing unit 310 processes the signals obtained from the corresponding signal processing input port 310 i and outputs them from the corresponding signal processing output port 310 o 。
[0141] Any signal source receiving end is connected to a signal selection port 100 of any one of the first-level multiplexers one by one si , and any one of the signal output ports 100 so is connected to the module input port 300 one by one i , and any module output port 300 o is connected to a signal selection port 200 of any one of the second-level multiplexers one by one si . The second-level signal output port 200 so is connected to the third-level signal input port 400 one by one si 。
[0142] The circuit further includes a channel selection module ( Figure 6 not shown in the figure). Through the channel selection module, Figure 6 in the figure, the third first-level signal selection port 100 of the second first-level multiplexer from top to bottom si is set to be conductive, the first second-level signal selection port 200 of the third second-level multiplexer 200 from top to bottom si is set to be conductive, and the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is set to be conductive.
[0143] The signal input from the third signal source receiving end S3 passes through the third first-level multiplexer 100 from top to bottom, and successively passes through the third signal processing unit 310c and the second signal processing unit 310b, and is transmitted from the second-level signal output port 200 of the third second-level multiplexer 200 from top to bottom so to the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so , as Figure 6 shown by the arrow path in the figure. The first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is connected to module 31 for module 31 to process the signal.
[0144] The setting method of the channel selection module is as described in Embodiment 1 and will not be elaborated here.
[0145] Embodiment 4
[0146] A signal preprocessing circuit, as Figure 7 shown in the figure, includes two first-level multiplexers 100, four second-level multiplexers 200, four third-level multiplexers 400, a signal processing module 300, and four signal source receiving ends.
[0147] The signal source receiving ends are respectively: the first signal source receiving end S1, the second signal source receiving end S2, the third signal source receiving end S3, and the fourth signal source receiving end S4.
[0148] Any one of the first-level multiplexers 100 respectively has four first-level signal selection ports 100 si , and one first-level signal output port 100 so .
[0149] Any one of the second-level multiplexers 200 respectively has two second-level signal selection ports 200 si , and one second-level signal output port 200 so .
[0150] Any one of the third-level multiplexers 400 respectively has a plurality of third-level signal selection ports 400so , and a third-level signal input port 400 si .
[0151] The signal processing module 300 has two module input ports 300 i and a module output port 300 o .
[0152] The signal processing module 300 includes a first signal processing unit 310a.
[0153] The first signal processing unit 310a has: two first signal unit input ports 310a i and a first unit signal output port 310a o .
[0154] The first signal processing unit 310a is a logic operation unit.
[0155] The logic operation unit includes: one or at least two combinations of basic logic gates, arithmetic units, numerical comparators, selectors, distributors, parity checkers, shift operation units, encoders, decoders, and numerical converters.
[0156] The two first signal unit input ports 310 ai serve as the module input ports 300 respectively i , and the first unit signal output port 310 ao serves as the module output port 300 o .
[0157] The signal processing unit 310 processes the signals obtained from the corresponding first signal unit input ports 310 ai and outputs them from the corresponding signal processing output ports 310 o .
[0158] Any signal source receiving end is connected to a signal gating port 100 of any first-level multiplexer si in a one-to-one correspondence, and any first-level signal output port 100 so is connected to the module input port 300 i in a one-to-one correspondence. Any module output port 300 o is connected to a second-level signal gating port 200 of any second-level multiplexer si in a one-to-one correspondence. The second-level signal output port 200 so is connected to the third-level signal input port 400 si in a one-to-one correspondence.
[0159] The circuit further includes a channel selection module ( Figure 7 not shown in the figure). Through the channel selection module, Figure 7Among them, the first first-level signal selection port 100 of the first first-level multiplexer from top to bottom si , and the second and signal selection ports 100 of the second first-level multiplexer si are set to be conductive; the first second-level signal selection port 200 of the third second-level multiplexer 200 from top to bottom si is set to be conductive, and the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is set to be conductive.
[0160] The signal input by the first signal source receiving end S1 and the second signal source receiving end S2 is logically operated by the first signal processing unit 310a and then transmitted to the first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so , as Figure 7 shown by the arrow path in. The first third-level signal selection port 400 of the third third-level multiplexer 400 from top to bottom so is connected to module 31 for module 31 to process the signal.
[0161] The setting method of the channel selection module is as described in the first embodiment and will not be elaborated here.
[0162] All the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present application, which will not be elaborated one by one here.
[0163] Note that the above is only the preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A signal preprocessing circuit, characterized in that, Including: At least one first-level multiplexer, at least one second-level multiplexer, a signal processing module, and several source receiving ends; Any one of the at least one first-level multiplexers has: a first-level signal selection port and a first-level signal output port; Any one of the at least one second-level multiplexers has: a second-level signal selection port and a second-level signal output port; The signal processing module has: a module input port and a module output port; Any one of the several source receiving ends is connected to the first-level signal selection port of any one of the first-level multiplexers in a one-to-one correspondence, any one of the first-level signal output ports is connected to the module input port in a one-to-one correspondence, and the module output port is connected to the second-level signal selection port of any one of the second-level multiplexers in a one-to-one correspondence; By setting the on or off state of the first-level signal selection port and the second-level signal selection port, the signal obtained by any one of the several source receiving ends is transmitted to a preset second-level signal output port after being processed by the signal processing module; Wherein, the signal processing module includes: a second signal processing unit and a third signal processing unit, and the second signal processing unit and the third signal processing unit are digital filters; The second signal processing unit has a second unit signal output port; The third signal processing unit has a third unit signal output port; The first-level multiplexer also has a processing signal receiving port; the second unit signal output port is connected to the processing signal receiving port of the first-level multiplexer connected to the third unit signal processing unit; the third unit signal output port is connected to the processing signal receiving port of the first-level multiplexer connected to the second unit signal processing unit.
2. The signal preprocessing circuit according to claim 1, wherein The signal processing module includes at least one signal processing unit; Any one of the at least one signal processing units has a signal processing input port and a signal processing output port; The signal processing input port serves as the module input port in a one-to-one correspondence, and the signal processing output port serves as the module output port in a one-to-one correspondence; The signal processing unit processes the signal obtained by the corresponding signal processing input port and outputs it from the corresponding signal processing output port.
3. The signal preprocessing circuit according to claim 1, wherein The second-level multiplexer further includes a source input port; The source input port is connected to the several source receiving ends in a one-to-one correspondence.
4. The signal preprocessing circuit according to claim 1, wherein The circuit further includes at least one third-level multiplexer; Any one of the at least one third-level multiplexers has: a third-level signal input port and a third-level signal selection port; The third-level signal input port is connected to the second-level signal output port in a one-to-one correspondence; The third-level signal selection port outputs the signal received by the second-level signal selection port that is set to be on among the second-level signal input ports of the corresponding connected second-level multiplexer.
5. The signal preprocessing circuit according to claim 4, wherein The number of the third-level multiplexers is equal to the number of the second-level multiplexers.
6. The signal preprocessing circuit according to claim 1, wherein The circuit further includes: a channel selection module; The channel selection module is connected to the first-level multiplexer, the second-level multiplexer, and the third-level multiplexer, and is used to set the on or off state of the first-level signal selection port, the second-level signal selection port, and the third-level signal selection port.
7. The signal preprocessing circuit according to any one of claims 1-6, characterized in that, The signal processing module includes a first signal processing unit; The first signal processing unit has at least two first unit signal input ports and a first unit signal output port; The at least two first unit signal input ports serve as the module input ports in a one-to-one correspondence; The first unit signal output port serves as the module output port.
8. The signal preprocessing circuit according to claim 7, wherein The first signal processing unit is a logic operation unit; The logic operation unit includes one or a combination of at least two of the following: basic logic gates, arithmetic units, numerical comparators, selectors, distributors, parity checkers, shift operation units, encoders, decoders, and numerical converters.
9. The signal preprocessing circuit according to claim 1, wherein The second signal processing unit is a low-pass filter, and the third signal processing unit is a high-pass filter.
Citation Information
Patent Citations
Signal transmission module, integrated circuit, electronic device and vehicle
CN119849391A
Test auxiliary device and system
CN222674326U