High-speed gating unit circuit

Abstract

The invention discloses a high-speed gating unit circuit which comprises a data input circuit, a data latch circuit and a data driving circuit which are connected in sequence. The data driving circuit quickly outputs the latched control signal to an output signal Q; the data latch circuit synchronizes the sampled enable signal value with a clock signal CK; the data input circuit receives an enable signal; each circuit is controlled by a clock signal CK; when the clock signal CK is at a low level, the data input circuit receives a new enable signal, and the data output signal Q is directly controlled by a complementary signal CKN of the clock signal CK and the clock signal CK in the data driving circuit to be pulled down to the low level; and when the clock signal CK is at a high level, the data latch circuit is in a maintenance state, and the data driving circuit is driven to update the value of the output signal Q. The circuit delay can be effectively reduced, and the circuit has the characteristic of high speed.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of digital logic circuits, and particularly relates to a high-speed gating unit circuit. Background Art

[0002] As Figure 1 shown, in modern digital circuit design, a gating circuit is a basic unit of digital circuit design, which is used to reduce clock flips and thus reduce circuit power consumption. The gating circuit is located in the clock tree, and more than 90% of the units in the clock tree are inverters or buffers. There are significant differences in the delays of different clock units, which makes it difficult to balance the clock tree branches with gating units and those without gating units. With the continuous reduction of the process, the number of design patterns and PVT (process, voltage & temperature) corners increases exponentially. The fluctuations of the gating unit delay under multi-mode and multi-corner conditions make it even more difficult to balance the clock tree.

[0003] In addition, with the development of integrated circuit technology, the operating frequency of chips is constantly increasing, and the demand for low delay is becoming more and more urgent. Traditional gating logic units are difficult to meet the requirements of the new generation of high-speed systems for fast signal transmission. Especially when facing problems such as short-channel effects and increased parasitic parameters at the nanometer process node, the limitations of traditional designs are more obvious. Therefore, exploring and developing new gating unit circuits with lower delay characteristics is an important current technical direction. Summary of the Invention

[0004] Aiming at the technical problems existing in the prior art, the present invention provides a high-speed gating unit circuit that can effectively reduce circuit delay.

[0005] To solve the above technical problems, the technical solution proposed by the present invention is as follows: A high-speed gating unit circuit includes a data input circuit, a data latch circuit, and a data drive circuit, and the data input circuit, the data latch circuit, and the data drive circuit are connected in sequence; The data drive circuit includes a third inverter unit, PMOS transistors MP6 - MP9, and NMOS transistors MN6 - MN9; The substrate and source of PMOS transistor MP6 are connected to the power supply VDD, the gate is driven by signal v3, and the drain is used to drive signal v4; The substrate and source of PMOS transistor MP7 are connected to the power supply VDD, the gate is driven by the clock signal CK, and the drain is used to drive signal v4; The substrate and source of NMOS transistor MN6 are connected to the ground VSS, the gate is controlled by signal v3, and the drain is connected to the source of NMOS transistor MN7; The substrate of NMOS transistor MN7 is grounded to VSS, the gate is controlled by clock signal CK, the source is connected to the drain of NMOS transistor MN6, and the drain is used to drive signal v4; The input terminal of the third inverter unit is connected to signal v4, and the output terminal is used to drive the gate control unit circuit to output signal Q; The substrate and source of PMOS transistor MP8 are connected to power supply VDD, the gate is controlled by signal v2, and the drain is connected to the source of PMOS transistor MP9; The substrate of PMOS transistor MP9 is connected to power supply VDD, the gate is controlled by the complementary signal CKN of clock signal CK, the source is connected to the drain of PMOS transistor MP8, and the drain is used to drive the output signal Q of the gate control unit circuit; CK and CKN are a pair of complementary signal pairs; The substrate and source of NMOS transistor MN8 are grounded to VSS, the gate is controlled by signal v2, and the drain is used to drive the output signal Q of the gate control unit circuit; The substrate and source of NMOS transistor MN9 are grounded to VSS, the gate is controlled by the complementary signal CKN of clock signal CK, and the drain is used to drive the output signal Q of the gate control unit circuit.

[0006] Preferably, the third inverter unit is inverter X3.

[0007] Preferably, the data latch circuit includes a second inverter unit, PMOS transistors MP4 - MP5, and NMOS transistors MN4 - MN5; The input terminal of the second inverter unit is driven by signal v2, and the output terminal is used to drive signal v3; The substrate and source of PMOS transistor MP4 are both connected to power supply VDD, the gate is driven by signal v3, and the drain is connected to the source of PMOS transistor MP5; The substrate of PMOS transistor MP5 is connected to power supply VDD, the gate is controlled by the complementary signal CKN of clock signal CK, the source is connected to the drain of PMOS transistor MP4, and the drain is used to drive signal v2; The substrate and source of NMOS transistor MN4 are grounded to VSS, the gate is controlled by signal v3, and the drain is connected to the source of NMOS transistor MN5; The substrate of NMOS transistor MN5 is grounded to VSS, the gate is controlled by clock signal CK, the source is connected to the drain of NMOS transistor MN4, and the drain is used to drive signal v2.

[0008] Preferably, the second inverter unit is inverter X2.

[0009] Preferably, the data input circuit includes a first inverter unit, PMOS transistors MP1 - MP3, and NMOS transistors MN1 - MN3; The input terminal of the first inverter unit is driven by clock signal CK, and the output terminal is used to drive signal CKN; The substrate and source of the PMOS transistor MP1 are both connected to the power supply VDD, the gate is controlled by the test enable signal TE, and the drain is connected to the source of the PMOS transistor MP2; The substrate of the PMOS transistor MP2 is connected to the power supply VDD, the gate is controlled by the enable signal E, the source is connected to the drain of the PMOS transistor MP1, and the drain is used to drive the signal v1; The substrate and source of the NMOS transistor MN1 are both grounded to VSS, the gate is controlled by the test enable signal TE, and the drain is used to drive the signal v1; The substrate and source of the NMOS transistor MN2 are both grounded to VSS, the gate is controlled by the enable signal E, and the drain is used to drive the signal v1; The substrate of the PMOS transistor MP3 is connected to the power supply VDD, the gate is controlled by the clock signal CK, the source is driven by the signal v1, and the drain is used to drive the signal v2; The substrate of the NMOS transistor MN3 is grounded to VSS, the gate is controlled by the complementary signal CKN of the clock signal CK, the source is driven by the signal v1, and the drain is used to drive the signal v2.

[0010] Preferably, the first inverting unit is an inverter X1.

[0011] Compared with the prior art, the advantages of the present invention are as follows: The high-speed gating unit circuit of the present invention includes a data input circuit, a data latch circuit, and a data drive circuit, and the circuit is controlled by the clock signal CK and its complementary signal CKN; under the control of the low-level clock, the data latch circuit samples the enable signal, and at the same time, the data drive circuit is directly pulled up by the clock signal and then inverts to drive the output signal Q, that is, the signal Q is at a low level; under the control of the high-level clock, the data latch circuit is in a holding state, and the value of the output signal Q of the data drive circuit is the value stored in the data latch circuit; compared with the traditional gating unit circuit, the high-speed gating unit circuit of the present invention realizes a significant reduction in the time from the clock signal CK transition to the output signal Q transition, significantly improving the speed and response efficiency of the gating unit circuit; through the optimized circuit structure design, the high-speed gating unit circuit of the present invention effectively reduces the circuit delay (the delay is reduced by 7% compared with the traditional gating unit), and the delay fluctuation under different PVT corners is smaller, realizing the optimization of the clock tree performance and the overall design optimization, and is more suitable for digital integrated circuit design. Description of the Drawings

[0012] Figure 1 It is the circuit structure diagram of the traditional gating circuit.

[0013] Figure 2 It is the circuit structure diagram of the high-speed gating unit circuit of the embodiment of the present invention.

[0014] Figure 3One of the working state diagrams of the high-speed gating unit circuit according to the embodiment of the present invention in specific applications (when at least one of the signals E / TE is at a high potential '1' and CK is at a high potential '0', the output signal is at a high potential '0').

[0015] Figure 4 Another working state diagram of the high-speed gating unit circuit according to the embodiment of the present invention in specific applications (when at least one of the signals E / TE is at a high potential '1' and CK is at a high potential '1', the output signal is at a high potential '1').

[0016] Figure 5 Another working state diagram of the high-speed gating unit circuit according to the embodiment of the present invention in specific applications (when both E / TE are at a low potential '0' and CK is at a low potential '0', the output signal is at a high potential '0').

[0017] Figure 6 Another working state diagram of the high-speed gating unit circuit according to the embodiment of the present invention in specific applications (when both E / TE are at a low potential '0' and CK is at a high potential '1', the output signal is at a high potential '0'). Detailed implementation manners

[0018] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0019] As Figure 2 shown, the high-speed gating unit circuit provided by the embodiment of the present invention includes a data input circuit, a data latch circuit, and a data drive circuit, which are connected in sequence; the data input circuit, the data latch circuit, and the data drive circuit are all controlled by a clock signal CK and its complementary signal CKN; wherein the clock signal CK and CKN are a pair of complementary signals. When the level value of the CK signal is at a low level, the level value of the CKN signal is at a high level; conversely, when the level value of the CK signal is at a high level, the level value of the CKN signal is at a low level. Specifically, the data drive circuit includes a third inverter unit (inverter X3), PMOS transistors MP6-MP9, and NMOS transistors MN6-MN9. The substrate and source of the PMOS transistor MP6 are connected to the power supply VDD, the gate is driven by the signal v3, and the drain is used to drive the signal v4. The substrate and source of the PMOS transistor MP7 are connected to the power supply VDD, the gate is driven by the clock signal CK, and the drain is used to drive the signal v4. The substrate and source of the NMOS transistor MN6 are grounded to VSS, the gate is controlled by the signal v3, and the drain is connected to the source of the NMOS transistor MN7. The substrate of NMOS transistor MN7 is grounded to VSS, the gate is controlled by clock signal CK, the source is connected to the drain of NMOS transistor MN6, and the drain is used to drive signal v4; The input terminal of inverter X3 is connected to signal v4, and the output terminal is used to drive the output signal Q of the gating unit circuit; The substrate and source of PMOS transistor MP8 are connected to power supply VDD, the gate is controlled by signal v2, and the drain is connected to the source of PMOS transistor MP9; The substrate of PMOS transistor MP9 is connected to power supply VDD, the gate is controlled by the complementary signal CKN of clock signal CK, the source is connected to the drain of PMOS transistor MP8, and the drain is used to drive the output signal Q of the gating unit circuit; The substrate and source of NMOS transistor MN8 are grounded to VSS, the gate is controlled by signal v2, and the drain is used to drive the output signal Q of the gating unit circuit; The substrate and source of NMOS transistor MN9 are grounded to VSS, the gate is controlled by the complementary signal CKN of clock signal CK, and the drain is used to drive the output signal Q of the gating unit circuit.

[0020] Specifically, the data latch circuit includes a second inverter unit (inverter X2), PMOS transistors MP4 - MP5, and NMOS transistors MN4 - MN5; The input terminal of inverter X2 is driven by signal v2, and the output terminal is used to drive signal v3; The substrate and source of PMOS transistor MP4 are connected to power supply VDD, the gate is driven by signal v3, and the drain is connected to the source of PMOS transistor MP5; The substrate of PMOS transistor MP5 is connected to power supply VDD, the gate is controlled by the complementary signal CKN of clock signal CK, the source is connected to the drain of PMOS transistor MP4, and the drain is used to drive signal v2; The substrate and source of NMOS transistor MN4 are grounded to VSS, the gate is controlled by signal v3, and the drain is connected to the source of NMOS transistor MN5; The substrate of NMOS transistor MN5 is grounded to VSS, the gate is controlled by clock signal CK, the source is connected to the drain of NMOS transistor MN4, and the drain is used to drive signal v2.

[0021] Specifically, the data input circuit, which is used to receive the clock signal and the control signal, includes a first inverter unit (inverter X1), PMOS transistors MP1 - MP3, and NMOS transistors MN1 - MN3; The input terminal of inverter X1 is driven by clock signal CK, and the output terminal is used to drive signal CKN; CK and CKN are a pair of complementary signal pairs; The substrate and source of PMOS transistor MP1 are connected to power supply VDD, the gate is controlled by test enable signal TE, and the drain is connected to the source of PMOS transistor MP2; The substrate of PMOS transistor MP2 is connected to power supply VDD, the gate is controlled by enable signal E, the source is connected to the drain of PMOS transistor MP1, and the drain is used to drive signal v1; The substrate and source of NMOS transistor MN1 are grounded to VSS, the gate is controlled by test enable signal TE, and the drain is used to drive signal v1; The substrate and source of NMOS transistor MN2 are grounded to VSS, the gate is controlled by enable signal E, and the drain is used to drive signal v1; The substrate of PMOS transistor MP3 is connected to power supply VDD, the gate is controlled by clock signal CK, the source is driven by signal v1, and the drain is used to drive signal v2; The substrate of NMOS transistor MN3 is grounded to VSS, the gate is controlled by the complementary signal CKN of clock signal CK, the source is driven by signal v1, and the drain is used to drive signal v2.

[0022] When the above gating unit circuit is specifically applied, the specific working principle is as follows: When at least one of enable signal E and test enable signal TE is at high level / logic '1', the above gating unit circuit is in the enable mode; at this time, at least one of MN2 transistor (i.e., NMOS transistor MN2, abbreviated as MN2 transistor, and the following is the same) and MN1 transistor is in the conducting state, while at least one of MP2 transistor and MP1 transistor is in the off state, so signal v1 is pulled down to low level / logic '0'; When the clock signal CK is at low level, its complementary signal CKN is at high level. Then, both MN7 transistor and MP9 transistor in the data driving circuit are in the off state, while both MP7 transistor and MN9 transistor are in the on state. MN9 transistor directly pulls down the output signal Q of the gating unit circuit to low level / logic '0', MP7 transistor directly pulls up signal v4 to high level / logic '1', and signal v4 then pulls the output signal Q of the gating unit circuit to low level / logic '0' through inverter X3; at the same time, as Figure 3 shown, MN3 transistor and MP3 transistor are conducting, MP5 transistor and MN5 transistor are cut off, and the data latch circuit starts to receive new data, so that signals v2 and v3 are updated to logic '0' and logic '1' respectively. At this time, the data latch circuit updates the data, and its behavior does not affect the working state of the subsequent data driving circuit. The output of the data latch circuit is shielded, and the level value of the output signal Q of the gating unit circuit is the same as the level value of the clock signal CK, that is, the low-level clock signal is not controlled by the enable signal E and the test enable signal TE.

[0023] When the clock signal CK jumps from low level to high level, MN3 transistor and MP3 transistor change from conducting to off, while MP5 transistor and MN5 transistor change from off to conducting. Then, the data latch circuit no longer updates the data and is in the holding state, that is, signals v2 and v3 maintain their original values.

[0024] When the clock signal CK is at a high level, its complementary signal CKN is at a low level. Thus, both MP7 and MN9 transistors are in the off state, while MN7 and MP9 transistors are in the on state. Then, the value of the data latch circuit will affect the output signal Q. Since the signal v2 receives the value of the signal v1 when the clock signal is at a low level, the value of v2 is logic '0'. Then, the value of the signal v3 is logic '1'. As Figure 4 shown, the signal v2 drives the MP8 transistor to conduct. Then, MP8 and MP9 transistors pull up the output signal Q of the gating unit circuit to a high level / logic '1'. At the same time, the signal v3 drives the MN6 transistor to conduct. Then, the signal v4 is pulled down to a low level / logic '0'. The signal v4 drives the inverter X3 to pull up the output signal Q of the gating unit circuit to a high level / logic '1'. It can be seen that the high-level clock signal CK is controlled by the enable signal E and the test enable signal TE, and this control is indirect. The high-level values of the enable signal E and the test enable signal TE are first latched and can control the output of the high-level clock signal CK to the output signal Q only in the next clock cycle.

[0025] Therefore, in the enable mode, the output signal Q of the above gating unit circuit always remains consistent with the clock signal CK.

[0026] When the enable signal E and the test enable signal TE are both at a low level / logic '0' simultaneously, the above gating unit circuit is in the control mode. At this time, both MP2 and MP1 transistors are in the on state, while both MN2 and MN1 transistors are in the off state. Then, the signal v1 is pulled up to a high level / logic '1'.

[0027] When the clock signal is at a low level, its complementary signal CKN is at a high level. Thus, both MN7 and MP9 transistors in the data driving circuit are in the off state, while MP7 and MN9 transistors are in the on state. The MN9 transistor directly pulls down the output signal Q of the gating unit circuit to a low level / logic '0'. The MP7 transistor directly pulls up the signal v4 to a high level / logic '1'. The signal v4 then pulls the output signal Q of the gating unit circuit to a low level / logic '0' through the inverter X3. At the same time, as Figure 5 shown, MN3 and MP3 transistors conduct, and MP5 and MN5 transistors cut off. The data latch circuit starts to receive new data, causing the signals v2 and v3 to be updated to logic '1' and logic '0' respectively. At this time, the data latch circuit updates the data, and its behavior does not affect the working state of the subsequent data driving circuit. The level value of the output signal Q of the unit circuit is the same as the level value of the clock signal CK.

[0028] When the clock signal CK transitions from low level to high level, the MN3 and MP3 transistors change from conducting to non-conducting, while the MP5 and MN5 transistors change from non-conducting to conducting. Then the data latch circuit stops updating data and enters a holding state, that is, the signals v2 and v3 maintain their original values.

[0029] When the clock signal CK is at high level, its complementary signal CKN is at low level. Then both the MP7 and MN9 transistors are in the non-conducting state, while the MN7 and MP9 transistors are in the conducting state. Thus, the value of the data latch circuit will affect the output signal Q of the cell circuit. Since the signal v2 received the value of the signal v1 when the clock signal was at low level, the value of v2 is logic '1'. Then the value of the signal v3 is logic '0'. As Figure 6 shown, the signal v2 drives the MN8 transistor to conduct, and then the MN8 transistor pulls down the output signal Q of the gated cell circuit to low level / logic '0'. At the same time, the signal v3 drives the MP6 transistor to conduct, causing the signal v4 to be pulled up to high level / logic '1'. The signal v4 drives the inverter X3 to pull down the output signal Q of the gated cell circuit to low level / logic '0'. It can be seen that the high-level clock signal CK is controlled by the enable signal E and the test enable signal TE, and this control is indirect. The low-level values of the enable signal E and the test enable signal TE are first latched and can control the high-level clock signal CK not to output to the output signal Q only in the next clock cycle, making the output signal Q remain low level.

[0030] Therefore, in the control mode, the output signal Q of the above-mentioned gated cell circuit always remains low level.

[0031] Finally, to compare the performance characteristics of the gated cell circuit proposed in the present invention, under a certain commercial FinFET bulk silicon process, the traditional gated cell and the gated cell circuit of the present invention were respectively analyzed and compared based on the standard cell characterization library building tool Liberate and the cell timing library comparison tool qualib. The comparison results of the signal transition and CK-Q delay of the cells are shown in Table 1: Table 1 Comparison of area and delay results

[0032] As shown in Table 1, compared with the traditional gated cell, when the area increases slightly, the signal transition of the gated cell circuit of the embodiment of the present invention becomes faster by an average of 15.0%, and the CK-Q delay is reduced by an average of 7%. Therefore, the high-speed gated cell circuit of the present invention is very suitable for use as a standard cell of digital circuits and has broad prospects in the design of digital chips with high performance requirements.

[0033] The high-speed gating unit circuit of the present invention includes a data input circuit, a data latch circuit, and a data driving circuit, and the circuit is controlled by a clock signal CK and its complementary signal CKN; under the control of the low-level clock, the data latch circuit samples the enable signal, and at the same time, the data driving circuit is directly pulled up by the clock signal and then drives the output signal Q in an inverted manner, that is, the signal Q is at a low level; under the control of the high-level clock, the data latch circuit is in a holding state, and the value of the output signal Q of the data driving circuit is the value stored in the data latch circuit; compared with the traditional gating unit circuit, the high-speed gating unit circuit of the present invention realizes a significant reduction in the time from the transition of the clock signal CK to the transition of the output signal Q, and significantly improves the speed and response efficiency of the gating unit circuit; through the optimized circuit structure design, the high-speed gating unit circuit of the present invention effectively reduces the circuit delay (the delay is reduced by 7% compared with the traditional gating unit), and the delay fluctuation under different PVT corners is smaller, realizes the optimization of the clock tree performance and the overall design optimization, and is more suitable for digital integrated circuit design.

[0034] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should be regarded as the protection scope of the present invention.

Claims

1. A high-speed gate control unit circuit, characterized in that: It includes a data input circuit, a data latch circuit and a data driving circuit, wherein the data input circuit, the data latch circuit and the data driving circuit are connected in sequence; The data driving circuit includes a third inverting unit, PMOS tubes MP6-MP9, and NMOS tubes MN6-MN9; The substrate and source of the PMOS tube MP6 are connected to the power supply VDD, the gate is driven by the signal v3, and the drain is used to drive the signal v4; The substrate and source of the PMOS tube MP7 are connected to the power supply VDD, the gate is driven by the clock signal CK, and the drain is used to drive the signal v4; The substrate and source of the NMOS tube MN6 are grounded to VSS, the gate is controlled by the signal v3, and the drain is connected to the source of the NMOS tube MN7; The substrate of the NMOS tube MN7 is grounded to VSS, the gate is controlled by the clock signal CK, the source is connected to the drain of the NMOS tube MN6, and the drain is used to drive the signal v4; The input terminal of the third inverting unit is connected to the signal v4, and the output terminal is used to drive the gate control unit circuit to output the signal Q; The substrate and source of the PMOS tube MP8 are connected to the power supply VDD, the gate is controlled by the signal v2, and the drain is connected to the source of the PMOS tube MP9; The substrate of the PMOS tube MP9 is connected to the power supply VDD, the gate is controlled by the complementary signal CKN of the clock signal CK, the source is connected to the drain of the PMOS tube MP8, and the drain is used to drive the output signal Q of the gate control unit circuit; CK and CKN are a pair of complementary signals; The substrate and source of the NMOS tube MN8 are grounded to VSS, the gate is controlled by the signal v2, and the drain is used to drive the output signal Q of the gate control unit circuit; The substrate and source of the NMOS tube MN9 are grounded to VSS, the gate is controlled by the complementary signal CKN of the clock signal CK, and the drain is used to drive the output signal Q of the gate control unit circuit.

2. The high-speed gate control unit circuit according to claim 1, characterized in that: The third inverting unit is an inverter X3.

3. The high-speed gate control unit circuit according to claim 1 or 2, characterized in that: The data latch circuit includes a second inverting unit, PMOS tubes MP4-MP5, and NMOS tubes MN4-MN5; The input end of the second inverting unit is driven by the signal v2, and the output end is used to drive the signal v3; The substrate and source of the PMOS tube MP4 are both connected to the power supply VDD, the gate is driven by the signal v3, and the drain is connected to the source of the PMOS tube MP5; The substrate of the PMOS tube MP5 is connected to the power supply VDD, the gate is controlled by the complementary signal CKN of the clock signal CK, the source is connected to the drain of the PMOS tube MP4, and the drain is used to drive the signal v2; The substrate and source of the NMOS tube MN4 are grounded to VSS, the gate is controlled by the signal v3, and the drain is connected to the source of the NMOS tube MN5; The substrate of the NMOS tube MN5 is grounded to VSS, the gate is controlled by the clock signal CK, the source is connected to the drain of the NMOS tube MN4, and the drain is used for driving the signal v2.

4. The high-speed gate control unit circuit according to claim 3, characterized in that: The second inverting unit is an inverter X2.

5. The high-speed gate control unit circuit according to claim 1 or 2, characterized in that: The data input circuit includes a first inverting unit, PMOS tubes MP1-MP3, and NMOS tubes MN1-MN3; The input end of the first inverting unit is driven by the clock signal CK, and the output end is used for driving the signal CKN; The substrate and source of the PMOS tube MP1 are both connected to the power supply VDD, the gate is controlled by the test enable signal TE, and the drain is connected to the source of the PMOS tube MP2; The substrate of the PMOS tube MP2 is connected to the power supply VDD, the gate is controlled by the enable signal E, the source is connected to the drain of the PMOS tube MP1, and the drain is used to drive the signal v1; The substrate and source of the NMOS tube MN1 are both grounded to VSS, the gate is controlled by the test enable signal TE, and the drain is used to drive the signal v1; The substrate and source of NMOS tube MN2 are both grounded to VSS, the gate is controlled by the enable signal E, and the drain is used to drive the signal v1; The substrate of the PMOS tube MP3 is connected to the power supply VDD, the gate is controlled by the clock signal CK, the source is driven by the signal v1, and the drain is used to drive the signal v2; The substrate of the NMOS tube MN3 is grounded to VSS, the gate is controlled by the complementary signal CKN of the clock signal CK, the source is driven by the signal v1, and the drain is used to drive the signal v2.

6. The high-speed gate control unit circuit according to claim 5, characterized in that: The first inverting unit is an inverter X1.

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