Zero blind area phase frequency detector circuit for high-speed interface self-biased phase-locked loop

Abstract

The invention discloses a zero-blind-area phase frequency detector circuit for a high-speed interface self-biased phase-locked loop, which comprises a UP path formed by cascading a real single-phase clock and a phase inverter and a DN path formed by cascading the real single-phase clock and the phase inverter, the zero-blind-area phase frequency detector is used for detecting the frequency difference and the phase difference between an input reference signal and a feedback signal in a self-biased phase-locked loop of a high-speed interface and converting the frequency difference and the phase difference into corresponding electric signals to serve as control signals for follow-up charge pump charging and discharging. The phase difference which can be detected by the phase frequency detector covers [-2pi, 2pi], meanwhile, output polarity errors caused by input signal rising edge loss can be avoided, the correctness of the output polarity of the phase frequency detector is ensured, the output average voltage is large, and the locking speed of the phase-locked loop can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop. Background Art

[0002] A phase-locked loop frequency synthesizer, usually abbreviated as PLL, is a core module in a high-speed interface circuit. It can achieve synchronization of the output signal with the reference signal in terms of frequency and phase through feedback control, playing a key role in high-speed data transmission to ensure signal stability and accuracy.

[0003] A traditional charge pump phase-locked loop includes: a phase frequency detector (PFD), a charge pump (CP), a loop filter (LP), a voltage controlled oscillator (VCO), and a frequency divider (DIV). The traditional charge pump phase-locked loop compares the phase difference between the input reference signal and the output signal of the voltage controlled oscillator to generate an error signal. The error signal is filtered by the loop filter to obtain a control voltage, and the control voltage acts on the voltage controlled oscillator to adjust its output frequency. Finally, the output frequency approaches the input signal frequency to achieve phase locking. The performance of the loop bandwidth, phase margin, etc. of the traditional phase-locked loop is related to various parameters such as the charge pump current, the RC parameters of the filter, and the division ratio, and these parameters are difficult to adaptively adjust. Due to the relatively fixed bandwidth, when facing a wide range of input reference frequencies, its performance may not be ideal.

[0004] A self-biased phase-locked loop (Self-biased PLL), based on the traditional phase-locked loop, associates parameters such as the charge pump current and the resistance in the loop filter. Through circuit design and a self-biased mechanism, the ratio of the loop bandwidth to the reference frequency and the damping factor are approximately constant values, thereby achieving adaptive adjustment of the bandwidth and having a wider frequency adaptation range.

[0005] The phase frequency detector is one of the important modules in the phase-locked loop, used to detect the frequency difference and phase difference between two input signals. The traditional phase frequency detector consists of two D flip-flops and an AND gate. When the rising edges of the input reference signal and the feedback signal arrive respectively, the output UP and DN signals are respectively output as high levels. When the UP and DN signals are both high, UP and DN are used as inputs to the AND gate, and the AND gate outputs a high level to reset the two D flip-flops. However, the traditional phase frequency detector has a blind-zone problem. When the phase difference between the input reference signal and the feedback signal is near ±2π, the phase frequency detector cannot detect the phase difference, resulting in the appearance of a blind zone. Summary of the Invention

[0006] The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, providing a zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, solving the blind-zone problem of the traditional frequency discriminator and phase detector, and improving the locking speed of the phase-locked loop.

[0007] The object of the present invention is achieved by the following technical solutions: A zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, comprising: a UP path and a DN path; wherein, the UP path is respectively connected to a first charge pump and a second charge pump; the DN path is respectively connected to the first charge pump and the second charge pump; the UP path is connected to the DN path; the UP path receives an input reference signal Fref, processes the input reference signal Fref to obtain a UP signal, and inputs the UP signal to the first charge pump and the second charge pump respectively, and both the first charge pump and the second charge pump obtain a charging signal according to the UP signal; the DN path receives a clock divided-frequency input signal Fdiv, processes the clock divided-frequency input signal Fdiv to obtain a DN signal, and inputs the DN signal to the first charge pump and the second charge pump respectively, and both the first charge pump and the second charge pump obtain a discharging signal according to the DN signal.

[0008] In the above zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, the UP path includes a true single-phase clock TSPC1, an inverter INV1, an inverter INV2, and an inverter INV3; wherein, the input end of the true single-phase clock TSPC1 is respectively connected to the output end of the inverter INV1 and the output end of the DN path, and the output end of the true single-phase clock TSPC1 is connected to the input end of the inverter INV1; the output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is respectively connected to the input end of the true single-phase clock TSPC1, the first charge pump, the second charge pump, and the input end of the DN path.

[0009] In the above-mentioned zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, the DN path includes a true single-phase clock TSPC2, an inverter INV4, an inverter INV5, and an inverter INV6; wherein, the input end of the true single-phase clock TSPC2 is respectively connected to the output end of the inverter INV3, the output end of the inverter INV4, and the output end of the inverter INV6; the output end of the true single-phase clock TSPC2 is connected to the input end of the inverter INV4, the output end of the inverter INV4 is connected to the input end of the inverter INV5, the output end of the inverter INV5 is connected to the input end of the inverter INV6, and the output end of the inverter INV6 is respectively connected to the input end of the true single-phase clock TSPC1, the first charge pump, and the second charge pump.

[0010] In the above zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, the true single-phase clock TSPC1 includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistors M7, M8, M9, M10, and M11; the inverter INV1 includes PMOS transistor M4 and NMOS transistor M12; the inverter INV2 includes PMOS transistor M5 and NMOS transistor M13; the inverter INV3 includes PMOS transistor M6 and NMOS transistor M14; wherein, the source of the PMOS transistor M1 is connected to the power supply, the drain of the PMOS transistor M1 is respectively connected to the drain of the NMOS transistor M7, the gate of the PMOS transistor M2, and the gate of the NMOS transistor M11, and the gate of the PMOS transistor M1 is connected to the input reference signal Fref; the source of the PMOS transistor M2 is connected to the power supply, the drain of the PMOS transistor M2 is respectively connected to the drain of the NMOS transistor M10, the drain of the PMOS transistor M3, the gate of the PMOS transistor M4, and the gate of the NMOS transistor M12; the source of the PMOS transistor M3 is connected to the power supply, and the gate of the PMOS transistor M3 is respectively connected to the drain of the PMOS transistor M4 and the drain of the NMOS transistor M12; the source of the PMOS transistor M5 is connected to the power supply, the gate of the PMOS transistor M5 is respectively connected to the drain of the PMOS transistor M4, the drain of the NMOS transistor M12, and the gate of the NMOS transistor M13, and the drain of the PMOS transistor M5 is connected to the drain of the NMOS transistor M13; the source of the PMOS transistor M6 is connected to the power supply, the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M14, and the gate of the PMOS transistor M6 is respectively connected to the gate of the NMOS transistor M14, the drain of the PMOS transistor M5, and the drain of the NMOS transistor M13; the gate of the NMOS transistor M7 is connected to the UP signal, the source of the NMOS transistor M7 is connected to the drain of the NMOS transistor M8, and the source of the NMOS transistor M7 is respectively connected to the drain of the PMOS transistor M1, the gate of the PMOS transistor M2, and the gate of the NMOS transistor M11; the gate of the NMOS transistor M8 is connected to the DN signal, and the source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M9; the gate of the NMOS transistor M9 is connected to the input reference signal Fref, and the source of the NMOS transistor M9 is grounded; the gate of the NMOS transistor M10 is connected to the input reference signal Fref, the source of the NMOS transistor M10 is connected to the drain of the NMOS transistor M11; the gate of the NMOS transistor M11 is respectively connected to the gate of the PMOS transistor M2, the drain of the PMOS transistor M1, and the drain of the NMOS transistor M7, and the source of the NMOS transistor M11 is grounded;The gate of the NMOS transistor M12 is connected to the gates of the PMOS transistors M4, the drain of the PMOS transistor M3, the drain of the PMOS transistor M2, and the drain of the NMOS transistor M10 respectively. The drain of the NMOS transistor M12 is connected to the drains of the PMOS transistors M4, the gate of the PMOS transistor M3, the gates of the PMOS transistors M5, and the gate of the NMOS transistor M13 respectively. The source of the NMOS transistor M12 is grounded. The gate of the NMOS transistor M13 is connected to the gates of the PMOS transistors M5, the drain of the PMOS transistor M4, and the drain of the NMOS transistor M12 respectively. The drain of the NMOS transistor M13 is connected to the drains of the PMOS transistors M5, the gate of the PMOS transistor M6, and the gate of the NMOS transistor M14 respectively. The source of the NMOS transistor M13 is grounded. The drain of the NMOS transistor M14 is connected to the drain of the PMOS transistor M6. The source of the NMOS transistor M14 is grounded.;

[0011] In the above-mentioned zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, the true single-phase clock TSPC2 includes PMOS transistor M15, PMOS transistor M16, PMOS transistor M17, NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24, and NMOS transistor M25; the inverter INV4 includes PMOS transistor M18 and NMOS transistor M26; the inverter INV5 includes PMOS transistor M19 and NMOS transistor M27; the inverter INV6 includes PMOS transistor M20 and NMOS transistor M28; wherein, the source of the PMOS transistor M15 is connected to the power supply, the gate of the PMOS transistor M15 is connected to the feedback signal Fdiv, and the drain of the PMOS transistor M15 is respectively connected to the drain of the NMOS transistor M21, the gate of the PMOS transistor M16, and the gate of the NMOS transistor M25; the source of the PMOS transistor M16 is connected to the power supply, and the drain of the PMOS transistor M16 is respectively connected to the drain of the NMOS transistor M24, the drain of the PMOS transistor M17, the gate of the PMOS transistor M18, and the gate of the NMOS transistor M26; the source of the PMOS transistor M17 is connected to the power supply, the gate of the PMOS transistor M17 is respectively connected to the drain of the PMOS transistor M18 and the drain of the NMOS transistor M26, and the drain of the PMOS transistor M17 is respectively connected to the drain of the PMOS transistor M16, the gate of the PMOS transistor M18, the drain of the NMOS transistor M24, and the gate of the NMOS transistor M26; the source of the PMOS transistor M18 is connected to the power supply, and the drain of the PMOS transistor M18 is respectively connected to the gate of the PMOS transistor M17, the drain of the NMOS transistor M26, the gate of the PMOS transistor M19, and the gate of the NMOS transistor M27; the source of the PMOS transistor M19 is connected to the power supply, and the drain of the PMOS transistor M19 is respectively connected to the gate of the PMOS transistor M20, the drain of the NMOS transistor M27, and the gate of the NMOS transistor M28; the source of the PMOS transistor M20 is connected to the power supply, and the drain of the PMOS transistor M20 is connected to the drain of the NMOS transistor M28, serving as the output terminal of the DN path; the gate of the NMOS transistor M21 is connected to the UP signal, the drain of the NMOS transistor M21 is respectively connected to the drain of the PMOS transistor M15, the gate of the PMOS transistor M16, and the gate of the NMOS transistor M25, and the source of the NMOS transistor M21 is connected to the drain of the NMOS transistor M22; the gate of the NMOS transistor M22 is connected to the DN signal, and the source of the NMOS transistor M22 is connected to the drain of the NMOS transistor M23; the gate of the NMOS transistor M23 is connected to the feedback signal Fdiv, and the source of the NMOS transistor M23 is grounded; the gate of the NMOS transistor M24 is connected to the feedback signal Fdiv, and the source of the NMOS transistor M24 is connected to the drain of the NMOS transistor M25;The gate of the NMOS transistor M25 is connected to the gate of the PMOS transistor M16, the drain of the PMOS transistor M15, and the drain of the NMOS transistor M21 respectively, and the source of the NMOS transistor M25 is grounded; the gate of the NMOS transistor M26 is connected to the gate of the PMOS transistor M18, the drain of the PMOS transistor M17, the drain of the PMOS transistor M16, and the drain of the NMOS transistor M24 respectively, the drain of the NMOS transistor M26 is connected to the drain of the PMOS transistor M18, the gate of the PMOS transistor M19, and the gate of the NMOS transistor M27 respectively, and the source of the NMOS transistor M26 is grounded; the drain of the NMOS transistor M27 is connected to the drain of the PMOS transistor M19, the gate of the PMOS transistor M20, and the gate of the NMOS transistor M28 respectively, and the source of the NMOS transistor M27 is grounded; the drain of the NMOS transistor M28 is connected to the drain of the PMOS transistor M20, and the source of the NMOS transistor M28 is grounded.;

[0012] In the above zero-blind-zone frequency discriminator and phase discriminator circuit for a high-speed interface self-biased phase-locked loop, the point where the drain of the PMOS transistor M1, the gate of the PMOS transistor M2, and the drain of the NMOS transistor M7 are all connected is defined as node A1, and the point where the drain of the PMOS transistor M2, the drain of the NMOS transistor M10, the drain of the PMOS transistor M3, and the gate of the PMOS transistor M4 are all connected is defined as node A2. The point where the gate of the PMOS transistor M5, the drain of the NMOS transistor M12, the drain of the PMOS transistor M4, and the gate of the NMOS transistor M13 are all connected is defined as node A3, and the point where the gate of the PMOS transistor M6, the gate of the NMOS transistor M14, the drain of the PMOS transistor M5, and the drain of the NMOS transistor M13 are all connected is defined as node A4; the point where the drain of the PMOS transistor M15, the drain of the NMOS transistor M21, the gate of the PMOS transistor M16, and the gate of the NMOS transistor M25 are all connected is defined as node B1, and the point where the gate of the PMOS transistor M17, the drain of the PMOS transistor M18, and the NMOS transistor M26 are all connected is defined as node B2. The point where the drain of the PMOS transistor M18, the drain of the NMOS transistor M26, the gate of the PMOS transistor M19, and the gate of the NMOS transistor M27 are all connected is defined as node B3, and the point where the drain of the PMOS transistor M19, the gate of the PMOS transistor M20, the drain of the NMOS transistor M27, and the gate of the NMOS transistor M28 are all connected is defined as node B4.

[0013] In the above zero-blind-zone frequency discriminator and phase discriminator circuit for a high-speed interface self-biased phase-locked loop, in the initial state, both the input reference signal Fref and the feedback signal Fdiv are at low level, and the PMOS transistors M1 and M15 are turned on to charge node A1 and node B1 to high level.

[0014] In the above zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, when the phase of the input reference signal Fref is ahead of the phase of the feedback signal Fdiv and the phase difference is within the range of [0, π], when the rising edge of the input reference signal Fref arrives, NMOS transistors M9 and M10 are turned on. At the same time, node A1 is at a high level, NMOS transistor M11 is turned on, node A2 is at a low level, and after passing through inverter INV1, node A3 is pulled high to a high level. Node A3 passes through inverter INV2 to pull node A4 low to a low level, and then through inverter INV3, the output UP signal is at a high level; when the rising edge of the feedback signal Fdiv arrives, NMOS transistors M23 and M24 are turned on, node B1 is at a high level, NMOS transistor M25 is turned on, node B2 is at a low level, and after passing through inverter INV4, node B3 is pulled high to a high level. Node B3 passes through inverter INV5 to pull node B4 low to a low level, and then through inverter INV6, the output DN signal is at a high level; at this time, the input reference signal Fref still remains at a high level, and both the UP signal and the DN signal are at a high level. At this time, NMOS transistors M7, M8, and M9 are turned on simultaneously, and NMOS transistors M21, M22, and M23 are turned on simultaneously. Node A1 and node B1 are pulled low, node A2 and node B2 become high levels, and the output UP signal and DN signal are both at low levels.

[0015] In the above zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, when the phase of the input reference signal Fref is ahead of the phase of the feedback signal Fdiv and the phase difference is within the range of [π, 2π], when the rising edge of the input reference signal Fref arrives, the UP signal is at a high level. When the rising edge of the feedback signal Fdiv arrives, the DN signal is at a high level, and the input signal Fref has already become a low level. NMOS transistors M9 and M10 are turned off, and node A2 maintains its original state. Therefore, the UP signal also remains at a high level. At this time, both the UP signal and the DN signal are at a high level. The NMOS transistors M21, M22, and M23 in the DN path are turned on, node B1 is discharged to a low level, node B2 becomes a high level, and after passing through three inverters, namely inverter INV4, inverter INV5, and inverter INV6, the output DN signal is at a low level.

[0016] In the above zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, when the phase difference between the input signal Fref and the feedback signal Fdiv is within the range of [-π, π], the zero-blind-zone frequency discriminator has a linear gain; when the phase difference between the input signal Fref and the feedback signal Fdiv is within the ranges of [-2π, -π] and [π, 2π], the zero-blind-zone frequency discriminator has a non-linear gain, and the output voltage is a constant.

[0017] The present invention has the following beneficial effects compared with the prior art:

[0018] The present invention can eliminate the blind area problem existing in the traditional frequency discriminator and phase detector, enable the phase difference that the frequency discriminator and phase detector can detect to cover [-2π, 2π], avoid the problem of loss of the rising edge of the input signal at the same time, ensure the correctness of the output polarity of the frequency discriminator and phase detector, and have a large average output voltage, thereby improving the locking speed of the phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0020] Figure 1 is a schematic circuit structure diagram of a zero-blind-area frequency discriminator and phase detector for a high-speed interface self-biased phase-locked loop provided by an embodiment of the present invention;

[0021] Figure 2 is a circuit structure diagram of a traditional frequency discriminator and phase detector provided by an embodiment of the present invention;

[0022] Figure 3 is a circuit structure diagram of a zero-blind-area frequency discriminator and phase detector provided by an embodiment of the present invention;

[0023] Figure 4 is a gain diagram of an ideal frequency discriminator and phase detector provided by an embodiment of the present invention;

[0024] Figure 5 is a gain diagram of a frequency discriminator and phase detector with a blind area provided by an embodiment of the present invention;

[0025] Figure 6 is a gain diagram of a zero-blind-area frequency discriminator and phase detector provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Hereinafter, the present invention will be described in detail with reference to the drawings and in combination with the embodiments.

[0027] This embodiment discloses a zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop, which is used to detect the frequency difference and phase difference between an input reference signal and a feedback signal in the high-speed interface self-biased phase-locked loop, convert them into corresponding electrical signals, and use them as control signals for subsequent charge pump charging and discharging. It can eliminate the blind-zone problem of traditional frequency discriminators and phase detectors, avoid incorrect output polarities caused by the loss of the rising edge of the input signal, and has a large output average voltage, thereby improving the locking speed of the phase-locked loop.

[0028] Figure 1 It is a schematic structural diagram of the zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop provided by an embodiment of the present invention. As Figure 1 shown, the zero-blind-zone frequency discriminator and phase detector circuit for a high-speed interface self-biased phase-locked loop includes: an UP path and a DN path; wherein, the UP path is respectively connected to a first charge pump and a second charge pump; the DN path is respectively connected to the first charge pump and the second charge pump; the UP path is connected to the DN path; the UP path receives an input reference signal Fref, processes the input reference signal Fref to obtain an UP signal, and inputs the UP signal to the first charge pump and the second charge pump respectively. Both the first charge pump and the second charge pump obtain a charging signal according to the UP signal; the DN path receives a clock divided input signal Fdiv, processes the clock divided input signal Fdiv to obtain a DN signal, and inputs the DN signal to the first charge pump and the second charge pump respectively. Both the first charge pump and the second charge pump obtain a discharging signal according to the DN signal.

[0029] The zero-blind-zone frequency discriminator and phase detector circuit includes an UP path and a DN path. The UP path is used to detect the input reference signal Fref and generate an UP signal to output to charge pump 1 and charge pump 2; the DN path is used to detect the feedback signal Fdiv and generate a DN signal to output to charge pump 1 and charge pump 2. The UP path includes a true single-phase clock TSPC1, an inverter INV1, an inverter INV2, and an inverter INV3; the DN path includes a true single-phase clock TSPC2, an inverter INV4, an inverter INV5, and an inverter INV6.

[0030] The high-speed interface self-biased phase-locked loop includes: a zero dead zone frequency detector and phase detector, charge pump 1, charge pump 2, capacitor C1, a bias generator, a voltage-controlled oscillator, and a frequency divider; the input of the zero dead zone frequency detector and phase detector is the input reference signal Fref and the feedback signal Fdiv output by the frequency divider, the UP signal and DN signal output by the zero dead zone frequency detector and phase detector are connected to the input ends of charge pump 1 and charge pump 2, the output VCTRL of charge pump 1 is connected to capacitor C1 and the bias generator, the output VBP and VBN of the bias generator are connected to the input end of the voltage-controlled oscillator, the output of charge pump 2 is connected to the output VBP of the bias generator, the output signal Fout of the voltage-controlled oscillator is the output of the self-biased phase-locked loop, Fout is simultaneously used as the input signal of the frequency divider, and the output signal Fdiv of the frequency divider is connected back to the zero dead zone frequency detector and phase detector in reverse.

[0031] As Figure 1 shown, the UP path includes a true single-phase clock TSPC1, an inverter INV1, an inverter INV2, and an inverter INV3; wherein, the input end of the true single-phase clock TSPC1 is respectively connected to the output end of the inverter INV1 and the output end of the DN path, and the output end of the true single-phase clock TSPC1 is connected to the input end of the inverter INV1; the output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is respectively connected to the input end of the true single-phase clock TSPC1, the first charge pump, the second charge pump, and the input end of the DN path.

[0032] The input of the true single-phase clock TSPC1 in the UP path of the zero dead zone frequency detector and phase detector includes the input reference clock, the output of the inverter INV1, the UP signal output by the UP path, and the DN signal output by the DN path. The output of the true single-phase clock TSPC1 is connected to the input end of the inverter INV1; the input of the inverter INV1 is the output signal of the true single-phase clock TSPC1, and the output is connected back to the true single-phase clock TSPC1 and the inverter INV2; the output of the inverter INV2 is connected to the input end of the inverter INV3; the output of the inverter INV3 serves as the charging signal UP of the charge pump and is connected to the input ends of charge pump 1 and charge pump 2.

[0033] As Figure 1As shown, the DN path includes a true single-phase clock TSPC2, an inverter INV4, an inverter INV5, and an inverter INV6. Among them, the input terminals of the true single-phase clock TSPC2 are respectively connected to the output terminal of the inverter INV3, the output terminal of the inverter INV4, and the output terminal of the inverter INV6. The output terminal of the true single-phase clock TSPC2 is connected to the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected to the input terminal of the inverter INV5. The output terminal of the inverter INV5 is connected to the input terminal of the inverter INV6. The output terminal of the inverter INV6 is respectively connected to the input terminal of the true single-phase clock TSPC1, the first charge pump, and the second charge pump.

[0034] The input of the true single-phase clock TSPC2 in the DN path of the zero dead zone frequency discriminator and phase detector includes the feedback clock, the output of the inverter INV4, the DN signal output by the DN path, and the UP signal output by the UP path. The output of the true single-phase clock TSPC2 is connected to the input terminal of the inverter INV4. The input of the inverter INV4 is the output signal of the true single-phase clock TSPC2, and the output is connected back to the true single-phase clock TSPC2 and the inverter INV5. The output of the inverter INV5 is connected to the input terminal of the inverter INV6. The output of the inverter INV6 serves as the discharge signal DN of the charge pump and is connected to the input terminals of charge pump 1 and charge pump 2.

[0035] Figure 2 The circuit structure diagram of the traditional frequency discriminator and phase detector is shown. It is composed of two D flip-flops and an AND gate. The two inputs of the AND gate are respectively the UP signal output by D flip-flop 1 and the DN signal output by the D flip-flop. The output of the AND gate is the reset signal reset, and the reset signal is input to the reset terminals of the two D flip-flops. When the rising edges of the input reference signal Fref and the feedback signal Fdiv arrive, the UP signal output by D flip-flop 1 is high, and the DN signal output by D flip-flop 2 is high. When the UP and DN signals are both high, the AND gate outputs a high-level reset signal reset, and the D flip-flops are reset. The traditional frequency discriminator and phase detector has a dead zone problem. Near ±2π, the traditional frequency discriminator and phase detector may have the situation of losing the rising edge of the input clock. Specifically, during the reset of the D flip-flop, due to a certain delay, if the rising edge of the input reference signal Fref arrives at this time, D flip-flop 1 will not be able to recognize this rising edge, and the UP signal will not change. When the rising edge of the feedback signal Fdiv arrives, DN jumps, resulting in the opposite polarity of the output.

[0036] As Figure 3As shown, the true single-phase clock TSPC1 includes PMOS transistor M1, PMOS transistor M2, PMOS transistor M3, NMOS transistor M7, NMOS transistor M8, NMOS transistor M9, NMOS transistor M10, and NMOS transistor M11; inverter INV1 includes PMOS transistor M4 and NMOS transistor M12; inverter INV2 includes PMOS transistor M5 and NMOS transistor M13; inverter INV3 includes PMOS transistor M6 and NMOS transistor M14; where,

[0037] The source of PMOS transistor M1 is connected to the power supply. The drain of PMOS transistor M1 is respectively connected to the drain of NMOS transistor M7, the gate of PMOS transistor M2, and the gate of NMOS transistor M11. The gate of PMOS transistor M1 is connected to the input reference signal Fref. The source of PMOS transistor M2 is connected to the power supply. The drain of PMOS transistor M2 is respectively connected to the drain of NMOS transistor M10, the drain of PMOS transistor M3, the gate of PMOS transistor M4, and the gate of NMOS transistor M12. The source of PMOS transistor M3 is connected to the power supply. The gate of PMOS transistor M3 is respectively connected to the drain of PMOS transistor M4 and the drain of NMOS transistor M12. The source of PMOS transistor M5 is connected to the power supply. The gate of PMOS transistor M5 is respectively connected to the drain of PMOS transistor M4, the drain of NMOS transistor M12, and the gate of NMOS transistor M13. The drain of PMOS transistor M5 is connected to the drain of NMOS transistor M13. The source of PMOS transistor M6 is connected to the power supply. The drain of PMOS transistor M6 is connected to the drain of NMOS transistor M14, serving as the output terminal of the UP path. The gate of PMOS transistor M6 is respectively connected to the gate of NMOS transistor M14, the drain of PMOS transistor M5, and the drain of NMOS transistor M13. The gate of NMOS transistor M7 is connected to the UP signal. The source of NMOS transistor M7 is connected to the drain of NMOS transistor M8. The source of NMOS transistor M7 is respectively connected to the drain of PMOS transistor M1, the gate of PMOS transistor M2, and the gate of NMOS transistor M11. The gate of NMOS transistor M8 is connected to the DN signal. The source of NMOS transistor M8 is connected to the drain of NMOS transistor M9. The gate of NMOS transistor M9 is connected to the input reference signal Fref. The source of NMOS transistor M9 is grounded. The gate of NMOS transistor M10 is connected to the input reference signal Fref. The source of NMOS transistor M10 is connected to the drain of NMOS transistor M11. The gate of NMOS transistor M11 is respectively connected to the gate of PMOS transistor M2, the drain of PMOS transistor M1, and the drain of NMOS transistor M7. The source of NMOS transistor M11 is grounded. The gate of NMOS transistor M12 is respectively connected to the gate of PMOS transistor M4, the drain of PMOS transistor M3, the drain of PMOS transistor M2, and the drain of NMOS transistor M10. The drain of NMOS transistor M12 is respectively connected to the drain of PMOS transistor M4, the gate of PMOS transistor M3, the gate of PMOS transistor M5, and the gate of NMOS transistor M13. The source of NMOS transistor M12 is grounded. The gate of NMOS transistor M13 is respectively connected to the gate of PMOS transistor M5, the drain of PMOS transistor M4, and the drain of NMOS transistor M12. The drain of NMOS transistor M13 is respectively connected to the drain of PMOS transistor M5, the gate of PMOS transistor M6, and the gate of NMOS transistor M14. The source of NMOS transistor M13 is grounded. The drain of NMOS transistor M14 is connected to the drain of PMOS transistor M6. The source of NMOS transistor M14 is grounded.

[0038] Such asFigure 3 As shown, the true single-phase clock TSPC2 includes PMOS transistor M15, PMOS transistor M16, PMOS transistor M17, NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24, and NMOS transistor M25; inverter INV4 includes PMOS transistor M18 and NMOS transistor M26; inverter INV5 includes PMOS transistor M19 and NMOS transistor M27; inverter INV6 includes PMOS transistor M20 and NMOS transistor M28. Among them,

[0039] The source of PMOS transistor M15 is connected to the power supply, the gate of PMOS transistor M15 is connected to the feedback signal Fdiv, and the drain of PMOS transistor M15 is respectively connected to the drain of NMOS transistor M21, the gate of PMOS transistor M16, and the gate of NMOS transistor M25; the source of PMOS transistor M16 is connected to the power supply, and the drain of PMOS transistor M16 is respectively connected to the drain of NMOS transistor M24, the drain of PMOS transistor M17, the gate of PMOS transistor M18, and the gate of NMOS transistor M26; the source of PMOS transistor M17 is connected to the power supply, the gate of PMOS transistor M17 is respectively connected to the drain of PMOS transistor M18 and the drain of NMOS transistor M26, and the drain of PMOS transistor M17 is respectively connected to the drain of PMOS transistor M16, the gate of PMOS transistor M18, the drain of NMOS transistor M24, and the gate of NMOS transistor M26; the source of PMOS transistor M18 is connected to the power supply, and the drain of PMOS transistor M18 is respectively connected to the gate of PMOS transistor M17, the drain of NMOS transistor M26, the gate of PMOS transistor M19, and the gate of NMOS transistor M27; the source of PMOS transistor M19 is connected to the power supply, and the drain of PMOS transistor M19 is respectively connected to the gate of PMOS transistor M20, the drain of NMOS transistor M27, and the gate of NMOS transistor M28; the source of PMOS transistor M20 is connected to the power supply, and the drain of PMOS transistor M20 is connected to the drain of NMOS transistor M28, serving as the output terminal of the DN path; the gate of NMOS transistor M21 is connected to the UP signal, the drain of NMOS transistor M21 is respectively connected to the drain of PMOS transistor M15, the gate of PMOS transistor M16, and the gate of NMOS transistor M25, and the source of NMOS transistor M21 is connected to the drain of NMOS transistor M22; the gate of NMOS transistor M22 is connected to the DN signal, and the source of NMOS transistor M22 is connected to the drain of NMOS transistor M23; the gate of NMOS transistor M23 is connected to the feedback signal Fdiv, and the source of NMOS transistor M23 is grounded; the gate of NMOS transistor M24 is connected to the feedback signal Fdiv, and the source of NMOS transistor M24 is connected to the drain of NMOS transistor M25; the gate of NMOS transistor M25 is respectively connected to the gate of PMOS transistor M16, the drain of PMOS transistor M15, and the drain of NMOS transistor M21, and the source of NMOS transistor M25 is grounded; the gate of NMOS transistor M26 is respectively connected to the gate of PMOS transistor M18, the drain of PMOS transistor M17, the drain of PMOS transistor M16, and the drain of NMOS transistor M24, the drain of NMOS transistor M26 is respectively connected to the drain of PMOS transistor M18, the gate of PMOS transistor M19, and the gate of NMOS transistor M27, and the source of NMOS transistor M26 is grounded; the drain of NMOS transistor M27 is respectively connected to the drain of PMOS transistor M19, the gate of PMOS transistor M20, and the gate of NMOS transistor M28, and the source of NMOS transistor M27 is grounded;The drain of NMOS transistor M28 is connected to the drain of PMOS transistor M20, and the source of NMOS transistor M28 is grounded.

[0040] The point where the drains of PMOS transistor M1, the gate of PMOS transistor M2, and the drain of NMOS transistor M7 are all connected is defined as node A1. The point where the drains of PMOS transistor M2, the drain of NMOS transistor M10, the drain of PMOS transistor M3, and the gate of PMOS transistor M4 are all connected is defined as node A2. The point where the gate of PMOS transistor M5, the drain of NMOS transistor M12, the drain of PMOS transistor M4, and the gate of NMOS transistor M13 are all connected is defined as node A3. The point where the gate of PMOS transistor M6, the gate of NMOS transistor M14, the drain of PMOS transistor M5, and the drain of NMOS transistor M13 are all connected is defined as node A4. The point where the drain of PMOS transistor M15, the drain of NMOS transistor M21, the gate of PMOS transistor M16, and the gate of NMOS transistor M25 are all connected is defined as node B1. The point where the gate of PMOS transistor M17, the drain of PMOS transistor M18, and NMOS transistor M26 are all connected is defined as node B2. The point where the drain of PMOS transistor M18, the drain of NMOS transistor M26, the gate of PMOS transistor M19, and the gate of NMOS transistor M27 are all connected is defined as node B3. The point where the drain of PMOS transistor M19, the gate of PMOS transistor M20, the drain of NMOS transistor M27, and the gate of NMOS transistor M28 are all connected is defined as node B4.

[0041] The circuit working process of the zero dead zone frequency discriminator and phase discriminator is as follows: In the initial state, both the input reference signal Fref and the feedback signal Fdiv are at low level. PMOS transistor M1 and PMOS transistor M15 are turned on, charging node A1 and node B1 to high level. When the phase of the input reference signal Fref leads the feedback signal Fdiv and the phase difference is within the range of [0, π], when the rising edge of the input reference signal Fref arrives, NMOS transistors M9 and M10 are turned on. At the same time, node A1 is at high level, NMOS transistor M11 is turned on, and node A2 is at low level. After passing through inverter INV1, node A3 is pulled high to high level. Node A3 passes through inverter INV2 to pull node A4 low to low level, and then through inverter INV3, the output UP signal is high level; when the rising edge of the feedback signal Fdiv arrives, NMOS transistors M23 and M24 are turned on, node B1 is at high level, NMOS transistor M25 is turned on, node B2 is at low level. After passing through inverter INV4, node B3 is pulled high to high level. Node B3 passes through inverter INV5 to pull node B4 low to low level, and then through inverter INV6, the output DN signal is high level; at this time, the input reference signal Fref still remains at high level, and both the UP signal and the DN signal are high level. At this time, NMOS transistors M7, M8 and M9 are turned on simultaneously, and NMOS transistors M21, M22 and M23 are turned on simultaneously. Node A1 and node B1 are pulled down to low level, node A2 and node B2 become high level, and both the output UP signal and the DN signal are low level. When the phase of the input reference signal Fref leads the feedback signal Fdiv and the phase difference is within the range of [π, 2π], when the rising edge of the input reference signal Fref arrives, the UP signal is high level. When the rising edge of the feedback signal Fdiv arrives, the DN signal is high level, and the input signal Fref has already become low level. NMOS transistors M9 and M10 are turned off, and node A2 maintains its original state. Therefore, the UP signal also remains high level. At this time, both the UP signal and the DN signal are high level. NMOS transistors M21, M22 and M23 in the DN path are turned on, node B1 is discharged to low level, and node B2 becomes high level. After passing through three inverters INV4, INV5 and INV6, the output DN signal is low level. When the phase of the input reference signal Fref lags behind the feedback signal Fdiv, the working process of the zero dead zone frequency discriminator and phase discriminator is the same.

[0042] In the UP path, PMOS transistor M3 and in the DN path, PMOS transistor M17 can quickly turn on or off the connection between nodes A2 and B2 and the power supply VDD, thereby accelerating the charging of nodes A2 and B2 to the high level or discharging them to the low level, and can eliminate interference; the gate of PMOS transistor M3 is connected to node A3, the source is connected to the power supply VDD, and the drain is connected to the drain of PMOS transistor M2, the drain of NMOS transistor M10, and at the same time the drain is connected to the gates of PMOS transistor M4 and NMOS transistor M12; the gate of PMOS transistor M17 is connected to node B3, the source is connected to the power supply VDD, and the drain is connected to the drains of PMOS transistor M16 and NMOS transistor M24, and at the same time the drain is connected to the gates of PMOS transistor M18 and NMOS transistor M26.

[0043] Figure 4 It is the gain graph of an ideal frequency discriminator and phase detector. The output of the frequency discriminator and phase detector is proportional to the phase difference between the input reference signal Fref and the feedback signal Fdiv.

[0044] Figure 5 It is the gain graph of a frequency discriminator and phase detector with dead zones. Near ±2π, the traditional frequency discriminator and phase detector has dead zones and cannot detect the rising edge of the input clock during the reset process, resulting in opposite output polarities. The average value of the output voltage of the frequency discriminator and phase detector is proportional to the loop gain of the phase-locked loop. The dead zone problem of the frequency discriminator and phase detector will cause the output signal polarities to be opposite, thereby reducing the average voltage value, reducing the loop gain, slowing down the locking speed of the phase-locked loop, and increasing the locking time.

[0045] Figure 6 It is the gain graph of the zero dead zone frequency discriminator and phase detector proposed in the embodiment of the present invention. When the phase difference between the input signal Fref and the feedback signal Fdiv of the zero dead zone frequency discriminator and phase detector is within the range of [-π, π], the zero dead zone frequency discriminator and phase detector has a linear gain; when the phase difference between the input signal Fref and the feedback signal Fdiv is within the ranges of [-2π, -π] and [π, 2π], the zero dead zone frequency discriminator and phase detector has a non-linear gain and the output voltage is a constant; the frequency discrimination and phase detection range of the zero dead zone frequency discriminator and phase detector is [-2π, 2π], which solves the dead zone problem of the traditional frequency discriminator and phase detector. At the same time, the average output voltage is high and the loop gain of the phase-locked loop is large, which can improve the locking speed of the phase-locked loop.

[0046] This embodiment includes a UP path formed by cascading a true single-phase clock and an inverter, and a DN path formed by cascading a true single-phase clock and an inverter, which are used to detect the frequency difference and phase difference between the input reference signal and the feedback signal in the self-biased phase-locked loop of a high-speed interface, convert them into corresponding electrical signals, and use them as the control signals for the subsequent charge pump to charge and discharge. This zero-blind-zone frequency discriminator and phase detector can eliminate the blind-zone problem of traditional frequency discriminators and phase detectors, enabling the phase difference that the frequency discriminator and phase detector can detect to cover [-2π, 2π]. At the same time, it can avoid the output polarity error caused by the loss of the rising edge of the input signal, ensure the correctness of the output polarity of the frequency discriminator and phase detector, and has a large output average voltage, which can improve the locking speed of the phase-locked loop.

[0047] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A zero blind zone frequency detector circuit for a high-speed interface self-biased phase-locked loop, characterized in that include: UP pathway and DN pathway; among them, The UP path is connected to the first charge pump and the second charge pump respectively; The DN path is connected to the first charge pump and the second charge pump respectively; The UP pathway is connected to the DN pathway; The UP path receives an input reference signal Fref, processes the input reference signal Fref to obtain an UP signal, and inputs the UP signal to the first charge pump and the second charge pump respectively, and the first charge pump and the second charge pump both obtain charging signals according to the UP signal; The DN path receives a clock division input signal Fdiv, processes the clock division input signal Fdiv to obtain a DN signal, and inputs the DN signal to the first charge pump and the second charge pump respectively. The first charge pump and the second charge pump both obtain discharge signals according to the DN signal.

2. The zero blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 1, characterized in that: The UP path includes a true single-phase clock TSPC1, an inverter INV1, an inverter INV2 and an inverter INV3; wherein, The input end of the true single-phase clock TSPC1 is connected to the output end of the inverter INV1 and the output end of the DN path respectively, and the output end of the true single-phase clock TSPC1 is connected to the input end of the inverter INV1; The output end of the inverter INV1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is respectively connected to the input end of the true single-phase clock TSPC1, the first charge pump, the second charge pump and the input end of the DN path.

3. The zero-blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 2, characterized in that: The DN path includes a true single-phase clock TSPC2, an inverter INV4, an inverter INV5 and an inverter INV6; wherein, The input end of the true single-phase clock TSPC2 is respectively connected to the output end of the inverter INV3, the output end of the inverter INV4 and the output end of the inverter INV6; The output end of the true single-phase clock TSPC2 is connected to the input end of the inverter INV4, the output end of the inverter INV4 is connected to the input end of the inverter INV5, the output end of the inverter INV5 is connected to the input end of the inverter INV6, and the output end of the inverter INV6 is respectively connected to the input end of the true single-phase clock TSPC1, the first charge pump and the second charge pump.

4. The zero-blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 2, characterized in that: The true single-phase clock TSPC1 includes a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M10 and an NMOS tube M11; The inverter INV1 includes a PMOS tube M4 and an NMOS tube M12; The inverter INV2 includes a PMOS tube M5 and an NMOS tube M13; The inverter INV3 includes a PMOS tube M6 and an NMOS tube M14; wherein, The source of the PMOS tube M1 is connected to a power supply, the drain of the PMOS tube M1 is respectively connected to the drain of the NMOS tube M7, the gate of the PMOS tube M2 and the gate of the NMOS tube M11, and the gate of the PMOS tube M1 is connected to an input reference signal Fref; The source of the PMOS tube M2 is connected to a power source, and the drain of the PMOS tube M2 is respectively connected to the drain of the NMOS tube M10, the drain of the PMOS tube M3, the gate of the PMOS tube M4 and the gate of the NMOS tube M12; The source of the PMOS tube M3 is connected to a power source, and the gate of the PMOS tube M3 is connected to the drain of the PMOS tube M4 and the drain of the NMOS tube M12 respectively; The source of the PMOS tube M5 is connected to a power supply, the gate of the PMOS tube M5 is respectively connected to the drain of the PMOS tube M4, the drain of the NMOS tube M12 and the gate of the NMOS tube M13, and the drain of the PMOS tube M5 is connected to the drain of the NMOS tube M13; The source of the PMOS tube M6 is connected to the power supply, the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M14, and the gate of the PMOS tube M6 is respectively connected to the gate of the NMOS tube M14, the drain of the PMOS tube M5, and the drain of the NMOS tube M13; The gate of the NMOS tube M7 is connected to the UP signal, the source of the NMOS tube M7 is connected to the drain of the NMOS tube M8, and the source of the NMOS tube M7 is respectively connected to the drain of the PMOS tube M1, the gate of the PMOS tube M2, and the gate of the NMOS tube M11; The gate of the NMOS tube M8 is connected to the DN signal, and the source of the NMOS tube M8 is connected to the drain of the NMOS tube M9; The gate of the NMOS tube M9 is connected to the input reference signal Fref, and the source of the NMOS tube M9 is grounded; The gate of the NMOS tube M10 is connected to the input reference signal Fref, and the source of the NMOS tube M10 is connected to the drain of the NMOS tube M11; The gate of the NMOS tube M11 is respectively connected to the gate of the PMOS tube M2, the drain of the PMOS tube M1 and the drain of the NMOS tube M7, and the source of the NMOS tube M11 is grounded; The gate of the NMOS tube M12 is respectively connected to the gate of the PMOS tube M4, the drain of the PMOS tube M3, the drain of the PMOS tube M2 and the drain of the NMOS tube M10; the drain of the NMOS tube M12 is respectively connected to the drain of the PMOS tube M4, the gate of the PMOS tube M3, the gate of the PMOS tube M5 and the gate of the NMOS tube M13; the source of the NMOS tube M12 is grounded; The gate of the NMOS tube M13 is respectively connected to the gate of the PMOS tube M5, the drain of the PMOS tube M4 and the drain of the NMOS tube M12, the drain of the NMOS tube M13 is respectively connected to the drain of the PMOS tube M5, the gate of the PMOS tube M6 and the gate of the NMOS tube M14, and the source of the NMOS tube M13 is grounded; The drain of the NMOS tube M14 is connected to the drain of the PMOS tube M6 , and the source of the NMOS tube M14 is grounded.

5. The zero-blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 3, characterized in that: The true single-phase clock TSPC2 includes a PMOS tube M15, a PMOS tube M16, a PMOS tube M17, an NMOS tube M21, an NMOS tube M22, an NMOS tube M23, an NMOS tube M24 and an NMOS tube M25; The inverter INV4 includes a PMOS tube M18 and an NMOS tube M26; The inverter INV5 includes a PMOS tube M19 and an NMOS tube M27; The inverter INV6 includes a PMOS tube M20 and an NMOS tube M28; wherein, The source of the PMOS tube M15 is connected to a power supply, the gate of the PMOS tube M15 is connected to a feedback signal Fdiv, and the drain of the PMOS tube M15 is respectively connected to the drain of the NMOS tube M21, the gate of the PMOS tube M16, and the gate of the NMOS tube M25; The source of the PMOS tube M16 is connected to a power source, and the drain of the PMOS tube M16 is respectively connected to the drain of the NMOS tube M24, the drain of the PMOS tube M17, the gate of the PMOS tube M18 and the gate of the NMOS tube M26; The source of the PMOS tube M17 is connected to a power supply, the gate of the PMOS tube M17 is connected to the drain of the PMOS tube M18 and the drain of the NMOS tube M26 respectively, and the drain of the PMOS tube M17 is connected to the drain of the PMOS tube M16, the gate of the PMOS tube M18, the drain of the NMOS tube M24 and the gate of the NMOS tube M26 respectively; The source of the PMOS tube M18 is connected to a power source, and the drain of the PMOS tube M18 is respectively connected to the gate of the PMOS tube M17, the drain of the NMOS tube M26, the gate of the PMOS tube M19, and the gate of the NMOS tube M27; The source of the PMOS tube M19 is connected to a power source, and the drain of the PMOS tube M19 is respectively connected to the gate of the PMOS tube M20, the drain of the NMOS tube M27, and the gate of the NMOS tube M28; The source of the PMOS tube M20 is connected to a power source, and the drain of the PMOS tube M20 is connected to the drain of the NMOS tube M28 as an output end of the DN path; The gate of the NMOS tube M21 is connected to the UP signal, the drain of the NMOS tube M21 is respectively connected to the drain of the PMOS tube M15, the gate of the PMOS tube M16 and the gate of the NMOS tube M25, and the source of the NMOS tube M21 is connected to the drain of the NMOS tube M22; The gate of the NMOS tube M22 is connected to the DN signal, and the source of the NMOS tube M22 is connected to the drain of the NMOS tube M23; The gate of the NMOS tube M23 is connected to the feedback signal Fdiv, and the source of the NMOS tube M23 is grounded; The gate of the NMOS tube M24 is connected to the feedback signal Fdiv, and the source of the NMOS tube M24 is connected to the drain of the NMOS tube M25; The gate of the NMOS tube M25 is respectively connected to the gate of the PMOS tube M16, the drain of the PMOS tube M15 and the drain of the NMOS tube M21, and the source of the NMOS tube M25 is grounded; The gate of the NMOS tube M26 is respectively connected to the gate of the PMOS tube M18, the drain of the PMOS tube M17, the drain of the PMOS tube M16, and the drain of the NMOS tube M24; the drain of the NMOS tube M26 is respectively connected to the drain of the PMOS tube M18, the gate of the PMOS tube M19, and the gate of the NMOS tube M27; the source of the NMOS tube M26 is grounded; The drain of the NMOS tube M27 is respectively connected to the drain of the PMOS tube M19, the gate of the PMOS tube M20 and the gate of the NMOS tube M28, and the source of the NMOS tube M27 is grounded; The drain of the NMOS tube M28 is connected to the drain of the PMOS tube M20 , and the source of the NMOS tube M28 is grounded.

6. The zero-blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 5, characterized in that: The point where the drain of the PMOS tube M1, the gate of the PMOS tube M2 and the drain of the NMOS tube M7 are all connected is defined as a node A1, the point where the drain of the PMOS tube M2, the drain of the NMOS tube M10, the drain of the PMOS tube M3 and the gate of the PMOS tube M4 are all connected is defined as a node A2, the point where the gate of the PMOS tube M5, the drain of the NMOS tube M12, the drain of the PMOS tube M4 and the gate of the NMOS tube M13 are all connected is defined as a node A3, and the point where the gate of the PMOS tube M6, the gate of the NMOS tube M14, the drain of the PMOS tube M5 and the drain of the NMOS tube M13 are all connected is defined as a node A4; The point where the drain of the PMOS tube M15, the drain of the NMOS tube M21, the gate of the PMOS tube M16 and the gate of the NMOS tube M25 are all connected is defined as a node B1, the point where the gate of the PMOS tube M17, the drain of the PMOS tube M18 and the NMOS tube M26 are all connected is defined as a node B2, the point where the drain of the PMOS tube M18, the drain of the NMOS tube M26, the gate of the PMOS tube M19 and the gate of the NMOS tube M27 are all connected is defined as a node B3, and the point where the drain of the PMOS tube M19, the gate of the PMOS tube M20, the drain of the NMOS tube M27 and the gate of the NMOS tube M28 are all connected is defined as a node B4.

7. The zero-blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 6, characterized in that: In the initial state, the input reference signal Fref and the feedback signal Fdiv are both at a low level, the PMOS tube M1 and the PMOS tube M15 are turned on, and the node A1 and the node B1 are charged to a high level.

8. The zero-blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 7, characterized in that: When the phase of the input reference signal Fref is ahead of the feedback signal Fdiv, and the phase difference is within the range of [0,π], when the rising edge of the input reference signal Fref arrives, the NMOS tubes M9 and M10 are turned on, and at the same time, the node A1 is at a high level, the NMOS tube M11 is turned on, the node A2 is at a low level, and the node A3 is pulled high to a high level through the inverter INV1, and the node A3 is pulled down to a low level through the inverter INV2, and then the UP signal is outputted at a high level through the inverter INV3; when the rising edge of the feedback signal Fdiv arrives, the NMOS tubes M23 and M24 are turned on, the node B1 is at a high level, and the NMOS tube M 25 is turned on, node B2 is at a low level, node B3 is pulled up to a high level through inverter INV4, node B3 is pulled down to a low level through inverter INV5, and then the output DN signal is at a high level through inverter INV6; at this time, the input reference signal Fref is still kept at a high level, the UP signal and the DN signal are at a high level at the same time, at this time, NMOS tubes M7, M8 and M9 are turned on at the same time, NMOS tubes M21, M22 and M23 are turned on at the same time, nodes A1 and B1 are pulled down to a low level, nodes A2 and B2 become high levels, and the output UP signal and DN signal are both low levels.

9. The zero-blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 7, characterized in that: When the phase of the input reference signal Fref is ahead of the feedback signal Fdiv, and the phase difference is in the range of [π, 2π], when the rising edge of the input reference signal Fref arrives, the UP signal is high, and when the rising edge of the feedback signal Fdiv arrives, the DN signal is high, the input signal Fref has become low, the NMOS tube M9 and the NMOS tube M10 are turned off, and the node A2 remains in its original state, so the UP signal also remains high. At this time, the UP signal and the DN signal are both high, the NMOS tubes M21, M22 and M23 of the DN path are turned on, the node B1 is discharged to a low level, and the node B2 becomes a high level. After passing through the three-stage inverters of inverter INV4, inverter INV5 and inverter INV6, the DN signal is output as a low level.

10. The zero-blind zone phase frequency detector circuit for a high-speed interface self-biased phase-locked loop according to claim 1, characterized in that: When the phase difference between the input signal Fref and the feedback signal Fdiv is in the range of [-π,π], the zero-blind zone frequency detector has a linear gain; when the phase difference between the input signal Fref and the feedback signal Fdiv is in the range of [-2π,-π] and [π,2π], the zero-blind zone frequency detector has a nonlinear gain and the output voltage is a constant.

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