Chip and frequency dividing circuit thereof, display panel and display equipment

Abstract

The invention discloses a chip and a frequency dividing circuit thereof, a display panel and a display device, and the frequency dividing circuit comprises a frequency divider which is used for obtaining a frequency dividing clock signal according to a reference clock signal, and the frequency dividing clock signal is a clock signal with the duty ratio being not 50%; and the asynchronous reset control circuit is connected with the frequency divider and is used for judging whether the working state of the frequency divider is a state in a frequency division loop working state machine or not and outputting a reset signal to the frequency divider according to a judgment result, so that a frequency division output result is not limited by an initial value after power-on, the frequency division loop working state machine can be immediately jumped to, and the frequency division loop working state machine can be switched to the frequency divider. And meanwhile, a few reference clock cycles do not need to be waited. In addition, the frequency dividing circuit further comprises a duty ratio adjusting circuit which is used for performing logical operation on the frequency dividing clock signal and the delayed frequency dividing clock signal to obtain an equal-duty-ratio frequency dividing clock signal; and the selector is used for selecting one of the frequency division clock signal and the equal-duty-ratio frequency division clock signal as an output frequency division clock signal according to the control signal.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency dividers, and particularly to a chip, its frequency division circuit, a display panel, and a display device. Background Art

[0002] With the large-scale development of the internal circuit system of a chip, especially in a complex digital-analog hybrid system, there are usually multiple clocks. In a multi-clock system, a digital counting frequency divider is often used to generate sub-clocks. In practical applications, the feedback clock in a phase-locked loop frequency multiplication circuit is also generated by a frequency divider. Therefore, the importance of a frequency divider with a preset frequency division duty cycle in the existing circuit system is obvious. For most frequency dividers, a 50% frequency division duty cycle is the optimal duty cycle. For the odd-frequency dividers in the prior art, under different implementations of the combined logic of the frequency division loop, when the initial value after power-on is not using synchronous reset, it may not be in the working state machine of the frequency division loop, thus generating an incorrect output signal, or it may be necessary to wait for several reference clock cycles to obtain the correct frequency division output, and its output cannot achieve a 50% frequency division duty cycle.

[0003] Figure 1 The circuit schematic diagram of a frequency divider according to the prior art is shown. Refer to Figure 1 , the frequency divider 100 is a 5-frequency odd-frequency divider, including three cascaded D flip-flops and a frequency division loop logic circuit 110. The output terminals Q of the three cascaded D flip-flops respectively provide output signals Q 2- Q 0 , the clock terminal CLK of each D flip-flop receives a reference clock signal CLK_REF, and the reset terminal RSTN receives a reset signal RST. Among them, the D flip-flop latches the signal at its input terminal D on the rising edge of the reference clock signal CLK_REF, and resets when the reset signal RST is at a low level. The frequency division loop logic circuit 110 is implemented by a NOR gate. The two input terminals of the NOR gate respectively receive the output signals Q 1 and Q 0 , and the output terminal is connected to the input terminal D of the first D flip-flop. The logic function of the frequency division loop is: , the frequency division duty cycle is 40%, and the Karnaugh map of the frequency division loop is:

[0004] It can be seen from the Karnaugh map that the working state machine of the frequency division loop of the frequency divider 100 does not include three states, namely "010", "101", and "111". When the initial value of Q 2 Q 1 Q 0 is one of these three states, it takes several reference clock cycles to jump to the state machine of the frequency division loop.

[0005] Figure 2 The circuit schematic diagram of another frequency division circuit according to the prior art is shown. Refer to Figure 1 and Figure 2 , the difference between the frequency divider 200 and the frequency divider 100 lies in the different frequency division loop logic circuits. The frequency division loop logic circuit 210 in the frequency divider 200 includes a NOT gate 211, an AND gate 212, an AND gate 213, and an OR gate 214. Two input terminals of the AND gate 212 respectively receive the output signal Q 0 and the output signal Q 1 after passing through the NOT gate 211. The output terminal of the AND gate 212 is connected to one of the input terminals of the OR gate 214. Three input terminals of the AND gate 213 respectively receive the output signal Q 2 , Q 1 , Q 0 . The output terminal of the AND gate 213 is connected to the other input terminal of the OR gate 214. The output terminal of the OR gate 214 is connected to the input terminal D of the first D flip-flop. The logic function of the frequency division loop is , the frequency division duty cycle is 60%, and the Karnaugh map of the frequency division loop is as follows:

[0006] It can be seen from the Karnaugh map that the working state machine of the frequency division loop of the frequency divider 200 does not include three states, namely "010", "011", and "100". When the initial value of Q 2 Q 1 Q 0 is "010", it can only jump to the working state machine of the frequency division loop after a reference clock cycle. When the initial value of Q 2 Q 1 Q 0 is "101" or "111", it will be locked between these two states and cannot jump to the working state machine of the frequency division loop, resulting in a functional error in the frequency divider 200.

[0007] Therefore, there is a need to propose a new frequency division circuit to solve the above problems. SUMMARY OF THE INVENTION

[0008] In view of the above problems, an object of the present invention is to provide a chip, its frequency division circuit, a display panel, and a display device, so that the frequency division output result is not limited by the initial value after power-on, can immediately jump to the working state machine of the frequency division loop, and does not need to wait for several reference clock cycles.

[0009] According to an aspect of the present invention, a frequency division circuit is provided, including a frequency divider for obtaining a frequency division clock signal according to a reference clock signal; an asynchronous reset control circuit connected to the frequency divider for judging whether the working state of the frequency divider is a state in the working state machine of the frequency division loop, and outputting a reset signal to the frequency divider according to the judgment result.

[0010] Optionally, the reference clock signal has a second active edge and a first active edge, and one clock cycle refers to the interval time between two adjacent first active edges of the reference clock signal. The divided clock signal is a clock signal with a duty cycle other than 50%.

[0011] Optionally, the frequency division circuit further includes a duty cycle adjustment circuit connected to the frequency divider. The duty cycle adjustment circuit is configured to obtain the divided clock signal when the first active edge of the reference clock signal arrives, latch the divided clock signal to obtain a delayed divided clock signal when the second active edge of the reference clock signal arrives, and perform a logical operation on the delayed divided clock signal and the divided clock signal to obtain an equal-duty-cycle divided clock signal.

[0012] Optionally, the frequency division circuit further includes a selector connected to the frequency divider and the duty cycle adjustment circuit. The selector is configured to select one of the divided clock signal and the equal-duty-cycle divided clock signal as the output divided clock signal according to a control signal.

[0013] Optionally, the frequency divider includes a plurality of cascaded first D flip-flops, and the output terminal of the last first D flip-flop provides the divided clock signal; a frequency division loop logic circuit, with multiple input terminals respectively connected to some or all of the output terminals of the plurality of first D flip-flops, and the output terminal is connected to the input terminal of the first first D flip-flop. Wherein, each first D flip-flop further includes a clock terminal and a reset terminal, the clock terminal receives the reference clock signal, and the reset terminal receives the reset signal.

[0014] Optionally, the number of the first D flip-flops is three; the frequency division loop logic circuit includes a first NOR gate, the first to second input terminals are respectively connected to the output terminals of the second and third first D flip-flops, and the output terminal is connected to the input terminal of the first first D flip-flop; the duty cycle adjustment circuit includes a second D flip-flop configured to latch the divided clock signal to obtain the delayed divided clock signal when the second active edge of the reference clock signal arrives; a second NOR gate configured to perform a NOR operation on the divided clock signal and the delayed divided clock signal to obtain the equal-duty-cycle divided clock signal. Wherein, the second D flip-flop further includes a clock terminal and a reset terminal, its clock terminal receives the reference clock signal, and its reset terminal receives the reset signal.

[0015] Optionally, the asynchronous reset control circuit includes a first AND gate having first to third input terminals and an output terminal; a second AND gate having first to second input terminals and an output terminal; a first NOT gate and a second NOT gate connected in sequence between the output terminal of a first D flip-flop and the first input terminal of the second AND gate, and an intermediate node between the first NOT gate and the second NOT gate is further connected to the first input terminal of the first AND gate; a third NOT gate and a fourth NOT gate connected in sequence between the output terminal of a second first D flip-flop and the second input terminal of the first AND gate; a fifth NOT gate and a sixth NOT gate connected in sequence between the output terminal of a third first D flip-flop and the second input terminal of the second AND gate, and an intermediate node between the fifth NOT gate and the sixth NOT gate is further connected to the third input terminal of the first AND gate; a third NOR gate, with its first to third input terminals respectively connected to the output terminal of the first AND gate, the output terminal of the second AND gate, and the turn-off signal, and its output terminal provides the reset signal.

[0016] Optionally, the number of the first D flip-flops is three; the frequency division loop logic circuit includes a third AND gate, with its first to third input terminals respectively connected to the output terminals of the three first D flip-flops; a fourth AND gate, with its first input terminal connected to the output terminal of the third first D flip-flop; a seventh NOT gate, with its input terminal connected to the output terminal of the second first D flip-flop and its output terminal connected to the second input terminal of the fourth AND gate; an OR gate, with its first and second input terminals respectively connected to the output terminal of the third AND gate and the output terminal of the fourth AND gate, and its output terminal connected to the input terminal of the first first D flip-flop; the duty cycle adjustment circuit includes a second D flip-flop for latching the frequency division clock signal to obtain the delayed frequency division clock signal when a second valid edge of the reference clock signal arrives; a fifth AND gate for performing an AND operation on the frequency division clock signal and the delayed frequency division clock signal to obtain the equal-duty-cycle frequency division clock signal, wherein the second D flip-flop further includes a clock terminal and a reset terminal, its clock terminal receives the reference clock signal, and its reset terminal receives the reset signal.

[0017] Optionally, the asynchronous reset control circuit includes a sixth AND gate having first to third input terminals and an output terminal; a seventh AND gate having first to third input terminals and an output terminal; an eighth NOT gate and a ninth NOT gate connected in sequence between the output terminal of the first first D flip-flop and the first input terminal of the seventh AND gate, and an intermediate node of the eighth NOT gate and the ninth NOT gate is further connected to the first input terminal of the sixth AND gate; a buffer, a tenth NOT gate, and an eleventh NOT gate connected in sequence between the output terminal of the second first D flip-flop and the second input terminal of the sixth AND gate; an intermediate node of the tenth NOT gate and the eleventh NOT gate is further connected to the second input terminal of the seventh AND gate; a twelfth NOT gate and a thirteenth NOT gate connected in sequence between the output terminal of the third first D flip-flop and the third input terminal of the sixth AND gate, and an intermediate node of the eleventh NOT gate and the twelfth NOT gate is further connected to the third input terminal of the seventh AND gate; a fourth NOR gate, the first to third input terminals of which are respectively connected to the output terminal of the sixth AND gate, the output terminal of the seventh AND gate, and a turn-off signal, and the output terminal provides the reset signal.

[0018] According to a second aspect of the present invention, there is provided a chip including the frequency division circuit as described above.

[0019] According to a third aspect of the present invention, there is provided a display panel including the frequency division circuit as described above.

[0020] Optionally, the display panel includes at least one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel, and a micro light emitting diode display panel.

[0021] According to a fourth aspect of the present invention, there is provided a display device including the chip as described above.

[0022] The chip, its frequency division circuit, display panel, and display device provided by the present invention detect whether the current state of the frequency divider is a state in the frequency division loop working state machine through an asynchronous reset control circuit, and output a reset signal according to the detection result, so that the frequency division output result is not limited by the initial value after power-on, and can immediately jump to the frequency division loop working state machine without waiting for several reference clock cycles.

[0023] In a preferred embodiment, by performing a logical operation on the frequency division clock signal and the delayed frequency division clock signal, an equal-duty-cycle frequency division clock signal can be obtained. The equal-duty-cycle frequency division clock signal can maintain the symmetry of the signal, avoid signal distortion, reduce electromagnetic interference and signal interference, and can be used in circuits that require precise timing.

[0024] In a preferred embodiment, the output frequency-divided clock signal of the frequency-dividing circuit can be switched between two signals with different duty cycles, namely the frequency-divided clock signal and the equal-duty-cycle frequency-divided clock signal, improving the compatibility of the frequency-dividing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features and advantages of the present invention will become more apparent. In the drawings: Figure 1 A circuit schematic diagram of a frequency-dividing circuit according to the prior art is shown; Figure 2 A circuit schematic diagram of another frequency-dividing circuit according to the prior art is shown; Figure 3 A structural schematic diagram of a frequency-dividing circuit according to an embodiment of the present invention is shown; Figure 4 A circuit schematic diagram of a frequency-dividing circuit according to the first embodiment of the present invention is shown; Figure 5 A circuit schematic diagram of a frequency-dividing circuit according to the second embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements or modules are denoted by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0027] It should be understood that in the following description, a "circuit" may include a single or a combination of multiple hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or when an element or circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0028] Meanwhile, in this patent specification and claims, certain terms are used to refer to specific components. Those of ordinary skill in the art should understand that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the criterion for distinction.

[0029] In addition, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0030] Figure 3 The structural schematic diagram of a frequency division circuit according to an embodiment of the present invention is shown.

[0031] See Figure 3 , the frequency division circuit 300 includes a frequency divider 310, an asynchronous reset control circuit 320, a duty cycle adjustment circuit 330, and a selector 340.

[0032] The frequency divider 310 is used to obtain a frequency division clock signal, i.e., the output signal Q, according to the reference clock signal CLK_REF 0 , the duty cycle of the frequency division clock signal Q 0 is not 50%. The frequency divider 310 includes a frequency division loop logic circuit and a plurality of cascaded first D flip-flops, and the plurality of cascaded first D flip-flops respectively provide a plurality of output signals Q N-1 -Q 0 (N represents the number of first D flip-flops). According to different frequency division loop logic circuits, the frequency division loop state machines of the frequency divider 310 are different, and the duty cycles of the frequency division clock signals Q 0 output by the frequency divider 310 are also different. The frequency divider 310 can select any existing odd-frequency divider as long as the duty cycle of the frequency division clock signal Q 0 output by it is not 50%. Among them, the reference clock signal CLK_REF has a first active edge and a second active edge, and one clock cycle refers to the interval time between two adjacent first active edges of the reference clock signal CLK_REF. By way of example, when the first active edge of the reference clock signal CLK_REF is a rising edge and the second active edge is a falling edge, one clock cycle refers to the interval time between two adjacent rising edges of the reference clock signal CLK_REF.

[0033] The asynchronous reset control circuit 320 is connected to the frequency divider 310 and is used to determine whether the current state of the frequency divider 310 is a state in the frequency division loop working state machine, and output a reset signal ASY_RST to the frequency divider 310 according to the determination result. Specifically, the asynchronous reset control circuit 320 determines whether the current state of the frequency divider 310 is a state in the frequency division loop working state machine according to a plurality of output signals Q N-1 -Q 0 When the current state of the frequency divider 310 is not a state in the frequency division loop working state machine, the reset signal ASY_RST is at a first level, and at this time, the reset signal ASY_RST controls the frequency divider 310 to reset; when the current state of the frequency divider 310 is a state in the frequency division loop working state machine, the reset signal ASY_RST is at a second level. It can be understood that the structure of the asynchronous reset control circuit 320 will change with the structure of the frequency division loop logic circuit in the frequency divider 310.

[0034] The duty cycle adjustment circuit 330 is connected to the frequency divider 310 and is used to obtain the divided frequency clock signal Q when the first valid edge of the reference clock signal CLK_REF arrives 0 and latch the divided frequency clock signal Q when the second valid edge of the reference clock signal CLK_REF arrives 0 to obtain a delayed divided frequency clock signal Q 0_1 and perform a logical operation on the delayed divided frequency clock signal Q 0_1 and the divided frequency clock signal Q 0 to obtain a divided frequency clock signal CLK1 with an equal duty cycle (duty cycle of 50%).

[0035] The selector 340 is used to select one of the equal duty cycle divided frequency clock signal CLK1 and the divided frequency clock signal Q according to the control signal SEL_DUTY 0 as the output divided frequency clock signal CLK_DIV of the frequency division circuit 300.

[0036] When the asynchronous reset control circuit 320 in the frequency division circuit 300 provided by the embodiment of the present invention detects that the current state of the frequency divider 310 is not a state in the frequency division loop working state machine, it will immediately control the frequency divider 310 to reset, so that the divided frequency output result is not limited by the initial value after power-on, and can immediately jump to the frequency division loop working state machine, and at the same time, there is no need to wait for several reference clock cycles.

[0037] Furthermore, by setting the selector 340, the output divided frequency clock signal CLK_DIV of the frequency division circuit 300 can be switched between different duty cycles.

[0038] Figure 4 FIG. shows a circuit schematic diagram of a frequency division circuit according to a first embodiment of the present invention.

[0039] See Figure 4 Figure 4 , the frequency divider 310 includes three cascaded first D flip - flops 311 - 313 and a frequency - division loop logic circuit 314. The output terminals Q of the three cascaded first D flip - flops respectively provide output signals Q 2- Q 0 0 . The clock terminal CLK of each first D flip - flop receives a reference clock signal CLK_REF, and the reset terminal RSTN receives a reset signal ASY_RST. Among them, the first D flip - flop latches the signal at its input terminal D on the first active edge of the reference clock signal CLK_REF and resets when the reset signal ASY_RST is at the first level. The frequency - division loop logic circuit 314 is implemented by a NOR gate. The first and second input terminals of the NOR gate are respectively connected to the output terminals of the first D flip - flops 312 and 313, and the output terminal of the NOR gate is connected to the input terminal D of the first D flip - flop 311. The frequency - division loop working state machine of the frequency divider 310 does not include three states, namely "010", "101", and "111".

[0040] The asynchronous reset control circuit 320 includes AND gates 321, 322, a NOR gate 323, and inverters 324 - 329. The AND gate 321 has first to third input terminals and an output terminal, and the AND gate 322 has first to second input terminals and an output terminal. The inverters 324 and 325 are sequentially connected between the output terminal of the first D flip - flop 311 and the first input terminal of the AND gate 322, and the intermediate node of the inverters 324 and 325 is connected to the first input terminal of the AND gate 321. The inverters 326 and 327 are sequentially connected between the output terminal of the first D flip - flop 312 and the second input terminal of the AND gate 321. The inverters 328 and 329 are sequentially connected between the output terminal of the first D flip - flop 313 and the second input terminal of the AND gate 322, and the intermediate node of the inverters 328 and 329 is connected to the third input terminal of the AND gate 321. The NOR gate 323 has first to third input terminals and an output terminal. The first to third input terminals are respectively connected to the output terminal of the AND gate 321, the output terminal of the AND gate 322, and a shutdown signal PD. The output terminal of the NOR gate 323 provides the reset signal ASY_RST. Among them, the shutdown signal PD is used to control the working state of the frequency - division circuit 300. When the shutdown signal PD is 1, the frequency - division circuit 300 is shut down, and when the shutdown signal PD is 0, the frequency - division circuit 300 works normally. By setting the inverters 324 - 329, the output signals Q 2- Q 0 0 are matched in the delay chain in the asynchronous reset logic to avoid glitches in the asynchronous reset logic. The logic function of the asynchronous reset control circuit 320 is: , and the Karnaugh map of the asynchronous reset is:

[0041] The duty cycle adjustment circuit 330 includes a second D flip-flop 331 and a NOR gate 332. The second D flip-flop 331 is used to latch the divided clock signal Q when the second valid edge of the reference clock signal CLK_REF arrives. 0 to obtain a delayed divided clock signal Q. 0_1 The NOR gate 332 is used to perform a NOR operation on the divided clock signal Q 0 and the delayed divided clock signal Q 0_1 to obtain an equal-duty-cycle divided clock signal CLK1. Among them, the input terminal D of the second D flip-flop 331 receives the divided clock signal Q 0 , the clock terminal CLK receives the reference clock signal CLK_REF, the reset terminal RSTN receives the reset signal ASY_RST, and the output terminal Q provides the delayed divided clock signal Q 0_1 . The first and second input terminals of the NOR gate 332 respectively receive the divided clock signal Q 0 and the delayed divided clock signal Q 0_1 , and the output terminal provides the equal-duty-cycle divided clock signal CLK1.

[0042] The selector 340 is used to select one of the equal-duty-cycle divided clock signal CLK1 and the divided clock signal Q 0 as the output divided clock signal CLK_DIV of the frequency division circuit 300, so that the output divided clock signal CLK_DIV of the frequency division circuit 300 can be switched between two different duty cycles.

[0043] Figure 5 FIG. shows a circuit schematic diagram of a frequency division circuit according to a second embodiment of the present invention.

[0044] Refer to Figure 5 , the frequency divider 310 includes three cascaded first D flip-flops 311-313 and a frequency division loop logic circuit 314. The output terminals Q of the three cascaded first D flip-flops respectively provide output signals Q 2- Q 0 . The clock terminal CLK of each first D flip-flop receives the reference clock signal CLK_REF, and the reset terminal RSTN receives the reset signal ASY_RST. Among them, the first D flip-flop latches the signal at its input terminal D on the first valid edge of the reference clock signal CLK_REF, and resets when the reset signal ASY_RST is at the first level.

[0045] The frequency division loop logic circuit 314 includes an OR gate 314a, a NOT gate 314d, and AND gates 314b and 314c. The input terminal of the NOT gate 314d is connected to the output terminal of the first D flip-flop 312. The first and second input terminals of the AND gate 314b are respectively connected to the output terminal of the first D flip-flop 313 and the output terminal of the NOT gate 314d, and the output terminal of the AND gate 314b is connected to the first input terminal of the OR gate 314a. The first to third input terminals of the AND gate 314c are respectively connected to the output terminals of the first D flip-flops 311 - 313, and the output terminal of the AND gate 314c is connected to the second input terminal of the OR gate 314a. The output terminal of the OR gate 314a is connected to the output terminal D of the first D flip-flop 311. Three states, namely "010", "011", and "100", are not included in the frequency division loop state machine of the frequency divider 310.

[0046] The asynchronous reset control circuit 320 includes AND gates 321 and 322, a NOR gate 323, NOT gates 324 - 329, and a buffer 320a. The AND gate 321 has first to third input terminals and an output terminal, and the AND gate 322 has first to third input terminals and an output terminal. The NOT gates 324 and 325 are sequentially connected between the output terminal of the first D flip-flop 311 and the first input terminal of the AND gate 322, and the intermediate node of the NOT gates 324 and 325 is connected to the first input terminal of the AND gate 321. The buffer 320a, the NOT gates 326 and 327 are sequentially connected between the output terminal of the first D flip-flop 312 and the second input terminal of the AND gate 321, and the intermediate node of the NOT gates 326 and 327 is connected to the second input terminal of the AND gate 322. The NOT gates 328 and 329 are sequentially connected between the output terminal of the first D flip-flop 313 and the third input terminal of the AND gate 321, and the intermediate node of the NOT gates 328 and 329 is connected to the third input terminal of the AND gate 322.

[0047] The NOR gate 323 has first to third input terminals and an output terminal. The first to third input terminals are respectively connected to the output terminal of the AND gate 321, the output terminal of the AND gate 322, and the shutdown signal PD, and the output terminal provides the reset signal ASY_RST. Among them, the shutdown signal PD is used to control the working state of the frequency division circuit 300. When the shutdown signal PD is 1, the frequency division circuit 300 is shut down, and when the shutdown signal PD is 0, the frequency division circuit 300 works normally. By setting the NOT gates 324 - 329 and the buffer 320a, the output signals Q of the first D flip-flops 311 - 313 can be made 2- Q 0 Match the delay chains in the asynchronous reset logic to avoid glitches in the asynchronous reset logic. The logic function of the asynchronous reset control circuit 320 is: , and the Karnaugh map of the asynchronous reset is:

[0048] The duty cycle adjustment circuit 330 includes a second D flip-flop 331 and an AND gate 332. The second D flip-flop 331 latches the divided clock signal Q when the second active edge of the reference clock signal CLK_REF arrives 0 to obtain an output delayed divided clock signal Q 0_1 . The AND gate 332 is used to perform an AND operation on the divided clock signal Q 0 and the delayed divided clock signal Q 0_1 to obtain an equal-duty-cycle divided clock signal CLK1. Among them, the input terminal D of the second D flip-flop 331 receives the divided clock signal Q 0 , the clock terminal CLK receives the reference clock signal CLK_REF, the reset terminal RSTN receives the reset signal ASY_RST, and the output terminal Q provides the delayed divided clock signal Q 0_1 . The first and second input terminals of the AND gate 332 respectively receive the divided clock signal Q 0 and the delayed divided clock signal Q 0_1 , and the output terminal provides the equal-duty-cycle divided clock signal CLK1.

[0049] The selector 340 is used to select one of the equal-duty-cycle divided clock signal CLK1 and the divided clock signal Q 0 as the output divided clock signal CLK_DIV of the frequency division circuit 300, so that the output divided clock signal CLK_DIV of the frequency division circuit 300 can be switched between two different duty cycles.

[0050] It can be understood that although the first and second embodiments of the present invention are described by taking a five-divider as an example, in actual applications, the divider adopted by the present invention can be any existing odd divider.

[0051] Furthermore, the present invention also provides a chip, including the above-mentioned frequency division circuit 300.

[0052] Furthermore, the present invention also provides a display panel, including the above-mentioned frequency division circuit 300. The display panel includes at least one of a liquid crystal display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a mini light-emitting diode display panel, and a micro light-emitting diode display panel.

[0053] Furthermore, the present invention also provides a display device, including the above-mentioned chip.

[0054] As described above with respect to the embodiments of the present invention, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications. The protection scope of the present invention shall be subject to the scope defined by the claims of the present invention and their equivalents.

Claims

1. A frequency division circuit, comprising: A frequency divider, used for obtaining a divided clock signal according to a reference clock signal; The asynchronous reset control circuit is connected to the frequency divider and is used to determine whether the working state of the frequency divider is the state in the frequency division loop working state machine, and output a reset signal to the frequency divider according to the determination result.

2. The frequency division circuit according to claim 1, wherein: The reference clock signal has a first effective edge and a second effective edge, a clock cycle refers to the interval time between two adjacent first effective edges of the reference clock signal, and the divided clock signal is a clock signal with a duty cycle other than 50%.

3. The frequency division circuit according to claim 2, further comprising: A duty cycle adjustment circuit is connected to the frequency divider and is used to obtain a divided clock signal when a first valid edge of the reference clock signal arrives, latch the divided clock signal when a second valid edge of the reference clock signal arrives to obtain a delayed divided clock signal, and perform logical operations on the delayed divided clock signal and the divided clock signal to obtain a divided clock signal with an equal duty cycle.

4. The frequency division circuit according to claim 3, further comprising: The selector is connected to the frequency divider and the duty cycle adjustment circuit, and is used for selecting one of the divided clock signal and the equal duty cycle divided clock signal as the output divided clock signal according to the control signal.

5. The frequency division circuit according to claim 3, wherein: The frequency divider comprises: A plurality of cascaded first D flip-flops, wherein the output end of the last first D flip-flop provides the frequency-divided clock signal; The frequency division loop logic circuit has a plurality of input terminals connected to part or all of the output terminals of a plurality of first D flip-flops respectively, and an output terminal connected to an input terminal of a first first D flip-flop, Each first D flip-flop further includes a clock terminal and a reset terminal, the clock terminal receives the reference clock signal, and the reset terminal receives the reset signal.

6. The frequency division circuit according to claim 5, wherein: The number of the first D flip-flops is three; the frequency division loop logic circuit comprises: A first NOR gate, wherein the first and second input terminals are respectively connected to the output terminals of the second and third first D flip-flops, and the output terminal is connected to the input terminal of the first first D flip-flop; The duty cycle adjustment circuit comprises: A second D flip-flop, used for latching the frequency-divided clock signal to obtain the delayed frequency-divided clock signal when a second valid edge of the reference clock signal arrives; A second NOR gate is used to perform a NOR operation on the divided frequency clock signal and the delayed divided frequency clock signal to obtain the divided frequency clock signal with equal duty ratio, The second D flip-flop further includes a clock terminal and a reset terminal, wherein the clock terminal receives the reference clock signal, and the reset terminal receives the reset signal.

7. The frequency division circuit according to claim 6, wherein: The asynchronous reset control circuit comprises: A first AND gate having first to third input terminals and an output terminal; A second AND gate having first and second input terminals and an output terminal; A first NOT gate and a second NOT gate are connected in sequence between an output terminal of a first D flip-flop and a first input terminal of the second AND gate, and an intermediate node between the first NOT gate and the second NOT gate is also connected to a first input terminal of the first AND gate; A third NOT gate and a fourth NOT gate are connected in sequence between the output terminal of the second first D flip-flop and the second input terminal of the first AND gate; A fifth NOT gate and a sixth NOT gate are connected in sequence between the output terminal of the third first D flip-flop and the second input terminal of the second AND gate, and an intermediate node between the fifth NOT gate and the sixth NOT gate is also connected to the third input terminal of the first AND gate; The third NOR gate has first to third input terminals connected to the output terminal of the first AND gate, the output terminal of the second AND gate and the shutdown signal respectively, and an output terminal providing the reset signal.

8. The frequency division circuit according to claim 5, wherein: The number of the first D flip-flops is three; the frequency division loop logic circuit comprises: A third AND gate, wherein the first to third input terminals are respectively connected to the output terminals of the three first D flip-flops; a fourth AND gate, a first input terminal connected to the output terminal of the third first D flip-flop; The seventh NOT gate has an input end connected to the output end of the second first D flip-flop, and an output end connected to the second input end of the fourth AND gate. An OR gate, wherein the first and second input terminals are respectively connected to the output terminal of the third AND gate and the output terminal of the fourth AND gate, and the output terminal is connected to the input terminal of the first first D flip-flop; The duty cycle adjustment circuit comprises: A second D flip-flop, used for latching the frequency-divided clock signal to obtain the delayed frequency-divided clock signal when a second valid edge of the reference clock signal arrives; a fifth AND gate, configured to perform an AND operation on the divided frequency clock signal and the delayed divided frequency clock signal to obtain the divided frequency clock signal with equal duty ratio, The second D flip-flop further includes a clock terminal and a reset terminal, wherein the clock terminal receives the reference clock signal, and the reset terminal receives the reset signal.

9. The frequency division circuit according to claim 8, wherein: The asynchronous reset control circuit comprises: a sixth AND gate having first to third input terminals and an output terminal; a seventh AND gate having first to third input terminals and an output terminal; An eighth NOT gate and a ninth NOT gate are connected in sequence between the output terminal of the first first D flip-flop and the first input terminal of the seventh AND gate, and the middle node of the eighth NOT gate and the ninth NOT gate is also connected to the first input terminal of the sixth AND gate; The buffer, the tenth NOT gate and the eleventh NOT gate are sequentially connected between the output terminal of the second first D flip-flop and the second input terminal of the sixth AND gate; the intermediate node of the tenth NOT gate and the eleventh NOT gate is also connected to the second input terminal of the seventh AND gate; The twelfth NOT gate and the thirteenth NOT gate are connected in sequence between the output terminal of the third first D flip-flop and the third input terminal of the sixth AND gate, and the intermediate node between the eleventh NOT gate and the twelfth NOT gate is also connected to the third input terminal of the seventh AND gate; The fourth NOR gate has first to third input terminals connected to the output terminal of the sixth AND gate, the output terminal of the seventh AND gate and the shutdown signal respectively, and an output terminal providing the reset signal.

10. A chip comprising the frequency division circuit according to any one of claims 1 to 9.

11. A display panel, comprising the frequency division circuit according to any one of claims 1 to 9.

12. The display panel according to claim 11, wherein: The display panel includes at least one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel and a micro light emitting diode display panel.

13. A display device comprising the chip according to claim 10.

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