High-speed high-precision peak detector in zero-intermediate-frequency receiver and receiver

Abstract

The invention provides a high-speed high-precision peak detector in a zero intermediate frequency receiver and a receiver, the peak detector is integrated at the output end of a trans-impedance amplifier, and the peak detector comprises a differential detection module working in a sub-threshold region; the high and low threshold voltage detection module provides a high threshold voltage control signal and a low threshold voltage control signal for the differential detection module, so that the differential detection module performs peak detection on the voltage signal output by the transimpedance amplifier and generates a level signal with ripples; the two parallel four-port high-speed comparators are used for carrying out peak detection based on the level signal and preset high and low threshold voltages so as to output a comparison level; and the shaping module is used for shaping the comparison level to obtain a corresponding code value, so that a receiver performs gain adjustment based on the code value, and the detection peak value of the output end of the trans-impedance amplifier is limited between the preset high and low threshold voltages. The peak detection precision and speed can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of digital-analog hybrid circuits, and in particular to a high-speed and high-precision peak detector and a receiver in a zero intermediate frequency receiver. Background Art

[0002] With the continuous evolution of communication protocols and the continuous progress of integrated circuit technology, the application of RFSOC (radio frequency system-level transceiver chip) is becoming more and more extensive. The integration of RF circuits, digital circuits and analog circuits in a single chip has become a mainstream direction for the future development of the integrated circuit field. As the main link part of the RFSOC receiving signal, the receiver undertakes the main functions of receiving, amplifying, mixing, filtering, digital-to-analog conversion, etc. In order to maintain the input swing of the ADC (digital-to-analog converter) within the allowable full swing range, it is necessary to configure different link gains for received signals of different strengths. It is required to monitor the voltage amplitude passing through the TIA (transimpedance amplifier) ​​and adjust the gain of the entire link by inputting the output code value into the digital circuit. The common peak detection circuit is composed of a diode and a capacitor. The unidirectional conduction characteristic of the diode is used to store the voltage in the capacitor. However, since the working performance of the diode is greatly affected by temperature and it takes a certain amount of time to conduct, this limits the accuracy and speed of the peak detection circuit. Summary of the invention

[0003] In view of the above problems existing in the prior art, the present invention proposes a high-speed and high-precision peak detector and a receiver in a zero intermediate frequency receiver, which mainly solves the problem that the accuracy and speed of the existing peak detection circuit are difficult to meet the actual application requirements.

[0004] In order to achieve the above purpose and other purposes, the technical solution adopted by the present invention is as follows.

[0005] The present application provides a high-speed and high-precision peak detector in a zero intermediate frequency receiver, wherein the peak detector is integrated at the output end of a transimpedance amplifier, and the peak detector comprises: a differential detection module, which operates in a subthreshold region; a high and low threshold voltage detection module, which provides a high threshold voltage control signal and a low threshold voltage control signal to the differential detection module, so that the differential detection module performs peak detection on the voltage signal output by the transimpedance amplifier to generate a level signal with ripples; two four-port high-speed comparators in parallel, which perform peak detection based on the level signal and preset high and low threshold voltages to output a comparison level; a shaping module, which shapes the comparison level to obtain a corresponding code value, so that the receiver performs gain adjustment based on the code value to limit the peak value detected at the output end of the transimpedance amplifier to between the preset high and low threshold voltages.

[0006] In an embodiment of the present application, the peak detector further includes a buffer, and the code value is input into a digital circuit after passing through the buffer to generate a gain of a corresponding link in the receiver.

[0007] In one embodiment of the present application, the differential detection module includes: a first NMOS tube, a second NMOS tube, a third PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh PMOS tube, a twelfth NMOS tube, a first capacitor, a second capacitor and a third capacitor; wherein the gate of the first NMOS tube serves as the positive input terminal of the peak detector, and the gate of the second NMOS tube serves as the negative input terminal of the peak detector; and the drain of the first NMOS tube is connected to the drain of the second NMOS tube and connected to the power supply voltage, the source of the first NMOS tube and the source of the second NMOS tube are connected and connected to the input terminal of the transmission gate circuit and the drain of the eighth NMOS tube, the third PMOS tube and the fourth NMOS tube constitute the transmission gate circuit, and the output terminal of the transmission gate circuit serves as the output terminal of the peak detector, and is connected to the drain of the twelfth NMOS tube and connected through the first circuit. The capacitor is grounded, and the source of the twelfth NMOS tube is grounded; the seventh NMOS tube and the eighth NMOS tube form a first current mirror circuit, and the source of the eleventh PMOS tube is connected to the seventh NMOS tube and the gate of the eighth NMOS tube, and is connected to the gate of the ninth NMOS tube and the gate of the tenth NMOS tube; the source of the ninth NMOS tube and the source of the tenth NMOS tube are grounded, the drain of the ninth NMOS tube is connected to the source of the fifth NMOS tube as the high threshold voltage output end of the peak detector and is grounded through the second capacitor; the drain of the tenth NMOS tube is connected to the source of the sixth NMOS tube as the low threshold voltage output end of the peak detector and is grounded through the third capacitor; the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are connected to the power supply voltage, the gate of the fifth NMOS tube is connected to the high threshold voltage control end of the high and low threshold voltage detection module, and the gate of the sixth NMOS tube is connected to the low threshold voltage control end of the high and low threshold voltage detection module.

[0008] In one embodiment of the present application, the high and low threshold voltage detection module includes a second current mirror circuit, a resistor array, a source follower and an operational amplifier. The second current mirror circuit provides an input level for the resistor array and the operational amplifier. The operational amplifier compares the input level with a reference level to generate a control level input to the control end of the source follower. The output end of the source follower provides a switching voltage for the switching devices in the resistor array to encode the resistor array and generate a high threshold voltage control signal and a low threshold voltage control signal.

[0009] In one embodiment of the present application, the resistor array includes 63 resistors connected in series in sequence, each end of each resistor is connected to two switching units in parallel with each other and are respectively connected to the high threshold voltage control end and the low threshold voltage control end. By controlling each switching unit to select the connected resistance value, the encoding is completed to generate a corresponding control signal.

[0010] In one embodiment of the present application, the high-speed comparator includes a PMOS input stage and an NMOS input stage, wherein the PMOS input stage has the same circuit structure as the NMOS input stage, and the device using the PMOS tube in the PMOS stage correspondingly uses the NMOS tube in the NMOS stage, and the NMOS input stage includes a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube, a first enabling PMOS tube, and a second enabling PMOS tube. S tube, a third enabling NMOS tube, a fourth enabling NMOS tube and an inverter; the gate of the thirteenth NMOS tube is connected to the output end of the peak detector, and the gate of the fourteenth NMOS tube is connected to the high threshold voltage output end or the low threshold voltage output end; the source of the thirteenth NMOS tube is connected to the source of the fourteenth NMOS tube and connected to the drain of the thirty-seventh NMOS tube, the drain of the thirteenth NMOS tube is respectively connected to the source of the fifteenth PMOS tube, the source of the seventeenth PMOS tube and the gate of the twentieth PMOS tube; the drain of the fourteenth NMOS tube is respectively connected to the source of the sixteenth PMOS tube, the source of the eighteenth PMOS tube and the gate of the twentieth PMOS tube; the drain of the fourteenth NMOS tube is respectively connected to the source of the sixteenth PMOS tube, the source of the eighteenth PMOS tube and the gate of the twentieth PMOS tube; The gate of the seventeenth PMOS tube is connected to the source, the gate of the eighteenth PMOS tube is connected to the source, the gate of the fifteenth PMOS tube is connected to the source of the sixteenth PMOS tube, and the source of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube; the drains of the fifteenth PMOS tube, the sixteenth PMOS tube, the seventeenth PMOS tube, the eighteenth PMOS tube, the nineteenth PMOS tube and the twentieth PMOS tube are connected to the power supply voltage; the gate of the nineteenth PMOS tube is also connected to the source of the first enabling PMOS tube, the drain of the first enabling PMOS tube is connected to the second enabling PMOS The gate of the 20th PMOS tube is also connected to the source of the second enabling PMOS tube, and the gate of the first enabling PMOS tube is connected to the gate of the second enabling PMOS tube; the source of the 19th PMOS tube is connected to the drain of the 21st NMOS tube, and the source of the 20th PMOS tube is connected to the drain of the 22nd NMOS tube as the output end of the high-speed comparator; the gate and drain of the 21st NMOS tube are connected and connected to the gate of the 22nd NMOS tube; the source of the 21st NMOS tube and the source of the 22nd NMOS tube are grounded respectively, and the drain of the third enabling NMOS tube is connected to the gate of the 22nd NMOS tube;The gate and drain of the thirty-sixth NMOS tube are connected and connected to the gate of the thirtieth NMOS tube, the source of the thirty-sixth NMOS tube and the source of the thirty-seventh NMOS tube are grounded respectively, the drain of the fourth enabling NMOS tube is connected to the gate of the thirty-seventh NMOS tube; the drain of the thirty-sixth NMOS tube is connected to the drain of the corresponding transistor of the PMOS input stage; the source of the third enabling NMOS tube and the source of the fourth enabling NMOS tube are grounded; the gate of the third enabling NMOS tube and the gate of the fourth enabling NMOS tube are connected to the output end of the inverter; the input end of the inverter of the NMOS input stage is connected to the output end of the inverter of the PMOS input stage; the input end of the inverter of the PMOS input stage is connected to the enable signal; the output end of the high-speed comparator is also connected to the drain of the fifth enabling NMOS tube, the gate of the fifth enabling NMOS tube is connected to the output end of the inverter of the NMOS input stage, and the source is grounded. ;

[0011] The present application also provides a zero intermediate frequency receiver, comprising the peak detector and a low noise amplifier, a mixer, a transimpedance amplifier, an active filter, and an analog-to-digital converter that are cascaded in sequence, wherein the peak detector is integrated at the output end of the transimpedance amplifier.

[0012] As described above, the high-speed and high-precision peak detector and receiver in a zero intermediate frequency receiver proposed in the present application have the following beneficial effects.

[0013] The present application integrates a high-speed and high-precision peak detector at the output end of a transimpedance amplifier. The current signal output by the RF front-end mixer is converted into a voltage signal by the transimpedance amplifier. The peak value is detected by a differential pair tube working in the subthreshold region and a level signal with ripple is output. The level signal and the set high and low threshold voltages are respectively input into two four-port high-speed comparators to achieve high-precision and high-speed detection of the peak detection circuit. The output level signal of the comparator is then shaped to obtain a corresponding code value. The code value is then sent to a digital circuit to adjust the receiver system gain so that the peak value detected at the output end of the transimpedance amplifier is within the set high and low voltage thresholds. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the overall architecture of a zero intermediate frequency receiver in one embodiment of the present application.

[0015] Figure 2 Schematic diagram of a differential detection module and a high and low threshold voltage detection module in an embodiment of the present application.

[0016] Figure 3 This is a circuit diagram of a high-speed comparator in one embodiment of the present application.

[0017] Figure 4Schematic diagram of the circuit architecture of the high and low threshold detection module in one embodiment of the present application.

[0018] Figure 5 This is a peak detection waveform diagram in one embodiment of the present application.

[0019] Description of Figure Numbers:

[0020] M1-first NMOS tube; M2-second NMOS tube; M3-third PMOS tube; M4-fourth NMOS tube; M5-fifth NMOS tube; M6-sixth NMOS tube; M7-seventh NMOS tube; M8-eighth NMOS tube; M9-ninth NMOS tube; M10-tenth NMOS tube; M11-eleventh PMOS tube; M12-twelfth NMOS; C1-first capacitor; C2-second capacitor; C3-third capacitor; M13-thirteenth NMOS tube; M14-fourteenth NMOS tube; M15-fifteenth PMOS tube; M16-sixteenth PMOS tube; M17-seventeenth PMOS tube; M18-eighteenth PMOS tube; M19-nineteenth PMOS tube; M20-twentieth PMOS tube; M21-twenty-first NMOS tube; M22-twenty-second NMOS tube; M36-thirty-sixth NMOS tube; M37-thirty-seventh NMOS tube. DETAILED DESCRIPTION

[0021] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0022] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0023] See also Figure 1 , Figure 1The overall architecture diagram of the zero intermediate frequency receiver in one embodiment of the present application. The receiver includes a peak detector and a low noise amplifier, a mixer, a transimpedance amplifier, an active filter, and an analog-to-digital converter that are cascaded in sequence, wherein the peak detector is integrated at the output end of the transimpedance amplifier. The receiver receives an external analog signal by an LNA (low noise amplifier) ​​and amplifies it, and then sends it to the mixer for down-mixing operation to generate a differential output current signal and then sends it to the input end of the TIA (transimpedance amplifier). After the transimpedance amplification of the TIA, the current signal is converted into a voltage signal and input to the next-level active filter, and then the voltage signal is further filtered and amplified by the active filter and sent to the ADC for digital-to-analog conversion to output a digital signal, which is received by a large digital module for signal processing operations. A peak detection module is introduced at the output end of the TIA to monitor the signal amplitude, which is composed of a detection circuit, a four-port high-speed comparator, a Schmitt trigger, a buffer, and a high and low threshold detection module to achieve high-precision and high-speed peak detection in the receiver.

[0024] In one embodiment, the peak detection circuit includes: a differential detection module, which works in the subthreshold region; a high and low threshold voltage detection module, which provides a high threshold voltage control signal and a low threshold voltage control signal for the differential detection module, so that the differential detection module performs peak detection on the voltage signal output by the transimpedance amplifier to generate a level signal with ripples; two four-port high-speed comparators in parallel, which perform peak detection based on the level signal and the preset high and low threshold voltages to output a comparison level; a shaping module, which shapes the comparison level to obtain a corresponding code value, so that the receiver performs gain adjustment based on the code value to limit the peak value detected at the output end of the transimpedance amplifier between the preset high and low threshold voltages. In one embodiment, the peak detector also includes a buffer, and the code value is input into a digital circuit after passing through the buffer to generate the gain of the corresponding link in the receiver. Among them, the Schmitt trigger can be used to shape the comparison level.

[0025] See also Figure 2 , Figure 2The schematic diagram of the differential detection module and the high and low threshold voltage detection module in an embodiment of the present application. The differential detection module includes: a first NMOS tube, a second NMOS tube, a third PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh PMOS tube, a twelfth NMOS tube, a first capacitor, a second capacitor and a third capacitor; wherein the gate of the first NMOS tube serves as the positive input terminal of the peak detector, and the gate of the second NMOS tube serves as the negative input terminal of the peak detector; and the drain of the first NMOS tube is connected to the drain of the second NMOS tube and connected to the power supply voltage, the source of the first NMOS tube and the source of the second NMOS tube are connected and connected to the input terminal of the transmission gate circuit and the drain of the eighth NMOS tube, the third PMOS tube and the fourth NMOS tube form a transmission gate circuit, and the output terminal of the transmission gate circuit serves as the output terminal of the peak detector, and is connected to the drain of the twelfth NMOS tube and connected to the power supply voltage. The first capacitor is connected to the ground, and the source of the twelfth NMOS tube is connected to the ground; the seventh NMOS tube and the eighth NMOS tube form a first current mirror circuit, and the source of the eleventh PMOS tube is connected to the gate of the seventh NMOS tube and the eighth NMOS tube, and the gate of the ninth NMOS tube and the gate of the tenth NMOS tube are connected; the source of the ninth NMOS tube and the source of the tenth NMOS tube are grounded, the drain of the ninth NMOS tube is connected to the source of the fifth NMOS tube as the high threshold voltage output end of the peak detector and is grounded through the second capacitor; the drain of the tenth NMOS tube is connected to the source of the sixth NMOS tube as the low threshold voltage output end of the peak detector and is grounded through the third capacitor; the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are connected to the power supply voltage, the gate of the fifth NMOS tube is connected to the high threshold voltage control end of the high and low threshold voltage detection module, and the gate of the sixth NMOS tube is connected to the low threshold voltage control end of the high and low threshold voltage detection module. Specifically, the differential detection module consists of a pair of differential pair tubes M1 and M2 working in the subthreshold region, transmission gate switches M3 and M4, high threshold detection MOS tube M5, low threshold detection MOS tube M6, current mirror loads M7, M8, M9, M10, detection circuit enable switches M11 and M12, and load capacitors C1, C2, and C3. M1, M2, M5, and M6 work in the subthreshold region. Since the working current of the MOS tube in the subthreshold region is very small, which is in the order of nA, the detection circuit can work under extremely low power consumption conditions, and the subthreshold region MOS tube presents a triode working state for peak detection, V p and V M They are respectively the positive input and negative input of the next low-pass filter, and its differential input is V in =v i cosωt, according to the subthreshold characteristics of the MOS tube, the total input current of the differential pair M1 and M2 tubes is Using the Bessel function approximation, we can get The input current of the threshold detection MOS tube is The input tubes in the circuit are designed to be the same size, and the current source replication ratio is set to the same value. According to the same current values ​​on the left and right sides, we can get V G1,2 Set to V B By setting the control value of the high and low threshold detection module, V G5 V B +LOT<5:0>*V Δ , V G6 V B +SOT<5:0>*V Δ , V Δ is the voltage across each resistor in the resistor array in the high and low threshold detection module. The voltage output by the source follower is From the formula, it can be seen that by reasonably setting the control values ​​of the high and low threshold detection modules, the amplitude range of the input to the peak detector can be accurately detected to achieve high-precision and high-speed detection functions. The signal after the detection circuit will be V A (peak detector output voltage), V L (set high threshold voltage), V S (The set low threshold voltage) is sent to the high-speed comparator for comparison.

[0027] See also Figure 3 , Figure 3The circuit diagram of the high-speed comparator in one embodiment of the present application is as follows. In one embodiment, the high-speed comparator includes a PMOS input stage and an NMOS input stage, wherein the circuit structure of the PMOS input stage is the same as that of the NMOS input stage, and the device using the PMOS tube in the PMOS stage uses the NMOS tube in the NMOS stage, and the NMOS input stage includes a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube, a first enabling PMOS tube, a second enabling PMOS tube, a third enabling NMOS tube, and a fourth The gate of the thirteenth NMOS tube is connected to the output end of the peak detector, and the gate of the fourteenth NMOS tube is connected to the high threshold voltage output end or the low threshold voltage output end; the source of the thirteenth NMOS tube is connected to the source of the fourteenth NMOS tube and connected to the drain of the thirty-seventh NMOS tube, and the drain of the thirteenth NMOS tube is respectively connected to the source of the fifteenth PMOS tube, the source of the seventeenth PMOS tube and the gate of the twentieth PMOS tube; the drain of the fourteenth NMOS tube is respectively connected to the source of the sixteenth PMOS tube, the source of the eighteenth PMOS tube and the gate of the nineteenth PMOS tube; the gate of the seventeenth PMOS tube is connected to the source, the gate of the eighteenth PMOS tube is connected to the source, and the gate of the tenth The gate of the fifth PMOS tube is connected to the source of the sixteenth PMOS tube, and the source of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube; the drains of the fifteenth PMOS tube, the sixteenth PMOS tube, the seventeenth PMOS tube, the eighteenth PMOS tube, the nineteenth PMOS tube and the twentieth PMOS tube are connected to the power supply voltage; the gate of the nineteenth PMOS tube is also connected to the source of the first enabling PMOS tube, and the drain of the first enabling PMOS tube is connected to the drain of the second enabling PMOS tube; the gate of the twentieth PMOS tube is also connected to the source of the second enabling PMOS tube, and the gate of the first enabling PMOS tube is connected to the gate of the second enabling PMOS tube; the source of the nineteenth PMOS tube is connected to the drain of the twenty-first NMOS tube , the source of the twentieth PMOS tube is connected to the drain of the twenty-second NMOS tube as the output end of the high-speed comparator; the gate and drain of the twenty-first NMOS tube are connected and connected to the gate of the twenty-second NMOS tube; the source of the twenty-first NMOS tube and the source of the twenty-second NMOS tube are grounded respectively, and the drain of the third enabling NMOS tube is connected to the gate of the twenty-second NMOS tube; the gate and drain of the thirty-sixth NMOS tube are connected and connected to the gate of the thirtieth NMOS tube, the source of the thirty-sixth NMOS tube and the source of the thirty-seventh NMOS tube are grounded respectively, and the drain of the fourth enabling NMOS tube is connected to the gate of the thirty-seventh NMOS tube; the drain of the thirty-sixth NMOS tube is connected to the drain of the corresponding transistor of the PMOS input stage;The source of the third enabling NMOS tube and the source of the fourth enabling NMOS tube are grounded; the gate of the third enabling NMOS tube and the gate of the fourth enabling NMOS tube are connected to the output of the inverter; wherein the input of the inverter of the NMOS input stage is connected to the output of the inverter of the PMOS input stage; the input of the inverter of the PMOS input stage is connected to the enable signal; the output of the high-speed comparator is also connected to the drain of the fifth enabling NMOS tube, the gate of the fifth enabling NMOS tube is connected to the output of the inverter of the NMOS input stage, and the source is grounded. Specifically, the four-port high-speed comparator is composed of a comparator with an NMOS input and a comparator with a PMOS input, M13 and M14 are NMOS input pair tubes, M15, M16, M17, and M18 are cross-coupled load tubes, and M19, M20, M21, and M22 are second-stage comparators. M23 and M24 are PMOS input pair transistors, M25, M26, M27, and M28 are cross-coupled load transistors, M29, M30, M31, and M32 are second-stage comparators, M33, M34, M35, M36, and M37 are current source transistors, and the remaining MOS transistors are enable transistors. V of the detection circuit; A As a high-speed comparator V P1 Terminal, V L and V S As the V of the high threshold detection high speed comparator and the low threshold detection high speed comparator respectively. M1 When the NMOS input high-speed comparator input V P1 is high, V M1 When V is low, the drain voltage of M13 is low and the drain voltage of M14 is high. The positive feedback of the cross-coupled load tube accelerates the decrease of the drain voltage of M13 and the increase of the drain voltage of M14. G19 The voltage is high, causing M21 to turn off, and M22 will also turn off accordingly, and V G20 The voltage is low, making the comparator output level high. Similarly, when the V input of the high-speed comparator of the PMOS input P1 is high, V M1 When V is low, the drain voltage of M23 is low and the drain voltage of M24 is high. The positive feedback of the cross-coupled load tube accelerates the decrease of the drain voltage of M23 and the increase of the drain voltage of M24. G29 The voltage is high, causing M31 to turn off, and M32 will also turn off accordingly, while V G30 The voltage is low, making the comparator output level high. Through the four-port input, the two comparators work together to accelerate the comparison speed of the comparator, and can realize high-speed comparison function. P1 >V M1 When the comparator output voltage is high, V P1 <V M1When the comparator output voltage is low, the output voltage is cascaded with a Schmitt trigger, which speeds up the rising or falling edge of the comparator output voltage value when it jumps to a high or low level, plays a role in waveform shaping, and is delayed by a group of buffers, and finally output to the digital circuit for processing and adjusts the gain value of the entire link through the internal algorithm.

[0028] See also Figure 4 , Figure 4 The circuit architecture diagram of the high and low threshold detection module in one embodiment of the present application. The high and low threshold voltage detection module includes a second current mirror circuit, a resistor array, a source follower and an operational amplifier. The second current mirror circuit provides an input level for the resistor array and the operational amplifier. The operational amplifier compares the input level with the reference level to generate a control level input to the control end of the source follower. The output end of the source follower provides a switching voltage for the switch device in the resistor array to encode the resistor array and generate a high threshold voltage control signal and a low threshold voltage control signal. The resistor array includes 63 resistors connected in series in sequence, and each end of each resistor is connected to two parallel switch units and connected to the high threshold voltage control end and the low threshold voltage control end respectively. By controlling each switch unit to select the resistance value connected, the encoding is completed to generate the corresponding control signal. Specifically, the high and low threshold voltage detection module has an operational amplifier to provide a positive terminal voltage and a negative terminal voltage for the resistor array. Each resistor is controlled by LOT<5:0> and SOT<5:0> to control the encoder, thereby controlling the transmission gate switch of the resistor array to control the size of the high and low thresholds. As can be seen from the figure, there are 63 resistors in total and 64 switches in total, providing a threshold range from Vref to Vout, which can achieve precise control of the threshold range.

[0029] See also Figure 5 , Figure 5 : is a peak detection waveform diagram in one embodiment of the present application. P is the positive input of the peak detector, V M The negative input of the peak detector, V CM Set to V ref Value, which is the common mode voltage value of the peak detection circuit input pair tube. A To detect the output voltage of the tube, V L is the voltage output by the high threshold detection tube, V S is the voltage output by the low threshold detection tube. CP_S is the voltage signal output by the low threshold detection comparator, and CP_L is the voltage signal output by the high threshold detection comparator.

[0030] The present application integrates a high-speed and high-precision peak detector at the output end of a transimpedance amplifier. The current signal output by the RF front-end mixer is converted into a voltage signal by the transimpedance amplifier. The peak value is detected by a differential pair tube working in the subthreshold region and a level signal with ripple is output. The level signal and the set high and low threshold voltages are respectively input into two four-port high-speed comparators to achieve high-precision and high-speed detection of the peak detection circuit. The output level signal of the comparator is then shaped to obtain a corresponding code value. The code value is then sent to a digital circuit to adjust the receiver system gain so that the peak value detected at the output end of the transimpedance amplifier is within the set high and low voltage thresholds.

[0031] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A high-speed and high-precision peak detector in a zero intermediate frequency receiver, characterized in that: The peak detector is integrated at the output end of the transimpedance amplifier, and the peak detector includes: A differential detection module, which operates in the subthreshold region; A high and low threshold voltage detection module, which provides a high threshold voltage control signal and a low threshold voltage control signal to the differential detection module, so that the differential detection module performs peak detection on the voltage signal output by the transimpedance amplifier to generate a level signal with ripples; Two four-port high-speed comparators in parallel with each other, which perform peak detection based on the level signal and preset high and low threshold voltages to output a comparison level; A shaping module shapes the comparison level to obtain a corresponding code value, so that the receiver performs gain adjustment based on the code value to limit the output end detection peak of the transimpedance amplifier to between the preset high and low threshold voltages.

2. The high-speed and high-precision peak detector in a zero intermediate frequency receiver according to claim 1, characterized in that: The peak detector further includes a buffer, and the code value is input into a digital circuit after passing through the buffer to generate a gain of a corresponding link in the receiver.

3. The high-speed and high-precision peak detector in a zero intermediate frequency receiver according to claim 1, characterized in that: The differential detection module includes: a first NMOS tube, a second NMOS tube, a third PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh PMOS tube, a twelfth NMOS tube, a first capacitor, a second capacitor and a third capacitor; wherein the gate of the first NMOS tube serves as the positive input terminal of the peak detector, and the gate of the second NMOS tube serves as the negative input terminal of the peak detector; and the drain of the first NMOS tube is connected to the drain of the second NMOS tube and connected to the power supply voltage, the source of the first NMOS tube and the source of the second NMOS tube are connected and connected to the input terminal of the transmission gate circuit and the drain of the eighth NMOS tube, the third PMOS tube and the fourth NMOS tube form the transmission gate circuit, and the output terminal of the transmission gate circuit serves as the output terminal of the peak detector, and is connected to the drain of the twelfth NMOS tube and grounded through the first capacitor, The source of the twelfth NMOS tube is grounded; the seventh NMOS tube and the eighth NMOS tube form a first current mirror circuit, and the source of the eleventh PMOS tube is connected to the gates of the seventh NMOS tube and the eighth NMOS tube, and is connected to the gates of the ninth NMOS tube and the tenth NMOS tube; the source of the ninth NMOS tube and the source of the tenth NMOS tube are grounded, the drain of the ninth NMOS tube is connected to the source of the fifth NMOS tube as the high threshold voltage output end of the peak detector and is grounded through the second capacitor; the drain of the tenth NMOS tube is connected to the source of the sixth NMOS tube as the low threshold voltage output end of the peak detector and is grounded through the third capacitor; the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are connected to the power supply voltage, the gate of the fifth NMOS tube is connected to the high threshold voltage control end of the high and low threshold voltage detection module, and the gate of the sixth NMOS tube is connected to the low threshold voltage control end of the high and low threshold voltage detection module.

4. The high-speed and high-precision peak detector in a zero intermediate frequency receiver according to claim 3, characterized in that: The high and low threshold voltage detection module includes a second current mirror circuit, a resistor array, a source follower and an operational amplifier. The second current mirror circuit provides an input level for the resistor array and the operational amplifier. The operational amplifier compares the input level with a reference level to generate a control level input to the control end of the source follower. The output end of the source follower provides a switching voltage for the switching devices in the resistor array to encode the resistor array and generate a high threshold voltage control signal and a low threshold voltage control signal.

5. The high-speed and high-precision peak detector in a zero intermediate frequency receiver according to claim 4, characterized in that: The resistor array includes 63 resistors connected in series in sequence, and each end of each resistor is connected to two switch units connected in parallel with each other and respectively connected to the high threshold voltage control end and the low threshold voltage control end. By controlling each switch unit to select the connected resistance value, encoding is completed to generate a corresponding control signal.

6. The high-speed and high-precision peak detector in a zero intermediate frequency receiver according to claim 3, characterized in that: The high-speed comparator includes a PMOS input stage and an NMOS input stage, wherein the PMOS input stage has the same circuit structure as the NMOS input stage, and the device using the PMOS tube in the PMOS stage uses the NMOS tube in the NMOS stage, and the NMOS input stage includes a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first NMOS tube, a twenty-second NMOS tube, a thirty-sixth NMOS tube, a thirty-seventh NMOS tube, a first enabling PMOS tube, a second enabling PMOS tube, and a third enabling The gate of the thirteenth NMOS tube is connected to the output end of the peak detector, and the gate of the fourteenth NMOS tube is connected to the high threshold voltage output end or the low threshold voltage output end; the source of the thirteenth NMOS tube is connected to the source of the fourteenth NMOS tube and connected to the drain of the thirty-seventh NMOS tube, and the drain of the thirteenth NMOS tube is respectively connected to the source of the fifteenth PMOS tube, the source of the seventeenth PMOS tube and the gate of the twentieth PMOS tube; the drain of the fourteenth NMOS tube is respectively connected to the source of the sixteenth PMOS tube, the source of the eighteenth PMOS tube and the gate of the The gate of the nineteenth PMOS tube is connected to the gate of the seventeenth PMOS tube; the gate of the seventeenth PMOS tube is connected to the source, the gate of the eighteenth PMOS tube is connected to the source, the gate of the fifteenth PMOS tube is connected to the source of the sixteenth PMOS tube, and the source of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube; the drains of the fifteenth PMOS tube, the sixteenth PMOS tube, the seventeenth PMOS tube, the eighteenth PMOS tube, the nineteenth PMOS tube and the twentieth PMOS tube are connected to the power supply voltage; the gate of the nineteenth PMOS tube is also connected to the source of the first enabling PMOS tube, the drain of the first enabling PMOS tube is connected to the drain of the second enabling PMOS tube The gate of the 20th PMOS tube is also connected to the source of the second enabling PMOS tube, and the gate of the first enabling PMOS tube is connected to the gate of the second enabling PMOS tube; the source of the 19th PMOS tube is connected to the drain of the 21st NMOS tube, and the source of the 20th PMOS tube is connected to the drain of the 22nd NMOS tube as the output end of the high-speed comparator; the gate and drain of the 21st NMOS tube are connected and connected to the gate of the 22nd NMOS tube; the source of the 21st NMOS tube and the source of the 22nd NMOS tube are grounded respectively, and the drain of the third enabling NMOS tube is connected to the gate of the 22nd NMOS tube;The gate and drain of the thirty-sixth NMOS tube are connected and connected to the gate of the thirtieth NMOS tube, the source of the thirty-sixth NMOS tube and the source of the thirty-seventh NMOS tube are grounded respectively, the drain of the fourth enabling NMOS tube is connected to the gate of the thirty-seventh NMOS tube; the drain of the thirty-sixth NMOS tube is connected to the drain of the corresponding transistor of the PMOS input stage; the source of the third enabling NMOS tube and the source of the fourth enabling NMOS tube are grounded; the gate of the third enabling NMOS tube and the gate of the fourth enabling NMOS tube are connected to the output end of the inverter; the input end of the inverter of the NMOS input stage is connected to the output end of the inverter of the PMOS input stage; the input end of the inverter of the PMOS input stage is connected to the enable signal; the output end of the high-speed comparator is also connected to the drain of the fifth enabling NMOS tube, the gate of the fifth enabling NMOS tube is connected to the output end of the inverter of the NMOS input stage, and the source is grounded. ; 7. A zero intermediate frequency receiver, characterized in that: The method comprises a peak detector as claimed in any one of claims 1 to 6 and a low noise amplifier, a mixer, a transimpedance amplifier, an active filter and an analog-to-digital converter which are cascaded in sequence, wherein the peak detector is integrated at the output end of the transimpedance amplifier.

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