High-reliability semi-backscatter communication method and system

By introducing LDPC encoding and CSS cascade technology into the LoRa backscatter communication system and integrating a single-frequency oscillator, the shortcomings of existing systems in communication reliability are solved, and higher signal diversity gain and anti-interference ability are achieved, which significantly improves the reliability and coverage of the system.

CN120050003APending Publication Date: 2025-05-27CHINA UNIV OF GEOSCIENCES (WUHAN)
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Patent Information

Application Number
CN202510267481.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-03-07
Publication Date
2025-05-27

AI Technical Summary

Technical Problem

The existing LoRa backscatter communication systems have poor reliability in communication, especially in long-distance communication and multipath environments.

Method used

By introducing LDPC encoding and CSS cascade technology into the LoRa physical layer, efficient error correction codewords are constructed and modulated in combination with bit interleaving technology to form a data frame. In addition, a single frequency oscillator is integrated at the transmitter of the scattering node to improve the stability of the carrier signal.

Benefits of technology

It significantly improves the diversity gain and anti-burst error capability of the signal, enhances the anti-interference ability and reliability of the system, and improves the reliability and coverage of communication.

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Abstract

The invention provides a high-reliability semi-backscatter communication method and system, and relates to the technical field of communication, and the method comprises the steps: carrying out the coding, modulation and data packaging of original data through a scattering node transmitting end, and obtaining a data frame; and receiving a data frame through a software-defined radio receiving end, and sequentially carrying out frame synchronization, demodulation and decoding on the data frame to obtain decoded data. The LoRa physical layer coding and decoding design is improved, LDPC coding is carried out on original data through a coding module, a quasi-cyclic LDPC code replaces a Hamming code to serve as an error correction code of the LoRa physical layer, a low-complexity check matrix is constructed by constructing a shift basis matrix, a coding codeword is constructed through the check matrix, and the coding efficiency of the LoRa physical layer is improved. And finally, cascading CSS modulation and coding codons by using a bit interleaving technology to construct a data frame so as to increase diversity gain of a signal, and meanwhile, due to the quasi-cyclic characteristic of coding, the LDPC code can obtain extremely strong burst error detection capability during short code input.
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Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a highly reliable semi-backscatter communication method and system. Background Art

[0002] With the rapid development of wireless communication technologies, the number of Internet of Things (IoT) devices has increased sharply. According to statistics, the number of IoT connections will increase sharply to 500 billion in 2030. When deploying the IoT on a large scale, the energy problem of nodes has gradually become a bottleneck restricting the development of the network. Although replacing the battery or charging the battery can extend the operation cycle of the node, it will greatly increase the cost, and sometimes it is not easy to implement (such as in remote areas, high-voltage, high-temperature harsh environment and other scenarios). For this reason, Backscatter Communication (BC) technology has emerged. Backscatter communication is a newly emerging ultra-low-power green communication technology in recent years. This technology has an extremely simple structure and extremely low cost. It does not need to use high-power source devices to generate radio frequency carrier signals and perform analog-to-digital conversion, but instead performs passive information transmission by simply modulating and reflecting the radio frequency signals sent by external radio frequency sources. Therefore, backscatter communication consumes 2 to 3 orders of magnitude less power than traditional active radio, and can not only achieve passive information transmission with ultra-low power consumption in the micro-watt level, but also easily meet energy self-sustainability and instant data communication. Therefore, it is regarded as an effective technical solution for passive IoT deployment.

[0003] Although BC networks have many advantages, they still face major challenges in practical applications. Affected by the two-way path loss, the signal-to-noise ratio of BC signals is extremely low and fluctuates violently, and the communication distance is limited. Usually, only a few meters to dozens of meters of transmission can be achieved at the micro-watt level of power consumption. At the same time, the dependence of BC systems on external radio frequency signals limits the coverage of their forward links. Large-scale network deployment often requires a large number of power stations to achieve wide coverage, but this method significantly increases the deployment cost. In addition, due to the limited storage resources and computing capabilities of BC nodes, they cannot support complex channel coding and decoding algorithms, and lack high-power power amplification devices, so their communication reliability is poor under harsh channel conditions.

[0004] In response to the above problems, scholars at home and abroad have proposed many effective methods. In 2017, the University of Washington in the United States proposed a LoRa backscatter communication scheme, which uses chirp spread spectrum modulation technology to improve the anti-noise ability and realizes backscatter communication of hundreds of meters. However, this method requires high-power-consuming digital-to-analog converters (DACs) and voltage-controlled oscillators (VCOs) to generate baseband square waves, and the system is complex and costly. In 2019, the team of Tang Xiaoqing developed a fully digital LoRa backscatter communication system based on direct digital frequency synthesis technology, which greatly reduces the system complexity. However, the reliability of this system is poor, especially in long-distance communication and multipath environments. In 2021, Niloofar et al. proposed a LoRa backscatter communication system based on ReDCoS technology, which improves the recovery ability of damaged frames by precoding data at the application layer. However, the data transmission reliability of this method is limited by Hamming coding in the physical layer to a certain extent. In addition, existing LoRa backscatter communications all adopt a bistatic architecture, and the communication link will suffer from two-way path fading, resulting in extremely poor signal-to-noise ratio of the BC signal when it reaches the receiving device with a long distance, and thus the reliability of communication is poor. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a highly reliable semi-backscatter communication method and system, which are used to solve the technical problem that the existing LoRa backscatter communication system has poor reliability during communication.

[0006] The present invention provides a highly reliable semi-backscatter communication method, including the steps of:

[0007] S1: Sequentially encode, modulate, and encapsulate the original data through the transmitting end of the scattering node to obtain a data frame;

[0008] S2: Receive the data frame through the receiving end of the software-defined radio, and sequentially perform frame synchronization, demodulation, and decoding on the data frame to obtain decoded data.

[0009] Preferably, step S1 is specifically:

[0010] S11: Obtain the original data K, and input the original data K into the MCU;

[0011] S12: Perform LDPC coding on the original data K through the coding module to obtain a coded codeword;

[0012] S13: Perform diagonal matrix interleaving and Gray coding on the coded codeword through the coding module, and then perform CSS modulation through the modulation module to obtain valid data;

[0013] S14: Construct a preamble, and splice and encapsulate the preamble and the valid data through the encapsulation module to obtain a data frame.

[0014] Preferably, step S12 is specifically as follows:

[0015] S121: Input the original data K into the encoding module, and generate a base matrix through the PEG algorithm;

[0016] S122: Replace all elements "0" in the base matrix with all-zero matrices, and replace elements "1" at different positions with cyclic shift matrices of different powers to obtain a parity-check matrix H;

[0017] S123: Calculate and obtain a generator matrix G through the parity-check matrix H, and the calculation formula is: G * H T = 0;

[0018] S124: Multiply the original data K by the generator matrix G to obtain an encoded codeword C, and the calculation formula is: C = K * G.

[0019] Preferably:

[0020] The data frame includes a preamble, an implicit frame header, valid data, and a data check code that are connected in sequence;

[0021] The preamble includes: 8 Up Chirp signals with a symbol value of "0" as a variable preamble, 2 Up Chirp signals with a symbol value of "24" as a synchronization code, and 2.25 Down Chirp signals with a symbol value of "0" as a frame start delimiter.

[0022] Preferably, step S2 is specifically as follows:

[0023] S21: The data frame passes through the radio frequency receiving unit, the frequency band conversion unit, the analog-to-digital conversion unit, the data sampling unit, and the frame synchronization module and the CSS demodulation module in the PC unit in sequence, and a symbol vector C' = [c 1 , c 2 ,..., c L is obtained, and the symbol vector is input into the decoding module;

[0024] S22: Obtain the parity-check matrix H, initialize the iteration number l to 1, and the maximum value of l is L;

[0025] S23: Perform the l-th iteration, and obtain the l-th bit node information c l of the symbol vector, and the l-th check node information y l of the parity-check matrix H;

[0026] S24: If y l > 0, then c l = 1; if y l < 0, then c l = 0;

[0027] S25: Let \(l = l + 1\);

[0028] S26: Repeat steps S23 - S25 until \(C'\) T \(H = 0\) or \(l = L\), and use the finally obtained symbol vector as the decoded data.

[0029] A highly reliable semi - backscatter communication system for implementing the highly reliable semi - backscatter communication method described above, comprising:

[0030] A scatter node transmitter and a software - defined radio receiver;

[0031] The scatter node transmitter is communicatively connected to the software - defined radio receiver.

[0032] Preferably:

[0033] The scatter node transmitter includes: a single - frequency oscillator, a radio - frequency switch, and an MCU;

[0034] The single - frequency oscillator and the MCU are connected to the radio - frequency switch;

[0035] The MCU includes: an encoding module, a modulation module, and a packaging module.

[0036] Preferably:

[0037] The software - defined radio receiver includes a radio - frequency receiving unit, a frequency - band conversion unit, an analog - to - digital conversion unit, a data sampling unit, and a PC unit connected in sequence;

[0038] Install a software platform in the PC unit, and the software platform includes: a frame synchronization module, a CSS demodulation module, and a decoding module.

[0039] The present invention has the following beneficial effects:

[0040] 1. Improve the LoRa physical - layer encoding and decoding design. The original data is LDPC - encoded by the encoding module. A quasi - cyclic LDPC code is used to replace the Hamming code as the error - correcting code of the LoRa physical layer. A low - complexity parity - check matrix is constructed by building a shift - based matrix, and the encoded codeword is constructed through the parity - check matrix. Finally, the CSS modulation and the encoded codeword are concatenated using bit - interleaving technology to construct a data frame, so as to increase the diversity gain of the signal. At the same time, the quasi - cyclic property of the encoding enables the LDPC code to also have a strong burst - error detection ability when the input is a short code;

[0041] 2. Integrate the single - frequency oscillator into the scatter node transmitter. At the cost of sacrificing a small amount of power consumption, it effectively solves the problem of limited forward link, completely eliminates the problem of radio - frequency signal self - interference, has a simple structure, is easy to implement, and has high reliability. Description of the Drawings

[0042] Figure 1It is the flowchart of the method in the embodiment of the present invention;

[0043] Figure 2 It is the flowchart for obtaining the encoded codeword;

[0044] Figure 3 It is the flowchart for obtaining the data frame;

[0045] Figure 4 It is the time-frequency diagram of the Chirp signal with the payload data symbol length of 8;

[0046] Figure 5 It is the flowchart of the timing output;

[0047] Figure 6 It is the structure diagram of the data frame;

[0048] Figure 7 It is the flowchart for obtaining the decoded data;

[0049] Figure 8 It is the structure diagram of the high-reliability semi-backscatter communication system;

[0050] Figure 9 It is the specific circuit diagram of the single-frequency oscillator;

[0051] Figure 10 It is the specific circuit diagram of the RF switch;

[0052] Figure 11 It is the system power consumption test platform;

[0053] Figure 12 It is the system stage power consumption diagram;

[0054] Figure 13 It is the PDR performance test platform;

[0055] Figure 14 It is the PDR performance comparison diagram;

[0056] The realization, functional features and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. Specific embodiments

[0057] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0058] Referring to Figure 1 , the present invention provides a high-reliability semi-backscatter communication method, including the steps:

[0059] S1: The original data is successively encoded, modulated and data encapsulated by the transmitting end of the scattering node to obtain a data frame;

[0060] As an embodiment, this patent constructs an improved LoRa physical layer based on LDPC coding and CSS concatenation technology. A quasi-cyclic low-density parity-check (QC-LDPC) code with excellent performance is selected to replace the Hamming code in the LoRa physical layer structure. Combining bit interleaving technology, QC-LDPC and CSS modulation are cascaded to output a data frame. First, an efficient error-correcting codeword is generated through LDPC coding. Subsequently, the encoded data is interleaved to improve the ability to resist burst errors, and Gray coding is further used to reduce the bit error rate. Finally, CSS modulation is used to map the signal into a chaotic sequence to enhance the anti-interference ability of the system.

[0061] Step S1 is specifically as follows:

[0062] S11: Obtain the original data K and input the original data K into the MCU.

[0063] S12: Perform LDPC coding on the original data K through an encoding module to obtain an encoded codeword.

[0064] Specifically, the channel coding adopted by the traditional LoRa physical layer is the Hamming code, which has four coding rates, and only the coding rates of 4 / 7 and 4 / 8 can correct one bit error, with limited error-correcting ability, resulting in poor communication quality. This patent adopts a quasi-cyclic LDPC (Quasi Cycle LDPC, QC-LDPC) channel coding method. This method constructs a parity-check matrix through a shift matrix and uses logarithmic likelihood ratio information iterative decoding, which can effectively improve communication quality and reduce the bit error rate.

[0065] As Figure 2 shown, in the encoding stage, first generate a base matrix with a short girth through the PEG algorithm, and then use the shift parameter formula to construct a cyclic shift matrix to expand the base matrix into a parity-check matrix H. The "0" in the parity-check matrix is replaced by an all-zero matrix, and the "1" with different positions is replaced by cyclic shift matrices with different powers, thereby optimizing the matrix structure and taking into account both high error-correcting performance and simplification of hardware implementation. After generating the parity-check matrix H, generate the generator matrix G through derivation. Finally, multiply the original information k by the generator matrix G to obtain the encoded codeword c to be transmitted.

[0066] Step S12 is specifically as follows:

[0067] S121: Input the original data K into the encoding module and generate a base matrix through the PEG algorithm.

[0068] S122: Replace all the elements "0" in the base matrix with an all-zero matrix, and replace the elements "1" with different positions with cyclic shift matrices with different powers to obtain the parity-check matrix H.

[0069] S123: Obtain the generating matrix G by calculating through the parity-check matrix H. The calculation formula is: G * H T = 0;

[0070] S124: Multiply the original data K by the generating matrix G to obtain the encoded codeword C. The calculation formula is: C = K * G.

[0071] S13: Perform diagonal matrix interleaving and Gray coding on the encoded codeword through the encoding module, and then perform CSS modulation through the modulation module to obtain the valid data;

[0072] Specifically, the process of generating the CSS modulation square wave using the DDS technology is as follows:

[0073] Assume that the upper frequency limit of the scattered modulation waveform to be generated is f H = f 0 + BW, and the lower frequency limit is f L = f 0 , the symbol frequency is f c = 1 / T c , and 2 SF = T c ·BW, the symbol value N, and the main clock frequency of the MCU is f M , the phase accumulator and the frequency control word are both 32 bits. Therefore, the number of waveform points P generated in each symbol period can be obtained as P = f M / f c . f L . f H , BW respectively correspond to the frequency control words f C_L = 2 32 ·f L / f M . f C_H = 2 32 ·f H / f M . f C_BW = 2 32 ·BW / f M , and the frequency control word updated in each clock cycle is:

[0074]

[0075] The increment of the frequency control word in each clock cycle is:

[0076]

[0077] And the value of the phase accumulator updated in each clock cycle is:

[0078]

[0079] where 0 ≤ m < p, and only the MSB of needs to be output in each clock cycle to obtain a CSS modulated square wave whose frequency changes with time. The Down Chirp signal can be generated by inverting the output bit by bit. The MSBs of the output are stored in a byte in groups of 8 to form a Chirp square wave code table. The number of bytes occupied by each symbol is:

[0080]

[0081] S14: Construct a preamble, and splice and encapsulate the preamble and valid data through an encapsulation module to obtain a data frame.

[0082] Specifically, as Figure 3 shown, the direct digital frequency synthesis (DDS) technology is used to generate the preamble. The phase of the sampling points in each clock cycle is calculated through the frequency control word and stored in the memory for use in the next symbol. The data needs to be encoded, interleaved, and then symbol - modulated. To save memory and power consumption, the pre - prepared code tables are spliced together. The symbol modulation is performed in a sliding window manner. Finally, the preamble symbols and data information symbols are spliced together to form a Chirp signal, which is transmitted to the radio frequency chip for transmission through SPI + DMA, specifically as follows:

[0083] Data splicing:

[0084] According to the designed physical layer frame structure, the DDS technology can be used to generate the Chirp signal in two parts. One part is the preamble without encoding: 8 Up Chirp symbols with a value of "0", 2 Up Chirp symbols with a value of "24", and 2.25 Down Chirp symbols with a value of "0". The other part is the encoded payload data. The length of the symbols in the payload data part is jointly determined by the codeword length and SF. Figure 4 shows the time - frequency diagram of the Chirp signal with a payload data symbol length of 8.

[0085] The preamble part of the Chirp signal serves as its identification and synchronization symbol. Under the condition that the configuration parameters remain unchanged (such as SF, CR, etc.), the square wave signal data generated each time is the same. Therefore, the MCU can calculate this part of the symbols only once during the initial process and store them in the memory. During the generation of the next Chirp signal, only read this memory in the standby mode of the MCU. Since the preamble part of the symbols has been stored in the memory, only the payload data part needs to be updated each time, and the head of the payload data symbol is connected to the tail of the preamble symbol. At this time, a marker M pream bl e_en d is used to record the tail of the preamble symbol.

[0086] As can be seen from Equation 4, when the value of f M / BW is 8, the symbols of adjacent code values differ by exactly one byte, thus avoiding frequent shift extraction of the code table. Since the main frequency of the external clock is 1 MHz, BW is adopted as 125 kHz. The Chirp code table can be extracted from the memory in a sliding window manner, and only the memory of two Chirp symbols is required to complete the modulation of the payload data. This method concatenates the heads and tails of two Up Chirps with the symbol "0" together, the length of the sliding window is the length of the entire Chirp symbol, and the symbol value is the starting position of the sliding window. Modulating Chirp signals with different symbol values only requires adjusting the starting position of the sliding window.

[0087] Timing output:

[0088] After the Chirp modulation signal data is generated, the signal data needs to be transmitted to the radio frequency chip. This patent uses the method of "DMA + SPI", as Figure 5 shown. Since the signal has strict timing requirements, an external high-precision clock is used to transmit the data from the MCU memory to the radio frequency chip through SPI, and cooperate with the Direct Memory Access (DMA) controller to complete the automatic transfer of the signal data from the memory to the radio frequency chip, and does not require the participation of the MCU, saving the operation main frequency of the MCU, and at the same time reducing the energy consumption of the system during the output of the scattered baseband signal.

[0089] As an embodiment, as Figure 6 shown;

[0090] The data frame includes a preamble, an implicit frame header, valid data, and a data check code connected in sequence;

[0091] The preamble includes: 8 Up Chirp signals with a symbol value of "0" as a variable preamble, 2 Up Chirp signals with a symbol value of "24" as a synchronization code, and 2.25 Down Chirp signals with a symbol value of "0" as a frame start delimiter.

[0092] S2: Receive the data frame through the software-defined radio receiver, and perform frame synchronization, demodulation, and decoding on the data frame in sequence to obtain the decoded data.

[0093] As an embodiment, as Figure 7As shown in the figure, in the decoding stage, a soft-decision logarithmic domain belief propagation algorithm is used for iterative decoding. The receiving end uses the hyperbolic tangent function relationship between the check nodes and the bit nodes according to the check matrix H and the received symbol vector y, and gradually updates the log-likelihood ratio (LLR) information until the check condition is met or the maximum number of iterations is reached, so as to recover the original codeword and output the decoded data;

[0094] Step S2 is specifically as follows:

[0095] S21: The data frame passes through the radio frequency receiving unit, the frequency band conversion unit, the digital-to-analog conversion unit, the data sampling unit, and the frame synchronization module and the CSS demodulation module in the PC unit in sequence to obtain the symbol vector C’ = [c 1 , c 2 ,..., c L , and the symbol vector is input into the decoding module;

[0096] S22: Obtain the check matrix H, initialize the number of iterations l to 1, and the maximum value of l is L;

[0097] S23: Perform the l-th iteration to obtain the l-th bit node information c l of the symbol vector, and the l-th check node information y l of the check matrix H;

[0098] S24: If y l > 0, then c l = 1; if y l < 0, then c l = 0;

[0099] S25: Let l = l + 1;

[0100] S26: Repeat steps S23 - S25 until C’ T H = 0 or l = L, and use the finally obtained symbol vector as the decoded data.

[0101] The present invention provides a highly reliable semi-backscatter communication system for implementing the highly reliable semi-backscatter communication method, including:

[0102] A scatter node transmitter and a software-defined radio receiver;

[0103] The scatter node transmitter is communicatively connected to the software-defined radio receiver.

[0104] Specifically, a highly reliable semi-backscatter communication system (BC system) with excellent performance is designed for the improved LoRa physical layer based on LDPC coding and CSS concatenation technology, such as Figure 8As shown in the figure, a low-power MCU is used as the baseband processor, and the generation of baseband digital signals is all realized in the digital domain, eliminating the additional power consumption of the DAC and VCO. At the same time, to solve the problem of two-way path fading in the communication link of the traditional BC system, this patent integrates a micro low-power single-frequency oscillator on the scattering node to establish a semi-backscatter communication system to improve the stability of the carrier signal and enhance the system reliability.

[0105] As an embodiment:

[0106] The transmitting end of the scattering node includes: a single-frequency oscillator, a radio frequency switch, and an MCU;

[0107] The single-frequency oscillator and the MCU are connected to the radio frequency switch;

[0108] The MCU includes: an encoding module, a modulation module, and a packaging module.

[0109] Specifically, the digital processor MCU is responsible for generating the improved LoRa physical layer baseband square wave. The data first passes through the encoding module, including LDPC encoding, diagonal matrix interleaving, and Gray encoding, and then is subjected to CSS modulation by the modulation module, and then data packaging is performed to package the modulated data into a specific data frame. The single-frequency oscillator is responsible for generating the carrier signal. The radio frequency switch is responsible for modulating the baseband square wave onto the carrier signal and transmitting it to the antenna for emission.

[0110] The MSP430FR5959 chip with low power consumption and high stability is selected as the MCU to ensure the long-term stable operation of the BC node. The single-frequency oscillator part uses the RO3101E quartz crystal oscillator with a frequency of 433.920 MHz, which has high stability. The specific circuit of the single-frequency oscillator is as Figure 9 shown. The oscillator is connected to the radio frequency chip through the peripheral circuit to provide a stable carrier signal for it. The radio frequency part uses the ADG936 radio frequency switch to transmit the sine wave signal and the Chirp square wave signal of the base station to achieve effective data emission. The specific circuit of the radio frequency switch is as Figure 10 shown.

[0111] As an embodiment:

[0112] The software-defined radio receiving end includes a radio frequency receiving unit, a frequency band conversion unit, an analog-to-digital conversion unit, a data sampling unit, and a PC unit connected in sequence;

[0113] A software platform is installed in the PC unit, and the software platform is designed to include: a frame synchronization module, a CSS demodulation module, and a decoding module.

[0114] Specifically, the radio frequency signal first passes through the radio frequency front end and is converted into an intermediate frequency signal. After the intermediate frequency signal is sampled through analog-to-digital conversion, the analog signal is converted into a digital signal, and then it is handed over to the GR platform for further processing. The GR platform is responsible for processing the digital signal. The data first passes through the frame synchronization module, and it is judged whether the signal is a data frame in a specific format. After the data synchronization is completed, it is demodulated by the CSS demodulation module, and then passes through the decoding module for Gray decoding, deinterleaving, LDPC iterative decoding to recover the data, and data verification is performed, and finally the communication is completed.

[0115] Build a software platform through GNU Radio. GNU Radio provides a large number of digital signal processing tools, which can be used to assist in the development of USRP devices. In the GR software, each module is an independent unit, and each module is connected by a connection line. The data in the module is transmitted between the modules in the form of a stream.

[0116] The CSS demodulation module includes an FFT demodulation module, and the decoding module includes a Gray decoding module, a deinterleaving module, an LDPC iterative decoding module, a CRC check and character output module. Therefore, the program mainly includes 7 modules, namely the USRP source module, the frame synchronization module, the FFT demodulation module, the Gray decoding module, the deinterleaving module, the LDPC iterative decoding module, and the CRC check and character output module.

[0117] The USRP source module is an internal module of the software. When used, its parameters can be configured to transmit the radio signal received by the USRP device to the frame synchronization module. The frame synchronization module receives the digital signal that has been processed by the USRP source module, samples it with an oversampling factor os_factor = 2, first checks whether the length of the preamble meets the set value. If it meets, the program flow continues to run, otherwise it stops here. Then it continues to judge the sync code value, search for the frame start symbol, and hand over the payload data information to the FFT module for demodulation; the FFT module uses soft decision demodulation to output LLR information for the Chirp signal. After the LLR information passes through Gray mapping and deinterleaving, it is handed over to the LDPC decoding module; the LDPC decoding module iteratively decodes with parameters CR = 2 and Nloop = 8 until the requirements are met, and then performs CRC verification and outputs the Payload information.

[0118] Test results:

[0119] (1) System power consumption test:

[0120] To test the system power consumption, a setup was built as Figure 11The test platform shown. The test method is as follows: A resistor R is connected in series between the power supply and the scattering node, and the oscilloscope collects the voltage across the resistor R, and then the current flowing through the scattering node can be calculated. Test tools: The button power supply voltage is 2.9V, and the resistor R is 100Ω. The parameter settings of the scattering node are: BW = 125kHz, SF = 7, CR = 4 / 8.

[0121] The scattering node is in the standby state by default, and its power consumption is mainly divided into two parts: standby power consumption and scattering communication power consumption. The system stage power consumption is as Figure 12 shown.

[0122] The power consumption during the system scattering period is carefully divided into four stages: startup, encoding, modulation, and transmission stages. The current at the moment of system startup is 752μA. After the system stabilizes for about 10ms, it enters the physical layer encoding and modulation stages. During the encoding stage, there is a continuous current of 952μA for a duration of 9ms. The continuous current during the modulation stage is 1.032mA for a duration of 9ms. Most of the system's working time is in the "SPI+DMA" process, during which the continuous current is 512μA for about 47ms. The system is in the standby state for the rest of the time, and the standby power consumption is about 0.4μA. During the entire cycle of the system, it only takes 75ms to complete the transmission of the Chirp signal. During this period, the power supply voltage of the system is referenced to 2.9V. The power consumptions of the four stages of system startup, encoding, modulation, and transmission are 2.181, 2.761, 2.993, and 1.485mW respectively. The rest of the time is in the ultra-low power standby state of 1.16μW. Therefore, the average power consumption of the system in one cycle is about 0.154mW.

[0123] The energy consumed by the system in one second cycle is 49.81mA·ms. For the convenience of calculation, the energy consumption is estimated to be 50mA·ms. Taking the button battery CR1220 as an example, the nominal capacity is 40mAh. The system can work continuously for 33 days. In actual applications, assuming that a data packet is sent every 5 minutes, the energy consumed in each cycle is 169.41mA·ms. If the self-discharge of the battery is not considered, only one button battery can run continuously for 8.09 years, which is sufficient to meet the needs of most Internet of Things applications.

[0124] (2) PDR performance comparison:

[0125] To test the packet arrival rate of this BC system, the following was set up as Figure 13The experimental platform shown includes backscatter nodes, a USRP B210 receiver, RF connecting cables, a 30 dB fixed attenuator, a 0-90 dB adjustable attenuator, and a laptop installed with GNURadio. The BC nodes generate BC signals. The BC signals pass through the 30 dB attenuator and the adjustable attenuator and are received by the USRP. After the USRP converts the frequency band and performs analog-to-digital conversion on the attenuated BC signals, they are transmitted to the computer for demodulation, decoding, and other operations.

[0126] Figure 14 It is a comparison of the PDR performance between the LoRa backscatter communication system using LDPC codes and the LoRa backscatter communication system using Hamming codes. The test conditions are that the LDPC-LoRa code rate CR = 1 / 5 and the Hamming-LoRa code rate CR = 4 / 8, and the Payloads sent by the two are different. One packet of data is sent per second, and the number of data packets with completely correct bits is recorded when 1000 packets of data are received. As the SNR increases, the PDR gradually rises from 0 to 1. However, for the LDPC code with SF = 8, it does not start from PDR = 0 because the data packets can still be received by the USRP and successfully demodulated after passing through a 120 dB (maximum) attenuator.

[0127] Taking PDR = 0.4 as the target, when SF = 7, the SNR of LDPC-LoRa is approximately -10.5 dB, and the SNR of Hamming-LoRa is approximately -9.75 dB. The performance of LDPC-LoRa is improved by approximately 0.75 dB compared to Hamming-LoRa, and it is also improved by approximately 0.75 dB in the case of SF = 8. For the BC system based on the LDPC-LoRa physical layer, when SF = 8, the PDR performance is improved by approximately 2 dB compared to when SF = 7. The improvement in PDR performance under different spreading factors in the field test is almost the same as the improvement in BER performance under theoretical analysis, which can verify the correctness of the semi-backscatter system designed in this patent. The experimental results show that the BC system designed in this patent has a PDR as high as 80% when the signal-to-noise ratio is as low as -12 dB, while the PDR of the BC system based on the traditional Hamming-LoRa physical layer under the same conditions is only 5%. Because the LDPC-LoRa physical layer of this patent adopts a high-performance and low-complexity QC-LDPC coding method, and uses the maximum likelihood estimation soft demodulation method and combines with the iterative decoding algorithm, the reliability of the BC system is greatly improved.

[0128] (3) Communication distance test and comparison:

[0129] To test the communication distance of the system, in an open scenario, the scattering nodes and the receiver are placed on a straight line during the test experiment, and the distance between the scattering nodes and the receiver is continuously increased, and the farthest communication distance under different SFs is recorded. The test results are shown in Table 2.

[0130] Table 1 Communication Distance Test

[0131]

[0132] Table 1 tested the system communication distance at the corresponding communication rates with a system bandwidth of 125 kHz and SF ranging from 7 to 12. As SF increases, the receiving sensitivity of the system will increase accordingly, and the communication distance will also increase accordingly. When SF = 12, the maximum communication distance reaches 189 m, which can meet the coverage requirements in scenarios such as smart factories and intelligent buildings.

[0133] Table 2 gives a comparison of the performance of this system with other LoRa backscatter communication systems. As shown in Table 2, compared with other LoRa backscatter communication systems, this system uses a low-power MCU as the processor. Its system architecture has obvious advantages in terms of hardware, power consumption, and cost compared with the architecture based on FPGA processors used in the existing method [1]. Compared with the communication method based on Hamming-LoRa used in the existing method [2], although the power consumption of this system is relatively high, due to the improvement of the LoRa physical layer coding, the communication reliability has been significantly improved. For details, see Figure 14 In addition, compared with this system, this system can complete instant and reliable communication without relying on a dedicated radio frequency power station, and has the advantages of convenient deployment and low cost.

[0134] Table 2 Comparison of Test Results with Other LoRa Backscatter Communication Systems

[0135]

[0136]

[0137] It should be noted that in this article, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or system. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or system including that element.

[0138] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments. In the several apparatus unit claims listing several apparatuses, several of these apparatuses may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not denote any order and these words may be interpreted as identifiers.

[0139] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be similarly included in the patent protection scope of the present invention.

Claims

1. A highly reliable semi-backscatter communication method, characterized in that: Includes steps: S1: The original data is encoded, modulated and encapsulated in sequence by the scattering node transmitter to obtain a data frame; S2: Receive data frames through the software defined radio receiving end, and perform frame synchronization, demodulation and decoding on the data frames in sequence to obtain decoded data.

2. The high-reliability semi-backscatter communication method based on LDPC code according to claim 1, characterized in that: Step S1 is specifically as follows: S11: Obtain original data K and input the original data K into MCU; S12: Perform LDPC encoding on the original data K through the encoding module to obtain an encoding codeword; S13: performing diagonal matrix interleaving and Gray coding on the coded codewords through the coding module, and then performing CSS modulation through the modulation module to obtain valid data; S14: construct a preamble code, and concatenate and encapsulate the preamble code and valid data through an encapsulation module to obtain a data frame.

3. The high-reliability semi-backscatter communication method based on LDPC code according to claim 2, characterized in that: Step S12 is specifically as follows: S121: input the original data K into the encoding module, and generate a basis matrix through the PEG algorithm; S122: Replace all elements "0" in the base matrix with an all-zero matrix, and replace elements "1" in different positions with cyclic shift matrices of different powers, to obtain a check matrix H; S123: Obtain the generator matrix G by calculating the check matrix H. The calculation formula is: G*H T =0; S124: Multiply the original data K by the generation matrix G to obtain the encoding codeword C, and the calculation formula is: C=K*G.

4. The high-reliability semi-backscatter communication method based on LDPC code according to claim 2, characterized in that: The data frame includes a preamble, an implicit frame header, valid data and a data validation code connected in sequence; The preamble includes: 8 Up Chirp signals with a symbol value of "0" as a variable preamble, 2 Up Chirp signals with a symbol value of "24" as a synchronization code, and 2.25 Down Chirp signals with a symbol value of "0" as a frame start delimiter.

5. The high-reliability semi-backscatter communication method based on LDPC code according to claim 1, characterized in that: Step S2 is specifically as follows: S21: The data frame is processed by the RF receiving unit, the frequency band conversion unit, the digital-to-analog conversion unit, the data sampling unit, and the frame synchronization module and the CSS demodulation module in the PC unit in sequence to obtain a symbol vector C'=[c1,c2,...,c L ], input the symbol vector into the decoding module; S22: Obtain the check matrix H, initialize the number of iterations l to 1, and the maximum value of l is L; S23: Perform the lth iteration to obtain the lth bit node information c of the symbol vector l , and the lth check node information y of the check matrix H l ; S24: If y l >0 then c l =1, if y l <0 then c l =0; S25: let l=l+1; S26: Repeat steps S23-S25 until C' T H=0 or l=L, and the finally obtained symbol vector is used as the decoded data.

6. A high-reliability semi-backscatter communication system, used to implement the high-reliability semi-backscatter communication method according to any one of claims 1 to 5, characterized in that: include: Scattering node transmitter and software defined radio receiver; The scatter node transmitter is communicatively connected with the software defined radio receiver.

7. The highly reliable semi-backscatter communication system according to claim 6, characterized in that: The transmitting end of the scattering node includes: a single-frequency oscillator, a radio frequency switch and an MCU; The single frequency oscillator and MCU are connected with the RF switch; The MCU includes: an encoding module, a modulation module and a packaging module.

8. The highly reliable semi-backscatter communication system according to claim 6, characterized in that: The software defined radio receiving end includes a radio frequency receiving unit, a frequency band conversion unit, a digital-to-analog conversion unit, a data sampling unit and a PC unit connected in sequence; A software platform is installed in the PC unit, and the software platform includes: a frame synchronization module, a CSS demodulation module and a decoding module.