DDR-SPI (Double Data Rate-Serial Peripheral Interface) module and correction sampling method compatible with multiple rates
By delaying the sampling clock in the DDR-SPI module, the delay problem of DDR-SPI protocol in actual transmission is solved, sampling errors are avoided, and compatibility with protocols of different speeds is achieved.
Patent Information
- Application Number
- CN202510196807.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2025-05-27
AI Technical Summary
The DDR-SPI protocol has delay problems in actual transmission, resulting in sampling errors. Especially when the total delay exceeds half of the sampling clock cycle, it may miss the rising or falling edges, causing sampling errors.
A DDR-SPI module and a multi-rate compatible correction sampling method are designed. By delaying the sampling clock in units of high-speed clock cycles, the sampling point position is adjusted to avoid sampling errors caused by total delay. The method includes generating a high-speed system clock signal with a frequency of F1, outputting a start pulse signal, outputting a counter enable signal according to the flip of the start pulse signal, and counting the high-speed system clock signal after receiving the enable signal, generating a serial clock signal and a sampling reference clock signal, and translating it on the basis of the sampling reference clock signal to obtain the sample clock signal.
By delay adjustment of the sampling clock, the sampling point position can be adjusted within a certain range, avoid sampling errors caused by total delay, and achieve compatibility with DDR-SPI protocols at different rates.
Smart Images
Figure CN120050017A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of communication technology, relates to a DDR-SPI transmission technology, and specifically relates to a DDR-SPI module and a multi-rate compatible correction sampling method. Background Art
[0002] The SPI (Serial Peripheral Interface) protocol has been widely used since the early 1980s, mainly for communication between microcontrollers and peripherals. With the development of technology, multiple SPI variants have emerged to meet different performance and application requirements. DDR-SPI (Double Data Rate Serial Peripheral Interface) is an extended protocol based on the traditional SPI protocol, designed to meet the needs of modern electronic devices for higher data transfer rates. The technology was originally introduced in the memory field to increase the data transfer rate. With the success of DDR technology in memory modules, it has gradually been applied to other scenarios, such as high-resolution images, real-time data processing, and large-scale data transmission.
[0003] Traditional SPI protocols usually transmit data on a single clock edge, while DDR-SPI can transmit data on both the rising and falling edges of the clock, so that twice the data can be transmitted in each clock cycle, significantly improving the data bandwidth. To ensure the accuracy and stability of the data, DDR SPI requires high-precision clock generation and strict timing control. Signal integrity management is also key to reduce interference and delays. In DDR SPI, data IO ports are usually driven into half-duplex multiple data channels, which again improves transmission efficiency. This requires designers to support the same protocol between master and slave devices, and to plan the hardware layout and connections reasonably to ensure optimal performance.
[0004] As an extended serial communication technology of SPI, DDR SPI combines the flexibility of traditional SPI and the efficiency of DDR, and adapts to the needs of modern electronic devices for high-speed data transmission. With the continuous development of technology, DDR SPI is expected to be applied in more fields and promote the further advancement of data communication technology.
[0005] When DDR SPI samples the signal through the trigger of SCK, each rising edge and falling edge will be sampled once. That is to say, 2 bits of data are sent or received in one clock cycle, so the read and write speed can be doubled without increasing the clock frequency. Figure 1A typical implementation of DDR-SPI is shown. SCK is the serial port clock signal, generated by the master device; CS is the chip select signal, which selects the only slave device and is controlled by the master device. Low level is valid; IO0-IO3 are different data lines.
[0006] DDR-SPI is an improvement and extension of the SPI protocol to increase data transfer rate and efficiency, and transmits data at the rising and falling edges of each clock cycle, thereby doubling the data transfer rate. This means that at the same clock frequency, the data throughput of DDR-SPI is twice that of SPI.
[0007] The above protocols are all based on ideal conditions. The actual SPI transmission must take into account the circuit transmission time and the device data preparation time. When the master device initiates a rising edge, the slave device cannot immediately obtain the rising edge. The delay during this period is the data transmission delay. Similarly, when the slave device wants to read data in a certain space, the slave device needs time to prepare the data, that is, there is also a data preparation delay.
[0008] Figure 2 This describes a typical process of the DDR-SPI protocol in actual transmission: at a certain moment, the master device clock signal Master SCK sends a rising edge jump; after data transmission on the circuit, the slave device Slave receives the rising edge jump after T1. Here, T1 is the delay caused by data transmission. It takes T2 time for the slave device Slave to prepare data, and at the same time, the Slave transmits the data back to the master device Master, which also needs to be transmitted through the circuit, so there will be a delay of T1 again. It can be seen that from the first rising edge of the clock signal sent by the master device Master to the correct sampling of data, the total delay is 2*T1+T2. After sending the address, the total delay TA=2*T1+T2 between the master and slave devices must be passed before the data is sampled to obtain the correct data. When the total delay TA exceeds half of the sampling clock period, the rising edge or falling edge will be missed, resulting in an error in the sampled value. Summary of the invention
[0009] In view of the defects of the above-mentioned prior art, the present invention discloses a DDR-SPI module and a multi-rate compatible correction sampling method.
[0010] The DDR-SPI module of the present invention includes a master device and a slave device, and also includes a system clock generation module and a first register, wherein the output end of the first register is connected to the enable end of the first counter and the second counter, the output end of the first counter is connected to the reference clock generation module and the serial port clock generation module, the output end of the reference clock generation module is connected to the second counter, the second counter is connected to the second register and the output end of the serial port clock generation module, the master device is connected to the second counter and the system clock generation module, and the slave device is connected to the master device and the output end of the serial port clock generation module.
[0011] Preferably, the first counter includes an equal logic module, the logic of the equal logic module is to output a high level signal when the two input ends are equal, otherwise it outputs a low level signal, the two input ends of the equal logic module are respectively connected to the first counter threshold and the output end of the first counter, the output end of the equal logic module is connected to the control end of the first selector, the output end of the first counter is also connected to an adder, the output end of the adder is connected to an input end of the first selector, the output end of the first selector is connected to an input end of the second selector, the control end of the second selector is connected to an enable signal, the output end of the second selector is connected to the input end of the first D flip-flop in the D flip-flop string, the D flip-flop string is composed of a plurality of D flip-flops connected in series, the Q end of the last D flip-flop is used as the output end of the first counter, and the clock end of each D flip-flop XD is connected to a high-speed system clock signal; The logical function of the selector is to select different input signals as output according to the control terminal level; the logical function of the adder is to add the values of the two input terminals and output them. The first selector, the second selector and the other input terminal of the adder are respectively connected to the fixed logic value signals of the external input.
[0012] Preferably, the second counter includes two branch modules, each branch module includes an AND gate, one input end of the AND gate is connected to the sampling reference clock signal, the output end is connected to an input end of the first OR gate, the other input end of the first OR gate is connected to the output end of an inverter, the output end of the first OR gate is connected to the control end of the first selector, and one input end of the first selector is connected to the output end of the adder; the output end of the first selector is connected to an input end of the second selector, the output end of the second selector is connected to a D flip-flop string, the D flip-flop string is composed of a plurality of D flip-flops connected in series, the Q end of each D flip-flop is connected to a high-speed system clock signal, the Q end of the last D flip-flop is connected to an input end of the equal logic module, the first selector and the adder, and the other input end of the equal logic module is connected to the second register; the output end of the equal logic module is also connected to the input end of the inverter and the control end of the second selector, and serves as the output end of the branch module; The logic of the equal logic module is to output a high level signal when the two input terminals are equal, otherwise it outputs a low level signal; the logic function of the selector is to select different input terminal signals as output according to the control terminal level; the logic function of the adder is to add the values of the two input terminals and then output; the other input terminal of the second selector and the adder are respectively connected to the fixed logic value signal of the external input; The other input end of the AND gate of the two branch modules is respectively connected to the in-phase and inverted signals of the serial port clock signal ddr_clk, and the output ends of the two branch modules are respectively connected to different input ends of the second OR gate, and the output end of the second OR gate serves as the output end of the second counter.
[0013] The present invention also discloses a multi-rate compatible correction sampling method, which is implemented based on the DDR-SPI module as claimed in claim 1; Step 1. Generate a high-speed system clock signal with a frequency of F1; Step 2. Output a start pulse signal, wherein the start pulse signal is a single pulse signal; Step 3. Use the flip edge of the start pulse signal as the trigger edge to output the counter enable signal EN; Step 4. After the first counter receives the counter enable signal, it starts to Counting and outputting a counting signal, the counting cycle of the counter is 2*(n+1); n is the set first counter threshold; Step 5. According to the counting signal, the master device generates and outputs a serial clock signal to the slave device, and the level flip time point of the serial port clock signal is set to any constant value of the counting signal; Step 6. Generate a sampling reference clock signal, wherein the high level time period of the sampling reference clock is the same as the maximum constant value of the counting signal, and if they are different, they are both the lowest time period; Step 7. Based on the sampled reference clock signal, shift several system clock signal cycles TC, and make the shift time greater than the total delay of the master and slave devices, where the system clock signal cycle TC = 1 / F1; obtain the sampled clock signal rx; Step 8. Sampling is performed during the high level period of the sampling clock signal and at the flip edge of the high-speed system clock signal.
[0014] Preferably, the specific implementation method of step 7 is to input the sampling reference clock signal into the second counter, the second counter reads the shift bit number W temporarily stored in the second register, shifts the sampling reference clock signal by several system clock signal cycles TC, and outputs the shifted sampling clock signal, wherein the system clock signal cycle TC=1 / F1.
[0015] The present invention delays the sampling clock in units of high-speed clock cycles, and can adjust the sampling point position within a certain range to avoid sampling errors caused by total delay. Since delay operations of different numbers of high-speed clock cycles can be performed, DDR-SPI protocols of different rates can be compatible. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The figure shows a typical implementation diagram of the master-slave device connection of DDR-SPI in the prior art; Figure 2 The figure shows a typical process in which the DDR-SPI protocol in the prior art causes delay in actual transmission; Figure 3 It is a schematic diagram of the timing sequence of each signal waveform of a specific implementation method of the sampling point correction transmission method of the present invention; Figure 4 FIG. 1 is a schematic diagram of a specific implementation of the DDR-SPI module of the present invention; Figure 5 FIG. 1 is a schematic diagram of a specific implementation of the first counter of the present invention; Figure 6 Shown is a schematic diagram of a specific implementation method of the second counter of the present invention. DETAILED DESCRIPTION
[0017] In order to more intuitively and clearly describe the specific details of the technical solution of the present invention, a detailed description will be given below in conjunction with specific embodiments and example drawings.
[0018] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the specific implementation methods of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0019] The modified sampling method compatible with multi-rate DDR-SPI of the present invention can be based on the following Figure 4 The DDR-SPI module implementation shown; The DDR-SPI module includes a master device MASTER and a slave device SLAVE, and also includes a system clock generation module and a first register, the output end of the first register is connected to the enable end of the first counter and the second counter, the output end of the first counter is connected to the reference clock generation module and the serial port clock generation module, the output end of the reference clock generation module is connected to the second counter, the second counter is connected to the second register, and the output ends of the second counter and the serial port clock generation module are also connected to the master device and the slave device.
[0020] The modified sampling method compatible with multi-rate DDR-SPI comprises the following steps: Step 1. Generate a high-speed system clock signal sys-clk with a frequency of F1; like Figure 4 As shown, the system clock generation module outputs a high-speed system clock signal sys-clk, and transmits it to each sub-module inside the DDR-SPI module as a global clock signal.
[0021] Step 2. Output a start pulse signal first, the start pulse signal is a single pulse signal; Step 3. Use the flip edge of the start pulse signal as the trigger edge to output the counter enable signal EN; the start pulse signal is input from the outside via the data transmission bus connected to the DDR-SPI module. Figure 4 In the specific implementation shown, the start pulse signal is input to the first register, which is usually a trigger, and the output value is initially zero. At the falling edge of the start pulse signal, the output value flips to a high level, that is, a counter enable signal EN is generated; Step 4. After receiving the counter enable signal, the first counter starts counting the high-speed system clock signal and outputs a counting signal cnt. The counting period of the counter is 2*(n+1); n is the threshold of the first counter; for example, when n=0, the counter realizes 2 division, and when n=1, 3, 7, it realizes 4 division, 8 division, and 16 division, respectively.
[0022] like Figure 3 and Figure 4 As shown, this step actually divides the high-speed system clock signal, and the frequency division multiple depends on the set first counter threshold; Figure 3 In the specific implementation shown, n=3 is set, and the counting cycle of the counter is 4, that is, the counter counts with four values of 0, 1, 2, and 3 as a period and repeatedly outputs the counting signal cnt; that is, the frequency of the counter after frequency division is one quarter of the frequency F1 of the high-speed system clock signal sys-clk; Among them, the first counter circuit involves frequency division processing and signal counting functions, and the specific implementation method is as follows Figure 5As shown, the first counter is activated by the enable signal EN to generate cnt with the set frequency division parameter.
[0023] The first counter includes an equal logic module X1. The logic of the equal logic module X1 is to output a high level signal when the two input ends are equal, otherwise it outputs a low level signal. The two input ends of the equal logic module are respectively connected to the first counter threshold n and the output end of the first counter, the output end of the equal logic module is connected to the control end of the first selector, the output end of the first counter is also connected to the adder X2, the output end of the adder X2 is connected to an input end of the first selector, the output end of the first selector is connected to an input end of the second selector, the control end of the second selector is connected to an enable signal EN, and the output end of the second selector is connected to the input end of the first D flip-flop in the D flip-flop string. The D flip-flop string is composed of a plurality of D flip-flops connected in series, whose Q ends are connected to the D end of the next D flip-flop, and the Q end of the last D flip-flop serves as the output end of the first counter, and the clock end CLK of each D flip-flop XD is connected to the high-speed system clock signal sys-clk.
[0024] In the circuit of the first counter, the system clock signal is counted. When the count reaches the set count cycle, the counter will be reset to zero and count again. The serial port clock signal and the sampling reference signal are generated based on the count value logic. The implementation method of the counter can meet the application requirements of simple structure and high flexibility.
[0025] The logic function of the selector X3 is to select different input terminal signals as output according to the control terminal level; the logic function of the adder X2 is to add the values of the two input terminals and then output them. The first selector, the second selector and the other input terminal of the adder are respectively connected to the fixed logic value signals input from the outside, for example Figure 5 Connect 0, 0, and 1 respectively.
[0026] After the counting signal cnt is obtained, different levels are used to trigger the counting points under the combinational logic to generate the serial port clock signal flip point ddr_ov and the sampling reference clock signal rx_base for the second counter.
[0027] Step 5. Output a serial port clock signal ddr-clk according to the counting signal, wherein the level flip time point of the serial port clock signal is set to any constant value of the counting signal; like Figure 3As shown, the frequency division parameter n=3 is set, that is, 8-frequency division is achieved. Then, the level flip time point of the serial port clock signal is when the counting signal cnt=1, which can be expressed as ddr_ov=(cnt==n / 2) in programming language. After the register beats, a stable serial clock signal ddr_clk is output. The serial port clock signal ddr-clk flips at any constant value of the counting signal, and two flips constitute a complete cycle. That is, the obtained serial port clock signal ddr-clk is actually half the frequency of the counting signal, which is one eighth of the frequency F1 of the high-speed system clock signal sys-clk.
[0028] The serial port clock signal ddr-clk is obtained by high-speed clock division of the master device MASTER and output to the slave device SLAVE. ddr_clk is the serial clock signal SCK in the SPI communication protocol, so as to achieve data synchronization during the SPI communication process.
[0029] Step 6. Generate a sampling reference clock signal rx-base, wherein the high level time period of the sampling reference clock is the same as the maximum constant value of the counting signal, and if they are different, they are both the lowest time period; Step 7. Based on the sampled reference clock signal rx-base, shift by several system clock signal cycles TC, and make the shift time greater than the total delay TA of the master and slave devices, where the system clock signal cycle TC = 1 / F1; obtain the sampled clock signal rx; The specific implementation of step 7 can be that the sampling reference clock signal rx-base is input to the second counter, the second counter reads the number of shift bits W temporarily stored in the second register, shifts the sampling reference clock signal by W periods TC of the system clock signal, and outputs the shifted sampling clock signal rx. The implementation principle is that the sampling reference clock signal rx-base activates the second counter, and counts using the system clock signal. After the count reaches W periods, the rx sampling clock signal is generated for data collection inside the MASTER, and SP is the actual sampling point.
[0030] The specific method of the second counter circuit is as follows: Figure 6As shown, it includes two branch modules, each branch module includes an AND gate AND, one input end of the AND gate is connected to the sampling reference clock signal rx-base, the output end is connected to an input end of the first OR gate, the other input end of the first OR gate is connected to the output end of an inverter INV, the output end of the first OR gate is connected to the control end of the first selector, and one input end of the first selector is connected to the output end of the adder X2; the output end of the first selector is connected to an input end of the second selector, and the output end of the second selector is connected to a D flip-flop string XDS, the D flip-flop string is composed of a plurality of D flip-flops connected in series, the Q end of each D flip-flop is connected to the high-speed system clock signal sys-clk, the Q end of the last D flip-flop is connected to an input end of the equal logic module X1, the first selector and the adder X2, the other input end of the equal logic module is connected to the second register, and the logic of the equal logic module X1 is that when the two input ends are equal, a high level signal is output, otherwise a low level signal is output; The output end of the equal logic module X1 is also connected to the input end of the inverter and the control end of the second selector, and serves as the output end of the branch module; The logic function of the selector X3 is to select different input terminal signals as output according to the control terminal level; the logic function of the adder X2 is to add the values of the two input terminals and then output them.
[0031] The other input end of the AND gate of the two branch modules is connected to the in-phase and inverted signals of the serial port clock signal ddr-clk, respectively. Figure 6 As shown, the serial port clock signal ddr-clk and the output signal of the serial port clock signal ddr-clk after passing through an inverter are directly connected respectively; the output ends of the two branch modules are respectively connected to different input ends of the second OR gate, and the output end of the second OR gate outputs the rx sampling clock signal.
[0032] The second counter uses the sampling reference clock signal rx-base as the pre-shift reference sampling signal to shift the actual sampling point by several clock cycles of the high-speed system clock signal sys-clk based on the sampling reference clock signal rx-base.
[0033] The second counter is enabled by the sampling reference clock signal rx-base and the serial port clock signal ddr-clk, and the value pre-stored in the second register is used as the counting cycle. The second counter circuit is divided into two parts, the upper part realizes the sampling point shift at the rising edge, and the lower part realizes the sampling point shift at the falling edge. The function of the logic circuit composed of the AND gate, the OR gate, the adder X2, the selector, etc. is to generate a trigger signal according to the storage value of the second register. The D flip-flop string receives the trigger signal to start counting, and returns the reset signal to reset the logic circuit after the input high-speed system clock signal sys-clk is used to count, thereby realizing the cycle shift; therefore, the overall circuit can meet the shift of the sampling point within a cycle range of the serial port clock signal ddr-clk. This method allows the parameters of the sampling point shift to be flexibly adjusted according to actual needs, and can adapt to different application scenarios and changing needs. Under the premise of meeting the simple circuit structure, it is easy to expand to other modules or circuits, providing greater flexibility in function.
[0034] After the circuit is finalized, the total delay TA of the master and slave devices can be obtained by simulation testing with a simulation tool, and the delay generated from the master device generating the clock signal to the slave device receiving the clock signal can be obtained.
[0035] Step 8. During the high level period of the sampling clock signal rx, sampling is performed at the flip edge of the high-speed system clock signal sys-clk. The SP curve of the sampling point is as follows: Figure 1 shown.
[0036] Figure 3 In the waveform shown, sampling is performed during the high level period of the sampling clock signal rx and at the rising edge of the high-speed system clock signal sys-clk.
[0037] After the set sampling time ends, the externally generated start pulse signal first generates a pulse signal again, and returns to step 2.
[0038] The present invention delays the sampling clock in units of high-speed clock cycles, and can adjust the sampling point position within a certain range to avoid sampling errors caused by total delay. Since delay operations of different numbers of high-speed clock cycles can be performed, DDR-SPI protocols of different rates can be compatible.
[0039] The foregoing describes various preferred embodiments of the present invention. Unless the preferred implementation modes in various preferred embodiments are obviously self-contradictory or based on a certain preferred implementation mode, various preferred implementation modes can be arbitrarily superimposed and used in combination. The embodiments and specific parameters in the embodiments are only for clearly describing the invention verification process of the inventor, and are not used to limit the patent protection scope of the present invention. The patent protection scope of the present invention shall still be based on its claims. All equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the protection scope of the present invention.
Claims
1. A DDR-SPI module, comprising a master device and a slave device, characterized in that: It also includes a system clock generation module and a first register, the output end of the first register is connected to the enable end of the first counter and the second counter, the output end of the first counter is connected to the reference clock generation module and the serial port clock generation module, the output end of the reference clock generation module is connected to the second counter, the second counter is connected to the second register and the output end of the serial port clock generation module, the master device is connected to the second counter and the system clock generation module, and the slave device is connected to the master device and the output end of the serial port clock generation module.
2. The DDR-SPI module according to claim 1, wherein: The first counter includes an equal logic module, the logic of the equal logic module is to output a high level signal when the two input ends are equal, otherwise it outputs a low level signal, the two input ends of the equal logic module are respectively connected to the first counter threshold and the output end of the first counter, the output end of the equal logic module is connected to the control end of the first selector, the output end of the first counter is also connected to an adder, the output end of the adder is connected to an input end of the first selector, the output end of the first selector is connected to an input end of the second selector, the control end of the second selector is connected to an enable signal, and the output end of the second selector is connected to the input end of the first D flip-flop in the D flip-flop string, the D flip-flop string is composed of a plurality of D flip-flops connected in series, the Q end of the last D flip-flop is used as the output end of the first counter, and the clock end of each D flip-flop XD is connected to a high-speed system clock signal; The logical function of the selector is to select different input signals as output according to the control terminal level; the logical function of the adder is to add the values of the two input terminals and output them. The first selector, the second selector and the other input terminal of the adder are respectively connected to the fixed logic value signals of the external input.
3. The DDR-SPI module according to claim 1, wherein: The second counter includes two branch modules, each branch module includes an AND gate, one input end of the AND gate is connected to the sampling reference clock signal, the output end is connected to an input end of the first OR gate, the other input end of the first OR gate is connected to the output end of an inverter, the output end of the first OR gate is connected to the control end of the first selector, and one input end of the first selector is connected to the output end of the adder; the output end of the first selector is connected to an input end of the second selector, the output end of the second selector is connected to a D flip-flop string, the D flip-flop string is composed of a plurality of D flip-flops connected in series, the Q end of each D flip-flop is connected to a high-speed system clock signal, the Q end of the last D flip-flop is connected to an input end of the equal logic module, the first selector and the adder, and the other input end of the equal logic module is connected to the second register; the output end of the equal logic module is also connected to the input end of the inverter and the control end of the second selector, and serves as the output end of the branch module; The logic of the equal logic module is to output a high level signal when the two input terminals are equal, otherwise it outputs a low level signal; the logic function of the selector is to select different input terminal signals as output according to the control terminal level; the logic function of the adder is to add the values of the two input terminals and then output; the other input terminal of the second selector and the adder are respectively connected to the fixed logic value signal of the external input; The other input end of the AND gate of the two branch modules is respectively connected to the in-phase and inverted signals of the serial port clock signal ddr_clk, and the output ends of the two branch modules are respectively connected to different input ends of the second OR gate, and the output end of the second OR gate serves as the output end of the second counter.
4. A multi-rate compatible modified sampling method, characterized in that: Based on the DDR-SPI module implementation as claimed in claim 1; Step 1. Generate a high-speed system clock signal with a frequency of F1; Step 2. Output a start pulse signal, wherein the start pulse signal is a single pulse signal; Step 3. Use the flip edge of the start pulse signal as the trigger edge to output the counter enable signal EN; Step 4. After the first counter receives the counter enable signal, it starts to Counting and outputting a counting signal, the counting cycle of the counter is 2*(n+1); n is the set first counter threshold; Step 5. According to the counting signal, the master device generates and outputs a serial clock signal to the slave device, and the level flip time point of the serial port clock signal is set to any constant value of the counting signal; Step 6. Generate a sampling reference clock signal, wherein the high level time period of the sampling reference clock is the same as the maximum constant value of the counting signal, and if they are different, they are both the lowest time period; Step 7. Based on the sampled reference clock signal, shift a number of system clock signal cycles TC, and make the shift time greater than the total delay of the master and slave devices, where the system clock signal cycle TC = 1 / F1; Get a sampling clock signal rx; Step 8. Sampling is performed during the high level period of the sampling clock signal and at the flip edge of the high-speed system clock signal.
5. The multi-rate compatible modified sampling method according to claim 4, characterized in that: The specific implementation method of step 7 is to input the sampling reference clock signal into the second counter, the second counter reads the number of shift bits W temporarily stored in the second register, shifts the sampling reference clock signal by several system clock signal cycles TC, and outputs the shifted sampling clock signal, wherein the system clock signal cycle TC=1 / F1.