Network convergence device

Abstract

The invention discloses a network convergence device, which comprises a receiving and transmitting cache module used for caching message data of different network protocols, re-packing received data and unpacking sent data; the verification and analysis module is used for verifying received message data, adding a verification field to sent message data and analyzing and extracting address information and data load in a data message; the address mapping module is used for completing mapping transformation among different network protocol addresses; and the format conversion module is used for completing format conversion among different network protocol messages. According to the network convergence device, efficient data transmission protocol conversion and cross-network data transmission can be achieved, and the cross-network problem of data transmission between the IB network and the Ethernet in the prior art is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of network technology, and particularly relates to a network fusion device. Background Art

[0002] Currently, in the fields of data centers and high-performance computing, two key network technologies, namely IB (InfiniBand) technology and Ethernet, are usually adopted. Among them, as the most widely used local area network technology at present, Ethernet has the advantages of low cost, good compatibility, easy expansion, etc.; however, Ethernet also has disadvantages such as high latency, limited bandwidth, and heavy CPU burden. The IB network adopts a channel-based architecture and can achieve high-bandwidth and low-latency data transmission; however, the IB network also faces disadvantages such as high cost, poor compatibility, and high complexity. The IB network and Ethernet have different applicable scenarios. Summary of the Invention

[0003] The present invention provides a network fusion device to solve the above-mentioned technical problems, and specifically adopts the following technical solutions: A network fusion device includes: A transceiver buffer module, configured to cache packet data of different network protocols, repackage received data, and unpack transmitted data; A check and parsing module, configured to verify received packet data, add a check field to transmitted packet data, and parse and extract address information and data payload in the data packet; An address mapping module, configured to complete mapping transformation between different network protocol addresses; A format conversion module, configured to complete format conversion between different network protocol packets.

[0004] Further, the transceiver buffer module includes: An IB network packet transceiver buffer module, configured to cache, repackage, and unpack IB network packet data; An Ethernet packet transceiver buffer module, configured to cache, repackage, and unpack Ethernet packet data.

[0005] Further, when receiving IB network packet data, it is determined whether it is an initial fragment according to the header information of the packet. If it is an initial fragment, a cache space of corresponding size is allocated in the buffer area and the data is cached; if the buffer area is full, the earliest cached data is deleted to make room; if it is a subsequent fragment, the data is cached to the corresponding buffer area and it is determined whether the packet is reassembled. If the reassembly is completed, the packet is output to the IB network packet check and parsing module; when transmitting IB network packet data, the complete packet is split into multiple fragments according to the size of the maximum transmission unit and sent sequentially; When receiving Ethernet packet data, determine whether it is the initial fragment according to the header information of the packet. If it is the initial fragment, allocate a buffer space of the corresponding size in the buffer and cache the data; if the buffer is full, delete the earliest cached data to free up space; if it is a subsequent fragment, cache the data to the corresponding buffer and determine whether the packet has been reassembled. If the reassembly is complete, output the packet to the Ethernet packet verification and parsing module; when sending Ethernet packet data, split the complete packet into multiple fragments according to the size of the maximum transmission unit and send them sequentially.

[0006] Further, the verification and parsing module includes: The IB network packet verification and parsing module is used to verify and validate the IB network packet data, add a verification field, and parse and extract the address information and data payload. The Ethernet packet verification and parsing module is used to verify and validate the Ethernet packet data, add a verification field, and parse and extract the address information and data payload.

[0007] Further, the IB network packet verification and parsing module sends the parsed address information to the address mapping module, and sends the header information and the parsed data payload to the format conversion module. The address mapping module performs a mapping transformation according to the address information and sends the mapped address information to the format conversion module. The format conversion module completes the packet format conversion according to the header information, data payload, and mapped address information, and outputs the converted packet to the Ethernet packet verification and parsing module; The Ethernet packet verification and parsing module sends the parsed address information to the address mapping module, and sends the header information and the parsed data payload to the format conversion module. The address mapping module performs a mapping transformation according to the address information and sends the mapped address information to the format conversion module. The format conversion module completes the packet format conversion according to the header information, data payload, and mapped address information, and outputs the converted packet to the IB network packet verification and parsing module.

[0008] Further, the IB network packet verification and parsing module verifies and validates the converted packet, adds a new verification field, and then sends the packet to the IB network packet transceiver buffer module; The Ethernet packet verification and parsing module verifies and validates the converted packet, adds a new verification field, and then sends the packet to the Ethernet packet transceiver buffer module.

[0009] Further, the IB network message transceiver buffer module receives the messages output by the IB network message verification and parsing module, and splits the complete messages into multiple fragments according to the maximum transmission unit size of the IB network, and sequentially sends the fragments to the IB network; the Ethernet message transceiver buffer module receives the messages output by the Ethernet message verification and parsing module, and splits the complete messages into multiple fragments according to the maximum transmission unit size of the Ethernet network, and sequentially sends the fragments to the Ethernet network.

[0010] Further, the address mapping module uses a hash algorithm for address mapping to achieve fast lookup and transformation between different network protocol addresses; the hash algorithm is the cuckoo hash algorithm, which realizes the storage and query of address mapping pairs through a double hash table and a double hash function.

[0011] Further, the network convergence device is based on a cooperative hardware architecture of CPU and FPGA, and is used to realize the operation of the address mapping table and the hardware acceleration of message processing.

[0012] Further, the FPGA uses BRAM resources to cache the address mapping table to shorten the clock cycle of hardware lookup and reduce latency; the maintenance of the address mapping table is realized through operations of addition, deletion, modification, and query; the CPU is responsible for the overall control and management of the system, including tasks such as initializing hardware resources, configuring parameters, and managing the address mapping table; the FPGA is responsible for processing real-time data streams, including hardware acceleration functions such as message reception, caching, verification, and format conversion; the CPU and the FPGA are connected through a high-speed interface to achieve efficient transmission of data and control signals.

[0013] The beneficial effect of the present invention lies in the provided network convergence device, which can realize efficient data transmission protocol conversion and cross-network data transmission, and solve the cross-network problem of data transmission between the IB network and the Ethernet in the prior art.

[0014] The beneficial effect of the present invention also lies in the provided network convergence device, which is based on a CPU+FPGA hardware system, thereby reducing the CPU load rate while increasing the bandwidth and reducing the latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 It is a schematic diagram of a network convergence device of the present application; Figure 2It is the workflow diagram of the transceiver buffer module of this application; Figure 3 It is the schematic diagram of the transceiver buffer module of this application for fragmenting the data payload; Figure 4 It is the processing schematic diagram of the verification and parsing module of this application; Figure 5 It is the specific process of inserting and looking up address mapping pairs using the cuckoo hash algorithm in this application; Figure 6 It is the schematic diagram of the implementation process based on CPU + FPGA in this application; Figure 7 It is the format conversion schematic diagram of the format conversion module of this application. Detailed implementation manners

[0017] The embodiments of this application are described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the drawings are exemplary and are intended to explain this application, and should not be construed as a limitation to this application.

[0018] As Figure 1 shown, a network fusion device of this application, as a network node, can realize the conversion and transmission of data packets between the IB network and the Ethernet at the transport layer. The network fusion device includes: a transceiver buffer module, a verification and parsing module, an address mapping module, and a format conversion module. The transceiver buffer module is used to cache the packet data of different network protocols, repackage the received data, and unpack the transmitted data. The verification and parsing module is used to verify and validate the received packet data, add a verification field to the transmitted packet data, and parse and extract the address information and data payload in the data packet. The address mapping module is used to complete the mapping transformation between different network protocol addresses. Specifically, the address mapping module is responsible for completing the mapping transformation between the IP address, UDP port number of the Ethernet packet and the LID (Local Identifier), QP (Queue Pair) number of the IB network. The format conversion module is used to complete the format conversion between different network protocol packets.

[0019] In the implementation manner of this application, the transceiver buffer module includes: an IB network packet transceiver buffer module and an Ethernet packet transceiver buffer module. The IB network packet transceiver buffer module is used to cache, repackage, and unpack the IB network packet data. The Ethernet packet transceiver buffer module is used to cache, repackage, and unpack the Ethernet packet data.

[0020] The transceiver buffer module uses DDR to buffer the message data to be transmitted and received, and performs packet splitting and reassembly on the message data. In the implementation of this application, as Figure 2 shown, the working principle of the IB network message transceiver buffer module is as follows: when receiving IB network message data, it is judged whether it is the initial fragment according to the OpCode (Operation Code) in the message header. If the OpCode of the message fragment is First or Only, it is judged that the fragment is the initial fragment, and then a buffer space of the corresponding size is allocated in the buffer and the data is buffered. If the buffer is full, the earliest buffered data is deleted to make room. If it is a subsequent fragment, the data is buffered to the corresponding buffer and it is judged whether the message has been reassembled. If the reassembly is completed, the message is output to the IB network message verification and parsing module. If the reassembly is not completed, this module will continue to wait for new messages to be received. When sending IB network message data, the complete message is split into multiple fragments according to the size of the Maximum Transmission Unit (MTU) and sent sequentially. As Figure 3 described, taking the case of 2*MTU < Length ≤ 3*MTU where the message length is Length as an example, the specific unpacking process is shown. Due to the limitation of the network MTU, the IB network message transceiver buffer module needs to fragment its data payload to obtain D1 (with a length of MTU), D2 (with a length of MTU), and D3 (with a length of Length - 2*MTU). Since the message fragments D1, D2, and D3 contain the same address information, the message fragment headers remain the same. The message header is reassembled with the data payloads D1, D2, and D3 to obtain three message fragments to complete the unpacking operation of the message, and the message fragments are sent out sequentially.

[0021] Similarly, the working principle of the Ethernet message transceiver buffer module is the same: when receiving Ethernet message data, it is judged whether it is the initial fragment according to the fragment offset in the message header. If the fragment offset is 0, it is judged that the fragment is the initial fragment, and then a buffer space of the corresponding size is allocated in the buffer and the data is buffered. If the buffer is full, the earliest buffered data is deleted to make room. If it is a subsequent fragment, the data is buffered to the corresponding buffer and it is judged whether the message has been reassembled. If the reassembly is completed, the message is output to the Ethernet message verification and parsing module. If the reassembly is not completed, this module will continue to wait for new messages to be received. When sending Ethernet message data, the complete message is split into multiple fragments according to the size of the Maximum Transmission Unit and sent sequentially. As Figure 3As described above, similar to the IB network packet processing process, if the packet length is Length, taking 2*MTU < Length ≤ 3*MTU as an example, the specific unpacking process is shown. Due to the limitation of the network MTU, the Ethernet packet transceiver buffer module also needs to fragment its data payload to obtain D1 (with a length of MTU), D2 (with a length of MTU), and D3 (with a length of Length - 2*MTU). Since the packet fragments D1, D2, and D3 contain the same address information, the packet fragment headers remain consistent. The packet header is recombined with the data payloads D1, D2, and D3 to obtain three packet fragments, so as to complete the unpacking operation of the packet, and the packet fragments are sent out in sequence.

[0022] In an embodiment of the present application, the verification and parsing module includes: an IB network packet verification and parsing module and an Ethernet packet verification and parsing module.

[0023] The IB network packet verification and parsing module is used to verify and validate the IB network packet data, add a verification field, and parse and extract the address information and data payload. The Ethernet packet verification and parsing module is used to verify and validate the Ethernet packet data, add a verification field, and parse and extract the address information and data payload.

[0024] Specifically, the IB network packets and Ethernet packets recombined by the transceiver buffer module usually consist of header information (Header Information), data payload (Data Payload), and a verification field. As Figure 4As shown in the figure, if the data is an Ethernet UDP packet, the One's Complement Sum algorithm is used, that is, the UDP pseudo-header (including some fields in the IP header), the UDP header, and the data part are segmented by 16 bits, and all 16-bit segments are added and verified one by one; if the data is an IB network UD packet, the CRC32 (Cyclic Redundancy Check) and CRC16 algorithms are used to generate ICRC (Invariant CRC) and VCRC (Variant CRC) check fields for the LRH (Local Route Header), GRH (Global Route Header), BTH (Base Transport Header), and data payload of the IB packet for verification. If the verification fails, it means that the packet has been damaged during transmission, and the packet data packet is discarded; if the verification passes, the check parsing module will parse out the address information in the packet header and output it to the address mapping module to achieve cross-network address mapping, and output the header information and data payload to the format conversion module to achieve cross-network protocol format conversion. After obtaining the new header information and reorganized data payload through format conversion, the check parsing module will calculate and add new check fields to form a complete packet data and send it out.

[0025] Specifically, as Figure 4 shown in the figure, the IB network packet check parsing module sends the parsed address information to the address mapping module, and sends the header information and the parsed data payload to the format conversion module. The address mapping module performs mapping transformation based on the address information and sends the mapped address information to the format conversion module. The format conversion module completes the packet format conversion according to the header information, data payload, and mapped address information, and outputs the converted packet to the Ethernet packet check parsing module. The IB network packet check parsing module verifies the converted packet and adds new check fields, and then sends the packet to the IB network packet transceiver buffer module. The IB network packet transceiver buffer module receives the packet output by the IB network packet check parsing module, and splits the complete packet into multiple fragments according to the maximum transmission unit size of the IB network and sends them to the IB network in sequence.

[0026] Similarly, the Ethernet packet verification and parsing module sends the parsed address information to the address mapping module, and sends the header information and the parsed data payload to the format conversion module. The address mapping module performs mapping transformation based on the address information and sends the mapped address information to the format conversion module. The format conversion module completes the packet format conversion based on the header information, data payload, and mapped address information, and outputs the converted packet to the IB network packet verification and parsing module. The Ethernet packet verification and parsing module verifies the converted packet and adds a new verification field, and then sends the packet to the Ethernet packet transceiver buffer module. The Ethernet packet transceiver buffer module receives the packet output by the Ethernet packet verification and parsing module, and splits the complete packet into multiple fragments according to the maximum transmission unit size of the Ethernet network and sends them to the Ethernet network in sequence.

[0027] The address mapping module is responsible for implementing the mutual mapping conversion between Ethernet addresses and IB network addresses. The key to the mutual conversion is to construct an address mapping table to store the address mapping pairs of Ethernet IP addresses, UDP port numbers, and IB network LIDs and QP numbers, and to use an efficient search algorithm to query the address mapping pairs. In the implementation manner of this application, the address mapping module uses a hash algorithm for address mapping to achieve fast search and transformation between different network protocol addresses. Specifically, the hash algorithm is the cuckoo hash algorithm, and the storage and query of address mapping pairs are realized through a double hash table and a double hash function.

[0028] Such as Figure 5The following shows the specific process of inserting and looking up address mapping pairs using the cuckoo hash algorithm. When it is known that an Ethernet IP address and a UDP port number need to be inserted into the corresponding IB network LID and QP number through the hash algorithm, the IP address and the UDP port number are used as the key values, and the hash functions h1(x) and h2(x) are used to calculate the storage positions i1 and i2 of the two hash mapping tables respectively. If one of the positions i1 in the first table or i2 in the second table is empty, insert directly; otherwise, move the data at that position to another unoccupied position. Repeat the above process until an empty position is found or the maximum number of loops (MaxLoop) is reached. When looking up the address mapping pair using the hash algorithm, the IP address and the UDP port number are used as the key values, and the hash functions h1(x) and h2(x) are used to calculate the storage positions i1 and i2 of the two hash mapping tables respectively. Look up the address pair (IP address, UDP port number, LID, QP number) at positions i1 and i2, and compare and verify it with the input key value (IP address and UDP port number). If they are the same, it means the lookup is correct; if not, it means the address pair does not exist in the hash table. In the selection of the hash function, the CRC12 algorithm, which is relatively fast to calculate on hardware, is adopted, and two CRC12 functions with different check codes are used as the hash functions h1(x) and h2(x). Similarly, when it is known the IB network LID and QP number and one wants to insert and look up the corresponding Ethernet IP address and UDP port number, the corresponding address mapping pair can be stored in the hash mapping table from the IB network to the Ethernet and looked up through the hash algorithm.

[0029] As Figure 6 shown, taking the mapping table from Ethernet to IB network as an example to show its implementation process based on CPU + FPGA. The user writes specific instructions to the relevant registers through the software interface based on the AXI (Advanced Xtensible Interface) bus. The contents of the registers are the operation instruction cmd (add, delete, modify, query), the instruction key value cmd_key (IP address, udp port number), and the instruction matching value cmd_value (cmd_key and its corresponding (QP number, LID)), as specifically Figure 4 shown. The output value of cmd_key after passing through the hash function is used as the write address addra of the dual-port BRAM, and cmd_value is used as the data dina stored at the corresponding address of the BRAM. cmd_done is the instruction completion flag bit. Pulling it high indicates that the instruction is completed. The status information of the completed instruction will be stored in the register, and the pulse signal of the completed instruction will trigger a CPU interrupt. After the software receives the interrupt request, it reads the completion status of the hash table instruction.

[0030] After receiving a complete UDP packet, the in-FPGA logic needs to query the address mapping hash table and read the relevant address information. During the query operation, the hardware logic extracts the query Key value, and the query instruction cmd_key of the hash table is set to the (IP address, UDP port number) to be queried. After passing through the hash function, the output value is used as the read address addrb of the dual-port BRAM. After the mapping table completes the query operation, it will pull up cmd_done to indicate that the operation is completed, output the data doutb stored at the corresponding address, and compare it with cmd_key for verification. If the comparison is successful, it means that the corresponding address pair is found. The mapping table will pull up the match success flag bit match to indicate a successful query, and return the match value match_value to the corresponding (QP number, LID); if the comparison fails, it means that the corresponding address cannot be found, and the mapping table will pull up the match failure flag error.

[0031] Hardware query is more convenient than software query because the address mapping table is stored in the hardware system itself. Therefore, the CPU and registers are not required during the query process. Just set the cmd line and cmd_key line to perform the query, but the hardware can only perform query operations on the mapping table.

[0032] The network fusion device of this application is based on the cooperative hardware architecture of the CPU and FPGA, and is used to implement the operation of the address mapping table and the hardware acceleration of packet processing. Specifically, this application selects to use the BRAM resources of the FPGA to cache the address mapping table to shorten the clock cycle of hardware lookup and reduce the latency. The maintenance of the mapping table is achieved through operations such as insert, delete, update, and select. The CPU is responsible for the overall control and management of the system, including tasks such as initializing hardware resources, configuring parameters, and managing the address mapping table; the FPGA is responsible for processing real-time data streams, including hardware acceleration functions such as packet reception, caching, verification, and format conversion. The CPU and FPGA are connected through a high-speed interface to achieve efficient transmission of data and control signals.

[0033] As Figure 7 shown, although both Ethernet UDP packets and IB network UD packets adopt the format of header information plus data payload, the meanings of the header fields are quite different, so format conversion is required. After receiving the verified packet data, the format conversion module will perform conversion according to the requirements of the network protocol, and add the address information from the address mapping module (IP address and UDP port number for Ethernet, LID and QP number for IB network) to complete the format conversion function. The converted packet will be output to the verification and parsing module to add a verification field and then sent out.

[0034] The basic principles, main features and advantages of the present invention have been shown and described above. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and all technical solutions obtained by means of equivalent replacement or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A network fusion device, characterized in that: include: The transceiver buffer module is used to buffer the message data of different network protocols, repack the received data, and unpack the sent data; The verification and parsing module is used to verify the received message data, add a verification field to the sent message data, and parse and extract the address information and data load in the data message; Address mapping module, used to complete the mapping transformation between different network protocol addresses; The format conversion module is used to complete the format conversion between different network protocol messages.

2. The network fusion device according to claim 1, characterized in that: The transceiver buffer module comprises: IB network message receiving and sending buffer module, used for buffering, packaging and unpacking IB network message data; The Ethernet message receiving and sending buffer module is used for buffering, assembling and unpacking Ethernet message data.

3. The network fusion device according to claim 2, characterized in that: When receiving IB network message data, determine whether it is an initial fragment based on the header information of the message. If it is an initial fragment, allocate a corresponding size of cache space in the cache area and cache the data; If the buffer is full, delete the earliest cached data to make room; if it is a subsequent fragment, cache the data in the corresponding buffer and determine whether the message is reassembled. If the message is reassembled, output the message to the IB network message verification and parsing module; when sending IB network message data, split the complete message into multiple fragments according to the size of the maximum transmission unit and send them in sequence; When receiving Ethernet message data, determine whether it is an initial fragment based on the header information of the message. If it is an initial fragment, allocate a corresponding size of cache space in the cache area and cache the data; If the buffer is full, delete the earliest cached data to make room; if it is a subsequent fragment, cache the data in the corresponding buffer and determine whether the message is reassembled. If the reassembly is complete, output the message to the Ethernet message verification and parsing module; when sending Ethernet message data, split the complete message into multiple fragments according to the size of the maximum transmission unit and send them in sequence.

4. The network fusion device according to claim 2, characterized in that: The verification and analysis module includes: IB network message verification and parsing module, used to verify the IB network message data, add verification fields, and parse and extract address information and data payload; The Ethernet message verification and parsing module is used to verify the Ethernet message data, add a verification field, and parse and extract the address information and data load.

5. The network fusion device according to claim 4, characterized in that: The IB network message verification and parsing module sends the parsed address information to the address mapping module, and sends the header information and the parsed data load to the format conversion module. The address mapping module performs mapping transformation according to the address information, and sends the mapped address information to the format conversion module. The format conversion module completes the message format conversion according to the header information, the data load and the mapped address information, and outputs the converted message to the Ethernet message verification and parsing module; The Ethernet message verification and parsing module sends the parsed address information to the address mapping module, and sends the header information and the parsed data load to the format conversion module. The address mapping module performs mapping transformation according to the address information, and sends the mapped address information to the format conversion module. The format conversion module completes the message format conversion according to the header information, data load and mapped address information, and outputs the converted message to the IB network message verification and parsing module.

6. The network fusion device according to claim 5, characterized in that: The IB network message verification and parsing module verifies and verifies the converted message, adds a new verification field, and then sends the message to the IB network message transceiver buffer module; The Ethernet message verification and analysis module verifies and verifies the converted message, adds a new verification field, and then sends the message to the Ethernet message transceiver buffer module.

7. The network fusion device according to claim 6, characterized in that: The IB network message transceiver cache module receives the message output by the IB network message verification and analysis module, splits the complete message into multiple fragments according to the maximum transmission unit size of the IB network, and sends them to the IB network in sequence; the Ethernet message transceiver cache module receives the message output by the Ethernet message verification and analysis module, splits the complete message into multiple fragments according to the maximum transmission unit size of the Ethernet network, and sends them to the Ethernet network in sequence.

8. The network fusion device according to claim 1, characterized in that: The address mapping module uses a hash algorithm to perform address mapping to achieve fast search and conversion between different network protocol addresses; the hash algorithm is a cuckoo hash algorithm, which implements storage and query of address mapping pairs through a double hash table and a double hash function.

9. The network fusion device according to claim 1, characterized in that: The network fusion device is based on a collaborative hardware architecture of CPU and FPGA, and is used to implement hardware acceleration of address mapping table operations and message processing.

10. The network fusion device according to claim 9, characterized in that: FPGA uses BRAM resources to cache the address mapping table to shorten the clock cycle of hardware search and reduce latency; the maintenance of the address mapping table is achieved through add, delete, modify, and query operations; the CPU is responsible for the overall control and management of the system, including initializing hardware resources, configuring parameters, managing address mapping tables and other tasks; FPGA is responsible for processing real-time data streams, including hardware acceleration functions such as message reception, caching, verification, and format conversion; the CPU and FPGA are connected through a high-speed interface to achieve efficient transmission of data and control signals.

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