Display control system and display control method

Abstract

The invention discloses a display control system and a display control method. The system comprises a control module, a switching chip, a serial-parallel conversion module and a display module. The control module is used for generating a configuration signal and a control signal; the switching chip outputs a clock signal and a code stream signal representing the port state of the equipment based on the configuration of the configuration signal; the serial-to-parallel conversion module samples the low level and the high level of the code stream signal based on the clock signal and converts the low level and the high level into a parallel data signal; the first end of the display module is connected to receive the control signal, and the second end of the display module receives the parallel data signal. According to the display control system and the display control method, the states of the 2N equipment ports can be displayed by adopting the N display modules through one pin of the control module and the N pins of the serial-parallel conversion module, so that the application of the original 2N pins can be reduced to N + 1, and the application of the pins is greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of device port status indication control, and particularly relates to a display control system and a display control method. Background Art

[0002] Whether it is a router or a switch, whether it is an optical fiber port or an Ethernet electrical port, generally each port has an LED indicator to indicate whether the port is in a working state, that is, whether the computer or network device connected to the port is in a working state and whether the connectivity is intact. When the device connected to the port is in a shutdown state or there is a problem with the link connectivity, the LED indicator of the corresponding port will go out. Only when the port has intact connectivity and the port is normally connected (link), the indicator will be lit.

[0003] When the number of LED indicators is limited due to space constraints or other reasons, in order to display the complete port status, dual-color LEDs are used. Taking the example of using 8 yellow-green dual-color LEDs to display 16 ports, the yellow indication state of the dual-color LED can represent ports 1 to 8, and the green indication state can represent ports 9 to 16. Therefore, in a periodic cycle, the status of ports 1 to 8 is displayed in the first time period T1, and the status of ports 9 to 16 is displayed in the second time period T2. The first time period T1 + the second time period T2 is a complete cycle, and it repeats continuously.

[0004] Figure 1 There is a control circuit for a dual-color LED. The switching chip is a chip that leads out the network device port and detects the port status. The CPLD (Complex Programmable Logic Device) is used to decode the LED_CLK and LED_DATA (two 16-bit serial code stream information) carrying the port connection (link) status output by the switching chip into 16 parallel signals and output them from pins GPIO1 to 16. The resistor R is a current-limiting resistor to ensure that the LED indicator works within the normal power range. D1 to D8 are dual-color LEDs, and one LED indicator is composed of a yellow lamp bead Y and a green lamp bead G.

[0005] During the first time period T1, the yellow lamp beads Y of the D1 - D8 indicator lights respectively correspond to ports 1 - 8. If ports 1 - 8 are working properly, the yellow lamp beads Y will be lit. It is required that the anode of the yellow lamp bead Y is at a high level and the cathode is at a low level. When the levels at both poles of the yellow lamp bead Y are the same, the lamp bead does not emit light. If the low - level lighting logic is adopted during the first time period T1, the second pin GPIO2, the fourth pin GPIO4, the sixth pin GPIO6, the eighth pin GPIO8, the tenth pin GPIO10, the twelfth pin GPIO12, the fourteenth pin GPIO14, and the sixteenth pin GPIO16 of the CPLD need to maintain a high - level state. The lighting and extinguishing of the lamp are only determined by the cathode level of the yellow lamp bead Y. That is, when port 1 is working properly, the first pin GPIO1 outputs a low level to light the yellow lamp bead Y of the D1 indicator light; when port 2 is working properly, the third pin GPIO3 outputs a low level to light the yellow lamp bead Y of the D2 indicator light... When port 8 is working properly, the fifteenth pin GPIO15 outputs a low level to light the yellow lamp bead Y of the D8 indicator light.

[0006] During the second time period T2, the green lamp beads of the D1 - D8 indicator lights respectively correspond to ports 9 - 16. If ports 9 - 16 are working properly, the green lamp beads G will be lit. It is required that the anode of the green lamp bead G is at a high level and the cathode is at a low level. When the levels at both poles of the green lamp bead G are the same, the lamp bead does not emit light. If the low - level lighting logic is adopted during the second time period T2, the first pin GPIO1, the third pin GPIO3, the fifth pin GPIO5, the seventh pin GPIO7, the ninth pin GPIO9, the eleventh pin GPIO11, the thirteenth pin GPIO13, and the fifteenth pin GPIO15 of the CPLD need to maintain a high - level state. The lighting and extinguishing of the lamp are only determined by the cathode level of the green lamp bead G. When port 9 is working properly, the second pin GPIO2 outputs a low level to light the green lamp bead G of the D1 indicator light; when port 10 is working properly, the fourth pin GPIO4 outputs a low level to light the green lamp bead G of the D2 indicator light... When port 16 is working properly, the sixteenth pin GPIO16 outputs a low level to light the green lamp bead G of the D8 indicator light.

[0007] Figure 2 It is a control circuit for a dual - color LED using a shift register 74HC164. Two 74HC164 are 8 - bit shift registers, which are used to decode the LED_CLK and LED_DATA (two 16 - bit serial code - stream information) carrying port status output by the switching chip into 16 parallel signals and output them to pins Q1 - 16. The resistor R is a current - limiting resistor to ensure that the LED works within the normal power range. D1 - D8 are dual - color LEDs, and one lamp position is composed of a yellow lamp bead Y and a green lamp bead G. Figure 2 The lighting principle of the dual - color LED in Figure 1 is the same.

[0008] Above Figure 1 In the example, 8 dual-color LEDs are used to indicate the status of 16 ports, which requires 16 GPIO pin resources of the CPLD. Figure 2 In the example, if an 8-bit shift register is used, 2 shift registers are needed, with a total of 16 bits of data output resources. Similarly, if N two-color LEDs are used to time-share 2N port states, 2N pin resources are needed. As the number of two-color LEDs increases, the occupied control pin resources will always double.

[0009] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0010] The object of the present invention is to provide a display control system and a display control method, which can reduce the occupation of pin resources.

[0011] In order to achieve the above objective, a specific embodiment of the present invention provides a display control system, including: a control module, a switching chip, a serial-to-parallel conversion module and a plurality of display modules.

[0012] The control module is used to generate a configuration signal and a periodic control signal; the switching chip outputs a clock signal and a code stream signal representing the state of the device port based on the configuration of the configuration signal; the serial-to-parallel conversion module is used to sample the low level and high level of the code stream signal based on the clock signal and convert it into a parallel data signal; the first end of each of the display modules is connected to receive the control signal, and the second end of each of the display modules is connected to the serial-to-parallel conversion module to receive the parallel data signal, and when the control signal is at a low level or a high level, each of the display modules displays the state of the device port based on the parallel data signal.

[0013] In one or more embodiments of the present invention, the display control system includes a switching module connected to the control module and the first end of each display module, and the switching module is used to convert the control signal into a preset voltage domain and output a converted control signal.

[0014] In one or more embodiments of the present invention, the switching module includes a first output transistor, a second output transistor, a first control unit, and a second control unit. The first end of the first output transistor is connected to a preset power supply voltage, the first end of the second output transistor is connected to a ground voltage, the control end of the first output transistor is connected to the output end of the first control unit, the control end of the second output transistor is connected to the output end of the second control unit. The input ends of the first control unit and the second control unit are used to receive control signals. The first control unit generates a corresponding first control signal based on the control of the control signal to control the turning on and off of the first output transistor. The second control unit generates a corresponding second control signal based on the control of the control signal to control the turning on and off of the second output transistor. The second end of the first output transistor is connected to the second end of the second output transistor to output a corresponding conversion control signal.

[0015] In one or more embodiments of the present invention, the first control unit includes a first bias unit, a first transistor, and a second bias unit. The first end of the first bias unit is connected to the control signal, the second end of the first bias unit is connected to the control end of the first transistor, the second end of the first transistor is connected to the second bias unit and the control end of the first output transistor, and the first end of the first transistor is connected to the ground voltage.

[0016] In one or more embodiments of the present invention, the first control unit further includes a delay unit, and the delay unit is connected between the second end of the second bias unit and the control end of the first transistor.

[0017] In one or more embodiments of the present invention, the delay unit includes a diode. The anode of the diode is connected to the second end of the first bias unit, and the cathode of the diode is connected to the control end of the first transistor.

[0018] In one or more embodiments of the present invention, the second control unit includes a third bias unit, a second transistor, and a fourth bias unit. The first end of the third bias unit is connected to the control signal, the second end of the third bias unit is connected to the control end of the second transistor, the second end of the second transistor is connected to the fourth bias unit and the control end of the second output transistor, and the first end of the second transistor is connected to the ground voltage.

[0019] In one or more embodiments of the present invention, the display module includes a first light-emitting diode and a second light-emitting diode. The cathode of the first light-emitting diode and the anode of the second light-emitting diode are connected to form the first end of the display module, and the anode of the first light-emitting diode and the cathode of the second light-emitting diode are connected to form the second end of the display module.

[0020] In one or more embodiments of the present invention, the display control system further includes a plurality of current limiting modules, which are in one-to-one correspondence with the respective display modules, and the current limiting module is connected between the second end of the display module and the serial-parallel conversion module.

[0021] Another specific embodiment of the present invention provides a display control method for the display control system, and the display control method includes:

[0022] Generating a configuration signal and a periodic control signal through a control module;

[0023] Outputting a clock signal and a bitstream signal representing the device port state based on the configuration of the configuration signal through a switching chip;

[0024] Sampling the low level and high level of the bitstream signal based on the clock signal through a serial-parallel conversion module and converting them into parallel data signals;

[0025] Displaying the state of the device port based on the parallel data signal through a plurality of display modules when the control signal is at a low level or a high level.

[0026] Compared with the prior art, the display control system and the display control method of the present invention can realize the display of the states of 2N device ports by using N display modules through one pin of the control module and N pins of the serial-parallel conversion module, so that the original 2N pin applications can be reduced to N + 1, greatly reducing the pin applications. Therefore, in the scenario where more display modules are used, the situation of insufficient pin resources caused by using a serial-parallel conversion module such as a CPLD can be solved. And if a shift register is used as the serial-parallel conversion module, the use of half of the shift registers can be reduced, greatly saving the hardware cost and reducing the space occupied on the PCB board. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 FIG. is a circuit schematic diagram of a display control system in the prior art.

[0029] Figure 2 FIG. is a circuit schematic diagram of another display control system in the prior art.

[0030] Figure 3 FIG. is a system schematic diagram of the display control system in an embodiment.

[0031] Figure 4 It is a partial circuit schematic diagram of a display control system in an embodiment.

[0032] Figure 5 It is a waveform diagram of a control signal in an embodiment.

[0033] Figure 6 It is a waveform diagram of a clock signal and a bitstream signal output by a switching chip indicating the status of a device port when all ports are working properly in a first time period in an embodiment.

[0034] Figure 7 It is a waveform diagram of a clock signal and a bitstream signal output by a switching chip indicating the status of a device port when all ports are not working in a first time period in an embodiment.

[0035] Figure 8 It is a waveform diagram of a clock signal and a bitstream signal output by a switching chip indicating the status of a device port when all ports are working properly in a second time period in an embodiment.

[0036] Figure 9 It is a waveform diagram of a clock signal and a bitstream signal output by a switching chip indicating the status of a device port when all ports are not working in a second time period in an embodiment. Detailed implementation manners

[0037] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0038] "Coupled" or "connected" or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through a circuit or component such as a switch, a follower circuit, etc. In addition, in the invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0039] In the detailed description of the specification, reference is made to the accompanying drawings that form a part hereof, in which like reference numerals always refer to like components, and which are shown by way of example embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense.

[0040] The various operations in the specification may be described sequentially as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0041] For the purposes of the present disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0042] Various components and devices may be referred to or shown herein in the singular form (e.g., “transistor,” “transistor,” “switch,” etc.), but this is merely for convenience of discussion, and any element referred to in the singular may include a plurality of such elements in accordance with the teachings herein.

[0043] The specification describes the use of the phrase “in one embodiment” or “in other embodiments” or “in some embodiments,” which may each refer to one or more of the same or different embodiments. Additionally, the terms “comprising,” “including,” “having,” etc., used with respect to the embodiments of the present disclosure are synonymous.

[0044] As Figure 3 shown, a display control system in an embodiment of the present invention includes: a control module 10, a switching chip 20, a serial-to-parallel conversion module 30, a switching module 40, and a plurality of display modules.

[0045] The control module 10 is configured to generate a configuration signal and a periodic control signal CPU_GPIO; the switching chip 20 outputs a clock signal LED_CLK and a bitstream signal LED_DATA representing the device port status based on the configuration of the configuration signal; the serial-to-parallel conversion module 30 is configured to sample the low and high levels of the bitstream signal LED_DATA based on the clock signal LED_CLK and convert them into parallel data signals.

[0046] The switching module 40 is connected to the control module 10 and the first ends of the respective display modules. The switching module 40 is configured to convert the control signal CPU_GPIO in a preset voltage domain and output a converted control signal. The first ends of the respective display modules are connected to receive the converted control signal. The second ends of the respective display modules are connected to the serial-to-parallel conversion module 30 to receive parallel data signals. When the converted control signal is at a low level or a high level, the respective display modules display the status of the device ports based on the parallel data signals. In other embodiments, the switching module 40 may not be provided.

[0047] In one embodiment, as Figure 4 shown, eight display modules D1, D2, D3 to D8 are provided, and each display module uses a two-color LED. Specifically, each display module includes a first light-emitting diode Y and a second light-emitting diode G. The cathode of the first light-emitting diode Y and the anode of the second light-emitting diode G are connected to form the first end of the display module. The anode of the first light-emitting diode Y and the cathode of the second light-emitting diode G are connected to form the second end of the display module. The first light-emitting diode Y emits yellow light when lit, and the second light-emitting diode G emits green light when lit. In other embodiments, light-emitting diodes of other colors may also be used.

[0048] The display control system further includes a plurality of current-limiting modules for current limiting. The current-limiting modules correspond to the respective display modules one by one. The current-limiting modules are connected between the second ends of the display modules and the serial-to-parallel conversion module 30. In one embodiment, as Figure 4 shown, the current-limiting module is composed of resistors. Eight current-limiting modules correspond to eight resistors R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, resistor R13, and resistor R14. The first end of resistor R7 is connected to the second end of display module D1, and the second end of resistor R7 is connected to pin Q1 of the serial-to-parallel conversion module 30; the first end of resistor R8 is connected to the second end of display module D2, and the second end of resistor R8 is connected to pin Q2 of the serial-to-parallel conversion module 30; the first end of resistor R9 is connected to the second end of display module D3, and the second end of resistor R9 is connected to pin Q3 of the serial-to-parallel conversion module 30; the first end of resistor R10 is connected to the second end of display module D4, and the second end of resistor R10 is connected to pin Q4 of the serial-to-parallel conversion module 30; the first end of resistor R11 is connected to the second end of display module D5, and the second end of resistor R11 is connected to pin Q5 of the serial-to-parallel conversion module 30; the first end of resistor R12 is connected to the second end of display module D6, and the second end of resistor R12 is connected to pin Q6 of the serial-to-parallel conversion module 30; the first end of resistor R13 is connected to the second end of display module D7, and the second end of resistor R13 is connected to pin Q7 of the serial-to-parallel conversion module 30; the first end of resistor R14 is connected to the second end of display module D8, and the second end of resistor R14 is connected to pin Q8 of the serial-to-parallel conversion module 30.

[0049] In one embodiment, the control module 10 may be a CPU, an FPGA, or other control modules; the serial-to-parallel conversion module 30 may be a CPLD (Complex Programmable Logic Device) or a shift register.

[0050] As Figure 4 shown, the switching module 40 includes a first output transistor MP, a second output transistor MN, a first control unit, and a second control unit. The first end of the first output transistor MP is connected to a preset power supply voltage, and the preset power supply voltage is 3.3V. The first end of the second output transistor MN is connected to the ground voltage. The control end of the first output transistor MP is connected to the output end of the first control unit, and the control end of the second output transistor MN is connected to the output end of the second control unit. The input ends of the first control unit and the second control unit are used to receive the control signal CPU_GPIO. The first control unit generates a corresponding first control signal based on the control of the control signal CPU_GPIO to control the turning on and off of the first output transistor MP. The second control unit generates a corresponding second control signal based on the control of the control signal CPU_GPIO to control the turning on and off of the second output transistor MN. The second end of the first output transistor MP is connected to the second end of the second output transistor MN to output a corresponding conversion control signal.

[0051] In one embodiment, the first output transistor MP is a P-channel MOS transistor, and the second output transistor MN is an N-channel MOS transistor. The first ends of the first output transistor MP and the second output transistor MN are source electrodes. The second ends of the first output transistor MP and the second output transistor MN are drain electrodes. The control ends of the first output transistor MP and the second output transistor MN are gate electrodes. In other embodiments, the first output transistor MP and the second output transistor MN may use other transistors.

[0052] As Figure 4 shown, the first control unit includes a first biasing unit, a first transistor M1, and a second biasing unit. The first end of the first biasing unit is connected to the control signal CPU_GPIO. The second end of the first biasing unit is connected to the control end of the first transistor M1. The second end of the first transistor M1 is connected to the second biasing unit and the control end of the first output transistor MP. The first end of the first transistor M1 is connected to the ground voltage.

[0053] The first control unit further includes a delay unit, and the delay unit is connected between the second end of the second biasing unit and the control end of the first transistor M1. Specifically, the delay unit includes a diode D0. The anode of the diode D0 is connected to the second end of the first biasing unit, and the cathode of the diode D0 is connected to the control end of the first transistor M1.

[0054] In one embodiment, the first bias unit includes a first resistor R1 and a third resistor R3, and the second bias unit includes a second resistor R2. The first end of the first resistor R1 is used to receive a control signal CPU_GPIO. The second end of the first resistor R1 is connected to the first end of the third resistor R3 and the anode of a diode D0. The cathode of the diode D0 is connected to the control end of a first transistor M1. The second end of the third resistor R3 is connected to a ground voltage. The first end of the second resistor R2 is connected to the second end of the first transistor M1 and the control end of a first output transistor MP. The second end of the second resistor R2 is connected to a preset power supply voltage, and the preset power supply voltage is 3.3V.

[0055] The second control unit includes a third bias unit, a second transistor M2, and a fourth bias unit. The first end of the third bias unit is connected to the control signal CPU_GPIO. The second end of the third bias unit is connected to the control end of the second transistor M2. The second end of the second transistor M2 is connected to the fourth bias unit and the control end of a second output transistor MN. The first end of the second transistor M2 is connected to a ground voltage.

[0056] In one embodiment, the third bias unit includes a fourth resistor R4 and a sixth resistor R6, and the fourth bias unit includes a fifth resistor R5. The first end of the fourth resistor R4 is used to receive the control signal CPU_GPIO. The second end of the fourth resistor R4 is connected to the first end of the sixth resistor R6 and the control end of the second transistor M2. The second end of the sixth resistor R6 is connected to a ground voltage. The first end of the fifth resistor R5 is connected to the second end of the second transistor M2 and the control end of the second output transistor MN. The second end of the fifth resistor R5 is connected to the preset power supply voltage, and the preset power supply voltage is 3.3V.

[0057] The first transistor M1 is an NPN type triode, and the second transistor M2 is a PNP type triode. The first ends of the first transistor M1 and the second transistor M2 are emitters. The second ends of the first transistor M1 and the second transistor M2 are collectors. The control ends of the first transistor M1 and the second transistor M2 are bases. In other embodiments, the first transistor M1 and the second transistor M2 can be other transistors.

[0058] The first resistor R1, the third resistor R3, the second resistor R2, the fourth resistor R4, and the sixth resistor R6, and the fifth resistor R5 all have the functions of voltage division and current limiting to ensure that appropriate biases are provided to the first transistor M1 and the second transistor M2. The diode D0 is a diode with a voltage drop of about 0.7V. Its function is to ensure that the first transistor M1 turns on with a certain delay compared to the second transistor M2 during the process of the control signal CPU_GPIO rising from a low level to a high level, achieving the purpose that the second output transistor MN turns off first and then the first output transistor MP turns on. Similarly, during the process of the control signal CPU_GPIO falling from a high level to a low level, it ensures that the second transistor M2 turns off with a certain delay compared to the first transistor M1, achieving the purpose that the first output transistor MP turns off first and then the second output transistor MN turns on. By setting the diode D0, it is possible to avoid the phenomenon of a short circuit between the preset power supply voltage and the ground voltage caused by the simultaneous conduction of the first output transistor MP and the second output transistor MN.

[0059] As Figure 3 shown, the input of the switching module 40 is controlled through one pin GPIO of the CPU to change whether the first end (the same pin) of all display modules (bi - color LEDs) is grounded or connected to the preset power supply voltage (3.3); then, by synchronously configuring the relevant registers of the switching chip 20 through the CPU, when changing the state of the corresponding device port of the switching chip 20, the change of the corresponding bit from a high level to a low level in the bit stream signal LED_DATA output is changed. By generating a periodic control signal CPU_GPIO through one pin GPIO of the CPU and generating parallel data signals through N pins of the serial - parallel conversion module 30, it is possible to control all bi - color LEDs to display two different colors, achieving the purpose of controlling N bi - color LEDs to display 2N port states with N + 1 pins.

[0060] As Figure 4 shown, taking the display of 16 device port states by 8 bi - color LEDs as an example, the display states of the first light - emitting diodes Y of the bi - color LEDs D1 - D8 can represent the first to eighth device port states, and the display states of the second light - emitting diodes G of D1 - D8 can represent the ninth to sixteenth device port states. Based on the control signal CPU_GPIO being a periodic signal with a period T of the first time period T1+ the second time period T2, therefore, in a periodic cycle manner, the states of the first to eighth device ports are displayed in the first time period T1, and the states of the ninth to sixteenth device ports are displayed in the second time period T2.

[0061] Furthermore, combining Figure 5 and Figure 4As shown, within the first time period T1, the statuses of the 1st to 8th device ports are displayed. The control signal CPU_GPIO outputs a low level. The first transistor M1 and the second transistor M2 are both turned off. The first output transistor MP is turned off, and the second output transistor MN is turned on, causing the first ends of all display modules (dual-color LEDs) to be connected to the ground voltage, which is equivalent to the cathodes of all the first light-emitting diodes Y of the display modules D1 to D8 being grounded. At this time, the CPU synchronously configures the relevant registers in the switching chip 20, adopts the high-level lighting logic, and outputs an 8-bit clock signal LED_CLK and a bitstream signal LED_DATA with the device port connection status. That is, when the 1st device port is operating normally, the corresponding bit in the bitstream signal LED_DATA output by the switching chip 20 is 1. After being decoded by the serial-to-parallel conversion module 30, a high level is output at the corresponding pin Q1, thereby directly lighting the first light-emitting diode Y of the display module D1. Similarly, when the 2nd device port is operating normally, a high level is output at the pin Q2 of the serial-to-parallel conversion module 30, directly lighting the first light-emitting diode Y of the display module D2;... When the 8th port is operating normally, a high level is output at the pin Q8 of the serial-to-parallel conversion module 30, directly lighting the first light-emitting diode Y of the display module D8.

[0062] Figure 6 Shown is the clock signal LED_CLK and the bitstream signal LED_DATA output by the switching chip 20 within the first time period T1 when all device ports are operating normally. The bitstream signal LED_DATA will periodically jump between high and low levels. At this time, the serial-to-parallel conversion module 30 samples the bitstream signal LED_DATA at the rising edge of the clock signal LED_CLK to obtain the corresponding parallel data signal (11111111).

[0063] Figure 7 Shown is that within the first time period T1 when all device ports are not operating normally, the bitstream signal LED_DATA is at a low level. The serial-to-parallel conversion module 30 samples the bitstream signal LED_DATA at the rising edge of the clock signal LED_CLK to obtain the corresponding parallel data signal (00000000).

[0064] Combined Figure 5 and Figure 4As shown, during the second time period T2, the statuses of the 9th to 16th device ports are displayed. The control signal CPU_GPIO outputs a high level. The first transistor M1 and the second transistor M2 are both turned on, the second output transistor MN is turned off, and the first output transistor MP is turned on. The first ends of all display modules are connected to a preset power supply voltage, which is equivalent to the anodes of all the second light-emitting diodes G of the display modules D1 to D8 being connected to a preset power supply voltage of 3.3V. At this time, the CPU synchronously configures the relevant registers of the switching chip 20, adopts a low-level lighting logic, and outputs an 8-bit clock signal LED_CLK and a sampled bitstream signal LED_DATA with the device port status. That is, when the 9th port is working properly, the corresponding bit in the bitstream signal LED_DATA output by the switching chip 20 is 0. After being decoded by the serial-to-parallel conversion module 30, the corresponding pin Q1 outputs a low level, thereby directly lighting the second light-emitting diode G of the display module D1. Similarly, when the 10th device port is working properly, the pin Q2 of the serial-to-parallel conversion module 30 outputs a low level, directly lighting the second light-emitting diode G of the display module D2;... When the 16th device port is working properly, the pin Q8 of the serial-to-parallel conversion module 30 outputs a low level, directly lighting the second light-emitting diode G of the display module D8.

[0065] Figure 8 It is shown that during the second time period T2, when all device ports are working properly, the clock signal LED_CLK and the bitstream signal LED_DATA output by the switching chip 20. The bitstream signal LED_DATA also periodically jumps between high and low levels. At this time, the serial-to-parallel conversion module 30 samples the bitstream signal LED_DATA at the rising edge of the clock signal LED_CLK to obtain the corresponding parallel data signal (00000000).

[0066] Figure 9 It is shown that during the second time period T2, when all device ports are not working properly, the bitstream signal LED_DATA is at a high level. At this time, the serial-to-parallel conversion module 30 samples the bitstream signal LED_DATA at the rising edge of the clock signal LED_CLK to obtain the corresponding parallel data signal (11111111).

[0067] The present invention also discloses a display control method for the above display control system. The display control method includes:

[0068] Generating a configuration signal and a periodic control signal through a control module.

[0069] Outputting a clock signal and a bitstream signal representing the device port status by a switching chip based on the configuration of the configuration signal.

[0070] The serial-parallel conversion module samples the low and high levels of the bitstream signal based on the clock signal and converts them into parallel data signals.

[0071] Through multiple display modules, when the control signal is at a low level or a high level, the status of the device ports is displayed based on the parallel data signals.

[0072] For the specific principle of the control method, reference can be made to the description of the display control system.

[0073] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

[0074] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A display control system, characterized in that, it includes: a control module for generating a configuration signal and a periodic control signal; a switching chip for outputting a clock signal and a bitstream signal representing the device port state based on the configuration of the configuration signal; a serial-to-parallel conversion module for sampling the low and high levels of the bitstream signal based on the clock signal and converting them into a parallel data signal; and a plurality of display modules, the first ends of each of the display modules are connected together to receive the control signal, the second ends of each of the display modules are connected to the serial-to-parallel conversion module to receive the parallel data signal, and when the control signal is at a low level or a high level, each of the display modules displays the state of the device port based on the parallel data signal.

2. The display control system according to claim 1, characterized in that, the display control system includes a switching module, the switching module is connected to the control module and the first ends of each display module, and the switching module is used to convert the control signal in a preset voltage domain and output a converted control signal.

3. The display control system according to claim 2, characterized in that, the switching module includes a first output transistor, a second output transistor, a first control unit and a second control unit, the first end of the first output transistor is connected to a preset power supply voltage, the first end of the second output transistor is connected to the ground voltage, the control end of the first output transistor is connected to the output end of the first control unit, the control end of the second output transistor is connected to the output end of the second control unit, the input ends of the first control unit and the second control unit are used to receive the control signal, the first control unit generates a corresponding first control signal based on the control of the control signal to control the turning on and off of the first output transistor, the second control unit generates a corresponding second control signal based on the control of the control signal to control the turning on and off of the second output transistor, and the second end of the first output transistor is connected to the second end of the second output transistor to output a corresponding converted control signal.

4. The display control system according to claim 3, characterized in that, the first control unit includes a first bias unit, a first transistor and a second bias unit, the first end of the first bias unit is connected to the control signal, the second end of the first bias unit is connected to the control end of the first transistor, the second end of the first transistor is connected to the second bias unit and the control end of the first output transistor, and the first end of the first transistor is connected to the ground voltage.

5. The display control system according to claim 4, characterized in that, the first control unit further includes a delay unit, and the delay unit is connected between the second end of the second bias unit and the control end of the first transistor.

6. The display control system according to claim 5, characterized in that, the delay unit includes a diode, the anode of the diode is connected to the second end of the first bias unit, and the cathode of the diode is connected to the control end of the first transistor.

7. The display control system according to claim 3, characterized in that, The second control unit includes a third biasing unit, a second transistor, and a fourth biasing unit. A first end of the third biasing unit is connected to a control signal, a second end of the third biasing unit is connected to a control end of the second transistor, a second end of the second transistor is connected to the fourth biasing unit and a control end of a second output transistor, and a first end of the second transistor is connected to a ground voltage.

8. The display control system according to claim 1, wherein, the display module includes a first light-emitting diode and a second light-emitting diode. A cathode of the first light-emitting diode and an anode of the second light-emitting diode are connected to form a first end of the display module, and an anode of the first light-emitting diode and a cathode of the second light-emitting diode are connected to form a second end of the display module.

9. The display control system according to claim 1, wherein, the display control system further includes a plurality of current-limiting modules. The current-limiting modules correspond to the respective display modules one by one, and the current-limiting modules are connected between a second end of the display module and the serial-parallel conversion module.

10. A display control method, wherein, for the display control system according to any one of claims 1 to 9, the display control method includes: generating a configuration signal and a periodic control signal through a control module; outputting a clock signal and a bitstream signal representing the state of the device port based on the configuration of the configuration signal through a switching chip; sampling the low level and high level of the bitstream signal based on the clock signal through a serial-parallel conversion module and converting them into parallel data signals; displaying the state of the device port based on the parallel data signals through a plurality of display modules when the control signal is at a low level or a high level.

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