Memory and method of making the same

Abstract

The present disclosure provides a memory and a manufacturing method thereof, and relates to the technical field of semiconductor technology, and is used to solve the technical problem of low yield of the memory. The memory comprises a bit line, a transistor, a capacitor, a contact structure and a support structure. A plurality of bit lines are arranged at intervals along a first direction. A plurality of transistors are arranged at intervals along the first direction and arranged at intervals along a second direction. The plurality of transistors along the first direction are correspondingly electrically connected to one bit line. The capacitor is correspondingly electrically connected to each transistor. Along a third direction, the capacitor and the bit line are located on both sides of the transistor. Each contact structure is correspondingly connected to one bit line. A plurality of support structures are arranged at intervals along the second direction and penetrate the plurality of bit lines. There are at least one support structure between the adjacent two contact structures, so as to support the plurality of bit lines, so that the adjacent two bit lines are kept at intervals, the bit lines are prevented from being contacted due to collapse, the stability of the manufacturing process of the memory is improved, the performance of the memory is ensured, and the yield of the memory is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a memory and a manufacturing method thereof. BACKGROUND

[0002] With the development of semiconductor technology, memory, especially dynamic random access memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read-write speed.

[0003] The dynamic random access memory includes a plurality of memory cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is connected to a word line (WL), the drain is connected to a bit line (BL), and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then the data information stored in the capacitor is read through the bit line or written into the capacitor through the bit line for storage.

[0004] In order to reduce the size of the memory and improve its storage density, the memory usually adopts a three-dimensional memory with horizontally placed capacitors, one end of which is connected to the transistor. A plurality of transistors in the horizontal direction are connected to a bit line, and the bit line is connected to the peripheral circuit through a vertical bit line plug. However, during the manufacturing process of the memory, especially the manufacturing process of the bit line, the stability of the structure is poor, and collapse is easy to occur, which affects the yield of the memory. SUMMARY

[0005] In view of the above problems, the embodiments of the present disclosure provide a memory and a manufacturing method thereof to improve the yield of the memory.

[0006] According to some embodiments, the present disclosure provides a memory, which includes: a plurality of bit lines, the plurality of bit lines are arranged at intervals along a first direction; a plurality of transistors, the plurality of transistors are arranged at intervals along the first direction and arranged at intervals along a second direction, a plurality of the transistors along the first direction correspondingly electrically connected to a bit line; a capacitor corresponding to each of the transistors, along a third direction, the capacitor and the bit line are located on both sides of the transistor, the first direction, the second direction and the third direction intersect with each other; a plurality of contact structures, the plurality of contact structures are arranged at intervals along the second direction and penetrate part of the bit lines, each of the contact structures correspondingly connected to a bit line; a plurality of support structures, the plurality of support structures are arranged at intervals along the second direction and penetrate the plurality of bit lines, there are at least one support structure between adjacent two contact structures.

[0007] In some possible embodiments, side walls of at least part of the support structure are formed with a plurality of first annular grooves arranged at intervals along the first direction; each of the bit lines comprises a first portion filled in the first annular grooves and a second portion located outside the first annular grooves, and along the first direction, a thickness of the first portion is smaller than a thickness of the second portion.

[0008] In some possible embodiments, the second portion comprises an extension and a connecting portion, the connecting portion connects two first portions adjacent along the second direction, and the extension connects the transistor and the first portion or the connecting portion opposite to the transistor.

[0009] In some possible embodiments, side walls of part of the contact structure opposite to the bit line are recessed from side walls of the remaining contact structure, so that the side walls of the contact structure are wavy.

[0010] In some possible embodiments, the memory further comprises a plurality of word lines arranged at intervals along the second direction, each of the word lines corresponds to a plurality of the transistors along the first direction and forms a gate electrode of the corresponding transistor; each of the transistors comprises a gate dielectric layer surrounding the gate electrode and a channel region surrounding the gate dielectric layer, and the channel region is connected to the bit line and the capacitor in correspondence.

[0011] In some possible embodiments, the gate dielectric layer comprises a body surrounding the gate electrode and an epitaxial portion connected to both ends of the body along the first direction, the epitaxial portions adjacent to each other of two gate dielectric layers along the first direction are in contact with each other, and a plurality of the gate dielectric layers along the first direction form an integrated body.

[0012] In some possible embodiments, the channel region covers surfaces opposite to each other of the corresponding epitaxial portions and a peripheral surface of the body, the channel region encloses a second annular groove, along the third direction, two sides of the channel region are respectively provided with the bit line and a connecting layer, and the bit line and the connecting layer extend into the second annular groove and are in corresponding contact with surfaces of the second annular groove, and the connecting layer is also in corresponding contact with the capacitor.

[0013] The memory provided by the embodiments of the present disclosure has at least the following advantages:

[0014] The memory provided by the embodiments of the present disclosure supports a plurality of bit lines by arranging a plurality of support structures penetrating through the plurality of bit lines, so that two adjacent bit lines are kept apart, the bit lines are prevented from contacting due to collapse, the stability of the memory manufacturing process is improved, the performance of the memory is ensured, and the yield of the memory is improved.

[0015] According to some embodiments, the disclosure also provides a method for manufacturing a memory, comprising: forming a stack structure on a substrate, the stack structure comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately along a first direction; forming a plurality of contact structures, a plurality of first intermediate structures and a plurality of second intermediate structures within the stack structure; wherein the plurality of contact structures, the plurality of first intermediate structures and the plurality of second intermediate structures are arranged spaced apart along a second direction, and along a third direction, the plurality of second intermediate structures are located on a side of the plurality of first intermediate structures away from the plurality of contact structures, each of the contact structures corresponds to a layer of the second sacrificial layers, the first intermediate structures and the second intermediate structures penetrate through the stack structure, and the first direction, the second direction and the third direction intersect with each other; forming at least one support structure between two adjacent contact structures along the second direction, the support structure penetrates through at least the stack structure; removing part of the stack structure between two adjacent first intermediate structures and two adjacent second intermediate structures along the second direction, forming a first isolation groove penetrating through the stack structure and arranged alternately with the first intermediate structures along the third direction, along the third direction, an end of the first isolation groove towards the support structure protrudes from an end of the first intermediate structure towards the support structure, and an end of the first isolation groove away from the support structure penetrates through the stack structure; removing the remaining second sacrificial layers to form a first filling space; forming a first conductive layer in the first filling space, the first conductive layer between the support structures, between the support structures and the contact structures, and between the support structures or the contact structures and the first intermediate structures forms a bit line, and the first conductive layer between the first intermediate structures and the second intermediate structures forms a connection layer; forming a first isolation layer in the first isolation groove, the first isolation layer fills the first isolation groove; removing the first intermediate structures to form a plurality of transistors arranged spaced apart along the first direction, removing the second intermediate structures to form a plurality of capacitors arranged spaced apart along the second direction, and removing the remaining first sacrificial layers to form a second isolation layer, along the third direction, each of the transistors is connected to one of the capacitors through the connection layer.

[0016] In some possible embodiments, forming at least one support structure between two contact structures adjacent along the second direction includes: etching the stack structure to form a plurality of first filling holes penetrating through the stack structure, the plurality of first filling holes being arranged at intervals along the second direction, and there being at least one first filling hole between two contact structures adjacent along the second direction; etching the first sacrificial layer exposed in the first filling hole to expand the first filling hole; thinning the second sacrificial layer exposed in the expanded first filling hole along the first direction to further expand the first filling hole and increase the distance between the adjacent portions of the second sacrificial layer exposed in the expanded first filling hole; and depositing the support structure, which fills the further expanded first filling hole.

[0017] In some possible embodiments, forming a plurality of contact structures, a plurality of first intermediate structures, and a plurality of second intermediate structures in the stack structure includes: etching the stack structure to form a plurality of second filling holes arranged at intervals along the second direction, each second filling hole corresponding to exposing one second sacrificial layer; forming a contact structure in the second filling hole, the contact structure filling the corresponding second filling hole; etching the stack structure to form a plurality of first intermediate holes on both sides of the contact structure along the third direction, the plurality of first intermediate holes on each side being arranged at intervals along the second direction, and each first intermediate hole exposing the substrate; forming the first intermediate structure in the first intermediate hole, the first intermediate structure filling the first intermediate hole; etching the stack structure to form a plurality of second intermediate holes on a side of the plurality of first intermediate structures away from the plurality of contact structures, the plurality of second intermediate holes on each side being arranged at intervals along the second direction, and along the third direction, each second intermediate hole being opposite to the first intermediate structure; and forming the second intermediate structure in the second intermediate hole, the second intermediate structure filling the second intermediate hole.

[0018] The method for manufacturing a memory provided by the embodiments of the present disclosure has at least the following advantages:

[0019] In the method for manufacturing a memory provided by the embodiments of the present disclosure, the plurality of support structures are formed to support the first sacrificial layers adjacent to each other, so that the two first sacrificial layers adjacent to each other are kept at intervals, thereby keeping the space for forming the bit lines, and after the bit lines are formed, the bit lines are prevented from being contacted due to collapse, the stability of the manufacturing process of the memory is improved, the performance of the memory is ensured, and the yield of the memory is improved. In addition, the first isolation layer and the second isolation layer are formed to ensure the insulation between the bit lines adjacent along the first direction, and the insulation between the two transistors adjacent along the second direction and the two capacitors adjacent along the second direction, thereby ensuring the performance of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A schematic diagram of an architecture of a memory in an embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of a structure of a memory in an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of a vertical cross-section of a structure of a memory in an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of a vertical cross-section of another structure of a memory in an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram of a top view cross-section of a memory in an embodiment of the present disclosure;

[0025] Figure 6 A Figure 5 A close-up view of a portion of the memory in an embodiment of the present disclosure;

[0026] Figure 7 A flowchart of a method of fabricating a memory in an embodiment of the present disclosure;

[0027] Figure 8 A perspective view of a substrate and stack structure in an embodiment of the present disclosure;

[0028] Figure 9 A schematic diagram of a cross-section of a substrate and stack structure in an embodiment of the present disclosure;

[0029] Figure 10 A perspective view after forming a first photoresist layer in an embodiment of the present disclosure;

[0030] Figure 11 A process diagram of forming a second fill hole in an embodiment of the present disclosure;

[0031] Figure 12 A process diagram of forming a contact structure in an embodiment of the present disclosure;

[0032] Figure 13 A perspective view after forming a second photoresist layer in an embodiment of the present disclosure;

[0033] Figure 14 A process diagram of forming a first intermediate hole in an embodiment of the present disclosure;

[0034] Figure 15 A process diagram of forming a first intermediate structure in an embodiment of the present disclosure;

[0035] Figure 16 A perspective view after forming a third photoresist layer in an embodiment of the present disclosure;

[0036] Figure 17 A process diagram of forming a second intermediate hole in an embodiment of the present disclosure;

[0037] Figure 18 A process diagram of forming a second intermediate structure in an embodiment of the present disclosure;

[0038] Figure 19 A perspective view after forming a second intermediate structure in an embodiment of the present disclosure;

[0039] Figure 20 A perspective view after forming a fourth photoresist layer in an embodiment of the present disclosure;

[0040] Figure 21 A process diagram of forming a first filling hole in an embodiment of the present disclosure;

[0041] Figure 22 A process diagram of thinning a second sacrifice layer in an embodiment of the present disclosure;

[0042] Figure 23 A process diagram of forming a support structure in an embodiment of the present disclosure;

[0043] Figure 24 A perspective view after forming a fifth photoresist layer in an embodiment of the present disclosure;

[0044] Figure 25 A perspective view after forming a first isolation groove in an embodiment of the present disclosure;

[0045] Figure 26 A cross-sectional view after forming a first filling space in an embodiment of the present disclosure;

[0046] Figure 27 A schematic view after a first conductive layer in an embodiment of the present disclosure;

[0047] Figure 28 A perspective view after forming a first isolation layer in an embodiment of the present disclosure;

[0048] Figure 29 A cross-sectional view after forming a first etching hole in an embodiment of the present disclosure;

[0049] Figure 30 A cross-sectional view after expanding a first etching hole in an embodiment of the present disclosure;

[0050] Figure 31 A cross-sectional view after a transistor in an embodiment of the present disclosure;

[0051] Figure 32 A cross-sectional view after removing a first sacrifice layer in an embodiment of the present disclosure;

[0052] Figure 33 a cross-sectional view after forming a second isolation layer in an embodiment of the present disclosure;

[0053] Figure 34 a process diagram of forming a lower electrode in an embodiment of the present disclosure;

[0054] Figure 35 a cross-sectional view after forming a lower electrode in an embodiment of the present disclosure.

[0055] Legend of reference signs:

[0056] 10 - substrate; 11 - substrate; 12 - protective layer; 13 - etching stop layer; 20 - stack structure; 21 - first sacrificial layer; 22 - second sacrificial layer; 23 - second filling hole; 24 - third sacrificial layer; 25 - fourth sacrificial layer; 26 - fifth sacrificial layer; 27 - sixth sacrificial layer; 31 - first mask layer; 32 - second mask layer; 33 - first photoresist layer; 34 - third mask layer; 35 - fourth mask layer; 36 - second photoresist layer; 37 - fifth mask layer; 38 - sixth mask layer; 39 - third photoresist layer; 41 - seventh mask layer; 42 - eighth mask layer; 43 - ninth mask layer; 44 - fourth photoresist layer; 45 - tenth mask layer; 46 - eleventh mask layer; 47 - fifth photoresist layer; 50 - contact structure; 51 - insulating layer; 52 - conductive column; 53 - first intermediate hole; 54 - first intermediate structure; 55 - second intermediate hole; 56 - second intermediate structure; 57 - first filling hole; 58 - support structure; 61 - first isolation groove; 62 - first filling space; 63 - first isolation layer; 64 - first isolation sublayer; 65 - second isolation sublayer; 66 - first etching hole; 67 - second filling space; 68 - second isolation layer; 69 - second etching hole; 70 - first conductive layer; 71 - first conductive sublayer; 72 - second conductive sublayer; 73 - bit line; 74 - connection layer; 75 - first part; 76 - second part; 77 - extension; 78 - connection part; 80 - transistor; 81 - channel layer; 82 - gate dielectric layer; 83 - body; 84 - epitaxial part; 85 - gate; 86 - channel region; 90 - capacitor; 91 - lower electrode layer; 92 - lower electrode; 93 - capacitor dielectric layer; 94 - upper electrode; 95 - capacitor plug. DETAILED DESCRIPTION

[0057] The embodiment of the present disclosure provides a memory. A plurality of support structures are arranged through a plurality of bit lines to support the plurality of bit lines, so that two adjacent bit lines are kept apart, the bit lines are prevented from contacting due to collapse, the stability of a manufacturing process of the memory is improved, the performance of the memory is ensured, and the yield of the memory is improved.

[0058] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0059] See Figures 1 to 5 This disclosure provides a memory including multiple bit lines 73, multiple transistors 80, multiple capacitors 90, multiple contact structures 50, and multiple support structures 58. The multiple bit lines 73 are arranged at intervals along a first direction, and the multiple transistors 80 are arranged at intervals along the first direction and at intervals along a second direction to form a multi-row, multi-column transistor array. The multiple transistors 80 along the first direction are electrically connected to a bit line 73.

[0060] The first direction intersects with the second direction, for example, they are perpendicular. For instance, the first direction is as follows: Figure 2 The Z direction is shown, and the second direction is as follows: Figure 1 and Figure 2 The Y direction is shown. In the transistor array formed by multiple transistors 80, each transistor 80 along the first direction is in contact with the end face of the corresponding bit line 73, as shown. Figure 1 As shown, the left end face of each of the multiple transistors 80 along the first direction is in contact with the right end face of the corresponding bit line 73.

[0061] Multiple transistors 80 also correspond to multiple capacitors 90, with each transistor 80 electrically connected to one capacitor 90. Along the third direction, the capacitors 90 and bit lines 73 are located on opposite sides of the transistor 80, as shown below. Figure 1 As shown, transistor 80 is disposed between the corresponding capacitor 90 and bit line 73. The third direction intersects both the first and second directions; that is, the first, second, and third directions intersect each other in pairs, for example, perpendicularly, to improve the memory's storage density. In the first direction, as shown... Figure 2 The Z direction is shown, and the second direction is as follows: Figure 1 and Figure 2 In the example shown in the Y direction, the third direction is as follows: Figure 1 The X direction is shown.

[0062] Multiple contact structures 50 correspond to multiple bit lines 73 respectively, and each contact structure 50 is connected to one bit line 73 to externally connect each bit line 73. The multiple contact structures 50 are spaced apart along a second direction, and along a first direction, one end of the multiple contact structures 50 ( Figure 2 The upper end (as shown) extends beyond multiple bit lines 73, and the other end (Figure 2 The lower end of the diagram shows a penetrating portion of bit line 73, and it makes contact with one of the bit lines 73. The surfaces of the multiple contact structures 50 that make contact with the bit lines 73 form a stepped shape.

[0063] It is understood that the contact structure 50 corresponding to each bit line 73 penetrates the bit line 73 on one side (e.g., above) and is insulated from the bit lines 73 above it, so as to achieve electrical connection between the corresponding contact structure 50 and the bit line 73, and electrical isolation from other bit lines 73. The bit line 73 located at the bottom along the first direction is not penetrated, and the contact structure 50 corresponding to this bit line 73 penetrates all other bit lines 73 and is insulated from all other bit lines 73. The contact structure 50 corresponding to the bit line 73 located at the top along the first direction does not penetrate any bit line 73.

[0064] For example, bit line 73 has N lines, where N is a positive integer greater than 1. Along Figure 2 As shown from top to bottom, these N bit lines are sequentially designated as bit line 1, bit line 2, ..., bit line N. The first bit line and the Nth bit line are located outside these N bit lines 73. The number of contact structures 50 is greater than or equal to N. For example, there are N contact structures 50, which are designated as contact structure 1, contact structure 2, ..., contact structure N. Among them, the i-th contact structure makes contact with the i-th bit line and has electrical connection with other bit lines 73, where i is greater than or equal to 1 and less than N.

[0065] Specifically, the first contact structure contacts the first bit line, the second contact structure contacts the second bit line, the third contact structure contacts the third bit line, and so on, with the Nth contact structure contacting the Nth bit line. To achieve contact between the corresponding contact structure 50 and the bit line 73, the i-th contact structure extends through all bit lines 73 above the i-th bit line. That is, the second contact structure extends through the first bit line to ensure that the lower end of the second contact structure contacts the second bit line. The third contact structure extends through both the second and first bit lines to ensure that the lower end of the third contact structure contacts the third bit line, and so on.

[0066] In some examples, the sidewall of the portion of the contact structure 50 opposite to the bit line 73 is recessed into the sidewall of the remaining contact structure 50, making the sidewall of the contact structure 50 wavy. This configuration allows the contact structure 50 to contact the side of the corresponding bit line 73, and also to contact the surface portion of the corresponding bit line 73 opposite each other along the first direction, increasing the contact area between the contact structure 50 and the corresponding bit line 73 and reducing the contact resistance between them.

[0067] Continue reading Figure 1 and 2Multiple support structures 58 are spaced apart along the second direction, and each support structure 58 penetrates multiple bit lines 73 to provide support for all bit lines 73, preventing the collapse of related film layers during the fabrication of bit lines 73 and ensuring the quality of bit lines 73. Along the second direction, at least one support structure 58 is provided between two adjacent contact structures 50 to improve the uniformity of the distribution of support structures 58 and enhance the support effect. The multiple support structures 58 and multiple contact structures 50 can be arranged spaced apart along the second direction. For example, along the third direction, the multiple support structures 58 and multiple contact structures 50 respectively correspond to multiple transistors 80 located in a column along the first direction. Figure 1 As shown, five of the six columns of transistors 80 correspond to a support structure 58, and the other column of transistors 80 corresponds to a contact structure 50.

[0068] Taking a plane perpendicular to the first direction as the cross-section, the cross-sectional shape of the support structure 58 can be rectangular, circular, elliptical, etc. The cross-sectional dimension of the support structure 58 is larger than that of the contact structure 50, so that the support structure 58 is more robust and has a better supporting effect. The material of the support structure 58 can be a low-k dielectric constant material.

[0069] See some possible examples. Figure 3 and Figure 4 At least a portion of the sidewall of the support structure 58 has a plurality of first annular grooves, which are spaced apart along a first direction. The first annular grooves surround the sidewall of the support structure 58, i.e., the outer circumferential surface of the support structure 58 has first annular grooves to accommodate a portion of the position lines 73. For example, the plurality of first annular grooves on a support structure 58 correspond to a plurality of position lines 73, each position line 73 including a first portion 75 filled within the first annular groove and a second portion 76 located outside the first annular groove. Along the first direction, the thickness of the first portion 75 is less than the thickness of the second portion 76.

[0070] In this configuration, along the first direction, the thickness of the first portion 75 is less than the thickness of the second portion 76; that is, the first portion 75 is thinner and the second portion 76 is thicker. This arrangement results in a greater spacing between adjacent first portions 75 than between adjacent second portions 76 along the first direction, thus reducing the parasitic capacitance between the first portions 75.

[0071] In some examples, the second part 76 can completely surround the first part 75, that is, the second part 76 circumferentially surrounds the first part 75, and both the support structure 58 and the contact structure 50 penetrate the second part 76. The outer peripheral surface of the first part 75 contacts the inner peripheral surface of the second part 76, and the inner peripheral surface of the second part 76 covers the outer peripheral surface of the first part 75, so as to increase the contact area between the first part 75 and the second part 76 and reduce the manufacturing difficulty of the bit line 73.

[0072] In some examples, referring to Figure 5 and Figure 6 , the second part 76 can partially surround the first part 75, for example, the second part 76 includes an extension 77 and a connecting part 78, the connecting part 78 connects two first parts 75 adjacent in the second direction, and the extension 77 connects the transistor 80 and the first part 75 or the connecting part 78 opposite to the transistor 80. As shown in Figure 5 , the connecting part 78 connects two first parts 75 adjacent in the second direction, and the contact structure 50 penetrates the connecting part 78. The extension 77 is located between the first part 75 and the transistor 80, or between the connecting part 78 and the transistor 80. In this way, the volume of the support structure 58 can be increased to provide stable support for the bit line 73.

[0073] It can be understood that when the transistor 80 and the support structure 58 are opposite in the third direction, the two ends of the extension 77 are connected to the transistor 80 and the first part 75, respectively. When the transistor 80 and the contact structure 50 are opposite in the third direction, the two ends of the extension 77 are connected to the transistor 80 and the connecting part 78, respectively. In the second direction, the width of the extension 77 can be less than the width of the first part 75.

[0074] In order to improve the storage density of the memory, in some examples, as shown in Figure 1 and Figure 5 , in the third direction, both sides of each bit line 73 are provided with a plurality of transistors 80 and a plurality of capacitors 90, and the plurality of transistors 80 and the plurality of capacitors 90 on the same side are correspondingly electrically connected. Among them, each bit line 73 is provided with a plurality of transistors 80 on both sides in the third direction, and the plurality of transistors 80 on each side are correspondingly connected to one bit line 73 in the second direction. Both sides of the plurality of bit lines 73 in the third direction are respectively provided with one transistor array, and the transistors 80 in the same row in the two transistor arrays are correspondingly connected to one bit line 73, that is, the two transistor arrays share the bit line 73, so as to improve the space utilization rate of the memory and improve the storage density.

[0075] Each transistor 80 is correspondingly electrically connected to one capacitor 90 on the side away from the bit line 73, as shown in Figure 1 , in the third direction, the capacitor 90, the transistor 80, the bit line 73, the transistor 80, and the capacitor 90 are arranged in sequence. The transistor 80, the capacitor 90, and the bit line 73 can be symmetrically distributed in the third direction, so as to improve the structural symmetry and compactness of the memory.

[0076] Continuing to refer to Figure 3 , Figure 4 and Figure 5In some examples, the memory further includes a plurality of word lines spaced along the second direction, for example each extending along the first direction. Each word line corresponds to a plurality of transistors 80 along the first direction and forms a gate 85 of the corresponding transistors 80, each transistor 80 including a gate dielectric layer 82 surrounding the corresponding gate 85, and a channel region 86 surrounding the gate dielectric layer 82, the channel region 86 corresponding to the bit line 73 and the capacitor 90.

[0077] In some examples, each word line surrounds the gate dielectric layer 82, the gate dielectric layer 82 surrounds the channel region 86, and the transistor 80 forms a Channel All Around (CAA) transistor 80 to improve the control ability of the gate 85 on the channel region 86. The same gate dielectric layer 82 surrounds a plurality of channel regions 86, the plurality of channel regions 86 are spaced along the first direction, and each channel region 86 corresponds to the bit line 73 and the capacitor 90 on two sides along the third direction. The material of the channel region 86 can include Indium Gallium Zinc Oxide (IGZO), which has a high carrier mobility to improve the performance of the channel region 86.

[0078] Continuing to refer to Figure 3 and Figure 4 In some examples, the gate dielectric layer 82 includes a body 83 surrounding the gate 85 and in contact with the gate 85, and an epitaxial portion 84 connected to two ends of the body 83 along the first direction, the epitaxial portions 84 of two adjacent gate dielectric layers 82 along the first direction are in contact with each other, and the plurality of gate dielectric layers 82 along the first direction form an integrated structure. In some examples, the body 83 surrounds the gate 85 and is in contact with the gate 85, that is, the body 83 is sleeved on the gate 85. Along the first direction, the opposite ends of the body 83 are respectively connected to one of the epitaxial portions 84, and the body 83 and the corresponding two epitaxial portions 84 form a third annular groove. Along the first direction, the surfaces of the epitaxial portions 84 of the two adjacent gate dielectric layers 82 opposite to each other are in contact with each other, so that the plurality of gate dielectric layers 82 along the first direction form an integrated structure, which is convenient for forming the gate dielectric layer 82.

[0079] On the basis of the above examples, the channel region 86 covers the surfaces of the corresponding epitaxial portions 84 opposite to each other and the outer circumferential surface of the body, and the channel region 86 forms a second annular groove. Along the third direction, the two sides of the channel region 86 are respectively provided with the bit line 73 and the connection layer 74, and the bit line 73 and the connection layer 74 extend into the second annular groove and correspondingly contact the surface of the second annular groove. The transistor 80 also corresponds to the capacitor 90.

[0080] The channel region 86 covers the sidewall and bottom wall of the third annular groove to increase the area of the channel region 86. The channel region 86 in the third annular groove forms a second annular groove. The bottom wall of the third annular groove is the outer circumferential surface of the body, and the sidewall of the third annular groove is the surface of the two extension portions 77 opposite to each other.

[0081] In the third direction, the two sides of the channel region 86 are connected to the bit line 73 and the connection layer 74, respectively, and the bit line 73 and the connection layer 74 are independent of each other. The opposite ends of the bit line 73 and the connection layer 74 extend into the second annular groove and are adapted to the second annular groove. In some examples, the second annular groove is a rectangular annular groove, that is, the cross section of the second annular groove is a rectangular annulus with a plane perpendicular to the first direction. The rectangular annular groove includes four groove segments connected end to end in sequence, and the bit line 73 and the connection layer 74 are located in two groove segments opposite in the third direction, respectively. In the first direction, the bit line 73 and the connection layer 74 fill the corresponding groove segments and extend outside the corresponding groove segments, that is, the bit line 73 and the connection layer 74 are in contact with the bottom wall and the sidewall of the corresponding groove segments to increase the contact area between the bit line 73 and the channel region 86 and between the connection layer 74 and the channel region 86. In the second direction, the length of the bit line 73 and the connection layer 74 is less than the length of the corresponding groove segment.

[0082] Continuing to refer to Figures 1 to 5 The capacitor 90 includes an upper electrode 94, a capacitor dielectric layer 93 surrounding the upper electrode 94, and a lower electrode 92 surrounding the capacitor dielectric layer 93, that is, the capacitor 90 is a columnar capacitor, and the lower electrode 92 is electrically connected to the transistor 80 through the connection layer 74. In order to increase the surface area of the lower electrode 92 to increase the capacitance of the capacitor 90, the inner circumferential surface of the lower electrode 92 is formed with a fourth annular groove. The capacitor dielectric layer 93 covers at least the sidewall and bottom wall of the fourth annular groove, and the capacitor dielectric layer 93 in the fourth annular groove forms a fifth annular groove. The upper electrode 94 covers at least the sidewall and bottom wall of the fifth annular groove.

[0083] In some examples, the plurality of upper electrodes 94 along the first direction are integrated, the plurality of capacitor dielectric layers 93 along the first direction are integrated, and the plurality of lower electrodes 92 along the first direction are spaced apart. In the second direction, a sixth annular groove is formed between two adjacent lower electrodes 92, and the depth of the sixth annular groove can be greater than the depth of the fourth annular groove. The capacitor dielectric layer 93 also covers the sidewall and bottom wall of the sixth annular groove and the inner circumferential surface of the lower electrode 92 to form an integrated body. The upper electrode 94 covers the capacitor dielectric layer 93 to form an integrated body.

[0084] To realize the external connection of the capacitor 90, the memory further comprises a plurality of capacitor plugs 95 which are arranged in the second direction and electrically connected with the upper electrode 94. For example, the upper electrode 94 surrounds the corresponding capacitor plug 95. To facilitate the manufacturing, the material of the capacitor plug 95 can be polysilicon, the materials of the upper electrode 94 and the lower electrode 92 can be metal or its compound, for example, titanium nitride, and the material of the capacitor dielectric layer 93 can be high-k material, for example, hafnium oxide.

[0085] In summary, in the memory of the embodiments of the present disclosure, the plurality of support structures 58 which penetrate the plurality of bit lines 73 are arranged to support the plurality of bit lines 73, so that the adjacent two bit lines 73 are kept apart to avoid the contact caused by the collapse of the bit lines 73, improve the stability of the manufacturing process of the memory, ensure the performance of the memory, and improve the yield of the memory.

[0086] The embodiments of the present disclosure further provide a manufacturing method of a memory, referring to Figures 7 to 35 The manufacturing method comprises the following steps.

[0087] Step S100: forming a stack structure on a substrate, the stack structure comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers which are arranged alternately in sequence along a first direction.

[0088] The substrate 10 provides support for the structures (for example, the contact structure 50, the bit line 73, etc.) on it, and the substrate 10 can comprise a substrate 11, a protection layer 12 and an etching stop layer 13 which are arranged in sequence. Before forming the protection layer 12, the substrate 11 can be cleaned first. The material of the substrate 11 can be a semiconductor material such as monocrystalline silicon, polysilicon, germanium, germanium silicon, silicon on insulator (SOI) or germanium on insulator (GOI). The material of the protection layer 12 can be silicon oxide, and the material of the etching stop layer 13 can be aluminum oxide which is relatively hard and can also be used as a hard mask layer.

[0089] Referring to Figure 8 and Figure 9 The stack structure 20 is formed on the substrate 10 and comprises a plurality of first sacrificial layers 21 and a plurality of second sacrificial layers 22 which are arranged alternately in sequence along a first direction. The first direction can be the Z direction as shown in the figure, the material of the first sacrificial layer 21 can be oxide such as silicon oxide, and the material of the second sacrificial layer 22 can be nitride such as silicon nitride. The first sacrificial layer 21 can be located on the substrate 10. Figure 8

[0090] ​Step S200: forming a plurality of contact structures, a plurality of first intermediate structures and a plurality of second intermediate structures in the stack structure; wherein the plurality of contact structures, the plurality of first intermediate structures and the plurality of second intermediate structures are arranged at intervals along the second direction, and along the third direction, the plurality of second intermediate structures are located on the side of the plurality of first intermediate structures away from the plurality of contact structures, each contact structure corresponds to a layer of the second sacrificial layer, the first intermediate structure and the second intermediate structure penetrate the stack structure, and the first direction, the second direction and the third direction are perpendicular to each other.

[0091] Referring to Figures 8 to 19 , etching to remove part of the stack structure 20 and backfilling to form a plurality of contact structures 50, a plurality of first intermediate structures 54 and a plurality of second intermediate structures 56. The contact structure 50 is used to connect the bit line 73, the first intermediate structure 54 is used to form the transistor 80, and the second intermediate structure 56 is used to form the capacitor 90.

[0092] Wherein the plurality of contact structures 50 are arranged at intervals along the second direction, the plurality of first intermediate structures 54 are arranged at intervals along the second direction, and the plurality of second intermediate structures 56 are arranged at intervals along the second direction, that is, the plurality of contact structures 50 form a row along the second direction, the plurality of first intermediate structures 54 form a row along the second direction, and the plurality of second intermediate structures 56 form a row along the second direction. And along the third direction, the plurality of second intermediate structures 56 are located on the side of the plurality of first intermediate structures 54 away from the plurality of contact structures 50, that is, along the third direction, the contact structure 50, the first intermediate structure 54 and the second intermediate structure 56 are arranged in sequence. The first direction, the second direction and the third direction are perpendicular to each other, for example. As shown in Figure 8 , the first direction is the Z direction as shown in Figure 8 , the second direction is the Y direction as shown in Figure 8 , and the third direction is the X direction as shown in

[0093] In some possible examples, the plurality of first intermediate structures 54 and the plurality of second intermediate structures 56 can be symmetrically arranged relative to the plurality of contact structures 50 to improve the compactness of the memory and increase the storage capacity. As shown in Figure 18 , the contact structure 50 forms a first intermediate structure 54 on each of the two opposite sides along the third direction, and a second intermediate structure 56 is formed on the side of the first intermediate structure 54 away from the contact structure 50. Along the third direction, the second intermediate structure 56, the first intermediate structure 54, the contact structure 50, the first intermediate structure 54 and the second intermediate structure 56 are arranged in sequence.

[0094] Step S300: forming at least one support structure between two contact structures adjacent along the second direction, the support structure penetrating at least the stack structure.

[0095] Referring to Figures 20 to 22The support structure 58 penetrates the stack structure 20, and can support the first sacrificial layer 21 arranged at intervals when the second sacrificial layer 22 is removed subsequently, so as to avoid the adjacent first sacrificial layer 21 from collapsing or even contacting, thereby ensuring the space for filling the bit line 73. In the second direction, at least one support structure 58 is arranged between two adjacent contact structures 50, so as to improve the uniformity of the distribution of the support structure 58 and improve the support effect. The plurality of support structures 58 and the plurality of contact structures 50 can be arranged at intervals in the second direction, and the plurality of support structures 58 and the plurality of contact structures 50 correspond to the plurality of first intermediate structures 54, respectively.

[0096] In the plane perpendicular to the first direction, the cross-sectional shape of the support structure 58 can be rectangular, circular, elliptical, etc. The cross-sectional size of the support structure 58 is greater than the cross-sectional size of the contact structure 50, so that the support structure 58 is relatively thick and has a better support effect. The material of the support structure 58 can be a low dielectric constant material.

[0097] In step S400, part of the stack structure between the two adjacent first intermediate structures and the two adjacent second intermediate structures in the second direction is removed, so as to form a first isolation groove penetrating the stack structure and arranged alternately with the first intermediate structure. In the third direction, the end of the first isolation groove facing the support structure protrudes from the end of the first intermediate structure facing the support structure, and the end of the first isolation groove away from the support structure penetrates the stack structure.

[0098] Referring to Figures 23 to 25 FIG. 1, the first isolation groove 61 is used to isolate the two adjacent first intermediate structures 54 in the second direction and the two adjacent second intermediate structures 56 in the second direction. In the third direction, the end of the first isolation groove 61 away from the support structure 58 extends to the end of the stack structure 20 away from the support structure 58, so as to form an opening. The distance between the end of the first isolation groove 61 facing the support structure 58 and the support structure 58 is less than the distance between the end of the first intermediate structure 54 facing the support structure 58 and the support structure 58.

[0099] In the following Figure 23 and Figure 24 , a forming process of the first isolation groove 61 is described.

[0100] Referring to Figure 23 , the fourth sacrificial layer 25, the tenth mask layer 45, the eleventh mask layer 46 and the fifth photoresist layer 47 are sequentially deposited on the stack structure 20, and the fifth photoresist layer 47 has a fifth mask pattern. The material of the fourth sacrificial layer 25 can be silicon oxide, which is formed by at least two times of deposition. The tenth mask layer 45 is a hard mask layer, and the material thereof can be amorphous carbon (ACL). The eleventh mask layer 46 is a conventional mask layer, and the material thereof can be silicon oxynitride.

[0101] Referring to Figure 24 The fifth photoresist layer 47 is used as a mask to etch the layers below it until the substrate 10, so as to form a plurality of first isolation grooves 61.

[0102] The layers above the fourth sacrificial layer 25 are removed to expose the fourth sacrificial layer 25. In the process of forming the first isolation grooves 61, the fifth photoresist layer 47 is removed at least partially. After the first isolation grooves 61 are formed, all the layers above the fourth sacrificial layer 25 are removed. The fourth sacrificial layer 25 covers at least the support structures 58 and the second intermediate structures 56, which can be protected and used as a mask.

[0103] It can be understood that in the example in which the third sacrificial layer 24 is provided on the stack structure 20, the fourth sacrificial layer 25, the tenth mask layer 45, the eleventh mask layer 46 and the fifth photoresist layer 47 are sequentially deposited on the third sacrificial layer 24. Among them, the third sacrificial layer 24 covers the contact structures 50 and the first intermediate structures 54, and the fourth sacrificial layer 25 covers the third sacrificial layer 24, the support structures 58 and the second intermediate structures 56. The subsequent process is the same as the process of forming directly on the stack structure 20 described above, and will not be described here.

[0104] Step S500: removing the remaining second sacrificial layer to form a first filling space.

[0105] Referring to Figure 25 and Figure 26 The exposed second sacrificial layer 22 is etched and removed using the first isolation grooves 61 to remove all the second sacrificial layer 22, so as to form a first filling space 62, which is in communication with the first isolation grooves 61.

[0106] Step S600: forming a first conductive layer in the first filling space, the first conductive layer located between the support structures, between the support structures and the contact structures, and between the support structures or the contact structures and the first intermediate structures forms a bit line, and the first conductive layer located between the first intermediate structures and the second intermediate structures forms a connection layer.

[0107] Referring to Figure 26 and Figure 27 A first conductive layer 70 is formed in the first filling space 62 to form a bit line 73 and a connection layer 74. Among them, the bit line 73 is located between adjacent support structures 58, between the support structures 58 and the contact structures 50, and between the support structures 58 or the contact structures 50 and the first intermediate structures 54. The two ends of the connection layer 74 are connected between the first intermediate structures 54 and the second intermediate structures 56, respectively.

[0108] It can be understood that, along the third direction, one part of the first intermediate structure 54 is opposite to the support structure 58, and the other part of the first intermediate structure 54 is opposite to the contact structure 50. The bit line 73 is connected between the support structure 58 and the opposite first intermediate structure 54, and the bit line 73 is also connected between the first intermediate structure 54 opposite to the contact structure 50, so as to ensure that each first intermediate structure 54 is connected with the bit line 73. The first conductive layer 70 is also formed on the side of the second intermediate structure 56 away from the first intermediate structure 54, and this part of the first conductive layer 70 is only used to fill between adjacent first sacrificial layers 21 and does not perform signal transmission.

[0109] In some possible implementation manners, the first conductive layer 70 formed in the first filling space 62 includes: depositing a first conductive sub-layer 71 on the side wall and bottom wall of the first isolation groove 61 and the inner wall of the first filling space 62, and depositing a second conductive sub-layer 72 on the first conductive sub-layer 71, the second conductive sub-layer 72 filling the remaining first filling space 62; and removing the first conductive sub-layer 71 and the second conductive sub-layer 72 in the first isolation groove 61, so that the remaining first conductive sub-layer 71 and the second conductive sub-layer 72 form the first conductive layer 70.

[0110] In some possible implementation manners, the material of the first conductive sub-layer 71 can be titanium nitride, and the material of the second conductive sub-layer 72 can be tungsten. When the first conductive sub-layer 71 and the second conductive sub-layer 72 in the first isolation groove 61 are removed, the first conductive sub-layer 71 and the second conductive sub-layer 72 in the first filling space 62 are removed at both ends along the second direction, and at this time, the partial area of the first isolation groove 61 is expanded to between adjacent first sacrificial layers 21.

[0111] Step S700: forming a first isolation layer in the first isolation groove, the first isolation layer filling the first isolation groove.

[0112] Referring to Figure 28 , the first isolation layer 63 can be a NON structure to improve the isolation effect. In some possible implementation manners, the first isolation layer 63 can be formed by the following process: depositing a first isolation sub-layer 64 in the first isolation groove 61, the first isolation sub-layer 64 covering the side wall and bottom wall of the first isolation layer 63; and depositing a second isolation sub-layer 65 in the remaining first isolation groove 61, the second isolation sub-layer 65 filling the first isolation groove 61, the first isolation sub-layer 64 and the second isolation sub-layer 65 forming the first isolation layer 63. The material of the first isolation sub-layer 64 is silicon nitride, and the material of the second isolation sub-layer 65 is silicon oxide.

[0113] In some examples, the first isolation layer 64 also covers the fourth sacrificial layer 25, and after forming the second isolation layer 65, the first isolation layer 64 and the second isolation layer 65 on the fourth sacrificial layer 25 are removed, and then the fifth sacrificial layer 26 is formed. The material of the fifth sacrificial layer 26 is the same as that of the second isolation layer 65, so that the fifth sacrificial layer 26 and the second isolation layer 65 can be removed together later. The material of the fifth sacrificial layer 26 and the material of the second isolation layer 65 are also the same as that of the seventh mask layer 41, so that the removal later is facilitated.

[0114] Step S800: removing the first intermediate structure to form a plurality of transistors spaced along the first direction, removing the second intermediate structure to form a plurality of capacitors spaced along the second direction, and removing the remaining first sacrificial layer to form a second isolation layer, each transistor being connected to one capacitor through the connection layer along the third direction.

[0115] Referring to Figures 29 to 35 Each transistor 80 includes a gate 85, a gate dielectric layer 82 surrounding the corresponding gate 85, and a channel region 86 surrounding the gate dielectric layer 82, i.e., the transistor 80 is a channel-all-surrounding transistor 80, so as to improve the control ability of the gate 85 on the channel region 86. The gates 85 of the transistors 80 along the first direction are integrated to serve as word lines. The material of the channel region 86 can include indium gallium zinc oxide, which has a high carrier mobility and improves the performance of the channel region 86.

[0116] Each capacitor 90 includes an upper electrode 94, a capacitor dielectric layer 93 surrounding the upper electrode 94, and a lower electrode 92 surrounding the capacitor dielectric layer 93, i.e., the capacitor 90 is a columnar capacitor, and the lower electrode 92 is electrically connected to the channel region 86 of the transistor 80 through the connection layer 74. The plurality of upper electrodes 94 along the first direction are integrated, and the plurality of capacitor dielectric layers 93 along the first direction are integrated.

[0117] In some possible implementations, as Figures 29 to 35 shown, the first intermediate structure 54 is removed to form a plurality of transistors 80 spaced along the first direction, the second intermediate structure 56 is removed to form a plurality of capacitors 90 spaced along the second direction, and the remaining first sacrificial layer 21 is removed to form a second isolation layer 68 (step S800), which includes:

[0118] Step S801: forming a first etching hole 66 in each first intermediate structure 54 by using a patterning process, and removing the remaining first intermediate structure 54 by using a first etching. The first etching hole 66 at least penetrates the corresponding first intermediate structure 54, and in the example in which the substrate 10 includes the substrate 11, the protection layer 12, and the etching stop layer 13, the first etching hole 66 also penetrates the etching stop layer 13 to expose the protection layer 12.

[0119] Step S802: forming a channel layer 81, a gate dielectric layer 82 and a gate electrode 85, the channel layer 81 covers the sidewall and the bottom wall of the first etching hole 66, the gate dielectric layer 82 covers the channel layer 81, and the gate electrode 85 covers the initial gate dielectric layer 82 and fills the remaining first etching hole 66. The channel layer 81, the gate dielectric layer 82 and the gate electrode 85 can be formed by deposition and etching back. The channel layer 81 conformally covers the sidewall and the bottom wall of the first etching hole 66, the gate dielectric layer 82 conformally covers the channel layer 81, and in the example where the fourth sacrificial layer 25 is provided in the stack structure 20, the channel layer 81 also covers the top surface of the fourth sacrificial layer 25.

[0120] Step S803: forming a second isolation groove in each first isolation layer 63 by using a patterning process, the second isolation groove is located in the first isolation groove 61, and the second isolation groove exposes the first sacrificial layer 21. In the example where the first isolation layer 63 includes the first isolation sublayer 64 and the second isolation sublayer 65, etching part of the second isolation sublayer 65 to form an initial second isolation groove, the initial second isolation groove exposes the first isolation sublayer 64 and the remaining second isolation sublayer 65, and etching the first isolation sublayer 64 exposed in the initial second isolation groove to form the second isolation groove. The remaining second isolation sublayer 65 and the remaining first isolation sublayer 64 are located between adjacent first sacrificial layers 21.

[0121] Step S804: etching and removing the remaining first sacrificial layer 21 by using the second isolation groove to form a second filling space 67, and etching and removing the channel layer 81 exposed in the second filling space 67, and the remaining channel layer 81 forms a plurality of channel regions 86 arranged at intervals along the first direction. The second filling space 67 is in communication with the second isolation groove.

[0122] Step S805: forming a second isolation layer 68 in the second filling space 67 and the second isolation groove, and the second isolation layer 68 fills the second filling space 67 and the second isolation groove. The second isolation layer 68 can be formed by deposition and etching back. Part of the second isolation layer 68 is used to isolate adjacent first conductive layers 70, and another part of the second isolation layer 68 and the first isolation layer 63 are used to isolate two transistors 80 adjacent along the second direction or two capacitors 90 formed subsequently and adjacent along the second direction.

[0123] Step S806: forming a second etching hole 69 in each second intermediate structure 56 by using a patterning process, and etching and removing the remaining second intermediate structure 56 by using a second etching process. The second etching hole 69 at least penetrates the corresponding second intermediate structure 56, and in the example where the substrate 10 includes the substrate 11, the protective layer 12 and the etching stop layer 13, the second etching hole 69 also penetrates the etching stop layer 13 to expose the protective layer 12.

[0124] Step S807: Forming the lower electrode layer 91 on the sidewall and bottom wall of the second etching hole 69, and removing the part of the lower electrode layer 91 which is in contact with the inner circumferential surface of the second isolation layer 68, and the remaining lower electrode layer 91 forms a plurality of lower electrodes 92 which are arranged in the first direction. As shown in Figure 34 the second etching hole 69 is in a wave shape, and the protruding part of the lower electrode layer 91 is protected by the sixth sacrifice layer 27, so that the lower electrode layer 91 is broken in the first direction to form the lower electrode 92.

[0125] Step S808: Forming the capacitor dielectric layer 93 on the sidewall and bottom wall of the second etching hole 69 in which the lower electrode 92 is formed, forming the upper electrode 94 on the capacitor dielectric layer 93, and forming the capacitor plug 95 on the upper electrode 94, and the capacitor plug 95 fills the second etching hole 69.

[0126] In summary, the manufacturing method of the memory in the embodiments of the present disclosure includes: forming a stack structure 20 on a substrate 10, the stack structure 20 including a plurality of first sacrificial layers 21 and a plurality of second sacrificial layers 22 arranged alternately along a first direction, and the first sacrificial layers 21 located on the substrate 10; forming a plurality of contact structures 50, a plurality of first intermediate structures 54 and a plurality of second intermediate structures 56 in the stack structure 20; wherein the plurality of contact structures 50, the plurality of first intermediate structures 54 and the plurality of second intermediate structures 56 are arranged at intervals along a second direction, and along a third direction, the plurality of second intermediate structures 56 are located on a side of the plurality of first intermediate structures 54 away from the plurality of contact structures 50, each contact structure 50 corresponds to a second sacrificial layer 22, the first intermediate structure 54 and the second intermediate structure 56 penetrate the stack structure 20, and the first direction, the second direction and the third direction intersect with each other; forming at least one support structure 58 between two adjacent contact structures 50 along the second direction, and the support structure 58 penetrates at least the stack structure 20; removing part of the stack structure 20 between two adjacent first intermediate structures 54 and two adjacent second intermediate structures 56 along the second direction, to form a first isolation groove 61 penetrating the stack structure 20 and arranged alternately with the first intermediate structure 54; removing the remaining second sacrificial layer 22 to form a first filling space 62, and forming a first conductive layer 70 in the first filling space 62, the first conductive layer 70 located between the support structures 58, between the support structure 58 and the contact structure 50, and between the support structure 58 or the contact structure 50 and the first intermediate structure 54 forms a bit line 73, and the first conductive layer 70 located between the first intermediate structure 54 and the second intermediate structure 56 forms a connection layer 74; forming a first isolation layer 63 in the first isolation groove 61, and the first isolation layer 63 fills the first isolation groove 61; removing the first intermediate structure 54 to form a plurality of transistors 80 arranged at intervals along the first direction, removing the second intermediate structure 56 to form a plurality of capacitors 90 arranged at intervals along the second direction, and removing the remaining first sacrificial layer 21 to form a second isolation layer 68, and along the third direction, each transistor 80 is connected to one capacitor 90 through the connection layer 74. By using the plurality of support structures 58, the adjacent first sacrificial layers 21 are supported, so that the two adjacent first sacrificial layers 21 are kept at intervals, thereby keeping the space for forming the bit line 73, after the bit line 73 is formed, the bit line 73 is prevented from being contacted due to collapse, the stability of the manufacturing process of the memory is improved, the performance of the memory is ensured, and the yield of the memory is improved. In addition, the first isolation layer 63 and the second isolation layer 68 can ensure the insulation between the adjacent bit lines 73 along the first direction, and the insulation between the two transistors 80 along the second direction and the two capacitors 90 along the second direction, thereby ensuring the performance of the memory.

[0127] In some possible examples, reference is made to Figures 8 to 19In the stack structure 20, a plurality of contact structures 50, a plurality of first intermediate structures 54 and a plurality of second intermediate structures 56 are formed (step S200), including:

[0128] Step S201: etching the stack structure 20 to form a plurality of second filling holes 23 arranged along the second direction, each of the second filling holes 23 corresponding to expose one of the second sacrificial layers 22.

[0129] Referring to Figure 10 and Figure 11 The depths of the plurality of second filling holes 23 can be different, so that at least one of the second sacrificial layers 22 is exposed in at least one of the second filling holes 23, i.e., each of the second sacrificial layers 22 is exposed in at least one of the second filling holes 23. For example, the depths of the plurality of second filling holes 23 are different, and the plurality of second filling holes 23 correspond to the plurality of second sacrificial layers 22 one by one. Each of the second sacrificial layers 22 is exposed in one of the second filling holes 23, and each of the second filling holes 23 corresponds to expose one of the second sacrificial layers 22.

[0130] Referring to Figure 10 and Figure 11 In some possible implementations, the plurality of second filling holes 23 can be formed by the following steps:

[0131] Step S2011: sequentially forming a first mask layer 31, a second mask layer 32 and a first photoresist layer 33 on the stack structure 20, the first photoresist layer 33 having a first mask pattern.

[0132] The first mask layer 31 covers the stack structure 20, the second mask layer 32 covers the first mask layer 31, and the first photoresist layer 33 covers the second mask layer 32. The first mask layer 31 is a hard mask layer, and the material thereof can be silicon nitride. The second mask layer 32 is a conventional mask layer, and the material thereof can be silicon oxynitride. The thickness of the first mask layer 31 can be greater than the thickness of the second mask layer 32.

[0133] Step S2012: etching the second mask layer 32, the first mask layer 31 and the stack structure 20 with the first photoresist layer 33 as a mask, to form the plurality of second filling holes 23 in the stack structure 20.

[0134] For example, the depths of the plurality of second filling holes 23 are different, so that each of the second sacrificial layers 22 can be exposed in one of the second filling holes 23, thereby realizing that each of the second sacrificial layers 22 can be in contact with the contact structure 50 formed subsequently, so as to ensure that each of the bit lines 73 formed after the replacement of each of the second sacrificial layers 22 can be circumscribed by the corresponding contact structure 50.

[0135] Step S2013: removing the film layers on the stack structure 20 to expose the stack structure 20.

[0136] In some examples, the film layers on the stack structure 20 include the first mask layer 31, the second mask layer 32 and the first photoresist layer 33, and the first mask layer 31, the second mask layer 32 and the first photoresist layer 33 are removed to expose the stack structure 20. In other examples, the first photoresist layer 33 is etched and removed at the same time when the plurality of second filling holes 23 are formed, and the film layers on the stack structure 20 include the first mask layer 31 and the second mask layer 32, and the first mask layer 31 and the second mask layer 32 are removed to expose the stack structure 20. In yet other examples, the first photoresist layer 33 and the second mask layer 32 are etched and removed at the same time when the plurality of second filling holes 23 are formed, and the film layers on the stack structure 20 include the first mask layer 31, and the first mask layer 31 is removed to expose the stack structure 20.

[0137] Step S202: forming a contact structure 50 in the second filling hole 23, the contact structure 50 filling the corresponding second filling hole 23.

[0138] Referring to Figure 12 The contact structure 50 includes an insulating layer 51 and a conductive column 52, and the insulating layer 51 is filled between the conductive column 52 and the second filling hole 23. The material of the insulating layer 51 can be silicon oxide or a low dielectric constant material, such as hafnium oxide, etc. The material of the conductive column 52 can be metal, such as tungsten.

[0139] The insulating layer 51 is provided to avoid the contact between the conductive column 52 and other second sacrificial layers 22, so as to isolate the conductive column 52 and the second sacrificial layer 22 forming the sidewall of the second filling hole 23 from each other, so that each conductive column 52 only corresponds to the second sacrificial layer 22 at the bottom of the second filling hole 23, to ensure the correspondence between the contact structure 50 and the subsequently formed bit line 73, and to avoid the electrical connection between one contact structure 50 and multiple bit lines 73.

[0140] Referring to Figure 12 In some possible implementations, the insulating layer 51 is deposited on the sidewall and the bottom wall of the second filling hole 23 and on the stack structure 20, and the insulating layer 51 located in the second filling hole 23 encloses a third filling hole. The insulating layer 51 is etched back to remove the insulating layer 51 on the stack structure 20 and the bottom wall of the second filling hole 23, and the insulating layer 51 located on the sidewall of the second filling hole 23 is retained to expose the corresponding second sacrificial layer 22. A second conductive layer is deposited in the third filling hole and on the stack structure 20, and the second conductive layer fills the third filling hole. The second conductive layer on the stack structure 20 is etched and removed, and the remaining second conductive layer forms a plurality of spaced conductive columns 52.

[0141] In some possible examples, before forming the contact structure 50 within the second filling hole 23 (step S202), the method of fabricating the memory may further include etching the first sacrificial layer 21 exposed within the second filling hole 23 to enlarge the second filling hole 23. This configuration results in a wavy sidewall of the second filling hole 23, increasing its space. The contact structure 50 fills the enlarged second filling hole 23, increasing the contact area between the contact structure 50 and the corresponding second sacrificial layer 22, and reducing contact resistance.

[0142] Step S203: Etch the stacked structure 20 to form a plurality of first intermediate holes 53 on both sides of the contact structure 50 along the third direction. The plurality of first intermediate holes 53 on each side are spaced apart along the second direction, and each first intermediate hole 53 exposes the substrate 10.

[0143] See Figure 13 and Figure 14 The etched stacked structure 20 forms a plurality of first intermediate holes 53 on the first side of the contact structure 50 and a plurality of first intermediate holes 53 on the second side of the contact structure 50. The first side of the contact structure 50 ( Figure 13 (shown on the left) and the second side ( Figure 13 (As shown on the right) are opposite along a third direction. A plurality of first intermediate holes 53 on the first side of the contact structure 50 are symmetrical to a plurality of first intermediate holes 53 on the second side of the contact structure 50. The plurality of first intermediate holes 53 on each side of the contact structure 50 are spaced apart along a second direction, and each first intermediate hole 53 penetrates the laminated structure 20 to expose the substrate 10.

[0144] See Figure 13 and Figure 14 In some possible implementations, multiple first intermediate holes 53 can be formed by the following process:

[0145] A third mask layer 34, a fourth mask layer 35, and a second photoresist layer 36 are sequentially formed on the stacked structure 20 and the contact structure 50. The second photoresist layer 36 has a second mask pattern. The third mask layer 34 covers the stacked structure 20 and the contact structure 50, the fourth mask layer 35 covers the third mask layer 34, and the second photoresist layer 36 covers the fourth mask layer 35. The third mask layer 34 is a hard mask layer, and its material can be silicon nitride. The fourth mask layer 35 is a conventional mask layer, and its material can be silicon oxynitride. The thickness of the third mask layer 34 can be greater than the thickness of the fourth mask layer 35.

[0146] Using the second photoresist layer 36 as a mask, the fourth mask layer 35, the third mask layer 34, and the stacked structure 20 are etched to form a plurality of first intermediate holes 53 in the stacked structure 20. The plurality of first intermediate holes 53 penetrate the stacked structure 20 and expose the substrate 10.

[0147] The film layer on the stack structure 20 and the contact structure 50 is removed to expose the stack structure 20 and the contact structure 50.

[0148] In some possible examples, before the first intermediate structure 54 is formed (step S204), the method further includes etching the first sacrificial layer 21 exposed in the first intermediate hole 53 to expand the first intermediate hole 53. In this way, the sidewall of the expanded first intermediate hole 53 is formed in a wavy shape to increase the contact area between the subsequently formed transistor 80 and the bit line 73, and reduce the contact resistance.

[0149] Step S204: Forming the first intermediate structure 54 in the first intermediate hole 53, the first intermediate structure 54 filling the first intermediate hole 53.

[0150] Referring to Figure 15 , the first intermediate structure 54 fills the first intermediate hole 53, i.e., the top surface of the first intermediate structure 54 is flush with the top surface of the stack structure 20. The material of the first intermediate structure 54 can be the same as the material of the substrate 10 exposed in the first intermediate hole 53, so as to facilitate the subsequent removal of part of the substrate 10 and reduce the connection between the subsequently formed transistor 80 and the substrate 10.

[0151] In some possible implementations, forming the first intermediate structure 54 in the first intermediate hole 53 includes: depositing a first intermediate layer in the first intermediate hole 53, on the stack structure 20, and on the contact structure 50, the first intermediate layer filling the first intermediate hole 53; etching back the first intermediate layer to remove the first intermediate layer on the stack structure 20 and the contact structure 50, expose the stack structure 20 and the contact structure 50, and the remaining first intermediate layer forms a plurality of first intermediate structures 54 independent of each other.

[0152] Step S205: etching the stack structure 20 to form a plurality of second intermediate holes 55 on the side of the plurality of first intermediate structures 54 away from the plurality of contact structures 50, respectively, the plurality of second intermediate holes 55 on each side are arranged at intervals along a second direction, and along a third direction, each second intermediate hole 55 is opposite to the first intermediate structure 54.

[0153] In the following Figure 16 and Figure 17 , a forming process of the plurality of second intermediate holes 55 is described.

[0154] First, a third sacrificial layer 24, a fifth mask layer 37, a sixth mask layer 38 and a third photoresist layer 39 are sequentially formed on the stack structure 20 and the contact structure 50, the third photoresist layer 39 having a third mask pattern. The third sacrificial layer 24 covers the stack structure 20 and the contact structure 50, the fifth mask layer 37 covers the third sacrificial layer 24, the sixth mask layer 38 covers the fifth mask layer 37, and the third photoresist layer 39 covers the sixth mask layer 38. The third sacrificial layer 24 is made of silicon, the fifth mask layer 37 is a hard mask layer and can be made of silicon nitride, and the sixth mask layer 38 is a conventional mask layer and can be made of silicon oxynitride.

[0155] Then, the sixth mask layer 38, the fifth mask layer 37, the third sacrificial layer 24 and the stack structure 20 are etched with the third photoresist layer 39 as a mask to form a plurality of second intermediate holes 55 in the stack structure 20. The plurality of second intermediate holes 55 all penetrate the sixth mask layer 38, the fifth mask layer 37, the third sacrificial layer 24 and the stack structure 20 and expose the substrate 10.

[0156] Then, the film layer on the third sacrificial layer 24 is removed to expose the third sacrificial layer 24.

[0157] In some possible examples, before the second intermediate structure 56 is formed (step S206), the method further includes etching the second sacrificial layer 22 exposed in the second intermediate hole 55 to expand the second intermediate hole 55. In this way, the sidewall of the expanded second intermediate hole 55 is formed in a wavy shape to increase the surface area of the lower electrode 92 of the capacitor 90 formed subsequently and increase the capacity of the capacitor 90.

[0158] Step S206: forming a second intermediate structure 56 in the second intermediate hole 55, the second intermediate structure 56 filling the second intermediate hole 55

[0159] Referring to Figure 18 The second intermediate structure 56 fills the second intermediate hole 55, and the top surface of the second intermediate structure 56 can be flush with the top surface of the stack structure 20. The second intermediate structure 56 can be made of the same material as the first intermediate structure 54. In some possible implementations, forming the second intermediate structure 56 in the second intermediate hole 55 includes depositing a second intermediate layer in the second intermediate hole 55 and on the third sacrificial layer 24, the second intermediate layer filling the second intermediate hole 55; etching back the second intermediate layer to remove the second intermediate layer on the third sacrificial layer 24 to expose the third sacrificial layer 24, and the remaining second intermediate layer forms a plurality of second intermediate structures 56 independent of each other.

[0160] The following will be described in combination with Figures 19 to 22A forming process of the support structure 58 is described. In some possible exemplary embodiments, at least one support structure 58 is formed between two contact structures 50 adjacent in the second direction (step S300), including the following steps:

[0161] Step S301: etching the stack structure 20 to form a plurality of first filling holes 57 penetrating the stack structure 20, the plurality of first filling holes 57 being spaced apart in the second direction and having at least one first filling hole 57 between two adjacent contact structures 50.

[0162] Referring to Figure 18 , for example, the seventh mask layer 41, the eighth mask layer 42, the ninth mask layer 43 and the fourth photoresist layer 44 are deposited, and the fourth photoresist layer 44 has a fourth mask pattern. The fourth photoresist layer is used as a mask to etch the film layers below the fourth photoresist layer until the substrate 10 is exposed to form a plurality of first filling holes 57. The film layers above the seventh mask layer 41 are removed to expose the seventh mask layer 41.

[0163] The seventh mask layer 41 covers the film layers below it, such as the stack structure 20. In the example in which the stack structure 20 is provided with the third sacrificial layer 24, the seventh mask layer 41 covers the third sacrificial layer 24 and the second intermediate layer, the eighth mask layer 42 covers the seventh mask layer 41, the ninth mask layer 43 covers the eighth mask layer 42, and the fourth photoresist layer 44 covers the ninth mask layer 43. The material of the seventh mask layer 41 includes polysilicon, the eighth mask layer 42 is a hard mask layer, and the material thereof can be silicon nitride. The ninth mask layer 43 is a conventional mask layer, and the material thereof can be silicon oxynitride.

[0164] The plurality of first filling holes 57 are opposite the contact structures 50 in the second direction. The plurality of first filling holes 57 each penetrate the ninth mask layer 43, the eighth mask layer 42, the seventh mask layer 41 and the stack structure 20, and expose the substrate 10. In the example in which the stack structure 20 is provided with the third sacrificial layer 24, the plurality of first filling holes 57 each also penetrate the third sacrificial layer 24.

[0165] Step S302: etching the first sacrificial layer 21 exposed in the first filling hole 57 to enlarge the first filling hole 57.

[0166] As Figure 20 shown, the first sacrificial layer 21 is etched along the first filling hole 57 to enlarge the first filling hole 57. In the enlarged first filling hole 57, the second sacrificial layer 22 protrudes from the first sacrificial layer 21, and the protruding second sacrificial layer 22 is annular.

[0167] Step S303: Thin the second sacrificial layer 22 exposed in the enlarged first filling hole 57 along the first direction to further enlarge the first filling hole 57 and increase the distance between adjacent portions of the second sacrificial layer 22 exposed in the enlarged first filling hole 57.

[0168] like Figure 21 As shown, the surface of the second sacrificial layer 22 exposed within the enlarged support hole is etched to thin the second sacrificial layer 22. A wet etching process is used to etch the protruding second sacrificial layer 22. Since the contact area between the two opposing surfaces of the exposed second sacrificial layer 22 along the first direction and the etching solution is relatively large, the thickness removed is relatively large. Conversely, the contact area between the inner circumferential surface of the exposed second sacrificial layer 22 and the etching solution is relatively small, and the thickness removed is negligible. This thins the second sacrificial layer 22 along the first direction, increasing the distance between adjacent second sacrificial layers 22 exposed within the first filling hole 57. When the second sacrificial layer 22 is subsequently replaced with bit lines 73, the spacing between the bit lines 73 extending into the support structure 58 can be increased to reduce the parasitic capacitance between adjacent bit lines 73 and improve memory performance.

[0169] Step S304: Deposit support structure 58, which fills the further enlarged first filling hole 57.

[0170] See Figure 22 The support structure 58 can be formed by deposition and etch-back. For example, a support layer is deposited in the enlarged first filling hole 57 and on the seventh mask layer 41, the support layer filling the enlarged first filling hole 57. The seventh mask layer 41 and the support layer on the seventh mask layer 41 are removed, and the remaining support layer forms a plurality of spaced support structures 58.

[0171] The support layer can be made of a low dielectric constant material to facilitate the subsequent removal of the first sacrificial layer 21, which is in contact with the support layer. In an example where a third sacrificial layer 24 is provided on the laminated structure 20, the top surface of the support structure 58, the top surface of the third sacrificial layer 24, and the top surface of the second intermediate structure 56 are flush.

[0172] The embodiments or examples in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between embodiments can be mutually referred to. The description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than limit it. Although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory, comprising: The memory comprises: a plurality of bit lines, which are arranged at intervals along a first direction; a plurality of transistors, which are arranged at intervals along the first direction and a second direction, and a plurality of the transistors along the first direction correspond to electrically connecting one bit line; a capacitor corresponding to each transistor, which is arranged along a third direction, and the capacitor and the bit line are located on both sides of the transistor, and the first direction, the second direction and the third direction intersect with each other; a plurality of contact structures, which are arranged at intervals along the second direction and penetrate part of the bit lines, and each contact structure corresponds to connecting one bit line; a plurality of support structures, which are arranged at intervals along the second direction and penetrate the plurality of bit lines, and there are at least one support structure between two adjacent contact structures.

2. The memory of claim 1, wherein, The sidewall of at least part of the support structure is formed with a plurality of first annular grooves arranged at intervals along the first direction; Each bit line comprises a first part filled in the first annular groove and a second part located outside the first annular groove, and along the first direction, the thickness of the first part is less than that of the second part.

3. The memory of claim 2, wherein, The second part comprises an extension and a connecting part, the connecting part connects two first parts adjacent along the second direction, and the extension connects the transistor and the first part or the connecting part opposite to the transistor.

4. The memory of any of claims 1-3, wherein, The sidewall of part of the contact structure opposite to the bit line is recessed to the sidewall of the remaining contact structure, so that the sidewall of the contact structure is wavy.

5. The memory of any of claims 1-3, wherein, The memory further comprises a plurality of word lines arranged at intervals along the second direction, each word line corresponds to a plurality of transistors along the first direction, and forms a gate electrode of the corresponding transistor; Each transistor comprises a gate dielectric layer surrounding the corresponding gate electrode, and a channel region surrounding the gate dielectric layer, and the channel region corresponds to the bit line and the capacitor.

6. The memory of claim 5, wherein, The gate dielectric layer comprises a body surrounding the gate electrode, and an epitaxial part connected at both ends of the body along the first direction, the epitaxial parts adjacent to each other of two gate dielectric layers along the first direction are in contact with each other, and a plurality of gate dielectric layers along the first direction form an integral.

7. The memory of claim 6, wherein, The channel region covers the surfaces opposite to each other of the corresponding epitaxial parts, and the outer circumferential surface of the body, and the channel region encloses a second annular groove, and along the third direction, the two sides of the channel region are respectively provided with the bit line and a connecting layer, and the bit line and the connecting layer extend into the second annular groove and correspondingly contact the surface of the second annular groove, and the connecting layer also corresponds to the capacitor.

8. A method of fabricating a memory, comprising: The method comprises: forming a stack structure on a substrate, the stack structure comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately along a first direction; forming a plurality of contact structures, a plurality of first intermediate structures and a plurality of second intermediate structures in the stack structure; wherein the plurality of contact structures, the plurality of first intermediate structures and the plurality of second intermediate structures are arranged in a second direction, and in a third direction, the plurality of second intermediate structures are located on a side of the plurality of first intermediate structures away from the plurality of contact structures, each of the contact structures corresponds to a contact with one of the second sacrificial layers, and the first intermediate structures and the second intermediate structures penetrate the stack structure, the first direction, the second direction and the third direction intersect with each other; forming at least one support structure between two adjacent contact structures in the second direction, the support structure penetrating the stack structure; removing part of the stack structure between two adjacent first intermediate structures and two adjacent second intermediate structures in the second direction to form first isolation grooves penetrating the stack structure and arranged alternately with the first intermediate structures, in the third direction, one end of the first isolation grooves towards the support structure protrudes from one end of the first intermediate structures towards the support structure, and the other end of the first isolation grooves away from the support structure penetrates the stack structure; removing the remaining second sacrificial layers to form first filling spaces; forming first conductive layers in the first filling spaces, the first conductive layers between the support structures, between the support structures and the contact structures, and between the support structures or the contact structures and the first intermediate structures form bit lines, and the first conductive layers between the first intermediate structures and the second intermediate structures form connection layers; forming first isolation layers in the first isolation grooves, the first isolation layers fill the first isolation grooves; removing the first intermediate structures to form a plurality of transistors arranged in the first direction, removing the second intermediate structures to form a plurality of capacitors arranged in the second direction, and removing the remaining first sacrificial layers to form second isolation layers, in the third direction, each of the transistors is connected to one of the capacitors through the connection layers.

9. The method of manufacturing according to claim 8, wherein, forming at least one support structure between two adjacent contact structures in the second direction, comprising: etching the stack structure to form a plurality of first filling holes penetrating the stack structure, the plurality of first filling holes are arranged in the second direction, and there is at least one first filling hole between two adjacent contact structures; etching the first sacrificial layer exposed in the first filling hole to enlarge the first filling hole; thinning the second sacrificial layer exposed in the enlarged first filling hole in the first direction to further enlarge the first filling hole and increase the distance between the adjacent part of the second sacrificial layer exposed in the enlarged first filling hole; depositing the support structure, the support structure fills the further enlarged first filling hole.

10. The production method according to claim 8 or 9, characterized by, forming a plurality of contact structures, a plurality of first intermediate structures and a plurality of second intermediate structures in the stack structure, comprising: etching the stack structure to form a plurality of second filling holes arranged along the second direction, each of the second filling holes exposing one of the second sacrificial layers; forming a contact structure in each of the second filling holes, the contact structure filling the corresponding second filling hole; etching the stack structure to form a plurality of first intermediate holes on both sides of the contact structure along the third direction, the plurality of first intermediate holes on each side arranged along the second direction, and each of the first intermediate holes exposing the substrate; forming the first intermediate structure in each of the first intermediate holes, the first intermediate structure filling the first intermediate hole; etching the stack structure to form a plurality of second intermediate holes on a side of the plurality of first intermediate structures away from the plurality of contact structures, the plurality of second intermediate holes on each side arranged along the second direction, and along the third direction, each of the second intermediate holes opposite to the first intermediate structure; forming the second intermediate structure in each of the second intermediate holes, the second intermediate structure filling the second intermediate hole.

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