Three-dimensional dynamic random access memory array structure and semiconductor device including the same

Abstract

The present disclosure provides a three-dimensional DRAM array structure and a semiconductor device including the same. The three-dimensional DRAM array structure includes: L layers of M rows of N column DRAM cell structures each including: first and second gate-all-around transistors each having a tubular channel, disposed in a vertical direction in order and electrically connected in parallel, and a storage capacitor having a tubular structure, disposed in the vertical direction between the first and second gate-all-around transistors, an inner electrode connected to first source / drain electrodes of the first and second gate-all-around transistors, and an outer electrode connected to a source line; M×N bit lines respectively extending inside the tubular structures collectively formed by the first and second gate-all-around transistors and the storage capacitor in the M rows of N column DRAM cell structures in the vertical direction, and respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; and L×M first and second word lines extending in a first horizontal direction and respectively connected to gate electrodes of the first and second gate-all-around transistors in the L layers of DRAM cell structures.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, the present disclosure relates to a three-dimensional dynamic random access memory (DRAM) array structure and a semiconductor device including the same. BACKGROUND

[0002] Since the invention of dynamic random access memory (DRAM) by Intel Corporation in the 1970s, DRAM has been widely used in various types of computing or control electronic circuit systems.

[0003] A DRAM cell circuit is generally composed of one selection transistor and one storage capacitor for storing charge (1T1C structure). In a DRAM cell structure using a conventional horizontal transistor based on a planar structure, such as a metal oxide semiconductor field effect transistor (MOSFET), the source, gate, and drain of the transistor are arranged in a horizontal direction parallel to the substrate surface. Since the source, gate, and drain of the transistor each occupy an independent area in the horizontal direction, the scaling of the DRAM cell circuit structure is limited by the gate length and contact size, which cannot meet the needs of continuous scaling of the DRAM device, thereby limiting further increases in the integration and bandwidth of the DRAM device.

[0004] Therefore, in recent years, a vertical DRAM cell structure has been proposed, in which the source, gate, and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without occupying additional area, which is conducive to the size scaling of the DRAM array structure. In addition, by vertically stacking multiple layers of DRAM cells to form a three-dimensional DRAM array, the memory integration density can be further improved.

[0005] DRAM manufacturing is a highly competitive industry. The industry continues to demand smaller individual cell sizes and increased memory cell densities, so that a single memory chip accommodates more memory.

[0006] The above information disclosed in this BACKGROUND section is only for the purpose of understanding the background of the present inventive concepts, and therefore, it can contain information that does not constitute prior art. SUMMARY

[0007] To solve the above problems existing in the prior art, the present disclosure proposes a novel three-dimensional dynamic random access memory (DRAM) array structure and a semiconductor device including the same.

[0008] According to one aspect of the present disclosure, there is provided a three-dimensional DRAM array structure including: a plurality of DRAM cell structures arranged in L layers, M rows, and N columns, wherein L, M, and N are natural numbers greater than 1, each of the plurality of DRAM cell structures including: first and second gate-all-around transistors each having a tubular structure, disposed in a vertical direction in order and electrically connected in parallel, and a storage capacitor having a tubular structure, disposed in the vertical direction between the first and second gate-all-around transistors, an inner electrode of which is connected to first source / drain electrodes of the first and second gate-all-around transistors, and an outer electrode of which is connected to a source line; M×N bit lines extending inside tubular structures collectively formed by the first and second gate-all-around transistors and the storage capacitor in the M rows and N columns of DRAM cell structures in the vertical direction, and connected to second source / drain electrodes of the first and second gate-all-around transistors in the M rows and N columns of DRAM cell structures, respectively; L×M first word lines extending in a first horizontal direction and connected to gate electrodes of the first gate-all-around transistors in the L layers and M rows of DRAM cell structures, respectively; and L×M second word lines extending in the first horizontal direction and connected to gate electrodes of the second gate-all-around transistors in the L layers and M rows of DRAM cell structures, respectively.

[0009] According to another aspect of the present disclosure, there is provided a semiconductor device including: the three-dimensional DRAM array structure according to the above aspect of the present disclosure; and a circuit substrate including a plurality of circuits, the three-dimensional DRAM array structure being disposed on the circuit substrate.

[0010] The DRAM cell structure constituting the DRAM array structure according to the present disclosure includes two gate-all-around transistors and one storage capacitor disposed in mirror image in the vertical direction, wherein the inner electrode of the storage capacitor and the source / drain electrodes and channel regions of the two gate-all-around transistors are formed by the same semiconductor material layer, thus having the advantages of simple structure, good switching performance, etc.

[0011] In addition, the DRAM array structure according to the present disclosure can realize three-dimensional vertical integration by stacking multiple layers of DRAM cells, thus improving the integration density. In addition, the DRAM array structure according to the present disclosure can be stacked on a circuit substrate including a plurality of circuits, thus realizing three-dimensional vertical integration at the system level, thus greatly reducing the area overhead of the circuit system.

[0012] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present inventive concepts.

[0014] Figure 1 is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0015] Figure 2 is a perspective view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0016] Figure 3 is a top view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0017] Figure 4 is a cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure taken along line AA' in Figure 3 .

[0018] Figure 5 is a cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure taken along line BB' in Figure 5 .

[0019] Figure 6 is a cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure taken along line CC' in Figure 4 .

[0020] Figure 7 is a cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure taken along line DD' in Figure 4 .

[0021] Figure 8 is an equivalent circuit diagram illustrating a DRAM array structure formed of the DRAM cell structure shown in Figure 1 .

[0022] Figure 9 is an equivalent circuit diagram illustrating a first row of DRAM cell structures of the DRAM array structure according to an embodiment of the present disclosure shown in Figure 8 .

[0023] Figure 10 is a schematic perspective view illustrating a first row of DRAM cell structures of a first layer of the DRAM array structure according to an embodiment of the present disclosure shown in Figure 8 .

[0024] Figure 11 is a schematic perspective view illustrating a first row of DRAM cell structures of a first layer of the DRAM array structure according to an embodiment of the present disclosure shown in Figure 8is a plan view of a partial DRAM array structure of a DRAM array structure according to an embodiment of the present disclosure.

[0025] Figure 12 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line AA' in Figure 11

[0026] Figure 13 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line BB' in Figure 11

[0027] Figure 14 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line CC' in Figure 12

[0028] Figure 15 is a cross-sectional view of a DRAM array structure according to an embodiment of the present disclosure taken along line DD' in Figure 12

[0029] Figure 16 is an equivalent circuit diagram illustrating a DRAM array structure having an alternative configuration of word lines according to an embodiment of the present disclosure.

[0030] Figure 17 is an equivalent circuit diagram illustrating a DRAM array structure having an alternative configuration of bit lines according to an embodiment of the present disclosure.

[0031] Figure 18 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0032] Figure 19 is a schematic block diagram illustrating a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more exemplary embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method incorporating one or more inventive concepts disclosed herein. It will be evident, however, that the exemplary embodiments can be practiced without these specific details, or with one or more equivalent configurations. In other instances, well-known structures and functions have not been described in detail in order to not unnecessarily obscure the disclosure. Also, the exemplary embodiments can be different from but complementary to each other, and some embodiments can be practiced with or without their corresponding complementary embodiments.

[0034] ​​​​Unless otherwise stated, the exemplary embodiments described should be understood to provide example features, which can be combined with each other in practice, to realize variations of the inventive concept in some ways. Therefore, features, components, modules, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the embodiments can be additionally combined, separated, interchanged, and / or reconfigured unless otherwise stated, without departing from the inventive concept.

[0035] For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of any two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] Although the terms "first," "second," etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "a," "an," "one," and / or "said" are used in the detailed description and / or claims, such terms are intended to be inclusive (i.e., in a manner that says that one), unless explicitly indicated to the contrary.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0039] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals denote the same parts throughout the drawings. Furthermore, in the drawings, parts are not necessarily drawn to scale for clarity, and the scale and dimensions of parts may be enlarged.

[0040] The dynamic random access memory (DRAM) cell structure according to embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0041] Figure 1 An equivalent circuit diagram of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown.

[0042] like Figure 1 As shown, the DRAM cell structure 100 according to the embodiments of this disclosure can adopt a 2T1C (i.e., two gate transistors and one storage capacitor) cell structure. Specifically, the DRAM cell structure 100 may include two gate-around-the-axle (GAA) transistors, namely a first GAA transistor T1 and a second GAA transistor T2, which are sequentially disposed in the vertical direction (z direction) and electrically connected in parallel. Both the first and second GAA transistors T1 and T2 may have (see below) Figures 2 to 17 The described channel is a tubular structure and is used as a gate transistor in the DRAM cell structure 100.

[0043] According to an embodiment of this disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are commonly connected to one plate (internal electrode) of the memory capacitor C, and the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 are commonly connected to the bit line BL. According to an embodiment of this disclosure, the bit line BL can extend in the vertical direction (z-direction). Furthermore, according to an embodiment of this disclosure, the gate G1 of the first GAA transistor T1 can be connected to the first word line WLA, and the gate G2 of the second GAA transistor T2 can be connected to the second word line WLB. According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can extend along a first horizontal direction (y-direction) and overlap in the vertical direction (z-direction). According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can be shorted together. Alternatively, according to embodiments of this disclosure, the first word line WLA and the second word line WLB may not be shorted together to control the first GAA transistor T1 and the second GAA transistor T2 respectively.

[0044] Furthermore, according to embodiments of the present disclosure, the other plate (outer electrode) of the storage capacitor C can be connected to the source line SL. Those skilled in the art will recognize that, in a DRAM array structure composed of the DRAM cell structure 100 according to the present disclosure, the source lines SL of all DRAM cell structures can be connected together collectively or in groups, and thus the source line SL can also be referred to herein as a "common electrode".

[0045] Figure 2 A perspective view of the DRAM cell structure 100 according to embodiments of the present disclosure is shown. Figure 3 A top view of the DRAM cell structure 100 according to embodiments of the present disclosure is shown. Figure 4 A cross-sectional view of the DRAM cell structure 100 according to embodiments of the present disclosure taken along the line AA' in Figure 3 Figure 5 A cross-sectional view of the DRAM cell structure 100 according to embodiments of the present disclosure taken along the line BB' in Figure 3 Figure 6 A cross-sectional view of the DRAM cell structure 100 according to embodiments of the present disclosure taken along the line CC' in Figure 4 Figure 7 A cross-sectional view of the DRAM cell structure 100 according to embodiments of the present disclosure taken along the line DD' in Figure 4

[0046] As shown in Figures 2 to 7 , according to embodiments of the present disclosure, the DRAM cell structure 100 can include a bit line hole (e.g., a hole with a circular cross-section as shown in Figure 3 , Figure 6 and Figure 7 ) extending in a vertical direction (z-direction), and a common electrode slot (e.g., a slot on both sides of the centrally located bit line hole as shown in Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 ) extending in a first horizontal direction (y-direction) and penetrating through the DRAM cell structure 100 in the vertical direction (z-direction).

[0047] As shown in Figures 2 to 7 , according to embodiments of the present disclosure, the DRAM cell structure 100 can include a conductor line 109 disposed in the bit line hole, the conductor line 109 extending in the vertical direction (z-direction) and can be used as a Figure 1 ​​​​The bit line BL of the DRAM cell structure 100 shown. According to embodiments of the present disclosure, the material used to form the conductor line 109 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. In particular, according to embodiments of the present disclosure, the conductor line 109 may have a cylindrical shape extending in the vertical direction (z-direction). For example, as Figure 3 , Figure 6 and Figure 7 As shown, conductor line 109 can be a cylinder with a first diameter d1.

[0048] like Figures 2 to 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include a semiconductor material layer 107 with a tubular structure and a first isolation material layer 111 disposed in a bit line hole surrounding a conductor line 109. Specifically, as Figure 4 and Figure 5 As shown more clearly, the upper and lower ends of the semiconductor material layer 107 are in direct contact with the conductor line 109, and the middle portion of the semiconductor material layer 107 is separated from the conductor line 109 by the first insulating material layer 111. In other words, according to embodiments of this disclosure, both the semiconductor material layer 107 and the first insulating material layer 111 have a tubular structure surrounding the conductor line 109. Although in Figure 3 , Figure 6 and Figure 7 In this invention, the tubular structure has a circular cross-section, but this disclosure is not limited to this. Those skilled in the art should recognize that the tubular structure may also have other arbitrary cross-sections, such as elliptical, square or rectangular cross-sections, in which case the cross-sectional shape of the conductor line 109 can be adjusted accordingly.

[0049] According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof. According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can also be a low-k material. Low-k materials can have a lower dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the first isolation material layer 111 can include a low-k material having a dielectric constant of about 3.9 or lower. According to embodiments of this disclosure, low-k materials can include porous silicon oxide (SiO2), organosilicon, fluorinated silicon glass (FSG), silsesquioxane (HSQ), silicon carbide (SiCOH), or polymer materials such as parylene and polyimide (PI). According to embodiments of this disclosure, the material used to form the first isolation material layer 111 can also be a combination of the above-mentioned dielectric materials and the above-mentioned low-k materials.

[0050] According to embodiments of the present disclosure, the material used to form the semiconductor material layer 107 can be a semiconductor thin film material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, a silicon germanide compound, a compound semiconductor, an oxide semiconductor, a sulfide semiconductor, graphene, or a combination thereof. According to embodiments of the present disclosure, the material used to form the semiconductor material layer 107 can be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO) of different ratios, indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO). In particular, according to embodiments of the present disclosure, the semiconductor material layer 107 can include a single layer of IGZO or a stack of multiple layers of IGZO of different ratios.

[0051] Further, according to embodiments of the present disclosure, as described in more detail below, the semiconductor material layer 107 can form source / drain regions and channel regions of a first GAA transistor T1 and a second GAA transistor T2 as shown in Figure 1 , where the source / drain regions of the first GAA transistor T1 and the second GAA transistor T2 correspond to a first source / drain S / D 11 and a second source / drain S / D 12 of the first GAA transistor T1 and a first source / drain S / D 21 and a second source / drain S / D 22 of the second GAA transistor T2. It is noted here that the source / drain regions described from a structural perspective are equivalent to the source / drain described from a circuit perspective. Further, according to embodiments of the present disclosure, the semiconductor material layer 107 can also form an internal electrode of a storage capacitor C as shown in Figure 1 . Thus, according to embodiments of the present disclosure, the storage capacitor C can also have a tubular structure.

[0052] As shown in Figures 2 to 7 , according to embodiments of the present disclosure, the DRAM cell structure 100 can include two first dielectric layers 106 disposed in the bit line hole around the upper end and the lower end of the semiconductor material layer 107, respectively. According to embodiments of the present disclosure, the two first dielectric layers 106 can form gate dielectrics of the first GAA transistor T1 and the second GAA transistor T2 as shown in Figure 1 , respectively. As shown in Figure 4 and Figure 5 , according to embodiments of the present disclosure, the first dielectric layer 106 can also have a tubular structure with a folded cross-section. In other words, as shown in Figures 2 to 5As shown, in a cross-section along the vertical direction (z-direction), the first dielectric layer 106 may have a thinner first portion near the end of the conductor line 109 and a thicker second portion relative to the first portion and away from the end of the conductor line 109. The first and second portions may be connected by a horizontal connecting portion. According to embodiments of this disclosure, the material used to form the first dielectric layer 106 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), or combinations thereof.

[0053] Therefore, according to the embodiments of this disclosure, both the first GAA transistor T1 and the second GAA transistor T2 are formed to have a tubular structure and both have a tubular channel.

[0054] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include a lower first gate layer 104 and an upper second gate layer 105 configured to surround a thicker second portion of a lower and upper first dielectric layer 106, respectively. Figure 2 and Figure 6 As shown, according to embodiments of the present disclosure, the first gate layer 104 and the second gate layer 105 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the first gate layer 104 may correspond to... Figure 1 The first GAA transistor T1 shown has a gate G1, and the second gate layer 105 can correspond to, as shown in the figure. Figure 1 The gate G2 of the second GAA transistor T2 is shown. Furthermore, as... Figure 2 , Figure 3 and Figure 5 As shown, according to an embodiment of this disclosure, the first gate layer 104 may extend in a first horizontal direction (y-direction) to further correspond to, as Figure 1 The first word line WLA is shown, connected to the first gate G1 of the first GAA transistor T1. Accordingly, according to embodiments of this disclosure, the second gate layer 105 may extend in the first horizontal direction (y direction) to further correspond to, as shown in the figure. Figure 1 The second word line WLB is shown connected to the gate G2 of the second GAA transistor T2. According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can be led out from the distal end in a first horizontal direction (y direction).

[0055] Therefore, according to embodiments of the present disclosure, the DRAM cell structure 100 may have a bit line BL extending in the vertical direction (z-direction), and a first word line WLA and a second word line WLB extending in the first horizontal direction (y-direction). According to embodiments of the present disclosure, the bit line BL of the DRAM cell structure 100 may extend vertically within a tubular structure formed by the first GAA transistor T1, the second GAA transistor T2, and the storage capacitor C. Furthermore, according to embodiments of the present disclosure, the first gate layer 104 and the second gate layer 105 corresponding to the first word line WLA and the second word line WLB of the DRAM cell structure 100 may overlap in the vertical direction (z-direction).

[0056] Furthermore, according to embodiments of this disclosure, the materials used to form the first gate layer 104 and the second gate layer 105 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0057] like Figures 2 to 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include two second insulating material layers 103 configured to surround, respectively, a thinner first portion of a first dielectric layer 106 above and below. Figure 2 and Figure 3 As shown, according to embodiments of the present disclosure, the second insulating material layer 103 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the material used to form the second insulating material layer 103 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCOH), or aluminum oxide (Al2O3). According to embodiments of the present disclosure, the first insulating material layer 111 and the second insulating material layer 103 may be formed of the same or different insulating materials.

[0058] like Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, as described above, the semiconductor material layer 107 along the vertical direction (z-direction) may include the formation indicated by the shaded area. Figure 1 The first portion 1071 of the channel region of the first and second GAA transistors T1 and T2 shown, and the formation between the first portions 1071. Figure 1A second portion 1072 of the first source / drain region of the first GAA transistor T1 (corresponding to the first source / drain S / D 11 of the first GAA transistor T1), the first source / drain region of the second GAA transistor T2 (corresponding to the first source / drain S / D 21 of the second GAA transistor T2), and the inner electrode of the memory capacitor C. Thus, according to embodiments of the present disclosure, the first source / drain S / D 11 of the first GAA transistor T1 and the first source / drain S / D 21 of the second GAA transistor T2 are connected together with the inner electrode of the memory capacitor C. According to embodiments of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 are separated from the conductor line 109 (bit line BL) by the first isolation material layer 111 surrounding the conductor line 109 (bit line BL).

[0059] According to embodiments of the present disclosure, the doping type, the doping concentration, and / or the atomic composition ratio of the second portion 1072 of the semiconductor material layer 107 can be changed by material modification processes such as doping, etching, etc. so that it has better conductive performance as the inner electrode of the memory capacitor C. That is, according to embodiments of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 can have different doping types, doping concentrations, and / or atomic composition ratios. According to embodiments of the present disclosure, when the semiconductor material layer 107 is an IGZO oxide semiconductor, all or part of the gallium (Ga) atoms in the second portion 1072 can be removed by, for example, an etching process to improve its conductivity, or part of the oxygen (O) atoms in the second portion 1072 can be removed by, for example, an etching process to form metal atom interstitials or oxygen atom vacancies to improve its conductivity.

[0060] In addition, as shown in FIG. 1C, according to embodiments of the present disclosure, the semiconductor material layer 107 can further include a first portion 1071 contacting both ends of the conductor line 109 along the vertical direction (z-direction) as described above. Figure 4 and Figure 5 As shown in FIG. 1C, according to embodiments of the present disclosure, the semiconductor material layer 107 can further include a first portion 1071 contacting both ends of the conductor line 109 along the vertical direction (z-direction) as described above. Figure 1 A third portion 1073 of the second source / drain region of the first GAA transistor T1 (corresponding to the second source / drain S / D 12 of the first GAA transistor T1) and the second source / drain region of the second GAA transistor T2 (corresponding to the second source / drain S / D 22 of the second GAA transistor T2), and a first horizontal connection portion 1074 connecting the first portion 1071 and the third portion 1073. Thus, according to embodiments of the present disclosure, the third portion 1073 of the semiconductor material layer 107 is in contact with the conductor line 109 so that the second source / drain S / D 12 of the first GAA transistor T1 and the second source / drain S / D 22 of the second GAA transistor T2 corresponding to the third portion 1073 of the semiconductor material layer 107 are connected to the bit line BL corresponding to the conductor line 109.

[0061] like Figure 3 As shown, according to an embodiment of this disclosure, the third portion 1073 of the tubular semiconductor material layer 107 may have a second diameter d2, which is larger than the first diameter d1 of the conductor line 109. Furthermore, as... Figures 3 to 7 As shown, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the tubular semiconductor material layer 107 may have a third diameter d3, which is larger than the second diameter d2 of the third portion 1073 of the semiconductor material layer 107.

[0062] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a second dielectric layer 108 disposed in a common electrode trench as a capacitor dielectric for a storage capacitor C. According to an embodiment of the present disclosure, the second dielectric layer 108 may be formed conformally along the trench wall of the common electrode trench. Figure 2 and Figure 4 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact the two second insulating material layers 103, the first gate layer 104, the second gate layer 105, and the second portion of the semiconductor material layer 107 in the second horizontal direction (x direction). Furthermore, as... Figure 2 and Figure 5 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact a second portion of the semiconductor material layer 107 in a first horizontal direction (y-direction). The first horizontal direction, i.e., the y-direction, can be perpendicular to the second horizontal direction, i.e., the x-direction.

[0063] Furthermore, according to embodiments of this disclosure, the material used to form the second dielectric layer 108 can be a high-k material. The high-k material can have a higher dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the second dielectric layer 108 can include a high-k material having a dielectric constant of about 4 or greater. According to embodiments of this disclosure, the high-k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanium oxide (SrTiO3), or combinations thereof.

[0064] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include an electrode layer 110 extending along the surface of the second dielectric layer 108 and filling a common electrode trench. According to an embodiment of the present disclosure, the electrode layer 110 may correspond to... Figure 1 The external electrode of the storage capacitor C is shown, i.e., the common electrode of the storage capacitor C, and the source line SL. For example... Figures 2 to 7As shown, according to embodiments of the present disclosure, the electrode layer 110 corresponding to the outer electrode of the storage capacitor C and the source line SL can extend in the first horizontal direction (y direction) and penetrate through the DRAM cell structure 100 in the vertical direction (z direction). According to embodiments of the present disclosure, the material used to form the electrode layer 110 can include titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polysilicon / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof. Thus, according to embodiments of the present disclosure, the storage capacitor C of the DRAM cell structure 100 can be formed as a pillar-shaped capacitor.

[0065] Further, although not shown in the figures, according to embodiments of the present disclosure, a third isolation material layer can also be provided between the first and second gate layers 104 and 105 and the second dielectric layer 108, for reducing the parasitic capacitance and leakage current between the outer electrode of the storage capacitor (source line SL) and the gates G1 and G2 (i.e., the first and second word lines WLA and WLB) of the first and second GAA transistors T1 and T2.

[0066] Figure 8 is an equivalent circuit diagram showing a DRAM array structure 200 formed by the DRAM cell structure shown in Figure 1 As shown, according to embodiments of the present disclosure, the DRAM array structure 200 formed by the DRAM cell structure shown in Figure 8 As shown, according to embodiments of the present disclosure, the DRAM array structure 200 formed by the DRAM cell structure shown in Figure 1 As shown, according to embodiments of the present disclosure, the DRAM array structure 200 formed by the DRAM cell structure shown in

[0067] As shown, according to embodiments of the present disclosure, the DRAM array structure 200 can include a plurality of DRAM cell structures 100 arranged in a matrix form, as shown in Figure 8 As shown, according to embodiments of the present disclosure, the DRAM array structure 200 can include a plurality of DRAM cell structures 100 arranged in a matrix form, as shown in Figure 1The plurality of DRAM cell structures 100 is shown. For the sake of clarity, certain reference numerals inside each DRAM cell structure are omitted. According to an embodiment of the present disclosure, the plurality of DRAM cell structures is arranged in L layers M rows N columns L, where L, M, and N are each a natural number greater than 1. Herein, each of the plurality of DRAM cell structures included in the DRAM array structure 200 can be denoted as Clmn, i.e., a DRAM cell structure located in the mth row, the nth column, and the lth layer in the DRAM array structure 200, where m, n, and l are natural numbers, and 1≤m≤M, 1≤n≤N, and 1≤l≤L. Further, herein, M denotes the number of rows of DRAM cell structures along a first horizontal direction (y direction) of the DRAM array structure 200, N denotes the number of columns of DRAM cell structures along a second horizontal direction (x direction) of the DRAM array structure 200, and L denotes the number of layers of DRAM cell structures along a vertical direction (z direction) of the DRAM array structure 200.

[0068] According to an embodiment of the present disclosure, a cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM and M×N bit lines BL11 to BLMN.

[0069] Accordingly, as Figure 8 shown, according to an embodiment of the present disclosure, in the DRAM array structure 200, each of the L layers of DRAM cell structures includes M rows N columns, i.e., M×N DRAM cell structures, each of the M rows of DRAM cell structures includes L layers N columns, i.e., L×N DRAM cell structures, and each of the N columns of DRAM cell structures includes L layers M rows, i.e., L×M DRAM cell structures.

[0070] As described above with reference to Figures 1 to 7 each of the plurality of DRAM cell structures included in the DRAM array structure 200 can include: a first GAA transistor and a second GAA transistor each having a tubular structure of a channel, disposed in a vertical direction in sequence and electrically connected in parallel; and a storage capacitor having a tubular structure, disposed in the vertical direction between the first GAA transistor and the second GAA transistor, an internal electrode of which is connected to a first source / drain of the first GAA transistor and the second GAA transistor.

[0071] Further, as Figure 8As shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include M×N bit lines BL11 to BLMN, which extend vertically inside a tubular structure formed by L first GAA transistors, L second GAA transistors, and L storage capacitors in the M-row N-column DRAM cell structure, and are respectively connected to the second source / drain of the L first GAA transistors and L second GAA transistors in the M-row N-column DRAM cell structure.

[0072] Furthermore, although not shown, according to embodiments of this disclosure, in each row of an M-row DRAM array structure, L first word lines WLA1m to WLALm can be respectively connected to L second word lines WLB1m to WLBLm. For example, as Figure 8 As shown, in the first row of the DRAM array structure, the first word line WLA11 can be connected to the second word line WLB11, the first word line WLA21 can be connected to the second word line WLB21, and so on, until the first word line WLAL1 can be connected to the second word line WLBL1. According to an embodiment of this disclosure, in each row of the M-row DRAM array structure, the corresponding connections of L first word lines and L second word lines can be implemented from the remote end outside the array. In this document, since the paired first word lines WLAlm and second word lines WLBlm extending along the first horizontal direction (y direction) can be connected together, they can be collectively referred to as word lines WL and assigned the same number as the corresponding first word line WLAlm and second word line WLBlm, i.e., WLlm. At this time, according to an embodiment of this disclosure, the cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M word lines WL11 to WLLM and M×N bit lines BL11 to BLMN.

[0073] Furthermore, according to embodiments of this disclosure, the DRAM array structure 200 may further include L source lines SL corresponding to the L-layer DRAM cell structure, which extend along a first horizontal direction (y-direction) and are respectively connected to the external electrodes of the storage capacitors in the L-layer DRAM cell structure. Additionally, as... Figure 8 As shown, according to an embodiment of this disclosure, L source lines SL can be connected together by a common electrode trench disposed between the bit lines that runs vertically (z-direction) through the entire DRAM array structure 200, while the source lines SL also extend vertically (z-direction). Although not shown, according to an alternative embodiment of this disclosure, the L source lines SL can also be connected together simply outside the DRAM array structure 200, either commonly or in groups, thus omitting the common electrode trench.

[0074] Figure 9 It is shown Figure 8An equivalent circuit diagram of the first row of DRAM cell structures C111 to CL1N of the DRAM array structure 200 according to the embodiment of the present disclosure is shown. As Figure 9 As shown, a first row first column first layer DRAM cell structure C111 is provided at the intersection of a first row first column bit line BL11 extending in a vertical direction (z direction) and a first layer word line (a first word line WLA11 and a second word line WLB11) extending in a first horizontal direction (y direction). By analogy, Figure 9 As shown, the first row of the DRAM array structure 200 includes N x L DRAM cell structures C111 to CL1N.

[0075] As described above with reference to Figure 1 According to the embodiment of the present disclosure, each of the plurality of DRAM cell structures constituting the DRAM array structure 200, for example Figure 9 As shown, the DRAM cell structure C111 includes a first GAA transistor T1, a second GAA transistor T2, and a storage capacitor C.

[0076] Figure 10 is a schematic perspective view showing Figure 8 As shown, the first layer first row DRAM cell structure of the DRAM array structure 200 according to the embodiment of the present disclosure is shown. As Figure 10 As shown, in the first layer first row DRAM cell structure of the DRAM array structure, the first layer first row word line WL11 (the first word line WLA11 and the second word line WLB11) can extend in the first horizontal direction (y direction), and the first row bit line (only BL11 to BL13 are shown) can extend in the vertical direction (z direction). According to the embodiment of the present disclosure, the source line SL of the first layer DRAM cell structure can extend in the first horizontal direction (y direction). In addition, as Figure 10 As shown, the source line SL can also be connected together with the source line SL in other layers in a common electrode groove extending in the vertical direction (z direction).

[0077] In addition, as Figures 8 to 10 As shown, according to the embodiment of the present disclosure, the mth row nth column bit line BLmn can be commonly connected to the second source / drain of the L first GAA transistors and the L second GAA transistors in the mth row nth column DRAM cell structure of the DRAM array structure 200, for performing a cell selection operation on the mth row nth column DRAM cell structure.

[0078] Figure 11 is a schematic perspective view showing Figure 8 As shown, a top view of a partial DRAM array structure 201 of the DRAM array structure 200 according to the embodiment of the present disclosure is shown. Figure 12 is a schematic perspective view showingFigure 11 a cross-sectional view of the DRAM array structure 201 according to the embodiment of the present disclosure taken along the line AA' in FIG. 2A. Figure 13 is a plan view showing the DRAM array structure 201 according to the embodiment of the present disclosure taken along the line BB' in FIG. 2B. Figure 11 a cross-sectional view of the DRAM array structure 201 according to the embodiment of the present disclosure taken along the line BB' in FIG. 2B. Figure 14 is a plan view showing the DRAM array structure 201 according to the embodiment of the present disclosure taken along the line CC' in FIG. 2C. Figure 12 a cross-sectional view of the DRAM array structure 201 according to the embodiment of the present disclosure taken along the line CC' in FIG. 2C. Figure 15 is a plan view showing the DRAM array structure 201 according to the embodiment of the present disclosure taken along the line DD' in FIG. 2D. Figure 12 a cross-sectional view of the DRAM array structure 201 according to the embodiment of the present disclosure taken along the line DD' in FIG. 2D.

[0079] Note that, Figures 11 to 15 a partial DRAM array structure 201 as a part of the DRAM array structure 200 shown in FIG. 2A is exemplarily shown in FIG. 2B, which includes the first layer first row first column to the second layer second row second column of the DRAM cell structures C111, C112, C121, C122, C211, C212, C221, and C222, which are arranged in a 2-row 2-column 2-layer form. Figure 8 a partial DRAM array structure 201 as a part of the DRAM array structure 200 shown in FIG. 2A is exemplarily shown in FIG. 2B, which includes the first layer first row first column to the second layer second row second column of the DRAM cell structures C111, C112, C121, C122, C211, C212, C221, and C222, which are arranged in a 2-row 2-column 2-layer form.

[0080] According to the embodiment of the present disclosure, the M rows N columns of the bit lines BL11 to BLMN of the DRAM array structure 200 can extend in the vertical direction (z direction) and be arranged in a 2x2 matrix form in the first horizontal direction (y direction) and the second horizontal direction (x direction). Further, according to the embodiment of the present disclosure, the L layers of the DRAM cell structures of the DRAM array structure 200 are sequentially stacked in the vertical direction, and each layer of the DRAM cell structures includes MxN DRAM cell structures.

[0081] Specifically, as shown in FIG. 2B, Figures 11 to 15 the two rows two columns of the four bit lines BL11, BL12, BL21, and BL22 can extend in the vertical direction (z direction) and be arranged in a 2x2 matrix form in the first horizontal direction (y direction) and the second horizontal direction (x direction). Further, as shown in FIG. 2C, Figure 12 and Figure 13 the first layer of the DRAM cell structures C111, C112, C121, and C122 is stacked above the second layer of the DRAM cell structures C211, C212, C121, and C222.

[0082] As shown in FIG. 2B, Figure 11 and Figure 12As shown, first tier first row first word line WLA11 is connected to the gates of the first GAA transistor in first tier first row DRAM cell structures C111 and C112, and first tier second word line WLB11 is connected to the gates of the second GAA transistor in first tier first row DRAM cell structures C111 and C112. Similarly, first tier second row first word line WLA12 is connected to the gates of the first GAA transistor in first tier second row DRAM cell structures C121 and C122, and first tier second row second word line WLB12 is connected to the gates of the second GAA transistor in first tier second row DRAM cell structures C121 and C122. Similarly, second tier first row first word line WLA21 is connected to the gates of the first GAA transistor in second tier first row DRAM cell structures C211 and C212, and second tier first row second word line WLB21 is connected to the gates of the second GAA transistor in second tier first row DRAM cell structures C211 and C212. Similarly, second tier second row first word line WLA22 is connected to the gates of the first GAA transistor in second tier second row DRAM cell structures C221 and C222, and second tier second row second word line WLB22 is connected to the gates of the second GAA transistor in second tier second row DRAM cell structures C221 and C222.

[0083] As Figures 11 to 15As shown, four bit lines BL11, BL12, BL21, and BL22 are formed in four bit line holes extending through the DRAM array structure in the vertical direction (z-direction). Specifically, the first row first column bit line BL11 extends in the vertical direction inside the tubular structure of the first GAA transistor and the second GAA transistor and the storage capacitor in the first row first column DRAM cell structure C111 and C211, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the first row first column DRAM cell structure C111 and C211. Similarly, the first row second column bit line BL12 extends in the vertical direction inside the tubular structure of the first GAA transistor and the second GAA transistor and the storage capacitor in the first row second column DRAM cell structure C112 and C212, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the first row second column DRAM cell structure C112 and C212. Similarly, the second row first column bit line BL21 extends in the vertical direction inside the tubular structure of the first GAA transistor and the second GAA transistor and the storage capacitor in the second row first column DRAM cell structure C121 and C221, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the second row first column DRAM cell structure C121 and C221. Similarly, the second row second column bit line BL22 extends in the vertical direction inside the tubular structure of the first GAA transistor and the second GAA transistor and the storage capacitor in the second row second column DRAM cell structure C122 and C222, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the second row second column DRAM cell structure C122 and C222.

[0084] According to embodiments of the present disclosure, in each of the M rows x N columns of DRAM cell structures, the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor are formed by the same semiconductor material layer. That is, according to embodiments of the present disclosure, in each of the M x N bit line holes extending through the L-layer DRAM cell structure in the vertical direction (z-direction), the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor in the L-layer DRAM cell structure are formed by the same semiconductor material layer having a tubular structure. That is, the semiconductor material layer having the tubular structure extends through the entire DRAM array structure 200 in the vertical direction (z-direction).

[0085] Specifically, as Figures 11 to 15As shown, the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor in the first layer DRAM cell structure C111 and the second layer DRAM cell structure C211 connected to the first column bit line BL11 of the first row are formed by the same semiconductor material layer. Similarly, the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor in the first layer DRAM cell structure C112 and the second layer DRAM cell structure C212 connected to the second column bit line BL12 of the first row are formed by the same semiconductor material layer. Similarly, the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor in the first layer DRAM cell structure C121 and the second layer DRAM cell structure C221 connected to the first column bit line BL21 of the second row are formed by the same semiconductor material layer. Similarly, the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor in the first layer DRAM cell structure C122 and the second layer DRAM cell structure C222 connected to the second column bit line BL22 of the second row are formed by the same semiconductor material layer.

[0086] According to embodiments of the present disclosure, the common electrode trench can extend in the first horizontal direction (y direction) and penetrate through the L-layer DRAM array structure in the vertical direction (z direction), at which time the L source lines SL corresponding to the L-layer DRAM cell structures can be connected together in the vertical direction (z direction). Further, according to embodiments of the present disclosure, the DRAM cell structures of adjacent rows in the second horizontal direction (x direction) can share the common electrode trench. Further, as described above, the capacitor dielectric and the outer electrode of the storage capacitor in each DRAM cell structure of the DRAM array structure 200 can be disposed in the common electrode trench.

[0087] Alternatively, according to embodiments of the present disclosure, in the DRAM array structure 200, the common electrode trench can also be omitted, at which time the source lines SL can extend only in the first horizontal direction (y direction) and be connected together commonly or in groups outside the DRAM array structure 200.

[0088] Figure 16 is an equivalent circuit diagram showing a DRAM array structure 200' having an alternative configuration of word lines according to embodiments of the present disclosure. In Figure 16 the same components are denoted by the same reference numerals, and repetitive description thereof will be omitted. Figure 8

[0089] In conjunction with Figure 8 Reference is made to Figure 16 , Figure 16 ​The illustrated DRAM array structure 200' can be further simplified to L word lines WL1 to WLL. At this time, according to embodiments of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented by the word line WLl and the bit line BLmn. Figure 8 The illustrated DRAM array structure 200 differs from the DRAM array structure 200' in that, in each of the L-tier DRAM cell structures, the M first word lines WLAl1 to WLAlM can be connected together to form a common first word line WLAl of the lth tier, and the M second word lines WLBl1 to WLBlM can be connected together to form a common second word line WLBl of the lth tier. Specifically, as illustrated, Figure 16 The first word lines WLA11 to WLA1M of the first-tier DRAM cell structure are connected together to form a first-tier common first word line WLA1, and the second word lines WLB11 to WLB1M of the first-tier DRAM cell structure are connected together to form a first-tier common second word line WLB1. Similarly, the first word lines WLA21 to WLA2M of the second-tier DRAM cell structure are connected together to form a second-tier common first word line WLA2, and the second word lines WLB21 to WLB2M of the second-tier DRAM cell structure are connected together to form a first-tier common second word line WLB2. In this way, the first word lines WLAL1 to WLALM of the L-tier DRAM cell structure are connected together to form an L-tier common first word line WLAL, and the second word lines WLBL1 to WLBLM of the L-tier DRAM cell structure are connected together to form an L-tier common second word line WLBL.

[0090] At this time, according to embodiments of the present disclosure, the DRAM array structure 200' has L first word lines WLA1 to WLAL, L second word lines WLB1 to WLBL, and MxN bit lines BL11 to BLMN. According to embodiments of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented by the first word line WLAl, the second word line WLBl, and the bit line BLmn.

[0091] In addition, according to embodiments of the present disclosure, in each of the M rows of the DRAM array structure, in the case where the L first word lines WLA1m to WLALm are respectively connected to the L second word lines WLB1m to WLBLm, Figure 16 The illustrated DRAM array structure 200' can be further simplified to L word lines WL1 to WLL. At this time, according to embodiments of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented by the word line WLl and the bit line BLmn.

[0092] Therefore, Figure 16 The illustrated DRAM array structure 200', compared to the DRAM array structure 200, Figure 8 The illustrated DRAM array structure 200' can be further simplified to L word lines WL1 to WLL. At this time, according to embodiments of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200' can be implemented by the word line WLl and the bit line BLmn.

[0093] Figure 17 is an equivalent circuit diagram showing a DRAM array structure 200" having an alternative configuration of bit lines according to an embodiment of the present disclosure. In Figure 17 Figure 8 The same components are denoted by the same reference numerals, and repetitive description thereof will be omitted.

[0094] Referring to Figure 8 Figure 17 , Figure 17 The DRAM array structure 200" shown in Figure 8 differs from the DRAM array structure 200 shown in Figure 17 in that, in each of the N columns of DRAM cell structures, the M bit lines BL1n to BLMn can be connected together to form a common bit line BLn for the nth column. Specifically, as shown in BL1n to BLMn of the second column of DRAM cell structures are connected together to form a common bit line BL2 for the first column. By analogy, bit lines BL1N to BLMN of the Nth column of DRAM cell structures are connected together to form a common bit line BLN for the Nth column.

[0095] At this time, according to an embodiment of the present disclosure, the DRAM array structure 200" has L x M first word lines WLAl1 to WLALM, L x M second word lines WLB11 to WLBLM, and N bit lines BL1 to BLN. According to an embodiment of the present disclosure, the selection operation of each DRAM cell structure Clmn in the DRAM array structure 200" can be implemented by the first word line WLAlm, the second word line WLBlm, and the bit line BLn.

[0096] Further, according to an embodiment of the present disclosure, in each of the M rows of DRAM array structures, in a case where the L first word lines WLAlm to WLALm are respectively connected to the L second word lines WLB1m to WLBLm, Figure 17 The DRAM array structure 200" shown in

[0097] Thus, the DRAM array structure 200" shown in Figure 17 , compared to the DRAM array structure 200 shown in Figure 8 , can simplify the bit line configuration.

[0098] ​According to embodiments of the present disclosure, since the DRAM array structure 200 is a three-dimensionally vertically integrated DRAM array structure, it is possible to stack the DRAM array structure 200 on a circuit substrate including various circuits, thereby implementing a vertically integrated semiconductor device.

[0099] Figure 18 is a schematic cross-sectional view illustrating a semiconductor device 400 according to embodiments of the present disclosure. According to embodiments of the present disclosure, the semiconductor device 400 can include a circuit substrate 300 and a DRAM array structure 200 disposed on the circuit substrate 300. Although Figure 18 only a partial DRAM array structure of the DRAM array structure 200 shown in FIG. 4A is shown, i.e., DRAM cell structures CLmn, C(L-1)nm, CL(m+1)n, and C(L-1)(m+1)n are stacked on the circuit substrate 300, it will be appreciated by those skilled in the art that the DRAM array structure 200 can be entirely stacked on the circuit substrate 300. Figure 8

[0100] As shown in FIG. 4B, according to embodiments of the present disclosure, the circuit substrate 300 can be a semiconductor substrate on which a plurality of circuits can be manufactured by a semiconductor manufacturing process such as a standard CMOS process. According to embodiments of the present disclosure, the L layers of DRAM cell structures of the DRAM array structure 200 can be stacked on the circuit substrate 300 in a vertical direction (z direction), thereby implementing a three-dimensionally vertically integrated system level. Figure 18 According to embodiments of the present disclosure, the plurality of circuits on the circuit substrate 300 can be connected to the DRAM array structure 200 by, for example, wires and vias extending in a vertical direction (z direction).

[0101]

[0102] is a schematic block diagram illustrating a semiconductor device 400 according to embodiments of the present disclosure. Figure 19 As shown in FIG. 4C, according to embodiments of the present disclosure, the plurality of circuits included in the circuit substrate 300 can be a memory controller circuit 302, a word line circuit 303, and a bit line circuit 304.

[0103] Figure 19 According to embodiments of the present disclosure, the memory controller circuit 302 can be a main management circuit of the DRAM array structure 200 for processing all instructions related to read and write operations of the DRAM array structure 200. In addition, the memory controller circuit 302 is also used to refresh the DRAM cell structures, since data stored in the DRAM cell structures gradually disappears over time, it is necessary to be periodically refreshed to maintain the integrity of the data.

[0104] According to embodiments of the present disclosure, the memory controller circuit 302 can be a main management circuit of the DRAM array structure 200 for processing all instructions related to read and write operations of the DRAM array structure 200. In addition, the memory controller circuit 302 is also used to refresh the DRAM cell structures, since data stored in the DRAM cell structures gradually disappears over time, it is necessary to be periodically refreshed to maintain the integrity of the data.

[0105] ​​According to embodiments of the present disclosure, the word line circuit 303 is used to select a group of DRAM cell structures connected to a specified word line in the DRAM array structure 200. For example, when data needs to be read from or written to the DRAM array structure, the word line circuit 303 is activated to select a group of DRAM cell structures connected to a specified word line. In addition, the bit line circuit 304 is used to select a specific DRAM cell structure in the group of DRAM cell structures connected to the specified word line. When the word line circuit 303 selects a group of DRAM cell structures, the bit line circuit 304 can select a bit line connected to a DRAM cell structure in the group of DRAM cell structures, thereby determining the exact location of the data. In addition, the bit line circuit 304 is also used to transmit data in read and write operations.

[0106] According to embodiments of the present disclosure, the word line circuit 303 can be connected to the word lines WL of the DRAM array structure 200, and the bit line circuit 304 can be connected to the bit lines BL of the DRAM array structure 200.

[0107] According to embodiments of the present disclosure, when Figure 8 When the DRAM array structure 200 shown in FIG. 2 is stacked on the circuit substrate 300, the word line circuit 303 can be connected to L x M word lines WL11 to WLLM (L x M first word lines WLA11 to WLALM and L x M second word lines WLB11 to WLBLM), and the bit line circuit 304 can be connected to M x N bit lines BL11 to BLMN. In addition, according to embodiments of the present disclosure, when Figure 16 When the DRAM array structure 200' shown in FIG. 2' is stacked on the circuit substrate 300, the word line circuit 303 can be connected to L word lines WL1 to WLL (L first word lines WLA1 to WLAL and L second word lines WLB1 to WLBL), and the bit line circuit 304 can be connected to M x N bit lines BL11 to BLMN. In addition, according to embodiments of the present disclosure, when Figure 17 When the DRAM array structure 200" shown in FIG. 2" is stacked on the circuit substrate 300, the word line circuit 303 can be connected to L x M word lines WL11 to WLLM (L x M first word lines WLA11 to WLALM and L x M second word lines WLB11 to WLBLM), and the bit line circuit 304 can be connected to N bit lines BL1 to BLN.

[0108] According to embodiments of the present disclosure, since the word lines WL extend in the first horizontal direction (y direction) in the three-dimensional DRAM array structure (200, 200', and 200") according to embodiments of the present disclosure, the word line circuit 303 can be connected to the word lines WL of the three-dimensional DRAM array structure through the conductive lines and the vias extending in the vertical direction (z direction). In addition, according to embodiments of the present disclosure, since the bit lines BL extend in the vertical direction (z direction) in the three-dimensional DRAM array structure (200, 200', and 200") according to embodiments of the present disclosure, the bit line circuit 304 can be directly connected to the bit lines BL.

[0109] In addition, according to embodiments of the present disclosure, the plurality of circuits included in the circuit substrate 300 can further include a circuit 301, which can be a processor circuit or a memory interface circuit. According to embodiments of the present disclosure, the circuit 301 can be connected to the memory controller circuit 302 for transmitting information such as an address, an instruction, and / or data, etc. thereto, and can be connected to the bit line circuit 304 for transmitting or receiving data thereto or therefrom.

[0110] According to embodiments of the present disclosure, when the circuit 301 is a processor circuit, the semiconductor device 400 can be a computing system, and when the circuit 301 is a memory interface circuit, the semiconductor device 400 can be a memory system.

[0111] According to embodiments of the present disclosure, the DRAM cell structure constituting the DRAM array structure includes two surround-gate transistors and one storage capacitor which are mirror-set in the vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two surround-gate transistors are formed by the same semiconductor material layer, thus having the advantages of simple structure, good switching performance, etc.

[0112] In particular, the cell structure solves the connection problem of the transistor source / drain and the inner electrode of the storage capacitor by using a vertical structure, is suitable for application in a three-dimensional vertical integration of a multi-layer cell, and is suitable for forming by one process for a multi-layer cell by using a vertical structure, without the need for multiple epitaxial processes and processing processes, thus having low manufacturing cost.

[0113] In addition, the DRAM array structure according to the present disclosure can realize three-dimensional vertical integration by stacking multi-layer DRAM cells, so that the integration density can be improved. In addition, the DRAM array structure according to the present disclosure can be stacked in a circuit substrate including a plurality of circuits, so that three-dimensional vertical integration at a system level can be realized, so that the area overhead of the circuit system can be greatly reduced.

[0114] While numerous details have been described herein, these should not be construed as limiting the disclosure or the scope of possible protection, but rather as describing features that can be particular to certain embodiments. Certain features described herein in the context of separate embodiments can also be implemented in combination. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Furthermore, although features can be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features from a claimed combination can be excised from the combination, and the claimed combination can be directed to a subcombination or variation of a subcombination.

Claims

1. A three-dimensional DRAM array structure, comprising: a plurality of DRAM cell structures arranged in L tiers by M rows by N columns, wherein L, M, and N are natural numbers greater than 1, each of the plurality of DRAM cell structures comprising: a first gate-all-around transistor and a second gate-all-around transistor each having a tubular structure, disposed in a vertical direction in series and electrically connected in parallel, and a storage capacitor having a tubular structure disposed in the vertical direction between the first gate-all-around transistor and the second gate-all-around transistor, an inner electrode of which is connected to first source / drain electrodes of the first gate-all-around transistor and the second gate-all-around transistor, and an outer electrode of which is connected to a source line; M x N bit lines extending in the vertical direction inside the tubular structures collectively formed by the first gate-all-around transistors and the second gate-all-around transistors and the storage capacitor in the M rows by N columns of DRAM cell structures, and respectively connected to second source / drain electrodes of the first gate-all-around transistors and the second gate-all-around transistors in the M rows by N columns of DRAM cell structures; L x M first word lines extending in a first horizontal direction and respectively connected to gate electrodes of the first gate-all-around transistors in the L tiers by M rows of DRAM cell structures; and L x M second word lines extending in the first horizontal direction and respectively connected to gate electrodes of the second gate-all-around transistors in the L tiers by M rows of DRAM cell structures.

2. The three-dimensional DRAM array structure of claim 1, further comprising: M x N bit line holes extending through the DRAM array structure in the vertical direction, the M x N bit lines respectively disposed in the M x N bit line holes.

3. The three-dimensional DRAM array structure of claim 1, wherein the L tiers of DRAM cell structures are stacked in series in the vertical direction, and in the M rows of DRAM cell structures, the L first word lines and the L second word lines are alternately stacked in series in the vertical direction.

4. The three-dimensional DRAM array structure of claim 1, wherein in each of the M rows of DRAM cell structures, the L first word lines are respectively connected to the L second word lines.

5. The three-dimensional DRAM array structure of claim 1, wherein in each of the L tiers of DRAM cell structures, the M first word lines are connected together, and the M second word lines are connected together.

6. The three-dimensional DRAM array structure of claim 1, wherein in each of the N columns of DRAM cell structures, the M bit lines are connected together.

7. The three-dimensional DRAM array structure of claim 1, further comprising: L source lines respectively corresponding to the L tiers of DRAM cell structures, extending in the first horizontal direction and respectively connected to the outer electrodes of the storage capacitors in the L tiers of DRAM cell structures.

8. The three-dimensional DRAM array structure of claim 7, further comprising: a common electrode trench extending in the first horizontal direction and through the DRAM array structure in the vertical direction, disposed between adjacent rows of DRAM cell structures, the L source lines being connected together through the common electrode trench.

9. The three-dimensional DRAM array structure of claim 7, wherein, the L source lines are connected together collectively or in groups outside the DRAM array structure.

10. The three-dimensional DRAM array structure of claim 1, wherein, the first source / drain and the second source / drain of the first and second gate-all-around transistors and the inner electrode of the storage capacitor in the L-tier DRAM cell structure of each of the M rows and N columns are formed by the same semiconductor material layer.

11. The three-dimensional DRAM array structure of claim 10, wherein, the semiconductor material layer includes a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

12. The three-dimensional DRAM array structure of claim 10, wherein, the semiconductor material layer includes single-crystal silicon, polycrystalline silicon, amorphous silicon, a silicon-germanium compound, an oxide semiconductor, a sulfide semiconductor, graphene, or a combination thereof.

13. A semiconductor device, comprising: the three-dimensional DRAM array structure of any one of claims 1 to 12; and a circuit substrate including a plurality of circuits, the three-dimensional DRAM array structure being disposed on the circuit substrate.

14. The semiconductor device of claim 13, wherein the plurality of circuits including a memory interface circuit, a memory controller circuit, a word line circuit, and a bit line circuit, wherein the bit line circuit is connected to a bit line of the three-dimensional DRAM array structure, wherein the word line circuit is connected to a word line of the three-dimensional DRAM array structure, and wherein the memory interface circuit is connected to the memory controller circuit and the bit line circuit.

15. The semiconductor device of claim 13, wherein the plurality of circuits including a processor circuit, a memory controller circuit, a word line circuit, and a bit line circuit, wherein the bit line circuit is connected to a bit line of the three-dimensional DRAM array structure, wherein the word line circuit is connected to a word line of the three-dimensional DRAM array structure, and wherein the processor circuit is connected to the memory controller circuit and the bit line circuit.

16. The semiconductor device of claim 14 or 15, wherein the word line circuit is connected to a word line of the three-dimensional DRAM array structure by a wire and a via extending in the vertical direction.

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