A resistive random access memory based memory array structure and method of operating the same

Abstract

The application discloses a novel storage array structure based on a resistance change memory and an operation method thereof, and belongs to the technical field of semiconductor integrated circuits. The novel storage array structure comprises storage units arranged in an array, each of the storage units is formed by a transistor and an RRAM in series, the RRAM is located at the drain of the transistor, each two storage units on the same row share a source, each N columns of storage units share a P-type substrate, the P-type substrates are separated by DTI deep trench isolation, all the storage units share a deep N well DNW, the deep N well DNW is located below the P-type substrate, the RRAM top electrode of each row of storage units is connected through a bit line BL, and the transistor gate and source of each column of storage units are connected through a word line WL and a source line SL respectively. The application only needs to apply a small input signal, and high current output can be realized, so that the performance and reliability of the storage unit are significantly improved while the power consumption is reduced.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor, memory, and CMOS hybrid integrated circuit technology, and more specifically, to a novel memory array structure based on resistive random access memory and its operation method. Background Technology

[0002] With the development of information technology and the widespread application of big data, the Internet of Things, specialized hardware, and cloud computing, the requirements for storage density and performance of non-volatile memory are constantly increasing. Traditional flash memory, with its constant programming voltage, reliability and data retention characteristics sensitive to device size, and physical limitations such as charge discontinuity, has its storage density and performance further limited, making it difficult to meet future non-volatile memory demands. Resistive Random Access Memory (RRAM), which can switch between high and low resistance states based on the voltage difference between two electrodes, is a promising new type of non-volatile memory with numerous advantages, including high storage density, fast erase and write speeds, ease of miniaturization and integration, and low power consumption.

[0003] 1T1R (1 Transistor 1 RRAM) is a common array structure for resistive random access memory (RRAM). Each cell in this structure consists of one RRAM and one transistor connected in series. The transistor acts as a selector; when it is turned on, the RRAM is selected and can be operated on; when it is turned off, the RRAM cannot be operated on. This structure enables random access and eliminates crosstalk.

[0004] However, traditional resistive random access memory (RRAM) structures have high requirements for the driving capability of the selector transistors and low parasitic resistance, which limits the storage density. During FORMING, SET, and RESET operations, the RRAM and the series-connected transistors form an equivalent voltage divider relationship. With a fixed total voltage difference, the larger the equivalent on-resistance of the transistors, the larger the voltage difference between the source and drain, and the smaller the voltage drop between the two electrodes of the RRAM. Therefore, the transistors need to have sufficiently small on-resistance, which severely limits the reduction of the transistor gate width, increases the cell size, and reduces the storage density of the RRAM. Since the RRAM itself occupies a very small area, reducing the area and spacing of the selector transistors by solving the above problems is an important means to improve the storage density of RRAMs. Summary of the Invention

[0005] This invention proposes a novel memory array structure and its operation method based on resistive random access memory, which relaxes the limitation on the minimum gate width of transistors without changing the performance.

[0006] A novel memory array structure based on resistive random access memory (RRAM) is characterized by comprising memory cells arranged in an array, each memory cell being formed by a transistor and a RRAM connected in series, the RRAM being located at the drain of the transistor, every two memory cells in the same row sharing a source, every N columns of memory cells sharing a P-type substrate, multiple P-type substrates being isolated from each other by a deep trench (DTI), all memory cells sharing a deep N-well (DNW) located below the P-type substrate, the top electrode of the RRAM of each row of memory cells being connected by a bit line (BL), and the gate and source of the transistors of each column of memory cells being connected by a word line (WL) and a source line (SL), respectively.

[0007] Furthermore, SL is located below the RRAM source of the memory cell and remains grounded.

[0008] Furthermore, every M rows of memory cells on the P-type substrate are provided with a transverse P+ doped region as a transverse substrate contact line, through which the potential of all memory cells on the entire P-substrate is controlled.

[0009] Furthermore, each P substrate is provided with a vertically oriented substrate lead-out line. The substrate contact line is connected to the vertically oriented substrate lead-out line through a through-hole, and the substrate contact line is controlled through the substrate lead-out line.

[0010] Furthermore, the edge of the deep N-well DNW is provided with an N+ type doped contact region, which is connected to a vertically oriented substrate lead-out line through a via.

[0011] Meanwhile, this invention provides an operation method for a novel memory array structure based on resistive random access memory, the steps of which include the following:

[0012] 1) When writing SET, apply a high level to BL and WL where the selected memory cell is located, and keep the rest of the connection grounded to the substrate. When the transistor in the memory cell to be written is turned on, the top electrode of the RRAM is BL high level and the bottom electrode is grounded, and is set to a low impedance state.

[0013] 2) During RESET, a high level is applied to the substrate of the memory cell to be erased, where the DNW has a higher level than the P-type substrate and the BL is grounded; WL is also grounded. At this time, all transistors are turned off, and the array is equivalent to a 1T1R array with BJTs as the selectors.

[0014] 3) During reading, a logic level is applied to the selected memory cell WL, and a smaller RRAM read voltage is applied to BL to achieve random access.

[0015] The beneficial effects of this invention are as follows:

[0016] Compared to existing resistive switching memory cell RESET methods based on the forward bias of a parasitic PN junction between a P-type substrate and the drain, the bipolar junction transistor (BJT) structure used in this invention significantly improves driving capability during the RESET operation. It relaxes the limitation on the minimum gate width of the transistor without changing performance, and only requires a small input signal to achieve high current output, thereby significantly improving the performance and reliability of the memory cell while reducing power consumption. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of the storage cell in the novel storage array structure of the present invention;

[0018] Figure 2 This is a schematic diagram of the novel storage array structure of the present invention;

[0019] Figure 3 This is a partial cross-sectional schematic diagram of the novel storage array structure of the present invention;

[0020] Figure 4 This is a cross-sectional schematic diagram of the novel storage array structure of the present invention;

[0021] Figure 5 This is a top view schematic diagram of the novel storage array structure of the present invention. Detailed Implementation

[0022] The present invention will be further described below with reference to specific embodiments and accompanying drawings.

[0023] This invention relates to a novel memory array structure based on resistive random access memory (RRAM), comprising several memory cells, such as... Figure 1 As shown, each memory cell is formed by a transistor and a RRAM connected in series, with the RRAM located at the transistor drain. Every two memory cells in the same row share a source. In this invention, every N columns of memory cells share a P-type substrate, and all memory cells share a deep n-well (DNW) located below the P-type substrate. With this structure, the deep n-well, P-type substrate, and transistor drain together constitute an NPN bipolar junction transistor (BJT). In this BJT, the deep n-well serves as the collector, the P-type substrate as the base, and the transistor drain as the emitter.

[0024] like Figure 2 As shown, in the novel memory array structure based on resistive random access memory of the present invention, the top electrode of each row cell RRAM is connected through a bit line (BL), and the gate and source of each column cell transistor are connected through a word line WL and a source line SL, respectively; wherein SL is located below the source and can be grounded.

[0025] During the write (SET) operation, a high-level signal is applied to the BL and WL pins of the selected memory cell, while the remaining connections are grounded to the substrate. The transistor in the memory cell to be written to is turned on, the top electrode of the RRAM is at a high level (BL), and the bottom electrode is approximately grounded, thus being set to a low-impedance state. Random writing can be achieved through cross-selection of BL and WL.

[0026] During the reset process, a high voltage level is applied to the substrate of the memory cell to be erased, with the DNW layer having a higher voltage level than the P-type substrate and its base plate (BL) grounded; the base plate (WL) layer is also grounded. At this time, all transistors are turned off, and the array is equivalent to a 1T1R array with BJTs as the gate transistors. The substrate voltage of the memory cell to be erased is high, while the top electrode of the RRAM is grounded. The emitter junction of the BJT formed by the substrate and drain is forward biased, and the collector junction is reverse biased. The BJT is in the forward active region (FAR), enabling linear amplification. The amplified current is output from the transistor drain (i.e., the BJT emitter) to the bottom electrode of the RRAM, setting the RRAM to a high-impedance state. Simultaneously, the non-selected cell's BL layer is connected to the same voltage level as the deep N-well, and the P-type substrate of the non-selected cell is grounded, protecting the non-selected cell. At this time, no voltage is directly applied between the two electrodes of the non-selected memory cell RRAM; and the parasitic PN junction between the base and emitter has a large reverse breakdown voltage, allowing only unidirectional current flow, cutting off crosstalk and leakage paths. Therefore, there is no crosstalk problem during the erase operation.

[0027] During reading, a logic level is applied to the target memory cell WL, and a small RRAM read voltage is applied to BL, enabling random access.

[0028] A cross-sectional view of the novel memory array structure based on resistive random access memory (RRAM) of this invention is shown below. Figure 3 Each memory cell is formed by a transistor connected in series with a RRAM, with the RRAM located at the drain of the transistor. Every two memory cells in the same row share a source. Every N columns of memory cells share a P-substrate (PW), and all memory cells share a DNW.

[0029] like Figure 4 As shown, a total of 4N column memory devices can be placed on each P substrate (N is the number of columns of memory cells on the substrate, which is a positive integer). The P-type substrates are isolated from each other by DTI deep trenches. Individual voltages can be applied to each part of the substrate through the substrate leads. The P-type substrates are isolated from each other by DTI deep trenches. The deep N-well DNW is located below the P-type substrate. The top electrode of the RRAM of each row of memory cells is connected by the bit line BL. The gate and common source of the transistor of each column of memory cells are connected by the word line WL and the source line SL, respectively.

[0030] like Figure 5As shown, each P-substrate has a vertically oriented substrate lead-out line, and every M rows of memory cells on the P-substrate has a long, horizontally oriented P+ doped region as a horizontal substrate contact (M is the number of memory cell rows, a positive integer). The potential of all memory cells on the entire P-substrate is controlled through the horizontal substrate contact lines. The substrate contact lines are connected to the vertically oriented substrate lead-out lines via vias, and the substrate contact lines and even the substrate potential are controlled through the led-out metal wires. A DTI (Digital Transmission Injection) is used to separate every two P-substrates. The DNW (Digital Transmission Wire) is connected to the vertically oriented substrate contact lines at the edge of the memory array via vias, or it can be led out using back-side power supply technology. This line can be grounded during use.

[0031] The specific operations for writing, erasing, and reading from a novel memory array structure based on resistive random access memory include the following steps:

[0032] 1) When BL k WL m When a write operation is performed on the located cell, the P-substrate containing that cell is grounded, and DNW is kept at a high level, causing the BJT emitter junction to be reverse-biased and the collector junction to be reverse-biased, operating in the cutoff region. For WL... m Applying a high level turns on the transistor, affecting BL. k By applying a write voltage and reading the response current through the corresponding SL of the cell, the write operation to that cell can be completed.

[0033] 2) When dealing with BL k WL m When erasing the located cell, an erasure voltage is applied to the P-substrate where the cell is located, and DNW is kept at a high level. It should be noted that the erasure voltage applied to the P-substrate should be lower than the high level of DNW, so that the BJT emitter junction is forward biased and the collector junction is reverse biased, operating in the amplification region. WL m and BL k All are grounded, with the non-selected WL grounded and the non-selected BL connected to the same high level as DNW. This reverse-biasses the emitter junction and collector junction of the BJT on the non-selected unit, putting it in the cutoff region and protecting the non-selected unit from parasitic effects. Through BL... k The erase operation of the cell can be completed by reading the response current.

[0034] 3) When dealing with BL k WL m When performing a read operation on the located cell, the P-substrate of that cell is grounded, and DNW is kept at a high level, causing the BJT emitter junction to be reverse-biased and the collector junction to be reverse-biased, operating in the cutoff region. For WL... m Applying a high level turns on the transistor, affecting BL. kBy applying a reading voltage and reading the response current through the corresponding SL of the cell, the reading operation of the cell can be completed.

[0035] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the claims.

Claims

1. A memory array structure based on resistive random access memory, characterized in that, The system includes arrayed memory cells, each formed by a transistor and a RRAM connected in series. The RRAM is located above the drain of the transistor. Every two memory cells in the same row share a source. Every N columns of memory cells share a P-type substrate. Multiple P-type substrates are isolated from each other by deep trenches (DTI). All memory cells share a deep N-well (DNW) located below the P-type substrate. The top electrode of the RRAM in each row of memory cells is connected by a bit line (BL). The gate and source of the transistor in each column of memory cells are connected by a word line (WL) and a source line (SL), respectively. Every M rows of memory cells on the P-type substrate have a lateral P+ doped region as a lateral substrate contact line, which controls the potential of all memory cells on the entire P-type substrate.

2. The memory array structure based on resistive random access memory as described in claim 1, characterized in that, The source line SL is located below the RRAM source of the memory cell and is kept grounded.

3. The memory array structure based on resistive random access memory as described in claim 1, characterized in that, Each P substrate has a vertically oriented substrate lead-out line. The substrate contact line is connected to the vertically oriented substrate lead-out line through a through-hole, and the substrate contact line is controlled through the substrate lead-out line.

4. The memory array structure based on resistive random access memory as described in claim 3, characterized in that, The edge of the deep N-well DNW is provided with an N+ type doped contact region, which is connected to a vertically oriented substrate lead-out through a via.

5. The operation method of the memory array structure based on resistive random access memory as described in claim 3, comprising the following steps: 1) When writing SET, apply a high level to BL and WL where the selected memory cell is located, and keep the other connections and substrate leads grounded. When the transistor in the memory cell to be written is turned on, the top electrode of RRAM is BL high level and the bottom electrode is grounded, and is set to a low impedance state. 2) During RESET, a high-level voltage is applied to the substrate containing the memory cell to be erased, with the voltage applied to DNW being higher than that of the P-type substrate, and BL being grounded; WL is also grounded. 3) During reading, a logic level is applied to the selected storage cell WL, and an RRAM read voltage is applied to BL to achieve random access.

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