Chip packaging structure and device

Abstract

The invention provides a chip packaging structure and equipment, and relates to the technical field of chip packaging. The chip packaging structure comprises a circuit board and a chip, the circuit board comprises at least two packaging areas, the packaging areas comprise a first packaging area and a second packaging area which are sequentially arranged in the first direction, the chip is at least packaged in the first packaging area and the second packaging area, each packaging area is composed of a first functional area, a second functional area and a third functional area, the first functional area, the second functional area and the third functional area are sequentially arranged in the first direction, the first functional area, the second functional area and the third functional area are sequentially arranged in the second direction perpendicular to the first direction, the data input and output point locations are distributed in the first functional area and the third functional area, and / or the differential clock signal point locations are distributed in the second functional area. The chip packaging structure provided by the invention is low in manufacturing process difficulty, flexible in signal point position arrangement, and beneficial to light and thin design of equipment.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and particularly to a chip packaging structure and device. Background Art

[0002] LPDDR (Low Power Double Data Rate SDRAM) chips are communication standards developed by the US JEDEC (Joint Electron Device Engineering Council) association for low-power memory. They are known for low power consumption and small size and are specifically used for mobile devices.

[0003] In the process of conceiving and implementing this application, the inventors found that there are at least the following problems: In some multi-channel (e.g., 4-channel) LPDDR chip packaging solutions, the LPDDR chips are stacked on a central processing unit (CPU), and the package-on-package (POP) process is used to directly package the LPDDR chips on the central processing unit. However, the method of packaging LPDDR chips on the central processing unit using the POP process has complex technology, high precision requirements, and great packaging difficulty. And / or, the height of the package is relatively large and it occupies more space, which is not conducive to the thin and light design of the device.

[0004] The foregoing description is for general background information and does not necessarily constitute prior art. Summary of the Invention

[0005] In view of the above technical problems, this application provides a chip packaging structure and device. The manufacturing process of the chip packaging structure has low difficulty, and the signal point layout is flexible, which is conducive to the thin and light design of the device.

[0006] One aspect of this application provides a chip packaging structure, including: a circuit board including at least two packaging areas, where the packaging areas include a first packaging area and a second packaging area arranged in sequence along a first direction; each packaging area includes a first functional area, a second functional area, and a third functional area arranged in sequence along a second direction, and the second direction is perpendicular to the first direction; chips are at least packaged in the first packaging area and the second packaging area; wherein, data input / output points are distributed in the first functional area and the third functional area, and / or, differential clock signal points are distributed in the second functional area.

[0007] Optionally, a set of clock points and a set of differential synchronization signal points are both arranged in the first functional area and the third functional area.

[0008] Optionally, each group of clock point positions includes a write clock point position and a read clock point position, and the write clock point position and the read clock point position are arranged diagonally adjacent or row-column adjacent.

[0009] Optionally, each group of differential synchronous signal point positions includes a differential write synchronous signal point position and a differential read synchronous signal point position, and the differential write synchronous signal point position and the differential read synchronous signal point position are arranged diagonally adjacent or row-column adjacent.

[0010] Optionally, the first encapsulation area is provided with 6 rows of signal point positions along the first direction, and the second encapsulation area is provided with 5 rows of signal point positions along the first direction.

[0011] Optionally, along the second direction, the first functional area includes 6 columns of signal point positions, the second functional area includes 4 columns of signal point positions, and the third functional area includes 7 columns of signal point positions.

[0012] Optionally, the chip select point positions are distributed in the second functional area.

[0013] Optionally, input data mask point positions are arranged in the first functional area and the third functional area.

[0014] Optionally, the encapsulation area further includes a third encapsulation area and a fourth encapsulation area arranged in sequence along the first direction.

[0015] Optionally, the third encapsulation area is symmetrically arranged with the second encapsulation area.

[0016] Optionally, the fourth encapsulation area is symmetrically arranged with the first encapsulation area.

[0017] Optionally, the chip further includes a chip encapsulated in the third encapsulation area and the fourth encapsulation area.

[0018] Optionally, there is at least one row of blank point positions between the second encapsulation area and the third encapsulation area.

[0019] Optionally, the diameter of the solder ball used to form the signal point position is 0.20 - 0.35 mm.

[0020] Optionally, along the first direction, the ball pitch between adjacent solder balls is 0.35 - 0.65 mm.

[0021] Optionally, along the second direction, the ball pitch between adjacent solder balls is 0.35 - 0.65 mm.

[0022] Another aspect of the present application provides a device, including the chip packaging structure described in any one of the above.

[0023] The device can be a chip (such as a storage chip, or an SOC chip set, etc.), or an electronic device (such as a smart terminal).

[0024] The chip packaging structure and device provided by the present application, the chip packaging structure includes a circuit board and a chip, the circuit board includes at least two packaging areas, the packaging areas include a first packaging area and a second packaging area arranged in sequence along a first direction, and the chip can be packaged in at least the first packaging area and the second packaging area. Each packaging area is composed of a first functional area, a second functional area and a third functional area, and the first functional area, the second functional area and the third functional area are arranged in sequence along a second direction perpendicular to the first direction. Among them, the data input / output points are distributed in the first functional area and the third functional area, or, the differential clock signal points are distributed in the second functional area, or, the data input / output points are all distributed in the first functional area and the third functional area, and the differential clock signal points are distributed in the second functional area.

[0025] In this way, the signal lines in the first packaging area and the second packaging area can all be led out from the first functional area, the second functional area and the third functional area arranged in the second direction, providing an independent wiring area, so that the chip and the central processing unit for controlling the chip can be connected in parallel on the circuit board through the wiring in the circuit board, without using the POP process for complex vertical stacking connection, and the manufacturing process difficulty is reduced. And / or, while reducing the thickness and improving the heat dissipation capacity, the mechanical stress caused by stacking can also be reduced, so that the long-term reliability of the package can be improved and it is beneficial to the thin and light design of the device.

[0026] Optionally, when the data input / output points are distributed in the first functional area and the third functional area on both sides of the packaging area, the flexible layout of the data input / output points for transmitting data can be realized, and the data transmission volume can be increased. And / or, the distribution on both sides of the data input / output points can also provide an independent wiring area for the data input / output signal lines of each packaging area, reducing signal crosstalk.

[0027] When the differential clock signal points are centrally arranged in the second functional area, the signal can be physically isolated from other types of signals as much as possible, reducing electromagnetic interference and crosstalk. And / or, it is also convenient to control the length matching, impedance control and symmetry of the signal path between the differential clock signal lines.

[0028] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions, and the beneficial effects brought by the technical features of these technical solutions, the other technical problems that the chip packaging structure and device provided by the embodiments of the present application can solve, the other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manner. Description of the Drawings

[0029] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other accompanying drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 A cross-sectional view of the chip packaging structure provided for the embodiments of this application;

[0031] Figure 2 An external connection schematic diagram of the chip packaging structure and the central processing unit provided for the embodiments of this application;

[0032] Figure 3 A layout schematic diagram of signal points on the circuit board provided for the embodiments of this application;

[0033] Figure 4 Another layout schematic diagram of signal points on the circuit board provided for the embodiments of this application;

[0034] Figure 5 A connection schematic diagram of the chip packaging structure and the central processing unit provided for the embodiments of this application;

[0035] Figure 6 Another connection schematic diagram of the chip packaging structure and the central processing unit provided for the embodiments of this application;

[0036] Figure 7 A hardware structure schematic diagram of a mobile terminal for implementing various embodiments of this application.

[0037] The implementation of the objectives of this application, functional features, and advantages will be further described in conjunction with the embodiments with reference to the accompanying drawings. Through the above accompanying drawings, the clear embodiments of this application have been shown, and there will be more detailed descriptions hereinafter. These accompanying drawings and text descriptions are not intended to limit the scope of the concept of this application in any way, but to explain the concept of this application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0038] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different accompanying drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are only examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0039] It should be noted that in this text, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising such element. Optionally, components, features, elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context in the specific embodiments.

[0040] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this text, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "upon" or "in response to determining". Furthermore, as used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising", "including" indicate the presence of the stated features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or", "and / or", "including at least one of the following" and the like used in this application can be interpreted inclusively, or mean any one or any combination. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C", and again, "A, B or C" or "A, B and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C". An exception to this definition only occurs when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0041] Depending on the context, the words "if", "when" as used herein can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detecting (stated condition or event)" can be interpreted as "when determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)".

[0042] It should be understood that the specific embodiments described herein are merely for explaining the present application and are not used to limit the present application.

[0043] In the following description, suffixes such as "module", "component", or "unit" used to represent elements are only for facilitating the description of the present application and have no specific meaning in themselves. Therefore, "module", "component", or "unit" can be used interchangeably.

[0044] The LPDDR chip is a type of volatile memory product, characterized by low power consumption and small size, and is specifically used for mobile devices. In some solutions, for the packaging scheme of multi-channel (e.g., 4-channel) LPDDR chips, the LPDDR chips are stacked on the Central Processing Unit (CPU). The Package on Package (POP) process is adopted to directly package the LPDDR chips on the central processor.

[0045] However, the method of packaging the LPDDR chip on the central processor using the POP process has complex technology, high precision requirements, and great packaging difficulty. And / or, the package occupies a relatively large space in the thickness direction, which is not conducive to the thinning of the device. And / or, the heat dissipation is more difficult with the chip stacking packaging method, which may lead to heat accumulation, an increase in chip temperature, and affect the device performance. And / or, due to the complexity of the stacking structure, the POP package may also face more reliability problems.

[0046] Taking the intelligent terminal as an example, as the consumer market has higher and higher requirements for the thinning, heat dissipation performance, and reliability of mobile phone products, using the POP process for packaging is not only not conducive to the optimization of the thickness of the mobile phone motherboard, but may also lead to a decline in the performance and reliability of the mobile phone motherboard due to an increase in the temperature of the motherboard chips and the failure of internal solder joints.

[0047] In view of this, the embodiments of the present application provide a chip packaging structure and a device. The chip packaging structure includes a circuit board and a chip. The circuit board includes at least two packaging areas. The packaging areas include a first packaging area and a second packaging area arranged in sequence along a first direction. The chip can be at least packaged in the first packaging area and the second packaging area. Each packaging area is composed of a first functional area, a second functional area, and a third functional area, and the first functional area, the second functional area, and the third functional area are arranged in sequence along a second direction perpendicular to the first direction. Optionally, all the data input / output points are distributed in the first functional area and the third functional area. Optionally, the differential clock signal points are distributed in the second functional area. Optionally, all the data input / output points are distributed in the first functional area and the third functional area, and the differential clock signal points are distributed in the second functional area.

[0048] In this way, the signal lines in the first encapsulation area and the second encapsulation area can all be led out from the first functional area, the second functional area, and the third functional area arranged in the second direction, providing independent wiring areas. Thus, through the wiring within the circuit board, the chip and the central processing unit for controlling the chip can be connected side by side on the circuit board without using the complex vertical stacking connection of the POP process, reducing the manufacturing process difficulty. Moreover, while reducing the thickness and improving the heat dissipation capacity, the mechanical stress caused by stacking can also be reduced, thereby improving the long-term reliability of the encapsulation and facilitating the thin and light design of the device.

[0049] Optionally, when the data input / output points are distributed in the first functional area and the third functional area on both sides of the encapsulation area, flexible layout of multiple data input / output points for transmitting data can be achieved, increasing the amount of transmitted data. Optionally, the distribution on both sides of the data input / output points can also provide independent wiring areas for the data input / output signal lines of each encapsulation area, reducing signal crosstalk.

[0050] Optionally, when the differential clock signal points are centrally arranged in the second functional area, the signal can be physically isolated from other types of signals as much as possible, reducing electromagnetic interference and crosstalk. And / or, it is also convenient to control the length matching, impedance control, and symmetry of the signal paths between the differential clock signal lines.

[0051] The chip encapsulation structure provided by the embodiments of the present application and the device equipped with this chip encapsulation structure will be described in detail below.

[0052] The chip encapsulation structure provided by the embodiments of the present application can be applied to large devices or small devices. Among them, the device can be a terminal device, and the terminal device can also be called a terminal, a user equipment (UE), a mobile station (MS), a mobile terminal (MT), etc.

[0053] The devices include, but are not limited to, mobile phones, smart TVs, wearable devices, tablets (Pads), computers with wireless transceiver functions, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0054] Figure 1 This is a cross-sectional view of the chip packaging structure provided by the embodiments of this application. Refer to Figure 1 As shown, the chip packaging structure in this embodiment includes a circuit board 100 and a chip 200. The circuit board 100 is provided with at least two packaging areas 110 (not shown in the figure). Correspondingly, the chip 200 includes chips 200 packaged in at least two packaging areas 110.

[0055] Optionally, the chip 200 referred to here can be a memory, or the chip 200 is a storage chip. For example, the chip 200 is the aforementioned LPDDR chip. In addition to the chip 200, other devices can also be provided on the circuit board 100. Optionally, a processor, a power manager, and other devices can be provided on the circuit board 100. The circuit board 100 serves to carry these devices and realize the communication connection between these devices.

[0056] Optionally, one packaging area 110 can form a separate storage channel in the storage chip, which can facilitate designers to select and configure different storage channels according to needs to meet different performance and capacity requirements. And / or, by separately packaging the storage channels, faults can be isolated and the impact of single-point faults can be reduced. When adopting the architecture of multiple packaging areas 110, the storage chip controller can communicate with multiple storage channels simultaneously. And / or, each channel can independently transmit data, thereby improving the overall data throughput and system performance. Optionally, the storage chip controller can be a central processing unit 400 (as Figure 2 shown).

[0057] Optionally, the circuit board 100 can be the main board in the device. The circuit board 100 includes, but is not limited to, a printed circuit board (PCB), a flexible printed circuit (FPC), and a rigid-flex circuit board, etc.

[0058] Optionally, at least one chip 200 is disposed in one encapsulation area 110, and the specific number of chips 200 is not limited herein. Optionally, only one chip 200 is disposed in one encapsulation area 110, so that the design and manufacturing difficulty can be reduced, and the communication delay between the chips 200 can be reduced.

[0059] Optionally, multiple chips 200 (such as 2, 3, 4) can be disposed in one encapsulation area 110. In this way, the chips encapsulated in a single encapsulation area can be flexibly designed, with smaller chip volume and more flexible layout. The following takes an encapsulation area 110 composed of one chip 200 as an example for illustration.

[0060] Optionally, when two encapsulation areas 110 are arranged on the circuit board 100, the two encapsulation areas 110 can be arranged in a vertically juxtaposed or horizontally side-by-side manner, which is not limited herein. In this way, the arrangement mode between the encapsulation areas 110 can be flexibly adjusted according to specific requirements or the positions of other devices on the circuit board 100, so as to effectively utilize the space of the circuit board 100.

[0061] Optionally, the number of encapsulation areas 110 on the circuit board 100 can be an even number greater than or equal to 2. Correspondingly, the number of chips 200 is also an even number greater than or equal to 2. Taking the number of encapsulation areas 110 on the circuit board 100 equal to 4 as an example, every two encapsulation areas 110 can form a group of encapsulation areas 110, and can be symmetrically distributed in pairs with another group of encapsulation areas 110. The chips 200 included in each encapsulation area 110 are symmetrically arranged in pairs correspondingly. Thus, the subsequent connection wiring can be simplified.

[0062] Continue to refer to Figure 1 As shown, a plurality of electrical connection balls 300 are disposed between the chip 200 and the circuit board 100. The electrical connection balls 300 are used to electrically connect the chip 200 to the circuit board 100. The plurality of electrical connection balls 300 can be arranged in an array as a whole. Optionally, the electrical connection balls 300 generally refer to solder balls or conductive bumps. Optionally, the electrical connection balls 300 can be tin balls or copper balls.

[0063] Optionally, pins may be arranged in the edge area of the chip 200. The pins of the chip 200 are connected to the circuits arranged inside the chip 200, so as to lead out the internal circuit of the chip 200 through the pins and connect it to an external circuit. These electrical connection balls 300 can be electrically connected to the pins of the chip 200 through the circuits inside the chip 200. Thus, the circuit board 100 can transmit signals to an external circuit through the chip 200 to achieve the electrical connection between the chip 200 and the external circuit.

[0064] Optionally, each pin of the chip 200 has its specific function and is used to transmit signals with different functions. Optionally, each pin transmits signals such as data transmission signals, power supply signals, control signals, and ground signals between the chip 200 and an external circuit. When the chip 200 is packaged on the circuit board 100, the pins of the chip 200 are correspondingly electrically connected to the respective electrical connection balls 300 through the circuits inside the chip 200. This connection method can ensure that the signals on the pins can be accurately transmitted to the electrical connection balls 300, thereby realizing the signal transmission between the chip 200 and the external circuit.

[0065] Optionally, the several electrical connection balls 300 arranged between the chip 200 and the circuit board 100 can be regarded as several signal points arranged in the packaging area 110 of the circuit board 100, and these several signal points are led out by the respective pins of the chip 200. Among them, each signal point is used to transmit different signals.

[0066] Figure 2 is an external connection schematic diagram of the chip packaging structure provided by the embodiment of the present application. Refer to Figure 2 As shown, the chip packaging structure further includes a central processing unit 400, and the central processing unit 400 is packaged on the circuit board 100. Optionally, the central processing unit 400 can be connected to the circuit board 100 through the electrical connection balls 300 to reduce the signal path length and improve the electrical performance. And / or, the central processing unit 400 can achieve electrical connection with each chip 200 through the wiring inside the circuit board 100, so that the central processing unit 400 can adjust and control the working states of the respective chips 200.

[0067] Optionally, the central processing unit 400 is arranged on the same side of each packaging area 110. With such an arrangement, the circuits arranged in the respective packaging areas 110 on the circuit board 100 can be led out from one side of the chip 200, thereby simplifying the circuits arranged between the chip packaging structure and the central processing unit 400 and reducing the wiring difficulty of the circuit board 100. Taking Figure 2 the paper surface direction shown as an example, the central processing unit 400 is arranged on the left side of each chip 200, and the circuits arranged in the packaging area 110 on the circuit board 100 can all be led out from the left side of the chip 200.

[0068] Figure 3This is a layout schematic diagram of signal points on the circuit board provided by the embodiments of the present application. Refer to Figure 3 As shown, the package area 110 on the circuit board 100 may include a first package area 111 and a second package area 112. Correspondingly, the chip 200 may be packaged in the first package area 111 and the second package area 112. Optionally, signal points are provided near the central processing unit 400 in both the first package area 111 and the second package area 112, so as to facilitate the wiring connection between the first package area 111, the second package area 112 and the central processing unit 400. Optionally, the first package area 111 and the second package area 112 may be arranged in sequence along a first direction. Wherein, the first direction may be Figure 3 and Figure 4 the Y direction shown in Figure 3 and Figure 4 the X direction perpendicular to the Y direction in

[0069] Optionally, the arrangement of the first package area 111 and the second package area 112 in the first direction can be set flexibly. Optionally, the first package area 111 and the second package area 112 may be arranged adjacent to each other along the first direction, or the first package area 111 and the second package area 112 may be arranged at intervals in the first direction.

[0070] The first package area 111 and the second package area 112 together form a basic package unit, and at least one basic package unit is provided on the circuit board 100. On this basis, other package units may also be provided on the circuit board, and the other package units may be symmetrically arranged with the basic package unit.

[0071] Optionally, since each package area 110 is electrically connected to the circuit board 100 through a plurality of electrical connection balls 300. Therefore, the area occupied by one electrical connection ball 300 can be defined as a signal point. The spaced arrangement between the first package area 111 and the second package area 112 here means that the first package area 111 and the second package area 112 are completely separated in the first direction. Optionally, there are blank signal points at intervals in the adjacent areas of the first package area 111 and the second package area 112 in the first direction. That is to say, there are signal points where the electrical connection balls 300 are not provided in the adjacent areas of the first package area 111 and the second package area 112.

[0072] The close arrangement between the first encapsulation area 111 and the second encapsulation area 112 here means that at the adjacent part of the first encapsulation area 111 and the second encapsulation area 112 in the first direction, they are not completely separated. Optionally, there is at least one adjacent area between the first encapsulation area 111 and the second encapsulation area 112 in the first direction where there is no blank point interval. That is to say, in the first direction, there is at least one signal point position for the electrical connection ball 300 arranged in the adjacent area between the first encapsulation area 111 and the second encapsulation area 112.

[0073] Optionally, both the first encapsulation area 111 and the second encapsulation area 112 can be designed to be narrow and long. The first direction is the width direction of the first encapsulation area 111 and the second encapsulation area 112, and the second direction is the length direction of the first encapsulation area 111 and the second encapsulation area 112. In this way, for the encapsulation unit formed by the first encapsulation area 111 and the second encapsulation area 112 as a whole, the length and width are closer, approximately in the shape of a square. The layout of the encapsulation unit is more reasonable, the signal point positions are more evenly distributed, which is convenient for chip design and encapsulation. And / or, on the basis of this encapsulation unit, other encapsulation units are symmetrically added, and the overall layout design is more regular.

[0074] The following takes the case where the first encapsulation area 111 and the second encapsulation area 112 are closely arranged in the first direction as an example for description, as Figure 3 shown, each signal point position can be arranged in an array along the X direction and the Y direction. A group of signal point positions located at the same part in the X direction and arranged in sequence along the Y direction is defined as a column of signal point positions. A group of signal point positions located at the same part in the Y direction and arranged in sequence along the X direction is defined as a row of signal point positions. Optionally, the first encapsulation area 111 and the second encapsulation area 112 can have signal point positions in different rows or different columns.

[0075] Optionally, each encapsulation area 110 can be divided into three sub-areas. In this embodiment, the three sub-areas are respectively defined as the first functional area 121, the second functional area 122, and the third functional area 123. The first functional area 121, the second functional area 122, and the third functional area 123 can be arranged in sequence along the second direction.

[0076] Optionally, within the encapsulation area 110, all signal point positions (or all electrical connection balls 300) are distributed in the first functional area 121, the second functional area 122, and the third functional area 123, and there are no signal point positions (or electrical connection balls 300) in the area outside the first functional area 121, the second functional area 122, and the third functional area 123.

[0077] Optionally, the arrangement of the first functional area 121, the second functional area 122, and the third functional area 123 in the second direction can be flexibly set. Optionally, the first functional area 121, the second functional area 122, and the third functional area 123 can be arranged adjacent to each other along the second direction, or the first functional area 121, the second functional area 122, and the third functional area 123 can be arranged at intervals in the second direction. Optionally, the first functional area 121 is arranged adjacent to the second functional area 122, and the second functional area 122 is arranged at intervals from the third functional area 123. Optionally, the first functional area 121 is arranged at intervals from the second functional area 122, and the second functional area 122 is arranged adjacent to the third functional area 123.

[0078] Optionally, the arrangement at intervals here means that the adjacent functional areas in the second direction are completely separated, and there are blank points at intervals at the adjacent positions of the adjacent functional areas in the second direction. The adjacent arrangement means that the adjacent functional areas in the second direction are not completely separated, and there is at least one position without a blank point at the adjacent position of the adjacent functional areas in the second direction. By arranging the first functional area 121, the second functional area 122, and the third functional area 123 adjacent to each other, the space occupied by the packaging area 110 on the circuit board 100 can be reduced, thereby reducing the overall volume of the packaging area 110 and facilitating the arrangement of other devices on the circuit board 100. And / or, it can also shorten the wiring length, improve the transmission speed, and reduce signal delay and signal attenuation.

[0079] The following takes the case where the first functional area 121, the second functional area 122, and the third functional area 123 are arranged adjacent to each other along the second direction as an example for description. Continue to refer to Figure 3 As shown, along the first direction, the first packaging area 111 can be provided with 6 rows of signal points, and the second packaging area 112 can be provided with 5 rows of signal points. That is, the 6 rows of signal points from the Figure 3 Ath row to the Fth row are the encapsulated range of the first packaging area 111. The 5 rows of signal points from the Gth row to the Lth row are the encapsulated range of the second packaging area 112. And / or, both the first packaging area 111 and the second packaging area 112 can include 17 columns of signal points.

[0080] Optionally, the first functional area 121, the second functional area 122, and the third functional area 123 arranged in sequence along the second direction together form the 17 columns of signal points included in each packaging area 110. Optionally, the first functional area 121 includes 6 columns of signal points, the second functional area 122 includes 4 columns of signal points, and the third functional area 123 includes 7 columns of signal points. That is, the 1st column to the 6th column are the first functional area 121. The 7th column to the 10th column are the second functional area 122. The 11th column to the 17th column are the third functional area 123.

[0081] Optionally, the first functional area 121 of the first encapsulation area 111 may be the overlapping area enclosed by columns 1 - 6 and rows A - F. The second functional area 122 of the first encapsulation area 111 may be the overlapping area enclosed by columns 7 - 10 and rows A - F. The third functional area 123 of the first encapsulation area 111 may be the overlapping area enclosed by columns 11 - 17 and rows A - F.

[0082] Optionally, the first functional area 121 of the second encapsulation area 112 may be the overlapping area enclosed by columns 1 - 6 and rows G - L. The second functional area 122 of the second encapsulation area 112 may be the overlapping area enclosed by columns 7 - 10 and rows G - L. The third functional area 123 of the second encapsulation area 112 may be the overlapping area enclosed by columns 11 - 17 and rows G - L.

[0083] Optionally, all signal points within the encapsulation area 110 may include data input / output points (DQ), power input / output points (VDD), ground points (VSS), chip select points (CS), address points (CA), clock points (WCK), differential clock signal points (CK), differential synchronous signal points (RDQS), and input data mask points (DMI).

[0084] Optionally, among the signal points of the first encapsulation area 111 and the second encapsulation area 112 close to the central processing unit 400, at least one data input / output point (DQ) is arranged, or at least one blank point is arranged, or at least one data input / output point (DQ) and at least one blank point are arranged.

[0085] Optionally, when at least one data input / output point (DQ) is arranged in a row of signal points of the first encapsulation area 111 and the second encapsulation area 112 close to the central processing unit 400, the signal transmission distance will be significantly shortened, thereby reducing the delay of data transmission. And / or, the shorter transmission path can support higher frequencies and faster data transmission rates to achieve fast processing of a large amount of data.

[0086] When there are also multiple blank points arranged in a row of signal points of the first encapsulation area 111 and the second encapsulation area 112 close to the central processing unit 400, it is convenient for the wiring connection between the chip 200 and the circuit board 100 to reduce the possible electromagnetic interference and crosstalk between signal lines.

[0087] Optionally, the following details the distribution design of each signal point in the first encapsulation area 111 and the second encapsulation area 112. Optionally, when there are two encapsulation areas 110, i.e., the first encapsulation area 111 and the second encapsulation area 112, on the circuit board 100, the electrically conductive balls 300 arranged in each encapsulation area 110 can serve as a separate signal transmission channel for the chip 200. As Figure 3 shown, the first encapsulation area 111 can form a separate signal transmission channel A for the chip 200. The second encapsulation area 112 can form a separate signal transmission channel C for the chip 200.

[0088] Optionally, the data input / output points (DQ) for data transmission can all be distributed in the first functional area 121 and the third functional area 123. By clearly defining the areas where the data input / output points (DQ) are located, flexible arrangement of multiple data input / output points (DQ) can be achieved. It is also convenient for the layout design of other signal points. And / or, the distribution on both sides of the data input / output points (DQ) can also provide an independent wiring area for each encapsulation area 110, reducing signal crosstalk. And / or, the chip 200 can be connected to the circuit board 100 by directly leading out from one side of the encapsulation area 110, realizing the parallel connection of the chip 200 and the central processing unit 400 on the circuit board 100.

[0089] Optionally, since the central processing unit 400 is arranged on one side of the chip 200, distributing the data input / output points (DQ) on the side close to the central processing unit can also reduce the signal delay in data transmission and facilitate wiring.

[0090] Optionally, the number of data input / output points (DQ) arranged in the first functional area 121 can be the same as the number of data input / output points (DQ) arranged in the third functional area 123. By evenly distributing all the data input / output points (DQ), the phenomenon that one of the first functional area 121 and the third functional area 123 has too many data input / output points (DQ) can be avoided. And / or, it can also leave more space in the first functional area 121 and the third functional area 123 for arranging other signal points.

[0091] Optionally, in this embodiment, all the data input / output points (DQ) arranged in one of the first functional area 121 and the third functional area 123 in a single encapsulation area 110 are defined as the first group of data input / output points, and all the data input / output points (DQ) arranged in the other of the first functional area 121 and the third functional area 123 in a single encapsulation area 110 are defined as the second group of data input / output points. The first group of data input / output points and the second group of data input / output points both include the same number of data input / output points (DQ).

[0092] Optionally, on the basis that the number of data input / output points (DQ) in the first set of data input / output points and the second set of data input / output points is the same, this embodiment does not limit the layout positions of the data input / output points (DQ) in the first set of data input / output points and the layout positions of the data input / output points (DQ) in the second set of data input / output points.

[0093] Optionally, with reference to Figure 3 As shown, the number of data input / output points (DQ) in each encapsulation area 110 is the same, and the number of data input / output points (DQ) in a single encapsulation area 110 can be 16. That is, both the first encapsulation area 111 and the second encapsulation area 112 are provided with 16 data input / output points (DQ), which are respectively set as DQ0 - DQ15. Among them, the number of the first set of data input / output points is 8, which are respectively DQ0 - DQ7. The number of the second set of data input / output points is also 8, which are respectively DQ8 - DQ15.

[0094] Optionally, taking the chip 200 as the A channel as an example, the 16 data input / output points (DQ) in the A channel are respectively DQ0 A - DQ15 A. Optionally, taking the layout of the first set of data input / output points in the first functional area 121 and the layout of the second set of data input / output points in the third functional area 123 as an example, the 8 data input / output points (DQ) arranged in the first functional area 121 are respectively DQ0A - DQ7 A, and the 8 data input / output points (DQ) arranged in the third functional area 123 are respectively DQ8A - DQ15A. The 8 data input / output points (DQ) DQ0A - DQ7A arranged in the first functional area 121 are distributed in rows B - F, columns 1 - 2, and columns 4 - 6. The 8 data input / output points (DQ) DQ8A - DQ15A arranged in the second functional area 122 are distributed in rows B - F, columns 11 - 16.

[0095] Optionally, taking the C channel of the chip 200 as an example, the 16 data input / output points (DQ) in the C channel are also DQ0 A - DQ15 A. Optionally, taking the arrangement of the first set of data input / output points in the first functional area 121 and the second set of data input / output points in the third functional area 123 as an example, the 8 data input / output points (DQ) arranged in the first functional area 121 are DQ0C - DQ7C respectively, and the 8 data input / output points (DQ) arranged in the third functional area 123 are DQ8C - DQ15C respectively. The 8 data input / output points (DQ) DQ0C - DQ7C arranged in the first functional area 121 are distributed in rows G - L, columns 1 - 2, and columns 5 - 6. The 8 data input / output points (DQ) DQ8C - DQ15C arranged in the third functional area 123 are distributed in rows G - H, rows K - L, columns 11 - 13, and columns 15 - 16. In this way, the data input / output points are preferentially arranged in a limited space, improving the data throughput, and thus significantly enhancing the data transmission capacity and parallel processing capacity of the chip 200.

[0096] Optionally, in the row of signal points closest to the central processing unit 400 in the first packaging area 111 (A channel) and the second packaging area 112 (C channel), that is, in the first column of signal points, at least one data input / output point (DQ) and at least one blank point can be arranged.

[0097] Optionally, the data input / output points (DQ) are preferentially arranged close to the central processing unit 400, which not only facilitates the wiring of the data input / output signal lines, but also can shorten the signal transmission path, reduce signal delay and attenuation, and improve signal integrity. And / or, the setting of multiple blank points facilitates the wiring connection with the central processing unit 400, can ensure that there is enough spacing between adjacent lines, and the risk of short - circuit of the lines arranged in the circuit board 100 and the chip 200 is small, thus improving the reliability of the chip packaging structure.

[0098] Optionally, in the first column of signal points in the first packaging area 111 and the second packaging area 112, the blank points can be arranged at least on one side of the data input / output points (DQ) for easy wire routing.

[0099] Optionally, in the first column of signal points in the first packaging area 111, two data input / output points (DQ) can be arranged, and there is a blank point between the two data input / output points (DQ). Or, in the first column of signal points in the second packaging area 112, two data input / output points (DQ) are arranged, and there is a blank point between the two data input / output points (DQ).

[0100] Optionally, in the first column of signal points in the first encapsulation area 111 and the second encapsulation area 112, two data input / output points (DQ) can be provided, and there is a blank point between the two data input / output points (DQ).

[0101] Optionally, by leaving a blank point between the two data input / output points, it is convenient for the routing setting of the data input / output signal lines, and / or physical isolation of different data input / output points can be achieved, reducing the electromagnetic interference between adjacent signal lines and improving the signal integrity and transmission quality. And / or, a thermal buffer can also be established to help with heat dissipation and prevent the performance of the data input / output points from being affected by overheating.

[0102] Optionally, a set of clock points (WCK) can be provided in both the first functional area 121 and the third functional area 123 of each encapsulation area 110. The clock points (WCK) can achieve precise alignment of the timing. Optionally, each set of clock points (WCK) can include a write clock point (WCK T) and a read clock point (WCK C).

[0103] Optionally, the write clock point (WCK T) and the read clock point (WCK C) are arranged diagonally adjacent. That is, the write clock point (WCK T) and the read clock point (WCK C) are located at the diagonal ends of adjacent rows and adjacent columns (as Figure 3 shown). Optionally, the write clock point (WCK T) and the read clock point (WCK C) are arranged adjacent in rows and columns. For example, the write clock point (WCK T) and the read clock point (WCK C) can be arranged at adjacent positions in the same row, and the write clock point (WCK T) and the read clock point (WCK C) can also be arranged at adjacent positions in the same column.

[0104] With such an arrangement, it is easier to achieve the synchronization of the clock signals, which helps to ensure that the clock signals for the write and read operations are consistent, improving the reliability of data transmission. It can also reduce the crosstalk and interference between signals and improve the signal integrity. And / or, it can also provide a more flexible routing path selection, reducing the complexity and crossing of the routing, simplifying the routing design, and reducing the manufacturing cost.

[0105] In this embodiment, two sets of clock points (WCK) are arranged in a single packaging area 110, and the two sets of clock points can be respectively defined as a first clock point (WCK0) and a second clock point (WCK1). One of the first clock point (WCK0) and the second clock point (WCK1) can be arranged in the first functional area 121, and the other can be arranged in the third functional area 123. The first clock point (WCK0) includes an adjacent first write clock point (WCK0 T) and a first read clock point (WCK0C), and the second clock point (WCK1) can include an adjacent second write clock point (WCK1 T) and a second read clock point (WCK1 C).

[0106] As Figure 3 shown, taking the chip 200 as channel A as an example, the first clock point (WCK0) can be located in the first functional area 121, the first write clock point (WCK0 T A) can be located at the 4th column of the Dth row in the first functional area 121, and the first read clock point (WCK0 C A) can be located at the 3rd column of the Eth row in the first functional area 121. The second clock point (WCK1) can be located in the third functional area 123, the second write clock point (WCK1 T A) can be located at the 12th column of the Dth row in the third functional area 123, and the second read clock point (WCK1 C A) can be located at the 13th column of the Eth row in the third functional area 123.

[0107] Optionally, taking the chip 200 as channel C as an example, the first clock point (WCK0) can be located in the first functional area 121, the first write clock point (WCK0 T C) can be located at the 4th column of the Kth row in the first functional area 121, and the first read clock point (WCK0 C C) can be located at the 3rd column of the Jth row in the first functional area 121. The second clock point (WCK1) can be located in the third functional area 123, the second write clock point (WCK1 T C) can be located at the 13th column of the Jth row in the third functional area 123, and the second read clock point (WCK1 C C) can be located at the 12th column of the Kth row in the third functional area 123.

[0108] Optionally, a set of differential synchronous signal points (RDQS) can be provided in both the first functional area 121 and the third functional area 123 of each packaging area 110. The differential synchronous signal points (RDQS) can implement the read operation of synchronous data.

[0109] Optionally, each group of differential synchronous signal points (RDQS) may include a differential write synchronous signal point (RDQS T) and a differential read synchronous signal point (RDQS C). The differential write synchronous signal point (RDQS T) and the differential read synchronous signal point (RDQS C) may be arranged adjacent diagonally or adjacent in rows and columns. This facilitates the positioning of the differential synchronous signal points (RDQS) and also facilitates the layout of the differential synchronous lines (for transmitting differential synchronous signals) within the circuit board 100 and the chip 200.

[0110] In this embodiment, two groups of differential synchronous signal points (RDQS) may be arranged within a single packaging area 110. In this embodiment, the two groups of differential synchronous signal points (RDQS) are respectively defined as a first differential synchronous signal point (RDQS0) and a second differential synchronous signal point (RDQS1). One of the first differential synchronous signal point (RDQS0) and the second differential synchronous signal point (RDQS1) may be arranged in the first functional area 121, and the other may be arranged in the third functional area 123. The first differential synchronous signal point includes an adjacent first differential read synchronous signal point (RDQS0 C) and a first differential write synchronous signal point (RDQS0 T), and the second differential synchronous signal point may include an adjacent second differential read synchronous signal point (RDQS1C) and a second differential write synchronous signal point (RDQS1 T).

[0111] Optionally, for the one of the first differential synchronous signal point (RDQS0) and the second differential synchronous signal point (RDQS1) arranged in the first functional area 121, the differential read synchronous signal point (RDQSC) and the differential write synchronous signal point (RDQS T) in this group of differential synchronous signal points (RDQS) may be arranged adjacent along the first direction, or adjacent along the second direction, or adjacent diagonally.

[0112] Optionally, as Figure 3 shown, taking the chip 200 as channel A as an example, the first differential synchronous signal point (RDQS0 A) may be located in the first functional area 121, the first differential read synchronous signal point (RDQS0C A) may be located in the 3rd column of the Cth row in the first functional area, and the first differential write synchronous signal point (RDQS0T A) may be located in the 4th column of the Bth row in the third functional area 123. The second differential synchronous signal point (RDQS1 A) may be located in the third functional area 123, the second differential read synchronous signal point (RDQS1C A) may be located in the 14th column of the Dth row in the third functional area 123, and the second differential write synchronous signal point (RDQS1T A) may be located in the 15th column of the Cth row in the third functional area 123.

[0113] Optionally, taking the chip 200 as the C channel as an example, the first differential synchronous signal point (RDQS0 C) may be located in the first functional area 121. The first differential read synchronous signal point (RDQS0 C C) may be located at the 4th column of the Hth row in the first functional area. The first differential write synchronous signal point (RDQS0 T C) may be located at the 3rd column of the Gth row in the third functional area 123. The second differential synchronous signal point (RDQS1 C) may be located in the third functional area 123. The second differential read synchronous signal point (RDQS1 C C) may be located at the 14th column of the Hth row in the third functional area 123. The second differential write synchronous signal point (RDQS1 T C) may be located at the 15th column of the Jth row in the third functional area 123.

[0114] Optionally, an input data mask point (DMI) may be evenly arranged in both the first functional area 121 and the third functional area 123 in a single packaging area 110. In this embodiment, the two input data mask points (DMI) are respectively defined as the first input data mask point (DMI0) and the second input data mask point (DMI1). Among them, one of the first input data mask point (DMI0) and the second input data mask point (DMI1) may be located in the first functional area 121, and the other may be located in the third functional area 123.

[0115] Optionally, as Figure 3 shown, taking the chip 200 as the A channel as an example, the first input data mask point (DMI0 A) is arranged at the 3rd column of the Fth row in the first functional area 121, and the second input data mask point (DMI1 A) is arranged at the 14th column of the Fth row in the third functional area 123.

[0116] Optionally, taking the chip 200 as the C channel as an example, the first input data mask point (DMI0 C) is arranged at the 3rd column of the Lth row in the first functional area 121, and the second input data mask point (DMI1 C) is arranged at the 14th column of the Kth row in the third functional area 123.

[0117] Optionally, the main signal points of the second functional area 122 are introduced below. As Figure 3 shown, differential clock signal points (CK) are distributed in the second functional area 122. Optionally, a group of differential clock signal points (CK) are arranged in the second functional area 122. Optionally, each group of differential clock signal points (CK) may include a write differential clock signal point (CK T) and a read differential clock signal point (CK C).

[0118] Optionally, the write differential clock signal point (CK T) and the read differential clock signal point (CK C) are diagonally adjacent. That is, the write differential clock signal point (CK T) and the read differential clock signal point (CK C) are located at the diagonal ends of adjacent rows and adjacent columns.

[0119] With such a setting, it is convenient to locate the differential clock signal point (CK), and it is also convenient to lay out the differential clock lines (for transmitting differential clock signals) in the circuit board 100 and the chip 200.

[0120] In this embodiment, a group of differential clock signal points (CK) are arranged in a single packaging area 110, and this group of differential clock signal points (CK) are arranged in the second functional area 122. That is to say, both the write differential clock signal point (CK T) and the read differential clock signal point (CK C) are arranged in the second functional area 122.

[0121] As Figure 3 shown, taking the chip 200 as the A channel as an example, the write differential clock signal point (CK T A) can be located at the 8th column of the Dth row in the second functional area 122, and the read differential clock signal point (CK C A) can be located at the 9th column of the Eth row in the second functional area 122.

[0122] Optionally, taking the chip 200 as the C channel as an example, the write differential clock signal point (CK T C) can be located at the 8th column of the Hth row in the second functional area 122, and the read differential clock signal point (CK C C) can be located at the 9th column of the Jth row in the second functional area 122.

[0123] Optionally, chip select points (CS) are also distributed in the second functional area 122. Optionally, the chip select points (CS) can include a first chip select point (CS 0) and a second chip select point (CS1). And / or, the first chip select point (CS 0) and the second chip select point (CS1) are diagonally adjacent.

[0124] With such a setting, it is convenient to locate the chip select point (CS), and it is also convenient to lay out the chip select signal lines (for transmitting chip select signals) in the circuit board 100 and the chip 200.

[0125] In this embodiment, a group of chip select points (CS) are arranged in a single packaging area 110, and this group of chip select points (CS) are all arranged in the second functional area 122. That is to say, both the first chip select point (CS 0) and the second chip select point (CS1) are arranged in the second functional area 122.

[0126] Optionally, as Figure 3As shown, taking the chip 200 as the A channel as an example, the first chip select point (CS 0A) and the second chip select point (CS1A) can be located at the 7th column of the C row and the 8th column of the B row in the second functional area 122 respectively.

[0127] Optionally, taking the chip 200 as the C channel as an example, the first chip select point (CS 0C) and the second chip select point (CS1C) can be located at the 8th column of the K row and the 9th column of the L row in the second functional area 122 respectively.

[0128] Optionally, some address points (CA) are also arranged in the second functional area 122. Multiple address points (CA) can be set, and are preferably set in the signal points in the second functional area 122 that are not occupied. And the remaining address points (CA) can be arranged adjacent to the second functional area 122. For example, the remaining address points (CA) can be set in the signal points in the adjacent column of the first functional area 121 close to the second functional area 122. The remaining address points (CA) can also be set in the signal points in the adjacent column of the third functional area 123 close to the second functional area 122. Of course, the remaining address points (CA) can also be set in the signal points in the adjacent column of the first functional area 121 close to the second functional area 122 and the adjacent column of the third functional area 123 close to the second functional area 122. In this embodiment, multiple address points (CA) are arranged in a single packaging area 110, and the multiple address points (CA) include a first address point (CA0), a second address point (CA1), a third address point (CA2), a fourth address point (CA3), a fifth address point (CA4), a sixth address point (CA5), and a seventh address point (CA6).

[0129] Optionally, as Figure 3 shown, taking the chip 200 as the A channel as an example, the first address point (CA0 A) can be located at the 6th column of the D row in the first functional area 121, the second address point (CA1 A) can be located at the 7th column of the E row in the second functional area 122. The third address point (CA2 A) can be located at the 8th column of the F row in the second functional area 122. The fourth address point (CA4 A) can be located at the 9th column of the C row in the second functional area 122. The fifth address point (CA5 A) can be located at the 10th column of the F row in the second functional area 122. The sixth address point (CA6 A) can be located at the 10th column of the D row in the second functional area 122. The seventh address point (CA7 A) can be located at the 10th column of the B row in the second functional area 122.

[0130] Optionally, taking the chip 200 as an example of the C channel, the first address point (CA0 C) may be located at the 6th column of the Hth row in the first functional area 121, the second address point (CA1 A) may be located at the 7th column of the Gth row in the second functional area 122. The third address point (CA2 A) may be located at the 7th column of the Jth row in the second functional area 122. The fourth address point (CA3 A) may be located at the 10th column of the Kth row in the second functional area 122. The fifth address point (CA4 A) may be located at the 10th column of the Hth row in the second functional area 122. The sixth address point (CA5 A) may be located at the 11th column of the Lth row in the third functional area 123. The seventh address point (CA6 A) may be located at the 11th column of the Jth row in the third functional area 123.

[0131] Optionally, continuing to refer to Figure 3 , in a single encapsulation area 110, there are multiple power input / output points (VDD) and ground points (VSS). The power input / output points (VDD) and ground points (VSS) can be distributed in three areas: the first functional area 121, the second functional area 122, and the third functional area 123. In this way, the power input / output points (VDD) and ground points (VSS) can be relatively evenly distributed within the entire encapsulation area 110, facilitating the layout of power lines (for transmitting power signals) and ground lines (for transmitting ground signals) in the circuit board 100 and the chip 200. And / or, it is also possible to reserve more scattered spaces, facilitating the layout of other signal points.

[0132] Optionally, except for a row of signal points in the first encapsulation area 111 far from the second encapsulation area 112 and a column of signal points close to the central processing unit 400, the ground points (VSS) can be arranged at intervals among the remaining rows and columns. And / or, the ground points (VSS) between adjacent rows or adjacent columns are arranged diagonally.

[0133] Optionally, the power input / output points (VDD) can be preferentially arranged in a row of signal points in the first encapsulation area 111 far from the second encapsulation area 112 (such as Figure 3 the A row in), so as to facilitate the wiring connection with the circuit board 100. The remaining power input / output points (VDD) can then be arranged according to the unoccupied points in each functional area.

[0134] Optionally, in a row of signal points in the first encapsulation area 111 far from the second encapsulation area 112, power input / output points (VDD) and blank points can be arranged. In this way, the power lines (for transmitting power signals) in the circuit board 100 and the chip 200 can be concentratedly arranged. And / or, the retention of blank points also further facilitates the wiring.

[0135] On this basis, among a row of signal points in the first encapsulation area 111 away from the second encapsulation area 112, there is one said blank point between two adjacent power input / output points (VDD). This can ensure that each power line can be routed separately, and it is not easy to cross, resulting in electromagnetic interference between adjacent signal lines.

[0136] Optionally, taking Figure 3 as an example, the layout structure of all signal points in the chip 200 encapsulated in the first encapsulation area 111 and the chip 200 encapsulated in the second encapsulation area 112 will be described.

[0137] Optionally, the following is the description of the layout structure of the A channel of the chip 200.

[0138] Optionally, the signal point at the C-th row in the first column is the first data input / output point of the A channel of the chip 200, and the signal point at the E-th row in the first column is the second data input / output point of the A channel of the chip 200.

[0139] Optionally, the signal point at the B-th row in the second column is the third data input / output point of the A channel of the chip 200, the signal point at the D-th row in the second column is the fourth data input / output point of the A channel of the chip 200, and the signal points at the C-th row and the E-th row in the second column are the ground points of the A channel of the chip 200.

[0140] Optionally, the signal point at the C-th row in the third column is the first differential read synchronization signal point of the A channel of the chip 200, the signal point at the E-th row in the third column is the first read clock point of the A channel of the chip 200, the signal point at the A-th row in the third column is the power input / output point of the A channel of the chip 200, and the signal points at the B-th row, the D-th row, and the F-th row in the third column are the ground points of the A channel of the chip 200.

[0141] Optionally, the signal point at the F-th row in the fourth column is the fifth data input / output point of the A channel of the chip 200, the signal point at the B-th row in the fourth column is the first differential write synchronization signal point of the A channel of the chip 200, the signal point at the D-th row in the fourth column is the first write clock point of the A channel of the chip 200, and the signal points at the C-th row and the E-th row in the fourth column are the ground points of the A channel of the chip 200.

[0142] Optionally, the signal point at the C-th row in the fifth column is the eighth data input / output point of the A channel of the chip 200, the signal point at the E-th row in the fifth column is the sixth data input / output point of the A channel of the chip 200, the signal point at the A-th row in the fifth column is the power input / output point of the A channel of the chip 200, and the signal points at the B-th row, the D-th row, and the F-th row in the fifth column are the ground points of the A channel of the chip 200.

[0143] Optionally, the signal point at the B-th row of the sixth column is the seventh data input / output point of the A channel of chip 200, the signal point at the D-th row of the sixth column is the first address point of the A channel of chip 200, the signal points at the C-th row and the E-th row of the sixth column are the ground points of the A channel of chip 200, and the signal point at the F-th row of the sixth column is the power input / output point of the A channel of chip 200.

[0144] Optionally, the signal point at the C-th row of the seventh column is the first chip select point of the A channel of chip 200, the signal point at the E-th row of the seventh column is the second address point of the A channel of chip 200, the signal point at the A-th row of the seventh column is the power input / output point of the A channel of chip 200, and the signal points at the B-th row, the D-th row, and the F-th row of the seventh column are the ground points of the A channel of chip 200.

[0145] Optionally, the signal point at the B-th row of the eighth column is the second chip select point of the A channel of chip 200, the signal point at the D-th row of the eighth column is the write differential clock signal point of the A channel of chip 200, the signal point at the F-th row of the eighth column is the third address point of the A channel of chip 200, and the signal points at the C-th row and the E-th row of the eighth column are the ground points of the A channel of chip 200.

[0146] Optionally, the signal point at the C-th row of the ninth column is the fourth address point of the A channel of chip 200, the signal point at the E-th row of the ninth column is the read differential clock signal point of the A channel of chip 200, the signal point at the A-th row of the ninth column is the power input / output point of the A channel of chip 200, and the signal points at the B-th row, the D-th row, and the F-th row of the ninth column are the ground points of the A channel of chip 200.

[0147] Optionally, the signal point at the B-th row of the tenth column is the seventh address point of the A channel of chip 200, the signal point at the D-th row of the tenth column is the sixth address point of the A channel of chip 200, the signal point at the F-th row of the tenth column is the fifth address point of the A channel of chip 200, and the signal points at the C-th row and the E-th row of the tenth column are the ground points of the A channel of chip 200.

[0148] Optionally, the signal point at the C-th row of the eleventh column is the sixteenth data input / output point of the A channel of chip 200, the signal point at the E-th row of the eleventh column is the fifteenth data input / output point of the A channel of chip 200, the signal point at the A-th row of the eleventh column is the power input / output point of the A channel of chip 200, and the signal points at the B-th row, the D-th row, and the F-th row of the eleventh column are the ground points of the A channel of chip 200.

[0149] Optionally, the signal point at the B-th row and the 12th column is the 14th data input / output point of the A channel of chip 200, the signal point at the E-th row and the 12th column is the second write clock point of the A channel of chip 200, the signal points at the C-th row and the E-th row of the 12th column are the ground points of the A channel of chip 200, and the signal point at the F-th row and the 12th column is the power input / output point of the A channel of chip 200.

[0150] Optionally, the signal point at the C-th row and the 13th column is the 13th data input / output point of the A channel of chip 200, the signal point at the E-th row and the 13th column is the second read clock point of the A channel of chip 200, the signal point at the A-th row and the 13th column is the power input / output point of the A channel of chip 200, and the signal points at the B-th row, the D-th row, and the F-th row of the 13th column are the ground points of the A channel of chip 200.

[0151] Optionally, the signal point at the B-th row and the 14th column is the 12th data input / output point of the A channel of chip 200, the signal point at the D-th row and the 14th column is the second differential read synchronization signal point of the A channel of chip 200, the signal point at the F-th row and the 14th column is the second input data mask point of the A channel of chip 200, and the signal points at the C-th row and the E-th row of the 14th column are the ground points of the A channel of chip 200.

[0152] Optionally, the signal point at the E-th row and the 15th column is the 11th data input / output point of the A channel of chip 200, the signal point at the C-th row and the 15th column is the second differential write synchronization signal point of the A channel of chip 200, the signal point at the A-th row and the 15th column is the power input / output point of the A channel of chip 200, and the signal points at the B-th row, the D-th row, and the F-th row of the 15th column are the ground points of the A channel of chip 200.

[0153] Optionally, the signal point at the D-th row and the 16th column is the 9th data input / output point of the A channel of chip 200, the signal point at the F-th row and the 16th column is the 10th data input / output point of the A channel of chip 200, the signal point at the B-th row and the 16th column is the unassigned point of the A channel of chip 200, and the signal points at the C-th row and the E-th row of the 16th column are the ground points of the A channel of chip 200.

[0154] Optionally, the signal point at the E-th row and the 17th column is the drive strength calibration signal point of the A channel of chip 200, the signal point at the C-th row and the 17th column is the power input / output point of the A channel of chip 200, and the signal points at the D-th row and the F-th row of the 17th column are the ground points of the A channel of chip 200.

[0155] The following is the layout structure description of the C channel of chip 200.

[0156] Optionally, the signal point at the J-th row of the first column is the first data input / output point of the C channel of chip 200, and the signal point at the L-th row of the first column is the second data input / output point of the C channel of chip 200. The signal point at the G-th row of the first column is the power input / output point of the C channel of chip 200.

[0157] Optionally, the signal point at the H-th row of the second column is the third data input / output point of the C channel of chip 200, the signal point at the K-th row of the second column is the fourth data input / output point of the C channel of chip 200, and the signal points at the G-th, J-th, and L-th rows of the second column are the ground points of the C channel of chip 200.

[0158] Optionally, the signal point at the G-th row of the third column is the first differential write synchronization signal point of the C channel of chip 200, the signal point at the J-th row of the third column is the first read clock point of the C channel of chip 200, the signal point at the L-th row of the third column is the first input data mask point of the C channel of chip 200, and the signal points at the H-th and K-th rows of the third column are the ground points of the C channel of chip 200.

[0159] Optionally, the signal point at the H-th row of the fourth column is the first differential read synchronization signal point of the C channel of chip 200, the signal point at the K-th row of the fourth column is the first write clock point of the C channel of chip 200, and the signal points at the G-th, J-th, and L-th rows of the fourth column are the ground points of the C channel of chip 200.

[0160] Optionally, the signal point at the G-th row of the fifth column is the fifth data input / output point of the C channel of chip 200, the signal point at the J-th row of the fifth column is the sixth data input / output point of the C channel of chip 200, the signal point at the L-th row of the fifth column is the seventh data input / output point of the C channel of chip 200, and the signal points at the H-th and K-th rows of the fifth column are the ground points of the C channel of chip 200.

[0161] Optionally, the signal point at the K-th row of the sixth column is the eighth data input / output point of the C channel of chip 200, the signal point at the H-th row of the sixth column is the first address point of the C channel of chip 200, and the signal points at the G-th, J-th, and L-th rows of the sixth column are the ground points of the C channel of chip 200.

[0162] Optionally, the signal point at the G-th row of the seventh column is the second address point of the C channel of chip 200, the signal point at the J-th row of the seventh column is the third address point of the C channel of chip 200, the signal point at the L-th row of the seventh column is the power input / output point of the C channel of chip 200, and the signal points at the H-th and K-th rows of the seventh column are the ground points of the C channel of chip 200.

[0163] Optionally, the signal point at the H-th row of the eighth column is the differential clock signal point for writing to the C channel of chip 200, the signal point at the K-th row of the eighth column is the first chip select point for the C channel of chip 200, and the signal points at the G-th, J-th, and L-th rows of the eighth column are the ground points for the C channel of chip 200.

[0164] Optionally, the signal point at the J-th row of the ninth column is the differential clock signal point for reading from the C channel of chip 200, the signal point at the L-th row of the ninth column is the second chip select point for the C channel of chip 200, the signal point at the G-th row of the ninth column is the power input / output point for the C channel of chip 200, and the signal points at the H-th and K-th rows of the ninth column are the ground points for the C channel of chip 200.

[0165] Optionally, the signal point at the H-th row of the tenth column is the fifth address point for the C channel of chip 200, the signal point at the K-th row of the tenth column is the fourth address point for the C channel of chip 200, and the signal points at the G-th, J-th, and L-th rows of the tenth column are the ground points for the C channel of chip 200.

[0166] Optionally, the signal point at the G-th row of the eleventh column is the sixteenth data input / output point for the C channel of chip 200, the signal point at the J-th row of the eleventh column is the seventh address point for the C channel of chip 200, the signal point at the L-th row of the eleventh column is the sixth address point for the C channel of chip 200, and the signal points at the H-th and K-th rows of the eleventh column are the ground points for the C channel of chip 200.

[0167] Optionally, the signal point at the H-th row of the twelfth column is the fifteenth data input / output point for the C channel of chip 200, the signal point at the K-th row of the twelfth column is the second read clock point for the C channel of chip 200, and the signal points at the G-th, J-th, and L-th rows of the twelfth column are the ground points for the C channel of chip 200.

[0168] Optionally, the signal point at the G-th row of the thirteenth column is the fourteenth data input / output point for the C channel of chip 200, the signal point at the L-th row of the thirteenth column is the thirteenth data input / output point for the C channel of chip 200, the signal point at the J-th row of the thirteenth column is the second write clock point for the C channel of chip 200, and the signal points at the H-th and K-th rows of the thirteenth column are the ground points for the C channel of chip 200.

[0169] Optionally, the signal point at the H-th row of the fourteenth column is the second differential read synchronization signal point for the C channel of chip 200, the signal point at the K-th row of the fourteenth column is the second input data mask point for the C channel of chip 200, and the signal points at the G-th, J-th, and L-th rows of the fourteenth column are the ground points for the C channel of chip 200.

[0170] Optionally, the signal point at the G-th row and the 15th column is the 12th data input / output point of Channel C of chip 200, the signal point at the L-th row and the 15th column is the 11th data input / output point of Channel C of chip 200, the signal point at the J-th row and the 15th column is the second differential write synchronization signal point of Channel C of chip 200, and the signal points at the H-th row and the K-th row and the 15th column are the ground points of Channel C of chip 200.

[0171] Optionally, the signal point at the H-th row and the 16th column is the 10th data input / output point of Channel C of chip 200, the signal point at the K-th row and the 16th column is the 9th data input / output point of Channel C of chip 200, and the signal points at the G-th row, the J-th row, and the L-th row and the 16th column are the ground points of Channel C of chip 200.

[0172] Optionally, the signal points at the G-th row and the L-th row and the 17th column are the power input / output points of Channel C of chip 200, and the signal points at the H-th row and the K-th row and the 17th column are the ground points of Channel A of chip 200.

[0173] Figure 4 This is another layout diagram of the signal points on the circuit board provided by the embodiment of the present application. Refer to Figure 4 As shown, four packaging areas 110 are arranged on the circuit board 100. In addition to the first packaging area 111 and the second packaging area 112, a third packaging area 113 and a fourth packaging area 114 are also arranged on the circuit board 100. Among them, the first packaging area 111, the second packaging area 112, the third packaging area 113, and the fourth packaging area 114 are arranged in sequence along the first direction. And / or, the chip 200 is also packaged in the third packaging area 113 and the fourth packaging area 114. Correspondingly, the third packaging area 113 can form a separate signal transmission channel D for the chip 200. The fourth packaging area 114 can form a separate signal transmission channel B for the chip 200.

[0174] Optionally, when the first packaging area 111, the second packaging area 112, the third packaging area 113, and the fourth packaging area are packaged on the circuit board 100, it can be that the signal transmission channel A of the chip 200, the signal transmission channel B of the chip 200, the signal transmission channel C of the chip 200, and the signal transmission channel D of the chip 200 all work simultaneously, or any two or any three of the signal transmission channel A of the chip 200, the signal transmission channel B of the chip 200, the signal transmission channel C of the chip 200, and the signal transmission channel D of the chip 200 work simultaneously, or any one of the signal transmission channel A of the chip 200, the signal transmission channel B of the chip 200, the signal transmission channel C of the chip 200, and the signal transmission channel D of the chip 200 works alone.

[0175] Optionally, the third encapsulation area 113 is symmetrically arranged with the second encapsulation area 112, and the fourth encapsulation area 114 is symmetrically arranged with the first encapsulation area 111. That is to say, the electrical connection balls 300 in the third encapsulation area 113 and the second encapsulation area 112 are symmetrically distributed, and the electrical connection balls 300 in the fourth encapsulation area 114 and the first encapsulation area 111 are symmetrically arranged. Correspondingly, the chips 200 encapsulated in the third encapsulation area 113 and the fourth encapsulation area 114 are also symmetrically arranged with the chips 200 encapsulated in the second encapsulation area 112 and the first encapsulation area 111. That is to say, the signal transmission channel A and the signal transmission channel B, and the signal transmission channel C and the signal transmission channel D are symmetrically arranged along the second direction.

[0176] Optionally, there may be at least one row of signal points between the second encapsulation area 112 and the third encapsulation area 113, so as to arrange the outgoing wires at the junction of the second encapsulation area 112 and the third encapsulation area 113. Refer to Figure 4 As shown, there are two complete rows of blank points (the Mth row and the Nth row in the figure) between the second encapsulation area 112 and the third encapsulation area 113. In this way, not only can an outgoing wire space be provided for the electrical connection balls 300 on the side of the second encapsulation area 112 close to the third encapsulation area 113, but also the outgoing wires of the electrical connection balls 300 on the side of the third encapsulation area 113 close to the second encapsulation area 112 are facilitated. In this way, when laying out a row of signal points where the second encapsulation area 112 and the third encapsulation area 113 are close to each other, there is no need to consider leaving a separate wiring space.

[0177] Optionally, there are no blank points in a row of signal points where the second encapsulation area 112 and the third encapsulation area 113 are close to each other. In this way, the compactness of the signal point layout can be increased, and thus the size of the chip 200 can be reduced.

[0178] Optionally, through the above layout and design, the sum of the number of electrical connection balls 300 (signal points) required to be arranged in the first encapsulation area 111, the second encapsulation area 112, the third encapsulation area 113, and the fourth encapsulation area 114 in this embodiment can be 352.

[0179] Optionally, the diameter of the electrical connection ball 300 used to form the signal point in this embodiment can be 0.20 mm - 0.35 mm. For example, the diameter of the electrical connection ball 300 is 0.20 mm, 0.25 mm, 0.30 mm, 0.35 mm, or a range composed of any two of them.

[0180] Optionally, along the first direction, the ball pitch between adjacent electrical connection balls 300 can be 0.35 mm - 0.65 mm. For example, along the first direction, the ball pitch between adjacent electrical connection balls 300 is 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, 0.6 mm, 0.65 mm, or the range formed by any two of them.

[0181] Optionally, along the second direction, the ball pitch between adjacent electrical connection balls 300 can be 0.35 - 0.65 mm. For example, along the second direction, the ball pitch between adjacent electrical connection balls 300 is 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, 0.6 mm, 0.65 mm, or the range formed by any two of them.

[0182] In this way, while ensuring reasonable wire routing, the point density can be increased, making the integration degree of the chip 200 higher, so that the miniaturization of the chip 200 can be achieved.

[0183] Optionally, in this embodiment, the diameter of the electrical connection ball 300 can be 0.25 mm, the ball pitch between adjacent rows of electrical connection balls 300 can be 0.5 mm, and the ball pitch between adjacent columns of electrical connection balls 300 can be 0.45 mm. With such a setting, the gap between adjacent electrical connection balls 300 can be ensured to be reasonable, facilitating wire routing and not easily causing signal interference. Optionally, since the number of columns in each packaging area 110 is more than the number of rows, and the ball pitch between adjacent rows of electrical connection balls 300 is greater than the ball pitch between adjacent columns of electrical connection balls 300, the overall length and width of the packaging unit formed by the first packaging area 111 and the second packaging area 112 can be made closer, which is beneficial to the layout of the packaging unit.

[0184] Optionally, the size of the chip packaging structure provided in this embodiment can be reduced to 8.2 mm * 12.4 mm. Optionally, 12.4 mm is the size of the chip 200 extending along the first direction, and 8.2 mm is the size of the chip 200 extending along the second direction.

[0185] Compared with the related art where the POP packaging process is used for chips 200 with large ball diameters and high point densities, in this embodiment, the central processor 400 and the chip 200 are placed side by side for packaging, and through the above signal point layout, reasonable wiring between the chip 200 and the circuit board 100 is achieved. And / or, the diameter of the electrical connection ball 300 is reduced and the ball pitch between adjacent electrical connection balls 300 is narrowed, so that the overall area of a single chip 200 is reduced on the basis of ensuring reasonable wire routing, and the overall size of the chip 200 is reduced. Furthermore, the space of the circuit board 100 can be saved, facilitating the layout design of other devices on the circuit board 100.

[0186] Based on the above embodiments, an embodiment of the present application further provides a device, and the processor in the device may be the above chip package structure. Figure 5 It is a schematic connection diagram of the chip package structure provided by the embodiment of the present application and the central processing unit 400. Figure 6 It is another schematic connection diagram of the chip package structure provided by the embodiment of the present application. Refer to Figure 5 and Figure 6 As shown, at least one central processing unit 400 is further provided on one side of the chip package structure. The central processing unit 400 is connected to the electrical connection ball 300 in the chip package structure by a trace crossing the target edge of the chip 200. Among them, the target edge extends from the completely blank area in the encapsulation area 110 to one side edge, such as Figure 5 and Figure 6 the left edge of the encapsulation area 110 shown in.

[0187] Optionally, the central processing unit 400 may be a SOC chip. The SOC chip is disposed on the circuit board 100 and is electrically connected to the foregoing chip 200. Among them, the SOC chip may include a first channel, a second channel, a third channel, and a fourth channel. The first channel is electrically connected to the A channel of the chip 200, the second channel is electrically connected to the B channel of the chip 200, the third channel is electrically connected to the C channel of the chip 200, and the fourth channel is electrically connected to the D channel of the chip 200.

[0188] Optionally, the device may be implemented in various forms. For example, the intelligent terminal described in the present application may include mobile terminals such as mobile phones, tablet computers, laptop computers, palmtop computers, personal digital assistants (PDAs), portable media players (PMPs), navigation devices, wearable devices, smart bracelets, pedometers, etc., and fixed terminals such as digital TVs and desktop computers.

[0189] In the subsequent description, a mobile terminal will be used as an example for illustration. Those skilled in the art will understand that, except for the components specifically for mobile purposes, the structure according to the embodiments of the present application can also be applied to fixed-type terminals.

[0190] Figure 7 It is a schematic hardware structure diagram of an intelligent terminal implementing various embodiments of the present application. Please refer to Figure 7, which is a schematic diagram of the hardware structure of a mobile terminal for implementing various embodiments of the present application. The mobile terminal 500 may include: an RF (Radio Frequency) unit 501, a WiFi module 502, an audio output unit 503, an A / V (audio / video) input unit 504, a sensor 505, a display unit 506, a user input unit 507, an interface unit 508, a memory 509, a processor 510, and a power supply 511, etc. Those skilled in the art can understand that Figure 7 the mobile terminal structure shown in

[0191] does not limit the mobile terminal. The mobile terminal may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements. Figure 7 The following specifically introduces each component of the mobile terminal:

[0192] The RF unit 501 can be used for receiving and transmitting signals during information reception or call processes. Specifically, after receiving the downlink information of the base station, it is given to the processor 510 for processing; in addition, the uplink data is sent to the base station. Usually, the RF unit 501 includes, but is not limited to, antennas, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, a duplexer, etc. In addition, the RF unit 501 can also communicate with the network and other devices through wireless communication. The above wireless communication can use any communication standard or protocol, including but not limited to GSM (Global System of Mobile communication), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division Duplexing-Long Term Evolution), TDD-LTE (Time Division Duplexing-Long Term Evolution), 5G, and 6G, etc.

[0193] WiFi belongs to short-range wireless transmission technology. The mobile terminal can help users send and receive emails, browse the web, and access streaming media through the WiFi module 502, providing users with wireless broadband Internet access. Although Figure 7 the WiFi module 502 is shown, it can be understood that it is not an essential component of the mobile terminal and can be omitted entirely within the scope of not changing the essence of the invention as needed.

[0194] The audio output unit 503 can convert the audio data received by the RF unit 501 or the WiFi module 502 or stored in the memory 509 into an audio signal and output it as sound when the mobile terminal 500 is in a call signal reception mode, a call mode, a recording mode, a voice recognition mode, a broadcast reception mode, etc. Moreover, the audio output unit 503 can also provide an audio output related to a specific function executed by the mobile terminal 500 (e.g., call signal reception sound, message reception sound, etc.). The audio output unit 503 can include a speaker, a buzzer, etc.

[0195] The A / V input unit 504 is used to receive audio or video signals. The A / V input unit 504 can include a Graphics Processing Unit (GPU) 5041 and a microphone 5042. The graphics processor 5041 processes the image data of still pictures or videos obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The processed image frames can be displayed on the display unit 506. The image frames processed by the graphics processor 5041 can be stored in the memory 509 (or other storage media) or transmitted via the RF unit 501 or the WiFi module 502. The microphone 5042 can receive sounds (audio data) via the microphone 5042 in operating modes such as a phone call mode, a recording mode, a voice recognition mode, etc., and can process such sounds into audio data. The processed audio (voice) data can be output in a format that can be transmitted to a mobile communication base station via the RF unit 501 in the case of a phone call mode. The microphone 5042 can implement various types of noise cancellation (or suppression) algorithms to eliminate (or suppress) the noise or interference generated during the reception and transmission of audio signals.

[0196] The mobile terminal 500 further includes at least one sensor 505, such as a light sensor, a motion sensor, and other sensors. Optionally, the light sensor includes an ambient light sensor and a proximity sensor. Optionally, the ambient light sensor can adjust the brightness of the display panel 5061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 5061 and / or the backlight when the mobile terminal 500 is moved to the ear. As a kind of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in all directions (generally three axes), and can detect the magnitude and direction of gravity when stationary, and can be used for applications that identify the posture of the mobile phone (such as horizontal and vertical screen switching, related games, magnetometer attitude calibration), vibration recognition related functions (such as pedometer, tapping), etc.; as for other sensors that the mobile phone can also be configured with, such as fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc., they will not be elaborated here.

[0197] The display unit 506 is used to display information input by the user or information provided to the user. The display unit 506 may include a display panel 5061, and the display panel 5061 can be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc.

[0198] The user input unit 507 can be used to receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the mobile terminal. Optionally, the user input unit 507 may include a touch panel 5071 and other input devices 5072. The touch panel 5071, also known as a touch screen, can collect touch operations of the user on or near it (such as operations of the user using a finger, a stylus, or any suitable object or accessory on or near the touch panel 5071), and drive the corresponding connection device according to a pre-set program. The touch panel 5071 can include two parts: a touch detection device and a touch controller. Optionally, the touch detection device detects the touch position of the user, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it to the processor 510, and can receive and execute the commands sent by the processor 510. In addition, the touch panel 5071 can be implemented in a variety of types, such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 5071, the user input unit 507 may further include other input devices 5072. Optionally, the other input devices 5072 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, power on / off keys, etc.), a trackball, a mouse, a joystick, etc., and specific details are not limited here.

[0199] Optionally, the touch panel 5071 may cover the display panel 5061. After the touch panel 5071 detects a touch operation on or near it, it is transmitted to the processor 510 to determine the type of touch event. Subsequently, the processor 510 provides a corresponding visual output on the display panel 5061 according to the type of touch event. Although in Figure 7 , the touch panel 5071 and the display panel 5061 are implemented as two independent components to realize the input and output functions of the mobile terminal, but in some embodiments, the touch panel 5071 and the display panel 5061 may be integrated to realize the input and output functions of the mobile terminal, and the specific implementation here is not limited.

[0200] The interface unit 508 serves as an interface through which at least one external device can be connected to the mobile terminal 500. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headset port, and so on. The interface unit 508 can be used to receive inputs from external devices (such as data information, power, etc.) and transmit the received inputs to one or more components within the mobile terminal 500 or can be used to transmit data between the mobile terminal 500 and external devices.

[0201] The memory 509 can be used to store software programs and various data. The memory 509 mainly includes a program storage area and a data storage area. Optionally, the program storage area can store an operating system, applications required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, phone book, etc.). In addition, the memory 509 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.

[0202] The processor 510 is the control center of the mobile terminal, connecting various parts of the entire mobile terminal using various interfaces and lines. By running or executing software programs and / or modules stored in the memory 509, and by calling data stored in the memory 509, it executes various functions of the mobile terminal and processes data, thereby monitoring the mobile terminal as a whole. The processor 510 may include one or more processing units; preferably, the processor 510 may integrate an application processor and a modem processor. Optionally, the application processor mainly processes the operating system, user interface, and applications, etc., and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor may not be integrated into the processor 510 either.

[0203] The mobile terminal 500 may further include a power source 511 (such as a battery) for powering each component. Preferably, the power source 511 may be logically connected to the processor 510 through a power management system, so as to implement functions such as management of charging, discharging, and power consumption management through the power management system.

[0204] Although Figure 7 not shown, the mobile terminal 500 may further include a Bluetooth module and the like, which will not be elaborated here.

[0205] It can be understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided by the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, as known to those of ordinary skill in the art, with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0206] The technical features of the technical solutions of the present application can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in the present application.

[0207] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip packaging structure, characterized in that: include: A circuit board, comprising at least two packaging areas, wherein the packaging areas include a first packaging area and a second packaging area sequentially arranged along a first direction; each of the packaging areas includes a first functional area, a second functional area and a third functional area sequentially arranged along a second direction, wherein the second direction is perpendicular to the first direction; A chip, packaged at least in the first packaging area and the second packaging area; Among them, data input and output points are distributed in the first functional area and the third functional area, and / or differential clock signal points are distributed in the second functional area.

2. The chip packaging structure according to claim 1, characterized in that: A group of clock points and a group of differential synchronization signal points are arranged in the first functional area and the third functional area.

3. The chip packaging structure according to claim 2, characterized in that: Each group of the clock points includes a write clock point and a read clock point, and the write clock point and the read clock point are arranged diagonally adjacent to each other or in rows and columns; and / or, Each group of the differential synchronization signal points includes a differential write synchronization signal point and a differential read synchronization signal point, and the differential write synchronization signal point and the differential read synchronization signal point are arranged diagonally adjacent to each other or in rows and columns.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: Along the first direction, the first packaging area is provided with 6 rows of signal points, and the second packaging area is provided with 5 rows of signal points; and / or, Along the second direction, the first functional area includes 6 columns of signal points, the second functional area includes 4 columns of signal points, and the third functional area includes 7 columns of signal points.

5. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip selection points are distributed in the second functional area.

6. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The first functional area and the third functional area are both provided with input data mask points.

7. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The packaging area further includes a third packaging area and a fourth packaging area sequentially arranged along the first direction, the third packaging area is symmetrically arranged with the second packaging area, and the fourth packaging area is symmetrically arranged with the first packaging area; The chip is also packaged in the third packaging area and the fourth packaging area.

8. The chip packaging structure according to claim 7, characterized in that: There is at least one row of blank spots between the second packaging area and the third packaging area.

9. The chip packaging structure according to any one of claims 1 to 3, characterized in that: Also includes at least one of the following: The diameter of the electric ball used to form the signal point is 0.20-0.35mm; Along the first direction, the ball spacing between adjacent electrical contact balls is 0.35-0.65 mm; Along the second direction, the ball spacing between adjacent electrical balls is 0.35-0.65 mm.

10. A device, characterized in that: A chip packaging structure comprising any one of claims 1 to 9.

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