Gallium oxide SBD device based on groove structure and preparation method thereof

Abstract

The invention provides a gallium oxide SBD device based on a trench structure. The gallium oxide SBD device comprises a cathode, a Ga2O3 substrate and the trench structure, wherein the trench structure is characterized in that the trench structure comprises a first Ga2O3 epitaxial layer, and the first Ga2O3 epitaxial layer is deposited on the upper surface of the Ga2O3 substrate; a plurality of second Ga2O3 epitaxial layers are deposited on the upper surface of the first Ga2O3 epitaxial layer, and grooves are formed between the adjacent second Ga2O3 epitaxial layers; a first high-resistance region is arranged in the first Ga2O3 epitaxial layer positioned below the groove; by performing Mg ion diffusion in the trench region and forming high-resistance regions on the first Ga2O3 epitaxial layer and the second Ga2O3 epitaxial layer, electrons at the bottom and on the side wall of the trench can be exhausted, so that the performance of the device is enhanced, the peak electric field and electric leakage of the anode region are effectively reduced, and the breakdown characteristic of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to a gallium oxide SBD device based on a trench structure and a preparation method thereof. Background Art

[0002] In recent years, with the rapid development of new energy vehicles, high-speed railways, space stations, and energy and other fields, the demand for power devices that can withstand ultra-high voltages has been increasing day by day. Silicon-based power devices are limited by the theoretical limit of materials and currently mainly occupy the low-voltage application market, facing problems such as increased conduction loss and switching loss in the high-voltage high-frequency field. Gallium oxide (Ga 2 O 3 ) as a typical representative of ultra-wide bandgap semiconductors has received extensive attention from the scientific research community, the industrial community, and the investment community. From the perspective of material properties, the bandgap width of β-Ga 2 O 3 is about 4.85 eV, and the theoretical value of the critical breakdown field strength can reach 8 MV / cm, which means that gallium oxide-based devices can achieve higher breakdown voltage and lower conduction loss, and have broad application prospects in the fields of high-frequency and high-power power electronics. In addition, β-Ga 2 O 3 can be used to prepare large-size high-quality single crystals by the liquid-phase melt method under normal pressure, and its wafer processing technology is also highly compatible with the existing semiconductor substrate processing production lines. Compared with silicon carbide and gallium nitride, β-Ga 2 O 3 exhibits significant cost advantages, providing strong support for subsequent realization of low-cost and high-quality homoepitaxy and development of high-performance β-Ga 2 O 3 -based devices.

[0003] Since no effective p-type doping has been found in gallium oxide, there are currently no reports on bipolar devices. Currently, the research on gallium oxide diodes mainly focuses on Schottky barrier diodes (SBDs). A gallium oxide Schottky barrier diode is a semiconductor device formed by a metal-semiconductor Schottky contact. Its advantages are that the device has a low turn-on voltage and conduction resistance, and has a faster reverse recovery time. However, the breakdown voltage of the current gallium oxide SBD is far from reaching the material's theoretical limit. The main reason is that when the device is under reverse high voltage, a peak electric field with a relatively high electric field intensity is likely to appear inside the device, leading to premature breakdown of the device at a low voltage. Therefore, it is necessary to optimize and improve from the device structure and process, and additionally introduce an effective edge termination (ET) technology to relieve the peak electric field inside the device, reduce the reverse leakage current, and thereby improve the breakdown performance of the device.

[0004] The existing solutions for alleviating the peak electric field of gallium oxide SBD are as follows: A trench structure is etched on the surface of gallium oxide by an etching method. Then, a dielectric material with a high dielectric constant is selected and deposited on the surface of gallium oxide. Subsequently, the surface dielectric material is removed through chemical polishing or etching processes, leaving only the dielectric material on the sidewalls and the bottom of the trenches. The disadvantages of this technical solution are as follows: First, to effectively reduce the peak electric field of the device, a relatively thick dielectric layer needs to be deposited or a dielectric material with a relatively high dielectric constant (high k) needs to be found. However, a thick dielectric layer will affect the application of the device, and other impurity contaminations may be brought during the deposition process of high k materials, and there are compatibility problems with the existing production process lines. Second, after depositing the dielectric material, the dielectric material on the surface of the trenches needs to be removed as the metal electrode contact area. This step usually uses chemical mechanical polishing (CMP) technology or self-reactive etching technology (SRE). However, the CMP technology has high requirements for process accuracy to avoid damaging the surface of the gallium oxide material, and the CMP technology will also increase the production cost.

[0005] Chinese invention patent with publication number CN115483274A discloses a gallium oxide field termination power diode based on SOG and its preparation method. Boron (B)-doped SOG is directly spin-coated on the surface of a gallium oxide sample to form a P-type SOG dielectric structure as the field termination. However, this invention only realizes the field termination structure in a planar structure; Chinese invention patent with publication number CN113964042A discloses a heterogeneous P-type terminal gallium oxide power diode and its preparation method. By etching a plurality of columnar structures on the drift layer, and at the same time, trenches are formed between adjacent columnar structures, and a P-type NiO dielectric layer is arranged at the bottom and inner wall of the trenches. However, this invention needs to remove the dielectric layer on the top of the columnar structure, and the process is complex and difficult.

[0006] In summary, there is an urgent need to develop a new technical solution to solve the problems existing in the prior art. Summary of the Invention

[0007] Based on this, the present invention provides a gallium oxide SBD device based on a trench structure and its preparation method. The gallium oxide SBD device based on the trench structure is provided with a Mg-doped high-resistance region on the gallium oxide SBD with the trench structure. First, a layer of silicon dioxide (SiO 2 ) is deposited on the surface of gallium oxide. Then, the trench positions are defined by photolithography and trench etching is carried out. Next, Mg ion diffusion is performed on the trench region through an Mg-doped SOG solution (Mg-SOG). Finally, the deposition of the cathode and anode metals is carried out. The trench structure is beneficial to increasing the Mg ion diffusion area, can effectively reduce the device leakage current, improve the breakdown voltage of the device, and improve the peak electric field that appears in the anode region of the gallium oxide SBD under high voltage conditions.

[0008] An object of the present invention is to provide a gallium oxide SBD device based on a trench structure. The gallium oxide SBD device based on a trench structure includes, from bottom to top, a cathode, Ga 2 O 3 substrate, and a trench structure;

[0009] Among them,

[0010] Trench structure: The trench structure includes a first Ga 2 O 3 epitaxial layer. The first Ga 2 O 3 epitaxial layer is deposited on the upper surface of the Ga 2 O 3 substrate;

[0011] On the upper surface of the first Ga 2 O 3 epitaxial layer, a plurality of second Ga 2 O 3 epitaxial layers are deposited. Trenches are formed between adjacent second Ga 2 O 3 epitaxial layers;

[0012] Above the interior of the first Ga 2 O 3 epitaxial layer below the trench, a first high-resistance region is provided;

[0013] On both sides of the interior of the second Ga 2 O 3 epitaxial layer, second high-resistance regions are provided. At the lower end of the second high-resistance regions, there are extension parts, and the extension parts extend into the first Ga 2 O 3 epitaxial layer. The thickness of the extension parts is the same as the thickness of the first high-resistance region;

[0014] Both the first high-resistance region and the second high-resistance region are Mg ion-doped regions;

[0015] The first high-resistance region and the second high-resistance region are respectively formed by Mg ions diffusing into the first Ga 2 O 3 epitaxial layer and the second Ga 2 O 3 epitaxial layer;

[0016] On the upper surfaces of the first Ga 2 O 3 epitaxial layer and the second Ga 2 O 3 epitaxial layer, an anode is deposited. The anode covers the first Ga 2 O 3 epitaxial layer, the second Ga2 O 3 The upper surfaces of the epitaxial layer and the trench are all covered.

[0017] Furthermore, the first Ga 2 O 3 epitaxial layer and the second Ga 2 O 3 The doping type of the epitaxial layer is n - type, and the doping type of the Ga 2 O 3 substrate is n + type.

[0018] Furthermore, the thickness of the first Ga 2 O 3 epitaxial layer is 9 - 11 μm.

[0019] Furthermore, the thickness of the second Ga 2 O 3 epitaxial layer is 400 - 600 nm.

[0020] Furthermore, the width of the second Ga 2 O 3 epitaxial layer is 2 - 5 μm.

[0021] Furthermore, the width of the trench is 2 - 5 μm, and the depth is 400 - 600 nm.

[0022] Furthermore, the thickness of the first high-resistance region is 700 - 900 nm.

[0023] Furthermore, the width of the second high-resistance region is 700 - 900 nm.

[0024] Furthermore, the concentration of the Mg ions is 1×10 17 ~4×10 21 cm -3 .

[0025] Furthermore, the thickness of the Ga 2 O 3 substrate is 550 - 750 μm.

[0026] The present invention also provides a method for manufacturing the gallium oxide SBD device based on the trench structure, including the following steps:

[0027] S1. Prepare an epitaxial wafer with a multi-layer structure, where the epitaxial wafer from bottom to top is successively a Ga 2 O 3 substrate and a Ga 2 O 3 epitaxial layer; On the Ga 2 O 3Deposit a silicon dioxide layer on the surface of the epitaxial layer as a hard mask to define the photolithography area of the trench;

[0028] S2. Spin-coat an adhesion promoter on the surface of the silicon dioxide layer, then drop-coat photoresist, perform pre-baking treatment, expose and remove the photoresist in the photolithography area of the trench, and perform post-baking and hardening treatment;

[0029] S3. Etch the photolithography area of the trench, and then etch the Ga 2 O 3 epitaxial layer in the photolithography area of the trench to form a trench;

[0030] S4. Spin-coat an Mg-doped SOG solution on the surface of the first Ga 2 O 3 epitaxial layer, the second Ga 2 O 3 epitaxial layer and the trench, bake to obtain an Mg-doped SOG coating, and anneal to diffuse Mg ions into the first Ga 2 O 3 epitaxial layer and the second Ga 2 O 3 epitaxial layer to form a first high-resistance region, a second high-resistance region and an extension part respectively, and remove the remaining Mg-doped SOG coating;

[0031] S5. Deposit a cathode at the bottom of the Ga 2 O 3 substrate to form an ohmic contact;

[0032] S6. Deposit an anode on the surface of the first Ga 2 O 3 epitaxial layer, the second Ga 2 O 3 epitaxial layer and the trench to obtain a gallium oxide Schottky diode with a high breakdown voltage.

[0033] Further, in step S3, BOE solution is used for etching the silicon dioxide layer.

[0034] Further, in step S4, the thickness of the Mg-doped SOG coating is 800 nm - 1 μm.

[0035] The present invention also provides an application of the gallium oxide SBD device based on the trench structure on a semiconductor device.

[0036] Further, the technical solution of the present invention is to implement the application of SOG on the trench structure, and at the same time adopt a rapid thermal annealing process to diffuse Mg ions into the Ga 2 O 3 material, which can more effectively reduce the reverse leakage current of the anode metal electrode and improve the breakdown voltage of the device.

[0037] Furthermore, the present invention directly uses the SOG solution to perform Mg ion diffusion on the trench to form a high-resistance region in the first Ga 2 O 3 epitaxial layer and the second Ga 2 O 3 epitaxial layer. The process is relatively simple and can reduce the deposition of the dielectric layer and the subsequent etching process. By using Mg ions to laterally modulate the electric field distribution of the gallium oxide channel, while reducing the reverse leakage current of the device, the breakdown voltage of the device is improved.

[0038] The fourth-generation semiconductor material gallium oxide has excellent properties such as higher breakdown characteristics and lower on-resistance, which is the focus of current research by scientific researchers. However, the performance of gallium oxide power diodes currently far from reaches the theoretical limit of the material, and it is necessary to optimize the device structure and process to improve the peak electric field and leakage at high voltages. The present invention mainly conducts electric field regulation and leakage suppression on the device from the perspective of the device field termination. Other solutions can also achieve the corresponding purposes, but most of them will involve other special processes or special structures, increasing the device preparation difficulty and production cost. The present invention uses the Mg-SOG solution for Mg ion thermal diffusion, which not only optimizes the breakdown characteristics of the device but also does not increase difficult process operations, and achieves the same purpose as other technologies by using a relatively simple method and at a lower cost.

[0039] The present invention has the following beneficial effects:

[0040] (1) The present invention provides a gallium oxide SBD device based on a trench structure and a preparation method thereof. The gallium oxide SBD device based on the trench structure adopts a unique trench structure design, and then through the Mg-SOG thermal diffusion process, Mg ion diffusion is carried out in the trench region to form a high-resistance region in the first Ga 2 O 3 epitaxial layer and the second Ga 2 O 3 epitaxial layer, which can deplete electrons at the bottom and side walls of the trench, thereby enhancing device performance, effectively reducing the peak electric field and leakage in the anode region, and improving the breakdown characteristics of the device. The design of the trench structure greatly increases the diffusion area of Mg ions, improves the Mg ion's ability to regulate the electric field, can effectively reduce the reverse leakage of the device, improve the breakdown voltage of the device, and improve the peak electric field that appears in the anode region of the gallium oxide SBD under high voltage conditions.

[0041] (2) The process flow of the present invention is simple, without additional mechanical polishing or etching processes, can effectively reduce costs, and is well compatible with the conventional process line. In addition, by designing the diffusion temperature and diffusion time, the diffusion concentration and depth can be controlled to achieve precise control of the diffusion concentration and depth. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 (a)-(j) show the schematic process preparation flow of the gallium oxide SBD device based on the trench structure prepared in Examples 1-2;

[0043] Figure 2 The flow block diagram of the gallium oxide SBD device based on the trench structure prepared in Examples 1-2 is shown;

[0044] In the figure: 1. Anode; 2. Ga 2 O 3 epitaxial layer; 21. First Ga 2 O 3 epitaxial layer; 22. Second Ga 2 O 3 epitaxial layer; 3. Ga 2 O 3 substrate; 4. Cathode; 5. First high-resistance region; 6. Silicon dioxide layer; 7. Photoresist; 8. Mg-doped SOG coating; 9. Second high-resistance region; 10. Trench; 11. Extension part. Detailed implementation manners

[0045] To more clearly illustrate the technical solutions of the present invention, the following examples are listed. The raw materials, reactions, and post-treatment means appearing in the examples are common raw materials on the market and technical means well-known to those skilled in the art, unless otherwise specifically stated.

[0046] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0047] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0048] Example 1

[0049] A gallium oxide SBD device based on a trench structure, such as Figure 1As shown in (a)-(j), the gallium oxide SBD device based on the trench structure includes, from bottom to top, a cathode 4 (Ti / Au, 20 nm / 100 nm), an n + Ga 2 O 3 substrate 3 (650 μm), and a trench structure;

[0050] Among them,

[0051] Trench structure: The trench structure includes a first Ga 2 O 3 epitaxial layer 21 (9.5 μm). The first Ga 2 O 3 epitaxial layer 21 is deposited on the upper surface of the Ga 2 O 3 substrate 3;

[0052] On the upper surface of the first Ga 2 O 3 epitaxial layer 21, a plurality of second Ga 2 O 3 epitaxial layers 22 (thickness 500 nm, width 4 μm) are deposited. Trenches 10 (width 4 μm, depth 500 nm) are formed between adjacent second Ga 2 O 3 epitaxial layers 22;

[0053] Above the interior of the first Ga 2 O 3 epitaxial layer 21 below the trench 10, a first high-resistance region 5 (thickness 800 nm) is provided. The width of the first high-resistance region 5 is adapted to the width of the trench 10;

[0054] On both sides of the interior of the second Ga 2 O 3 epitaxial layer 22, second high-resistance regions 9 (width 800 nm) are provided. At the lower end of the second high-resistance region 9, an extension part 11 is provided, and the extension part 11 extends into the first Ga 2 O 3 epitaxial layer 21. The thickness of the extension part 11 is the same as the thickness of the first high-resistance region 5;

[0055] Both the first high-resistance region 5 and the second high-resistance region 9 are Mg ion-doped regions;

[0056] The first high-resistance region 5 and the second high-resistance region 9 are formed by diffusing Mg ions into the first Ga 2 O 3 epitaxial layer 21 and the second Ga 2 O 3 epitaxial layer 22 respectively;

[0057] The first Ga 2 O 3 epitaxial layer 21 and the second Ga 2 O 3 An anode 1 (Ni / Au, 50 nm / 200 nm) is deposited on the upper surface of the epitaxial layer 22. The anode 1 covers the upper surfaces of the first Ga 2 O 3 epitaxial layer 21, the second Ga 2 O 3 epitaxial layer 22 and the trench 10 entirely.

[0058] The method for preparing the gallium oxide SBD device based on the trench structure includes the following steps:

[0059] S1-1. Prepare an epitaxial wafer with a multi-layer structure. The epitaxial wafer, from bottom to top, is an n + Ga 2 O 3 substrate 3 and an n - Ga 2 O 3 epitaxial layer 2: Clean the epitaxial wafer. Immerse the epitaxial wafer in acetone, isopropyl alcohol, and deionized water for 3 minutes each in sequence, blow dry with a nitrogen gun, and then place it on a hot plate to heat and remove the residual moisture on the surface;

[0060] S1-2. Deposit a silicon dioxide layer 6 (300 nm) on the Ga 2 O 3 epitaxial layer 2 by using a PECVD device. When depositing the silicon dioxide, a silicon wafer needs to be placed simultaneously for co-deposition as a companion wafer to facilitate the subsequent calibration of the etching rate. After depositing the silicon dioxide layer 6, define the photolithography area of the trench 10 by using a photolithography process;

[0061] S2. Dropwise apply a tackifier (HMDS) on the surface of the silicon dioxide layer 6, spin coat it at a speed of 3000 revolutions for 30 s in a spin coater and then let it stand for 1 min, and then dropwise apply a photoresist 7 (1 μm) and spin coat it at a speed of 3000 revolutions for 35 s; After the spin coating of the photoresist 7 is completed, place the epitaxial wafer on a 100°C hot plate and bake it for 180 s for pre-baking; Subsequently, perform a photolithography process. Use a photomask exposure machine for photolithography alignment, and use the hard contact mode for exposure to remove the photoresist 7 in the photolithography area of the trench 10. Place the epitaxial wafer in a developer and shake it for development for 30 s, rinse it with deionized water, and blow it dry with a nitrogen gun; Finally, place the epitaxial wafer on a 120°C hot plate and bake it for 90 s for post-baking and hardening the film;

[0062] S3. Use the wet etching process to etch the silicon dioxide layer 6 on the lithography area of the trench 10 with BOE solution for 10 s to ensure that the silicon dioxide is completely etched away. After the wet etching is completed, use an ICP device to etch the Ga 2 O 3 epitaxial layer 2 on the lithography area of the trench 10 to form the trench 10;

[0063] Since the Ga 2 O 3 material has poor heat dissipation performance, a large amount of heat will be generated during the etching process; thermal grease needs to be applied to the bottom for auxiliary heat dissipation before etching; after the etching process is completed, the epitaxial wafer needs to be placed in acetone solution for ultrasonic cleaning to remove the photoresist 7 and thermal grease; after the acetone cleaning is completed, the epitaxial wafer also needs to be soaked in piranha solution (H 2 SO 4 :H 2 O 2 = 4:1, v / v) for 15 min to remove the residual thermal grease and the plasma remaining on the surface of the epitaxial wafer after etching, then place the epitaxial wafer under deionized water for rinsing and blow dry with a nitrogen gun;

[0064] S4. Spin coat a 4×10 2 O 3 concentration of Mg-doped SOG solution on the surfaces of the first Ga 2 O 3 epitaxial layer 21, the second Ga 21 cm -3 epitaxial layer 22 and the trench 10. Immediately after the spin coating is completed, place it on a hot plate at 200 °C and bake for 40 min to form a Mg-doped SOG coating 8 (1 μm). Then place it in a rapid thermal annealing (RTP) device and perform annealing for 60 s at 950 °C in a nitrogen atmosphere to diffuse the Mg ions into the first Ga 2 O 3 epitaxial layer 21 and the second Ga 2 O 3 epitaxial layer 22 to form the first high-resistance region 5, the second high-resistance region 9 and the extension part 11 respectively; after the annealing is completed, the epitaxial wafer needs to be placed in BOE solution for 1 h to remove the residual Mg-doped SOG coating 8 with the BOE solution;

[0065] S5. Spin coat photoresist 7 on the surface of the epitaxial wafer, and then use an electron beam evaporation (EBE) device on the Ga 2 O 3Deposit metal Ti / Au (20 nm / 100 nm) on the bottom of the substrate 3 as the cathode 4, then place it in a DMSO solution at 80 °C to remove the photoresist 7 on the surface, and then perform annealing for 60 s at 500 °C in a nitrogen atmosphere in an RTP equipment to form an ohmic contact;

[0066] S6. First, realize the pattern transfer of the anode 1 region through a double-layer resist process. Drop the adhesion promoter (HMDS) on the surface of the epitaxial wafer, spin-coat it at a speed of 3000 revolutions for 30 s in a spin coater and then let it stand for 1 min, and then drop the photoresist (LOR) and spin-coat it at a speed of 4000 revolutions for 60 s; after the photoresist spin-coating is completed, place the epitaxial wafer on a hot plate at 170 °C and bake it for 480 s, then drop the photoresist and spin-coat it at a speed of 3000 revolutions for 35 s. After the photoresist spin-coating is completed, place the epitaxial wafer on a hot plate at 100 °C and bake it for 180 s for pre-baking; then use an electron beam evaporation (EBE) equipment to deposit metal Ni / Au (50 nm / 200 nm) on the surface of the first Ga 2 O 3 epitaxial layer 21, the second Ga 2 O 3 epitaxial layer 22 and the trench 10 as the anode 1, and then place it in a DMSO solution at 80 °C to strip the metal in the non-anode region to obtain a gallium oxide SBD device based on a trench structure.

[0067] Example 2

[0068] A gallium oxide SBD device based on a trench structure, as Figure 1 (a)-(j) shown, the gallium oxide SBD device based on a trench structure includes, from bottom to top, in sequence: a cathode 4 (Ti / Au, 20 nm / 100 nm), an n + Ga 2 O 3 substrate 3 (650 μm), a trench structure;

[0069] Among them,

[0070] Trench structure: The trench structure includes a first Ga 2 O 3 epitaxial layer 21 (9.5 μm), and the first Ga 2 O 3 epitaxial layer 21 is deposited on the upper surface of the Ga 2 O 3 substrate 3;

[0071] On the upper surface of the first Ga 2 O 3 epitaxial layer 21, a number of second Ga 2 O 3Epitaxial layer 22 (thickness 500 nm, width 3 μm), adjacent to the second Ga 2 O 3 A trench 10 (width 3 μm, depth 500 nm) is formed between the epitaxial layers 22;

[0072] The first Ga 2 O 3 Above the interior of the epitaxial layer 21 of the first Ga

[0073] The second Ga 2 O 3 Second high-resistance regions 9 (width 800 nm) are provided on both sides inside the epitaxial layer 22 of the second Ga 2 O 3 Inside the epitaxial layer 21 of the first Ga

[0074] Both the first high-resistance region 5 and the second high-resistance region 9 are Mg ion-doped regions;

[0075] The first high-resistance region 5 and the second high-resistance region 9 are respectively formed by diffusing Mg ions into the first Ga 2 O 3 Epitaxial layer 21 and the second Ga 2 O 3 Inside the epitaxial layer 22;

[0076] The first Ga 2 O 3 Epitaxial layer 21 and the second Ga 2 O 3 An anode 1 (Ni / Au, 50 nm / 200 nm) is deposited on the upper surfaces of the epitaxial layer 21 of the first Ga 2 O 3 Epitaxial layer 21, the second Ga 2 O 3 The upper surfaces of the epitaxial layer 22 and the trench 10 are all covered.

[0077] The preparation method of the gallium oxide SBD device based on the trench structure includes the following steps:

[0078] S1-1. Prepare an epitaxial wafer with a multi-layer structure, and the epitaxial wafer from bottom to top is an n + Ga 2 O 3 Substrate 3 and an n - Ga 2 O 3Epitaxial layer 2: Clean the epitaxial wafer. Immerse the epitaxial wafer in acetone, isopropyl alcohol, and deionized water for 3 minutes each in sequence, dry it with a nitrogen gun, and then place it on a hot plate to heat and remove the residual moisture on the surface.

[0079] S1-2. Use a PECVD device to deposit a silicon dioxide layer 6 (300 nm) on the Ga 2 O 3 epitaxial layer 2. When depositing silicon dioxide, a silicon wafer needs to be placed simultaneously for co-deposition as a companion wafer to facilitate subsequent calibration of the etching rate. After depositing the silicon dioxide layer 6, the photolithography process is required to define the photolithography area of the trench 10.

[0080] S2. Dropwise apply an adhesion promoter (HMDS) on the surface of the silicon dioxide layer 6, spin-coat it at a speed of 3000 revolutions per minute in a spin coater for 30 s and then let it stand for 1 min. Then, dropwise apply a photoresist 7 (1 μm) and spin-coat it at a speed of 3000 revolutions per minute for 35 s. After the spin-coating of the photoresist 7 is completed, place the epitaxial wafer on a 100 °C hot plate and bake it for 180 s for pre-baking. Subsequently, perform the photolithography process, use a photomask exposure machine for photolithography alignment, and use the hard contact mode for exposure to remove the photoresist 7 in the photolithography area of the trench 10. Place the epitaxial wafer in the developer solution and shake it for development for 30 s, rinse it with deionized water, and blow it dry with a nitrogen gun. Finally, place the epitaxial wafer on a 120 °C hot plate and bake it for 90 s for post-baking to harden the film.

[0081] S3. Adopt a wet etching process to etch the silicon dioxide layer 6 on the photolithography area of the trench 10 with a BOE solution for 10 s to ensure that the silicon dioxide is completely etched away. After the wet etching is completed, use an ICP device to etch the Ga 2 O 3 epitaxial layer 2 located in the photolithography area of the trench 10 to form the trench 10.

[0082] Due to the poor heat dissipation performance of the Ga 2 O 3 material, a large amount of heat will be generated during the etching process. It is necessary to apply thermal grease at the bottom for auxiliary heat dissipation before etching. After the etching process is completed, the epitaxial wafer needs to be placed in an acetone solution for ultrasonic cleaning to remove the photoresist 7 and the thermal grease. After the acetone cleaning is completed, the epitaxial wafer also needs to be immersed in a piranha solution (H 2 SO 4 :H 2 O 2 =4:1, v / v) for 15 min to remove the residual thermal grease and the plasma remaining on the surface of the epitaxial wafer after etching, then place the epitaxial wafer under deionized water for rinsing, and blow it dry with a nitrogen gun.

[0083] S4. On the first Ga 2 O 3The epitaxial layer 21, the second Ga 2 O 3 The surfaces of the epitaxial layer 22 and the trench 10 are spin-coated with a Mg-doped SOG solution with a concentration of 4×10 21 cm -3 After the spin coating is completed, it is immediately placed on a hot plate at 200°C and baked for 40 min to form a Mg-doped SOG coating 8 (1 μm). Then it is placed in a rapid thermal annealing (RTP) equipment and annealed for 60 s at 950°C in a nitrogen atmosphere, so that Mg ions diffuse into the first Ga 2 O 3 epitaxial layer 21 and the second Ga 2 O 3 epitaxial layer 22 to form a first high-resistance region 5, a second high-resistance region 9 and an extension part 11 respectively; after the annealing is completed, the epitaxial wafer needs to be placed in a BOE solution for 1 h to remove the remaining Mg-doped SOG coating 8 with the BOE solution;

[0084] S5. A photoresist 7 is spin-coated on the surface of the epitaxial wafer, and then a metal Ti / Au (20 nm / 100 nm) is deposited on the bottom of the Ga 2 O 3 substrate 3 as the cathode 4 by using an electron beam evaporation (EBE) equipment. Then it is placed in an 80°C DMSO solution to remove the photoresist 7 on the surface, and then it is annealed for 60 s at 500°C in a nitrogen atmosphere in the RTP equipment to form an ohmic contact;

[0085] S6. First, the pattern transfer of the anode 1 region is realized through a bilayer resist process. A tackifier (HMDS) is dropped on the surface of the epitaxial wafer and spin-coated at a speed of 3000 rpm for 30 s and then left standing for 1 min, and then a photoresist (LOR) is dropped and spin-coated at a speed of 4000 rpm for 60 s; after the photoresist spin coating is completed, the epitaxial wafer is placed on a hot plate at 170°C and baked for 480 s, and then a photoresist is dropped and spin-coated at a speed of 3000 rpm for 35 s. After the photoresist spin coating is completed, the epitaxial wafer is placed on a hot plate at 100°C and baked for 180 s for pre-baking; then a metal Ni / Au (50 nm / 200 nm) is deposited on the surfaces of the first Ga 2 O 3 epitaxial layer 21, the second Ga 2 O 3 epitaxial layer 22 and the trench 10 as the anode 1, and then it is placed in an 80°C DMSO solution to strip the metal in the non-anode region, and a gallium oxide SBD device based on a trench structure is obtained.

[0086] Comparative Example 1

[0087] A device, which is different from that in Embodiment 1 in that the preparation method of the device in this comparative example refers to the preparation method of Embodiment 1 of the Chinese invention patent with the publication number of CN117457482A: directly on n - Ga 2 O 3 The surface of the epitaxial layer 2 is spin-coated with a Mg-doped SOG solution of 4×10 21 cm -3 to form a plurality of Mg-doped SOG coatings 8, and the interval between adjacent Mg-doped SOG coatings 8 is 4 μm. (That is, in step S3, the first Ga 2 O 3 epitaxial layer 21, the second Ga 2 O 3 epitaxial layer 22 and the preparation of the trench 10 are removed), and other structures and materials are the same as those in Embodiment 1.

[0088] Comparative Example 2

[0089] A device, the preparation method of the device in this comparative example refers to the preparation method of Embodiment 1 of the Chinese invention patent with the publication number of CN113964211A: etching a plurality of trenches arranged at intervals on the gallium oxide drift layer, and depositing NiO on the bottom and side walls of the trenches to form a dielectric layer.

[0090] Test Example

[0091] Perform performance tests on the devices of Embodiment 1 and Comparative Examples 1-2.

[0092] The test method is as follows:

[0093] Current density test method: Use a 4200-csc type semiconductor characteristic analysis system to test the current density of the device.

[0094] Breakdown voltage test method: Use a B1505A power device analyzer to test the breakdown voltage of the device.

[0095] On-resistance test method: Calculate the on-resistance according to the current density test results.

[0096] The test results are shown in Table 1:

[0097] Table 1 Performance test results

[0098] Test parameters <![CDATA[Current density (A / cm 2 )]]> <![CDATA[On-resistance (mΩ·cm 2 )]]> Breakdown voltage (V) Example 1 500 4.8 2200 Comparative Example 1 300 5 1200 Comparative Example 2 230 9 1500

[0099] It can be seen from the above test results that the electrical properties such as the current density, on-resistance, and breakdown voltage of the device of the present invention are significantly better than those of the comparative examples. This is because the diffusion of Mg at the bottom and side walls of the trenches slows down the generation of the peak electric field, thereby achieving a higher breakdown voltage.

[0100] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention.

[0101] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A gallium oxide SBD device based on a trench structure, characterized in that: The trench structure-based gallium oxide SBD device includes, from bottom to top, a cathode, a Ga2O3 substrate, and a trench structure; in, Groove structure: the groove structure comprises a first Ga2O3 epitaxial layer, and the first Ga2O3 epitaxial layer is deposited on the upper surface of the Ga2O3 substrate; A plurality of second Ga2O3 epitaxial layers are deposited on the upper surface of the first Ga2O3 epitaxial layer, and grooves are formed between adjacent second Ga2O3 epitaxial layers; A first high resistance region is disposed above the interior of the first Ga2O3 epitaxial layer located below the trench; A second high resistance region is provided at both sides of the second Ga2O3 epitaxial layer, an extension portion is provided at the lower end of the second high resistance region and extends into the first Ga2O3 epitaxial layer, and the thickness of the extension portion is the same as that of the first high resistance region; The first high resistance region and the second high resistance region are formed by Mg ions diffused into the first Ga2O3 epitaxial layer and the second Ga2O3 epitaxial layer respectively; The first high resistance region and the second high resistance region are both Mg ion doped regions; Anodes are deposited on the upper surfaces of the first Ga2O3 epitaxial layer and the second Ga2O3 epitaxial layer, and the anodes completely cover the upper surfaces of the first Ga2O3 epitaxial layer, the second Ga2O3 epitaxial layer and the groove.

2. The trench-structured gallium oxide SBD device according to claim 1, characterized in that: The width of the second Ga2O3 epitaxial layer is 2-5 μm.

3. The trench-structured gallium oxide SBD device according to claim 1, characterized in that: The width of the groove is 2-5 μm, and the depth is 400-600 nm.

4. The trench structure-based gallium oxide SBD device according to claim 1, characterized in that: The thickness of the first high resistance region is 700-900 nm.

5. The trench structure-based gallium oxide SBD device according to claim 1, characterized in that: The width of the second high resistance region is 700-900nm.

6. The trench-structured gallium oxide SBD device according to claim 1, characterized in that: The concentration of Mg ions is 1×10 17 ~4×10 19 cm -3 .

7. The method for preparing a trench-structured gallium oxide SBD device according to any one of claims 1 to 6, characterized in that: The steps include: S1. Prepare a multi-layer epitaxial wafer, wherein the epitaxial wafer comprises a Ga2O3 substrate and a Ga2O3 epitaxial layer from bottom to top; deposit a silicon dioxide layer on the surface of the Ga2O3 epitaxial layer as a hard mask to define a lithography area of ​​a groove; S2, spin coating a tackifier on the surface of the silicon dioxide layer, then drop coating a photoresist, pre-baking, exposing and removing the photoresist in the photolithography area of ​​the groove, and post-baking for hardening the film; S3, etching the photolithography area of ​​the groove, and then etching the Ga2O3 epitaxial layer located in the photolithography area of ​​the groove to form a groove; S4, spin coating a Mg-doped SOG solution on the surface of the first Ga2O3 epitaxial layer, the second Ga2O3 epitaxial layer and the groove, baking to obtain a Mg-doped SOG coating, annealing to diffuse Mg ions into the first Ga2O3 epitaxial layer and the second Ga2O3 epitaxial layer to form a first high resistance region, a second high resistance region and an extension portion, respectively, and removing the residual Mg-doped SOG coating; S5, depositing a cathode at the bottom of the Ga2O3 substrate to form an ohmic contact; S6. Depositing anodes on the surfaces of the first Ga2O3 epitaxial layer, the second Ga2O3 epitaxial layer and the trench to obtain a gallium oxide Schottky diode with a high breakdown voltage.

8. The method for preparing a trench-structured gallium oxide SBD device according to claim 7, characterized in that: In step S3, the silicon dioxide layer is etched using a BOE solution.

9. The method for preparing a trench-structured gallium oxide SBD device according to claim 7, characterized in that: In step S4, the thickness of the Mg-doped SOG coating is 800 nm-1 μm.

10. Application of the trench structure-based gallium oxide SBD device according to any one of claims 1 to 6 in semiconductor devices.

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