Semiconductor device structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device structure and a forming method thereof. The structure includes a source / drain region disposed over a substrate, an interlayer dielectric layer disposed over the source / drain region, a first conductive feature disposed over the source / drain region, a gate electrode layer disposed over the substrate, and a dielectric layer surrounding the first conductive feature. The dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, where at least a portion of the first portion has a first thickness and the second portion has a second thickness substantially greater than the first thickness.

Description

Technical Field

[0001] This application generally relates to the field of semiconductor manufacturing, and more particularly to semiconductor device structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. During the evolution of ICs, the functional density (i.e., the number of interconnect devices per chip area) generally increases, while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of fabricating ICs.

[0003] Accordingly, there is a need to improve the processing and fabrication of ICs. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a semiconductor device structure includes: a source / drain region disposed on a substrate; an interlayer dielectric layer disposed on the source / drain region; a first conductive feature disposed on the source / drain region; a gate electrode layer disposed on the substrate; and a dielectric layer surrounding the first conductive feature, wherein the dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, wherein at least a portion of the first portion has a first thickness, and the second portion has a second thickness significantly greater than the first thickness.

[0005] According to a second aspect of the present disclosure, a semiconductor device structure includes: a first source / drain region and a second source / drain region disposed on a substrate, wherein each of the first source / drain region and the second source / drain region includes a substance, the first source / drain region has a first concentration of the substance, and the second source / drain region has a second concentration of the substance, the second concentration being significantly less than the first concentration; a first conductive feature disposed on the first source / drain region, wherein the first conductive feature has a first size; and a second conductive feature disposed on the second source / drain region, wherein the second conductive feature has a second size significantly less than the first size.

[0006] According to a third aspect of the present disclosure, a method of forming a semiconductor device structure includes: forming a fin structure from a substrate; recessing a portion of the fin structure to expose a portion of the substrate; forming source / drain regions over the portion of the substrate; forming a gate electrode layer over the substrate; depositing an interlayer dielectric layer over the source / drain regions; forming an opening in the interlayer dielectric layer to expose the source / drain regions; depositing a dielectric layer in the opening, wherein the dielectric layer includes a first portion disposed in a first plane and a second portion disposed in a second plane, the second plane being substantially perpendicular to the first plane; performing an angled implant process to implant a material into the dielectric layer, wherein the material concentration in the first portion of the dielectric layer is significantly greater than the material concentration in the second portion of the dielectric layer; performing a cleaning process to remove a portion of the first portion of the dielectric layer; and filling the opening with a conductive feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figures 1 to 6 is a perspective view of various stages of fabricating a semiconductor device structure in accordance with some embodiments.

[0009] Figures 7A to 12A is in accordance with some embodiments along Figure 6 is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line A-A.

[0010] Figures 7B to 12B is in accordance with an alternative embodiment along Figure 6 is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line B-B.

[0011] Figures 7C to 12C is in accordance with an alternative embodiment along Figure 6 is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line C-C.

[0012] Figures 13A to 13G is in accordance with an alternative embodiment along Figure 6 is a cross-sectional side view of various stages of fabricating a semiconductor device structure taken along line C-C.

[0013] Figure 13D-1 shows the concentration distribution of a material in two source / drain regions of a semiconductor device structure in accordance with some embodiments.

[0014] Figure 13F-1is a top view of a dielectric layer of a semiconductor device structure according to some embodiments.

[0015] Figures 14A to 14B is one of the cross-sectional side views of the respective stages of manufacturing a semiconductor device structure taken along Figure 6 lines A-A and line C-C according to some embodiments.

[0016] Figures 15A to 15B is one of the cross-sectional side views of the respective stages of manufacturing a semiconductor device structure taken along Figure 6 lines A-A and line C-C according to some embodiments.

[0017] Figures 16A to 16C is a cross-sectional side view of the stages of manufacturing a semiconductor device structure taken along Figure 6 line C-C according to an alternative embodiment. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific instances of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] In addition, spatially relative terms (such as, "beneath", "below", "lower", "above", "on top", "up", "top", "upper", etc.) may be used herein to facilitate describing one element or feature shown in the figures relative to another (one or more) element or (one or more) feature. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0020] Although embodiments of the present disclosure are discussed with respect to nanostructure channel FETs (e.g., gate-all-around (GAA) FETs (e.g., horizontal gate-all-around (HGAA) FETs or vertical gate-all-around (VGAA) FETs)), implementations of some aspects of the present disclosure can be used in other processes and / or other devices (e.g., planar FETs, finFETs, and other suitable devices). Those of ordinary skill in the art will readily understand other modifications that may be contemplated within the scope of the present disclosure. In the case of employing a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes (including double patterning processes or multiple patterning processes) can be used to pattern these structures. Generally, double patterning processes or multiple patterning processes combine lithography processes and self-alignment processes, thereby allowing patterns to be created with pitches, for example, smaller than those obtainable using a single direct lithography process otherwise. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0021] Figures 1 to 15B An exemplary process for manufacturing a semiconductor device structure 100 in accordance with an embodiment of the present disclosure is shown. It should be understood that additional operations can be provided before, during, and after the Figures 1 to 15B shown process, and for additional embodiments of the method, some of the operations described below can be replaced or eliminated. The order of the operations / processes is not restrictive and can be interchanged.

[0022] Figures 1 to 6 is a perspective view of various stages of manufacturing a semiconductor device structure 100 in accordance with some embodiments. As Figure 1 shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a front side of a substrate 101. The substrate 101 can be a semiconductor substrate. The substrate 101 can include crystalline semiconductor materials such as, but not limited to: silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhanced insulation. In one aspect, the insulating layer is an oxygen-containing layer.

[0023] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for an n-type field effect transistor (n-type FET) and boron for a p-type field effect transistor (p-type FET).

[0024] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of a nanostructured channel in a multi-gate device (e.g., a nanostructured channel FET). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0025] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). By way of example, epitaxial growth of the layers of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0026] The first semiconductor layer 106 or portions thereof may form the (one or more) nanostructured channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanostructure is used herein to denote any material portion having nanoscale or even micron-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions having circular and substantially circular cross-sections, as well as bar-shaped or strip-shaped material portions including, for example, those having cylindrical or substantially rectangular cross-sections. The (one or more) nanostructured channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructure transistors. Nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge-channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0027] Each first semiconductor layer 106 may have a thickness in the range between about 5 nm and about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range between about 2 nm and about 50 nm. As Figure 1 shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for illustrative purposes only and is not intended to limit the scope specifically recited in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0028] In Figure 2In [description], fin structures 112 are formed from the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from the substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using a multi-patterning operation including a lithography process and an etching process. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process can include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element can be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in unprotected areas, leaving multiple extended fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or a combination thereof can be used to etch the trenches 114.

[0029] In Figure 3 [description], after forming the fin structures 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation (e.g., a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed such that the tops of the fin structures 112 are exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0030] In Figure 4 [description], the insulating material 118 is recessed to form isolation regions 120. The recessing of the insulating material 118 exposes portions of the fin structures 112, such as the semiconductor layer stack 104. The recessing of the insulating material 118 reveals the trenches 114 between adjacent fin structures 112. The isolation regions 120 can be formed using a suitable process (e.g., a dry etching process, a wet etching process, or a combination thereof). The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from the substrate 101.

[0031] InFigure 5 In Figure 5 , one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing uniform thickness layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Then, a gate spacer 138 is formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacer 138 may be formed by conformally depositing one or more layers of the gate spacer 138 and anisotropically etching the one or more layers. In some embodiments, the gate spacer 138 is also formed on the sidewalls of the exposed portions of the fin structure 112. Although one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be arranged along the X direction in some embodiments.

[0032] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material (such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or a combination of the foregoing).

[0033] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100.

[0034] In Figure 6 Figure 6 , the portions of the fin structure 112 not covered by the sacrificial gate structure 130 and the gate spacer 138 are recessed to a level above, at, or below the top surface of the isolation region 120. The recessing of these portions of the fin structure 112 may be accomplished by an etching process (isotropic or anisotropic etching process), and the etching process may be selective to one or more crystal planes of the substrate 101. The etching process may be a dry etching (such as RIE, NBE, etc.) or a wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH) or any suitable etchant).

[0035] Figure 7A 、 Figure 7B and 7C are respectively along Figure 61 is a cross-sectional side view of the semiconductor device structure 100 taken along lines AA, BB, and CC.

[0036] Figure 8A , Figure 8B and Figure 8C According to some embodiments, Figure 6 AA, BB and CC of FIG. 1 are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100. Figure 8A As shown, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, these portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a wet etchant (such as, but not limited to, ammonium hydroxide (NH 2 4 OH), tetramethylammonium hydroxide (TMAH), ethylenediaminecatechol (EDP) or potassium hydroxide (KOH) solution) to selectively etch the second semiconductor layer 108.

[0037] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 can be made of a low-K dielectric material (e.g., SiON, SiCN, SiOC, SiOCN, or SiN). The dielectric spacer 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), and then removing the portion of the conformal dielectric layer other than the dielectric spacer 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0038] Figure 9A , Figure 9B and Figure 9C According to some embodiments, Figure 6 AA, BB and CC of FIG. 1 are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100. Figure 9A and Figure 9CAs shown, source / drain (S / D) regions 146 are formed from substrate portion 116. The S / D regions 146 can grow vertically and horizontally to form facets that can correspond to the crystal planes of the material for the substrate portion 116. In the present disclosure, the source region and the drain region can be used interchangeably, and their structures are substantially the same. In addition, the (one or more) source / drain regions can refer to the source or the drain, individually or jointly depending on the context. The S / D regions 146 can be made of one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For p-channel FETs, a p-type dopant (such as boron (B)) can also be included in the S / D regions 146. The S / D regions 146 can be formed by an epitaxial growth method using CVD, ALD, or MBE.

[0039] In some embodiments, the S / D regions 146 are n-type epitaxial materials, and a dielectric layer 202 can be formed under the S / D regions 146 ( Figure 13A ). The dielectric layer 202 can prevent current leakage through the substrate portion 116. The dielectric layer 202 can include any suitable dielectric material, such as SiN. The dielectric layer 202 can be formed by first forming a conformal layer on the semiconductor device structure 100, forming a mask on a portion of the conformal layer, and removing the exposed portion of the conformal layer. In some embodiments, as Figure 13A shown, the dielectric layer 202 is formed under the S / D regions 146 that are n-type epitaxial materials, rather than under the S / D regions that are p-type epitaxial materials.

[0040] Figure 10A 、 Figure 10B and Figure 10C are cross-sectional side views of one of the respective stages of manufacturing the semiconductor device structure 100 taken along lines A-A, B-B, and C-C of Figure 6 , respectively, according to some embodiments. In Figure 10A 、 Figure 10B and Figure 10CIn [the figure], a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D regions 146. The CESL 162 can include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc., or a combination thereof, and can be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 over the semiconductor device structure 100. The material of the ILD layer 164 can include a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. An organic material (such as a polymer) can also be used for the ILD layer 164. The ILD layer 164 can be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after the ILD layer 164 is formed, the semiconductor device structure 100 can be heat-treated to anneal the ILD layer 164.

[0041] After the ILD layer 164 is formed, a planarization operation (such as CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as Figure 10A and Figure 10B shown.

[0042] Figure 11A , Figure 11B and Figure 11C are cross-sectional side views of one of the respective stages of manufacturing the semiconductor device structure 100 taken along lines A-A, B-B, and C-C of Figure 6 [the figure]. As Figure 11A and Figure 11B shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms openings between the gate spacers 138 and between the first semiconductor layer 106. The ILD layer 164 protects the S / D regions 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can first be removed by any suitable process (such as dry etching, wet etching, or a combination thereof), and subsequently the sacrificial gate dielectric layer 132 can be removed, which can also be performed by any suitable process (such as dry etching, wet etching, or a combination thereof). In some embodiments, a wet etchant (such as a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the ILD layer 164, and the CESL 162.

[0043] Portions of the second semiconductor layer 108 can be removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process will remove the SiGe while substantially not affecting the Si, the dielectric material of the gate spacer 138, and the dielectric spacer 144. In one embodiment, a wet etchant (such as but not limited to, hydrofluoric acid (HF), nitric acid (HNO 3 ), hydrochloric acid (HCl), phosphoric acid (H 3 PO 4 ), a dry etchant (such as fluorine-based (such as F 2 ) or chlorine-based gas (such as Cl 2 ), or any suitable isotropic etchant can be used to remove the second semiconductor layer 108.

[0044] After forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 can be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) (not shown) is formed between the exposed surface of the first semiconductor layer 106 and the gate dielectric layer 170. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO 2 -Al 2 O 3 ) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 can include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 can be deposited above the upper surface of the ILD layer 164. Then, the gate dielectric layer 170 and the gate electrode layer 172 formed above the ILD layer 164 are removed by using, for example, CMP until the top surface of the ILD layer 164 is exposed.

[0045] Figure 12A , Figure 12B and Figure 12C are cross-sectional side views of one of the respective stages of fabricating semiconductor device structure 100 taken along lines A-A, B-B, and C-C of Figure 6 as shown in Figure 12B and Figure 12C . A cut metal gate (CMG) process is performed. The CMG process separates the gate electrode layer 172 into multiple segments that can be controlled individually. In some embodiments, openings are formed in the gate electrode layer 172. The openings can extend into the S / D regions, such as between adjacent S / D regions 146, as shown in Figure 12C . A dielectric material 176 is formed in the openings. The dielectric material 176 can be any suitable material, such as SiN. In some embodiments, seams 178 are formed in the dielectric material 176 due to the high aspect ratio of the openings.

[0046] Figures 13A to 13F is a cross-sectional side view of one of the respective stages of fabricating semiconductor device structure 100 taken along line C-C of Figure 6 according to an alternative embodiment. For clarity, the CESL 162 is omitted in Figures 13A to 13F . As shown in Figure 13A , an etch stop layer 204 and another ILD layer 206 are formed over the ILD layer 164, the dielectric material 176, and the gate structure 174 ( Figure 12A ). The etch stop layer 204 can include the same material as the CESL 162, and the ILD layer 206 can include the same material as the ILD layer 164. Next, openings 208 are formed in the ILD layer 164, the ILD layer 206, the etch stop layer 204, and the CESL 162 to expose the S / D regions 146. In some embodiments, multiple openings 208 are formed, some of the openings 208 each expose two or more S / D regions 146, while some of the openings 208 each expose a single S / D region 146, as shown in Figure 13A . In some embodiments, two or more S / D regions 146 that are n-type epitaxial material are exposed in a single opening 208, while a single S / D region 146 that is p-type epitaxial material is exposed in an opening 208. The openings 208 can have different sizes (i.e., critical dimensions), such as ranging from about 20 nm to about 30 nm, from about 40 nm to about 60 nm, or greater than 80 nm.

[0047] In some embodiments, the portion of the CESL 162 ( Figure 12A ) that is formed on the sidewalls of the gate spacers 138 ( Figure 12A ) is removed during the formation of the openings 208. To improve the subsequently formed conductive features (Figure 14A in 230) and the gate electrode layer 172 ( Figure 14A ), a dielectric layer 210 is formed in the opening 208, as Figure 13B shown. The dielectric layer 210 may include any suitable dielectric material. In some embodiments, the dielectric layer 210 includes SiO 2 , SiOC, SiOCN or SiN. The dielectric layer 210 can be formed by any suitable process. In some embodiments, the dielectric layer 210 is a conformal layer and is formed by ALD. Next, an anisotropic etching process is performed to remove the horizontal portions of the dielectric layer 210. After the anisotropic etching process, the dielectric layer 210 is disposed on the sidewalls in the opening 208. The dielectric layer 210 can be formed on the sidewalls of the ILD layer 206, the ILD layer 164, the etch stop layer 204, and the CESL 162 in the XZ plane, as Figure 13C shown. The dielectric layer 210 can also be formed on the sidewalls of the gate spacer 138, the ILD layer 206, and the etch stop layer 204 in the YZ plane, as Figure 14A shown. The portion of the dielectric layer 210 disposed in the YZ plane contacts the gate spacer 138, and the gate spacer 138 is located near the gate electrode layer 172. The portion of the dielectric layer 210 disposed in the XZ plane is not disposed near the conductive material. At the current stage of manufacturing (i.e., after the anisotropic etching process), the thickness of the portion of the dielectric layer 210 disposed in the XZ plane and the thickness of the portion of the dielectric layer 210 disposed in the YZ plane are substantially the same.

[0048] As Figure 13D shown, an angled implantation process 212 is performed to implant a substance into the portion of the dielectric layer 210 disposed in the XZ plane. The angled implantation process 212 implants a substance such as Ge, Xe, Ar, Si or other suitable substances into the portion of the dielectric layer 210 disposed in the XZ plane, while the portion of the dielectric layer 210 disposed in the YZ plane is substantially not affected by the angled implantation process 212. In some embodiments, the angled implantation process 212 has an implantation energy ranging from about 0.3 keV to about 50 keV, a range from about 5E13 atoms / cm 2 to about 1E16 atoms / cm 2The implantation dose and a processing temperature ranging from about -100 degrees Celsius to about 500 degrees Celsius. To implant a substance into a portion of the dielectric layer 210 disposed in the XZ plane while avoiding implanting the substance into a portion of the dielectric layer 210 disposed in the YZ plane, the tilt implantation process 212 has a tilt angle ranging from about 1 degree to about 60 degrees, such as from about 5 degrees to about 45 degrees. In addition, the substrate 101 is not rotated during the tilt implantation process 212.

[0049] In some embodiments, the tilt angle A of the tilt implantation is relatively small, such as less than about 15 degrees, such as from about 5 degrees to about 10 degrees. As a result, the portion of the dielectric layer 210 disposed in the XZ plane is implanted with the substance from bottom to top. In other words, the substance can reach the bottom of the portion of the dielectric layer disposed in the XZ plane at a relatively small tilt angle A. In such embodiments, more substance can be implanted into two or more S / D regions 146 exposed in a single opening 208 compared to the substance implanted into a single S / D region 146 exposed in a single opening 208. The larger opening 208 allows more substance to reach the S / D region 146 located at the bottom of the larger opening 208. The size of the opening 208 (i.e., the critical dimension of the opening 208 in the Y direction) determines the size of the subsequently formed conductive feature 230 ( Figure 13G ). Thus, in some embodiments, there is a direct relationship between the size of the conductive feature 230 and the concentration of the substance in the S / D region 146 electrically connected to the conductive feature 230. For example, the concentration of the substance in two S / D regions 146 exposed in a single opening 208 is significantly greater than the concentration of the substance in a single S / D region 146 exposed in a single opening 208.

[0050] Figure 13D-1 Shows the concentration distribution of the substance in two source / drain regions 146 of the semiconductor device structure 100 according to some embodiments. In some embodiments, the concentration of the substance in the first S / D region 146 (which can be one of the two S / D regions 146 exposed in a single opening 208) has a first concentration distribution 302, while the concentration of the substance in the second S / D region 146 (which can be the single S / D region 146 exposed in a single opening 208) has a concentration distribution 304. As Figure 13D-1 shown, the concentration of the substance in the first S / D region 146 is significantly greater than the concentration of the substance in the second S / D region 146. Both concentration distributions 302 and 304 show that the concentration of the substance decreases in a direction away from the top surfaces of the first S / D region 146 and the second S / D region 146.

[0051] In some embodiments, the tilt angle A of the tilted injection is relatively large, e.g., greater than about 30 degrees, e.g., from about 40 degrees to about 60 degrees. As a result, in the larger opening 208, the portion of the dielectric layer 210 disposed in the XZ plane is injected with material from bottom to top, while in the smaller opening 208, the portion of the dielectric layer 210 disposed in the XZ plane is injected with material at the top. In other words, in the smaller opening 208, the material cannot reach the bottom of the portion of the dielectric layer disposed in the XZ plane at a relatively large tilt angle A. In such embodiments, in the larger opening 208, more of the portion of the dielectric layer 210 disposed in the XZ plane is injected with material, while in the smaller opening 208, only the top of the portion of the dielectric layer 210 disposed in the XZ plane is injected with material. For example, in the smallest opening 208, the top in the Z direction of the portion of the dielectric layer 210 disposed in the XZ plane is injected with material, while in the largest opening 208, the entire portion in the Z direction of the portion of the dielectric layer 210 disposed in the XZ plane is injected with material. As the size of the opening 208 increases, the length of the top of the dielectric layer 210 injected with material in the Z direction may increase.

[0052] The portion of the dielectric layer 210 injected with material (e.g., the top of the entire portion of the portion of the dielectric layer 210 disposed in the XZ plane) may have a material concentration ranging from about 0.5% to about 10%, while the portion of the dielectric layer 210 not injected with material (e.g., the portion of the dielectric layer 210 disposed in the YZ plane and the bottom of the portion of the dielectric layer 210 disposed in the XZ plane) may have a material concentration ranging from about 0.01% to about 0.1%.

[0053] In some embodiments, after the tilted injection process, another injection process is performed to inject dopant into the S / D region 146. The dopant can be any suitable dopant, e.g., Ge. The injection process may not have a tilt angle, and the substrate 101 may be rotated during the injection process. Thus, this injection process is different from the tilted injection process.

[0054] As Figure 13EAs shown, a cleaning process is performed on the semiconductor device structure 100. The cleaning process is used to remove any residual etchant from the processes of forming the opening 208 and forming the dielectric layer 210. In some embodiments, during the cleaning process, the etching rate of the implanted portion of the dielectric layer 210 is significantly greater than the etching rate of the non-implanted portion of the dielectric layer 210. As a result, the implanted portion of the dielectric layer 210 is removed by the cleaning process. The cleaning process can be a chemical oxide removal (COR) dry etching process or a wet etching process using diluted HF. In some embodiments, the material is Ge and the cleaning process is a wet cleaning process using diluted HF. As a result, a thickness greater than 1 nm of the implanted portion of the dielectric layer 210 is removed by the cleaning process. As Figure 13E shown, in some embodiments, the portion of the dielectric layer 210 disposed in the XZ plane has a thickness T1, and the thickness T1 is significantly less than the thickness of the portion of the dielectric layer 210 disposed in the XZ plane before the cleaning process. Since the entire portion in the Z direction of the portion of the dielectric layer 210 disposed in the XZ plane is implanted with the material, the thickness T1 can be substantially uniform.

[0055] In some embodiments, the portion of the dielectric layer 210 disposed in the Z direction has a non-uniform thickness after the cleaning process. As Figure 13F shown, in the smaller opening 208, the portion of the dielectric layer 210 disposed in the XZ plane includes a top having a thickness T1 and a bottom having a thickness T2, and the thickness T2 is significantly greater than the thickness T1. As described above, in some embodiments, the bottom of the portion of the dielectric layer 210 disposed in the XZ plane in the smaller opening 208 is not implanted with the material. As a result, in the smaller opening 208, the bottom of the portion of the dielectric layer 210 disposed in the XZ plane is substantially unaffected by the cleaning process, while in the smaller opening 208, the thickness of the top of the portion of the dielectric layer 210 disposed in the XZ plane is reduced by the cleaning process. In some embodiments, since the entire portion in the Z direction of the portion of the dielectric layer 210 disposed in the XZ plane in the larger opening 208 is implanted with the material, the thickness of the portion of the dielectric layer 210 disposed in the XZ plane is reduced to T1 by the cleaning process in the larger opening 208. As described above, the size of the conductive feature 230 is determined by the size of the opening 208. In some embodiments, there is a directional relationship between the ratio of the portion of the dielectric layer 210 disposed in the XZ plane having a thickness T1 to the portion of the dielectric layer 210 disposed in the XZ plane having a thickness T2 and the size of the conductive feature 230. For example, as Figure 13FAs shown, in the minimum opening 208, the portion of the dielectric layer 210 having a thickness T1 and the portion of the dielectric layer 210 having a thickness T2, both of which are disposed in the XZ plane, may have a first ratio. In an opening 208 larger than the minimum opening 208 (intermediate opening 208), the portion of the dielectric layer 210 having a thickness T1 and the portion of the dielectric layer 210 having a thickness T2, both of which are disposed in the XZ plane, may have a second ratio, and this second ratio is greater than the first ratio because the portion of the dielectric layer 210 having a thickness T1 disposed in the XZ plane increases. In the maximum opening 208, none of the portions of the dielectric layer 210 have a thickness T2, and the ratio of the portion of the dielectric layer 210 having a thickness T1 disposed in the XZ plane to the portion of the dielectric layer 210 having a thickness T2 disposed in the XZ plane will be infinite.

[0056] After the cleaning process, a silicide layer 214 is formed on each exposed S / D region 146, as Figure 13E and Figure 13F shown. The silicide layer 214 may include any suitable material, such as NiSi, TiSi, CoSi, RuSi, or WSi. The silicide layer 214 may be formed by any suitable process. In some embodiments, the silicide layer 214 is selectively formed on the S / D regions 146.

[0057] Figure 13F-1 is a top view of the dielectric layer 210 of a semiconductor device structure according to some embodiments. After the cleaning process, the dielectric layer 210 includes a first portion 210a having a thickness T1 and a second portion 210b having a second thickness T2, and the second thickness T2 is significantly greater than the first thickness T1. The first portion 210a may be the portion disposed in the XZ plane, while the second portion 210b may be the portion disposed in the YZ plane. The first portion 210a is connected to the second portion 210b. As described above, the first portion 210a is implanted with a substance, while the second portion 210b is not implanted. As a result, the cleaning process removes a part of the first portion 210a, while the second portion 210b is substantially unaffected by the cleaning process. In some embodiments, the first portion 210a has different thicknesses in the Z direction. For example, the thickness T2 at the bottom of the first portion 210a is significantly greater than the thickness T1 at the top of the first portion 210a. In some embodiments, the difference between the thickness T2 and the thickness T1 is greater than 1 nm.

[0058] As Figure 13GAs shown, a conductive feature 230 is formed in the opening 208. The conductive feature 230 can be conductive and can include a material having one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The conductive feature 230 can be formed by any suitable method, such as electrochemical plating (ECP) or PVD. A planarization operation (such as a CMP method) is performed to remove the portion of the conductive feature 230 that is formed on the ILD layer 206. Referring again to Figure 13F-1 , in some embodiments, a dielectric layer 210 surrounds the conductive feature 230.

[0059] Figures 14A to 14B is a cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100 taken along line A-A and line C-C, respectively, according to some embodiments. For clarity, components such as the gate dielectric layer 170, the silicide layer 214, and the CESL 162 are omitted. As Figure 6 shown, the conductive feature 230 and the gate electrode layer 172 are separated by the gate spacer 138 and a second portion 210b of the dielectric layer 210. The thickness of the second portion 210b of the dielectric layer 210 is substantially unaffected by the cleaning process. As a result, the electrical insulation between the conductive feature 230 and the gate electrode layer 172 is improved. As Figure 14A shown, the thickness of the first portion 210a of the dielectric layer 210 is reduced by the cleaning process. As a result, the process window for forming the conductive feature 240 ( Figure 14B ) is enlarged. Figure 15B

[0060] Figures 15A to 15B is a cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100 taken along line A-A and line C-C, respectively, according to some embodiments. For clarity, components such as the gate dielectric layer 170, the silicide layer 214, and the CESL 162 are omitted. As Figure 6 shown, an etch stop layer 216 is formed on the ILD layer 206, the dielectric layer 210, and the conductive feature 230, and a dielectric layer 218 is formed on the etch stop layer 216. The etch stop layer 216 can include the same material as the etch stop layer 204, and the dielectric layer 218 can include the same material as the ILD layer 206. A conductive feature 220 is formed in the dielectric layer 218, the etch stop layer 216, the ILD layer 206, and the etch stop layer 204 to be electrically connected to the gate electrode layer 172. As Figure 15A shown, in Figure 15A and Figure 15BAs shown, conductive features 240 are formed in dielectric layer 218 and etch stop layer 216, and conductive features 240 are electrically connected to conductive features 230. In some embodiments, conductive features 240 are in direct contact with conductive features 230. As Figure 15B shown, due to the reduced thickness of the first portion 210a of dielectric layer 210, the process window for forming conductive features 240 is enlarged. Additionally, in some embodiments, conductive features 240 contact both conductive features 230 and the first portion 210a of dielectric layer 210, as Figure 15B shown. Due to the small thickness T1 of the first portion 210a of dielectric layer 210, the contact resistance of conductive features 240 is reduced.

[0061] Figures 16A to 16C is a cross-sectional side view of various stages of manufacturing semiconductor device structure 100 taken along line C-C of Figure 6 . In some embodiments, an angled implant process 212 is performed after depositing dielectric layer 210 but before the anisotropic etch process to remove the horizontal portion of dielectric layer 210. The angled implant process implants material in the portion of dielectric layer 210 that is disposed in the XZ plane. In such embodiments, the material from angled implant process 212 may not be implanted into the S / D regions 146. Similar to the process described in Figure 13D , the top or entire portion (or first portion 210a) of dielectric layer 210 that is disposed in the XZ plane may be implanted with material, depending on the angle A ( Figure 13D ).

[0062] As Figure 16B shown, an anisotropic etch process is performed to remove the horizontal portion of dielectric layer 210. The material in the portion of dielectric layer 210 substantially does not affect the result of the anisotropic etch process. In other words, at the end of the anisotropic etch process, the thickness of dielectric layer 210 may be substantially uniform.

[0063] As Figure 16C shown, an implant process, a clean process, and a process for forming silicide layer 214 are performed. Similar to the processes described in Figure 13E , Figure 13F and Figure 13F-1 , the thickness of dielectric layer 210 changes after the clean process. Then the processes described in Figure 14A , Figure 14B , Figure 15A , Figure 15B are performed. By performing angled implant process 212 before the anisotropic etch process, no material is implanted into the S / D regions 146.

[0064] Embodiments of the present disclosure provide a semiconductor device structure 100. The semiconductor device structure 100 includes a dielectric layer 210 having a first portion 210a disposed in a first plane and a second portion 210b disposed in a second plane substantially perpendicular to the first plane. The first portion 210a has a first thickness T1, while the second portion 210b has a second thickness T2 significantly greater than the first thickness T1. Some embodiments can achieve various advantages. For example, through the larger thickness T2, the electrical insulation between the conductive feature 230 and the gate electrode layer 172 is improved. Through the smaller thickness T1, the process window for forming the conductive feature 240 is enlarged.

[0065] One embodiment is a semiconductor device structure. The structure includes source / drain regions disposed over a substrate, an interlayer dielectric layer disposed over the source / drain regions, a first conductive feature disposed over the source / drain regions, a gate electrode layer disposed over the substrate, and a dielectric layer surrounding the first conductive feature. The dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, wherein at least a portion of the first portion has a first thickness and the second portion has a second thickness significantly greater than the first thickness.

[0066] Another embodiment is a semiconductor device structure. The structure includes a first source / drain region and a second source / drain region disposed over a substrate. Each of the first source / drain region and the second source / drain region includes a material. The first source / drain region has a first concentration of the material, while the second source / drain region has a second concentration of the material, and the second concentration is significantly less than the first concentration. The structure further includes a first conductive feature disposed over the first source / drain region, and the first conductive feature has a first size. The structure further includes a second conductive feature disposed over the second source / drain region, and the second conductive feature has a second size significantly less than the first size.

[0067] Another embodiment is a method. The method includes: forming a fin structure from a substrate; recessing a portion of the fin structure to expose a portion of the substrate; forming source / drain regions over the substrate portion; forming a gate electrode layer over the substrate; depositing an interlayer dielectric layer over the source / drain regions; forming an opening in the interlayer dielectric layer to expose the source / drain regions; depositing a dielectric layer in the opening. The dielectric layer includes a first portion disposed in a first plane and a second portion disposed in a second plane, the second plane being substantially perpendicular to the first plane. The method further includes: performing an angled implantation process to implant a material into the dielectric layer, and a material concentration in the first portion of the dielectric layer being significantly greater than a material concentration in the second portion of the dielectric layer. The method further includes: performing a cleaning process to remove a portion of the first portion of the dielectric layer, and filling the opening with a conductive feature.

[0068] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0069] Example

[0070] Example 1. A semiconductor device structure includes: source / drain regions disposed over a substrate; an interlayer dielectric layer disposed over the source / drain regions; a first conductive feature disposed over the source / drain regions; a gate electrode layer disposed over the substrate; and a dielectric layer surrounding the first conductive feature, wherein the dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, wherein at least a portion of the first portion has a first thickness and the second portion has a second thickness significantly greater than the first thickness.

[0071] Example 2. The semiconductor device structure according to Example 1, wherein a difference between the first thickness and the second thickness is greater than about 1 nm.

[0072] Example 3. The semiconductor device structure according to Example 1, wherein the dielectric layer includes SiO 2 , SiOC, SiOCN, or SiN.

[0073] Example 4. The semiconductor device structure according to Example 1 further includes a silicide layer disposed between the source / drain region and the first conductive feature.

[0074] Example 5. The semiconductor device structure according to Example 4 further includes a second conductive feature in contact with the first conductive feature and a first portion of the dielectric layer.

[0075] Example 6. The semiconductor device structure according to Example 1 further includes a plurality of semiconductor layers, wherein the gate electrode layer surrounds at least a portion of each of the plurality of semiconductor layers.

[0076] Example 7. The semiconductor device structure according to Example 1, wherein the first portion includes a top having the first thickness and a bottom having a third thickness significantly greater than the first thickness.

[0077] Example 8. The semiconductor device structure according to Example 7, wherein the third thickness is substantially the same as the second thickness.

[0078] Example 9. A semiconductor device structure includes: a first source / drain region and a second source / drain region disposed on a substrate, wherein each of the first source / drain region and the second source / drain region includes a substance, the first source / drain region has a first concentration of the substance, and the second source / drain region has a second concentration of the substance, the second concentration being significantly less than the first concentration; a first conductive feature disposed on the first source / drain region, wherein the first conductive feature has a first size; and a second conductive feature disposed on the second source / drain region, wherein the second conductive feature has a second size significantly less than the first size.

[0079] Example 10. The semiconductor device structure according to Example 9 further includes: a dielectric layer surrounding the first conductive feature.

[0080] Example 11. The semiconductor device structure according to Example 10, wherein the dielectric layer includes a first portion and a second portion, wherein the first portion is connected to the second portion and is substantially perpendicular to the second portion.

[0081] Example 12. The semiconductor device structure according to Example 11, wherein the first portion has a first thickness and the second portion has a second thickness significantly greater than the first thickness.

[0082] Example 13. The semiconductor device structure according to Example 11, wherein the first part includes a top having a third thickness and a bottom having a fourth thickness, and the fourth thickness is significantly greater than the third thickness.

[0083] Example 14. The semiconductor device structure according to Example 9, wherein the substance includes Xe or Ar.

[0084] Example 15. A method of forming a semiconductor device structure, comprising: forming a fin structure from a substrate; recessing a portion of the fin structure to expose a substrate portion; forming source / drain regions over the substrate portion; forming a gate electrode layer over the substrate; depositing an interlayer dielectric layer over the source / drain regions; forming an opening in the interlayer dielectric layer to expose the source / drain regions; depositing a dielectric layer in the opening, wherein the dielectric layer includes a first part disposed in a first plane and a second part disposed in a second plane, and the second plane is substantially perpendicular to the first plane; performing an inclined implantation process to implant a substance into the dielectric layer, wherein the substance concentration in the first part of the dielectric layer is significantly greater than the substance concentration in the second part of the dielectric layer; performing a cleaning process to remove a portion of the first part of the dielectric layer; and filling the opening with a conductive feature.

[0085] Example 16. The method according to Example 15, further comprising: removing a horizontal portion of the dielectric layer before performing the inclined implantation process.

[0086] Example 17. The method according to Example 15, further comprising: removing a horizontal portion of the dielectric layer after performing the inclined implantation process, and the cleaning process is performed after removing the horizontal portion of the dielectric layer.

[0087] Example 18. The method according to Example 15, wherein the cleaning process is a wet cleaning process using diluted HF.

[0088] Example 19. The method according to Example 15, wherein the inclined implantation process has an inclination angle in a range from about 1 degree to about 60 degrees.

[0089] Example 20. The method according to Example 19, wherein the substance includes Ge, Xe, Ar, or Si.

Claims

1. A semiconductor device structure, comprising: A source / drain region is disposed on the substrate; An interlayer dielectric layer, disposed on the source / drain region; a first conductive feature disposed over the source / drain region; A gate electrode layer, disposed on the substrate; as well as A dielectric layer surrounding the first conductive feature, wherein the dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, wherein at least a portion of the first portion has a first thickness and the second portion has a second thickness significantly greater than the first thickness.

2. The semiconductor device structure according to claim 1, wherein: A difference between the first thickness and the second thickness is greater than about 1 nm.

3. The semiconductor device structure according to claim 1, wherein: The dielectric layer includes SiO2, SiOC, SiOCN or SiN. 4 . The semiconductor device structure of claim 1 , further comprising a silicide layer disposed between the source / drain regions and the first conductive feature. 5 . The semiconductor device structure of claim 4 , further comprising a second conductive feature in contact with the first conductive feature and the first portion of the dielectric layer.

6. The semiconductor device structure according to claim 1, further comprising a plurality of semiconductor layers, wherein: The gate electrode layer surrounds at least a portion of each of the plurality of semiconductor layers.

7. The semiconductor device structure according to claim 1, wherein: The first portion includes a top portion having the first thickness and a bottom portion having a third thickness that is substantially greater than the first thickness.

8. The semiconductor device structure according to claim 7, wherein: The third thickness is substantially the same as the second thickness.

9. A semiconductor device structure, comprising: A first source / drain region and a second source / drain region disposed on a substrate, wherein each of the first source / drain region and the second source / drain region comprises a substance, the first source / drain region has a first concentration of the substance, and the second source / drain region has a second concentration of the substance, the second concentration being significantly less than the first concentration; a first conductive feature disposed over the first source / drain region, wherein the first conductive feature has a first size; and A second conductive feature is disposed over the second source / drain region, wherein the second conductive feature has a second dimension that is significantly smaller than the first dimension.

10. A method for forming a semiconductor device structure, comprising: forming a fin structure from a substrate; recessing a portion of the fin structure to expose a substrate portion; forming a source / drain region over the substrate portion; forming a gate electrode layer on the substrate; depositing an interlayer dielectric layer over the source / drain regions; forming an opening in the interlayer dielectric layer to expose the source / drain region; depositing a dielectric layer in the opening, wherein the dielectric layer includes a first portion disposed in a first plane and a second portion disposed in a second plane, the second plane being substantially perpendicular to the first plane; performing a tilted implantation process to implant a species into the dielectric layer, wherein a concentration of the species in a first portion of the dielectric layer is significantly greater than a concentration of the species in a second portion of the dielectric layer; performing a cleaning process to remove a portion of the first portion of the dielectric layer; and The opening is filled with a conductive feature.

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