Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. According to the manufacturing method, first conduction type ions with the same doping dosage are formed in each polycrystalline silicon resistor by means of first conduction type ion implantation carried out on a device region, and second conduction type ions with different doping dosages are formed in each polycrystalline silicon resistor by means of second conduction type ion implantation carried out on the device region. After heat treatment, the polycrystalline silicon resistors form different net doping concentrations and resistivity, and the polycrystalline silicon resistors provide a wide resistance value range for designers. And a polycrystalline silicon resistor formed in the polycrystalline silicon resistor region and an electronic component formed in the device region can meet the design requirements under the condition of not adding an additional ion implantation process. The semiconductor structure is formed by adopting the manufacturing method.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Polycrystalline silicon resistors are one of the most commonly used components in semiconductor integrated circuit design. Polycrystalline silicon has the advantages of being easy to pattern and having low parasitic resistance. By adjusting the doping ions and doping levels, resistors with suitable resistance values can be obtained. Polycrystalline silicon resistors can be used as voltage dividers, current dividers, load resistors, etc. in a circuit.

[0003] Polycrystalline silicon resistors are usually formed in the polycrystalline silicon resistor region and the device region of the same substrate respectively with electronic components (such as MOS devices) that use the ion implantation process. And usually, the polycrystalline silicon in the polycrystalline silicon resistor region is ion implanted simultaneously by using the ion implantation in the device region process to form a polycrystalline silicon resistor in the polycrystalline silicon resistor region. However, the ion implantation is usually set according to the requirements of the device region process and may not meet the requirements for the doping level of the polycrystalline silicon resistor. Therefore, there is often a situation where the performance of the electronic components fabricated in the device region meets the design requirements, but the doping level or resistance of the polycrystalline silicon resistor cannot meet the design requirements. If the ion implantation shared by the device region and the polycrystalline silicon resistor region is directly adjusted, it will affect the process of the device region and the performance of the electronic components. If additional ion implantation is added to ion implant the polycrystalline silicon in the polycrystalline silicon resistor region, it will inevitably increase the production cost and complicate the production process. Summary of the Invention

[0004] In order to form electronic components that meet the design requirements in the device region and at the same time form polycrystalline silicon resistors that meet the design requirements in the polycrystalline silicon resistor region, and without adding an additional ion implantation process, the present invention provides a manufacturing method of a semiconductor structure, and also provides a semiconductor device.

[0005] On the one hand, the present invention provides a manufacturing method of a semiconductor structure, and the manufacturing method includes:

[0006] Providing a substrate, where the substrate has a device region and a polycrystalline silicon resistor region;

[0007] Forming at least two polycrystalline silicon resistors with different thicknesses in the polycrystalline silicon resistor region;

[0008] Performing ion implantation of a first conductivity type on the device region while exposing each of the polycrystalline silicon resistors to form ions of the first conductivity type with the same doping dose in each of the polycrystalline silicon resistors;

[0009] Perform ion implantation of the second conductivity type on the device region, and at the same time, form different ion blocking thicknesses on each of the polysilicon resistors by using a photoresist layer, and form ions of the second conductivity type with different doping doses in each of the polysilicon resistors; and

[0010] Perform heat treatment to make each of the polysilicon resistors have different net doping concentrations.

[0011] Optionally, the device region includes a MOS region of the first conductivity type and a MOS region of the second conductivity type; before performing ion implantation of the first conductivity type on the device region, the manufacturing method further includes: forming a first polysilicon gate in the MOS region of the first conductivity type, and forming a second polysilicon gate in the MOS region of the second conductivity type, wherein the thicknesses of the first polysilicon gate and the second polysilicon gate are both smaller than the maximum thickness of the polysilicon resistor.

[0012] Optionally, performing ion implantation of the first conductivity type on the device region includes: protecting the MOS region of the second conductivity type by using a patterned first photoresist layer, and exposing the MOS region of the first conductivity type and the polysilicon resistor region, and performing source / drain implantation of the first conductivity type.

[0013] Optionally, performing ion implantation of the second conductivity type on the device region includes: protecting the MOS region of the first conductivity type and at least part of the polysilicon resistor region by using a patterned second photoresist layer, and exposing the MOS region of the second conductivity type, and performing source / drain implantation of the second conductivity type.

[0014] Optionally, forming the first polysilicon gate, the second polysilicon gate, and each of the polysilicon resistors includes:

[0015] Form a polysilicon layer on the substrate, and the polysilicon layer has a first thickness;

[0016] Selectively thin the polysilicon layer to make the polysilicon layer in the polysilicon resistor region form at least two regions with different thicknesses, and the minimum thickness of the polysilicon layer in the polysilicon resistor region is greater than or equal to the thickness of the polysilicon layer in the MOS region of the first conductivity type and the MOS region of the second conductivity type; and

[0017] Pattern the polysilicon layer, form the first polysilicon gate in the MOS region of the first conductivity type, form the second polysilicon gate in the MOS region of the second conductivity type, and form at least two polysilicon resistors with different thicknesses in the polysilicon resistor region.

[0018] Optionally, selectively thinning the polysilicon layer includes:

[0019] Form a patterned first mask layer on the polysilicon layer, and openings in the first mask layer expose the first-conductivity-type MOS region, the second-conductivity-type MOS region, and part of the polysilicon resistor region;

[0020] Use the first mask layer as an etching mask to etch the polysilicon layer, so that the exposed polysilicon layer is thinned from a first thickness to a second thickness;

[0021] Form a patterned second mask layer on the polysilicon layer, and openings in the second mask layer expose the first-conductivity-type MOS region, part of the polysilicon resistor region covered with the polysilicon layer of the second thickness, and part of the polysilicon resistor region covered with the polysilicon layer of the first thickness;

[0022] Use the second mask layer as an etching mask to etch the polysilicon layer, so that the exposed polysilicon layer of the first thickness is thinned from the first thickness to a third thickness, and the exposed polysilicon layer of the second thickness is thinned from the second thickness to a fourth thickness; and

[0023] Form a patterned third mask layer on the polysilicon layer, and openings in the third mask layer expose the second-conductivity-type MOS region; and

[0024] Use the third mask layer as an etching mask to etch the polysilicon layer, so that the polysilicon layer of the exposed second-conductivity-type MOS region is thinned from the second thickness to the fourth thickness.

[0025] Optionally, the substrate includes isolation regions and active regions defined by the isolation regions, and the polysilicon resistor region is located in the isolation regions.

[0026] Optionally, before forming the polysilicon layer, the manufacturing method further includes:

[0027] Perform a second-conductivity-type well implantation on the substrate of the first-conductivity-type MOS region, and perform a first-conductivity-type well implantation on the substrate of the second-conductivity-type MOS region;

[0028] Wherein, the mask pattern used for the second-conductivity-type well implantation is obtained using the same photomask as the pattern of the second mask layer, and the mask pattern used for the first-conductivity-type well implantation is obtained using the same photomask as the pattern of the third mask layer.

[0029] Optionally, after selectively thinning and etching the polysilicon layer, four polysilicon resistors with thicknesses of a first thickness, a second thickness, a third thickness, and a fourth thickness are formed in the polysilicon resistor region, and the first thickness, the third thickness, the second thickness, and the fourth thickness decrease in sequence.

[0030] Optionally, the second photoresist layer covers each of the polysilicon resistors. The second photoresist layer on the polysilicon resistor with the fourth thickness blocks the ions of the second-conductivity-type source / drain ion implantation from passing through, and the second photoresist layers on the polysilicon resistors with the first thickness, the second thickness, and the third thickness only partially block the ions of the second-conductivity-type source / drain ion implantation from passing through.

[0031] Optionally, the first conductivity type is P-type and the second conductivity type is N-type.

[0032] On the other hand, the present invention provides a semiconductor structure formed by using the manufacturing method of the above semiconductor structure. The semiconductor structure includes:

[0033] A substrate having a device region and a polysilicon resistor region; and

[0034] At least two polysilicon resistors with different thicknesses, formed in the polysilicon resistor region, and each of the polysilicon resistors has a different net doping concentration.

[0035] Optionally, at least two of the polysilicon resistors have the same width, the same length, or the same aspect ratio.

[0036] In the manufacturing method of the semiconductor structure provided by the present invention, the first-conductivity-type ions implanted into the device region are used to form the first-conductivity-type ions with the same doping dose in each of the polysilicon resistors, and the second-conductivity-type ions implanted into the device region are used to form the second-conductivity-type ions with different doping doses in each of the polysilicon resistors, so that the first-conductivity-type doping doses in each of the polysilicon resistors are the same while the second-conductivity-type doping doses are different. After heat treatment, each of the polysilicon resistors forms different net doping concentrations and resistivities. This manufacturing method forms at least two polysilicon resistors with different thicknesses and different net doping concentrations in the polysilicon resistor region while performing the device region process. These polysilicon resistors provide a wider optional resistance value range for designers, which helps to make both the polysilicon resistors formed in the polysilicon resistor region and the electronic components formed in the device region meet the design requirements without adding an additional ion implantation process.

[0037] The semiconductor structure provided by the present invention is formed by using the manufacturing method of the above semiconductor structure. Among them, at least two polysilicon resistors with different thicknesses and different net doping concentrations are formed in the polysilicon resistor region, and the formation of each of the polysilicon resistors does not affect the doping process in the device region, which helps to make the electronic components in the device region and the polysilicon resistors in the polysilicon resistor region both meet the design requirements and improve the quality of the semiconductor structure. Description of the Drawings

[0038] Figure 1 It is a schematic flowchart of the manufacturing method of the semiconductor structure according to an embodiment of the present invention.

[0039] Figures 2A through 2L It is a schematic cross-sectional view of the manufacturing method of the semiconductor structure according to an embodiment of the present invention. Detailed Description of the Embodiment

[0040] The semiconductor structure and its manufacturing method of the present invention will be further described in detail below with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings in the specification are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the methods presented herein is not necessarily the only order in which these steps are to be performed. Some of the described steps may be omitted and / or some other steps not described herein may be added to the method. It should be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation of the device depicted in the figures. For example, if the structure in the drawings is inverted or positioned in some other different way (such as rotated), the exemplary term "on" may also include "under" and other orientation relationships.

[0041] The embodiment of the present invention relates to a manufacturing method of a semiconductor structure and a semiconductor structure. By using the manufacturing method, at least two polysilicon resistors with different net doping concentrations are formed on the substrate without adding an additional ion implantation process, that is, polysilicon resistors with different resistivity are obtained, which is convenient for meeting the design requirements of the polysilicon resistors. At the same time, the formation of polysilicon resistors with different net doping concentrations does not affect the doping process in the device region, which is convenient for ensuring that the electronic components fabricated in the device region meet the design requirements, thereby improving the quality of the semiconductor structure. The following combines Figures 1 through 2L to describe the manufacturing method.

[0042] Referring to Figure 1 and Figure 2A , for the manufacturing method of the semiconductor structure according to an embodiment of the present invention, first step S1 is performed to provide a substrate 100, and the substrate 100 has a device region 10 and a polysilicon resistor region 20.

[0043] The substrate 100 can be a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a group III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate), etc., or it can also be other substrates for carrying semiconductor components well-known to those skilled in the art. In the following description, the substrate 100 is, for example, a silicon substrate. Certain doping ions can be implanted into the substrate 100 according to design requirements to adjust electrical parameters. Moreover, an isolation structure (such as a shallow trench isolation, STI) can be formed within the substrate 100 to define and isolate electrical regions.

[0044] In this embodiment, the substrate 100 includes an isolation region in which an isolation structure is formed and an active region isolated by the isolation region. The polysilicon resistor region 20 is, for example, located in the isolation region and is used to form a polysilicon resistor. The device region 10 refers to the formation region of electronic components (such as MOS transistors) that use the ion implantation process during the manufacturing process, and the device region 10 is located in the active region. As an example, the device region 10 includes a first-conductivity-type MOS region 11 for forming a first-conductivity-type channel MOS device and a second-conductivity-type MOS region 12 for forming a second-conductivity-type channel MOS device. The first-conductivity-type MOS region 11 and the second-conductivity-type MOS region 12 can be isolated by a shallow trench isolation (STI). It should be noted that in this article, "MOS device" can include MOS transistors or other devices with a MOS structure having a gate, a source region, and a drain region (such as a floating-gate type storage device).

[0045] In the following description, the first conductivity type is, for example, P-type (such as doped with boron or indium), the second conductivity type is N-type (such as doped with arsenic or phosphorus), the first-conductivity-type MOS region 11 is used to form a P-type MOS device, and the second-conductivity-type MOS region 12 is used to form an N-type MOS device. However, the present invention is not limited thereto. In another embodiment, the first conductivity type can also be N-type and the second conductivity type can be P-type. Then, the first-conductivity-type MOS region is used to form an N-type MOS device, and the second-conductivity-type MOS region is used to form a P-type MOS device.

[0046] Before performing step S2, well implantations can be performed on the substrate 100 corresponding to the first-conductivity-type MOS region 11 and the second-conductivity-type MOS region 12, respectively. When performing well implantation corresponding to the first-conductivity-type MOS region 11, a patterned implantation mask is first formed on the substrate 100 to expose the first-conductivity-type MOS region 11 through the openings in the implantation mask, and then ion implantation of the second-conductivity-type well region is performed to form a second-conductivity-type well region in the substrate 100 of the first-conductivity-type MOS region 11 ( Figure 2A(not shown). When performing well implantation corresponding to the second-conductivity-type MOS region 12, a patterned implantation mask is first formed on the substrate 100, so that the openings in the implantation mask expose the second-conductivity-type MOS region 12, and then ion implantation of the well region of the first conductivity type is performed to form a well region of the first conductivity type in the substrate 100 of the second-conductivity-type MOS region 12. Figure 2A (not shown). Since the well region is formed corresponding to the active region, when performing the above well region ion implantation, the openings in the implantation mask can also expose at least part of the isolation region and the polysilicon resistor region 20 located in the isolation region, without affecting the formation of the well region.

[0047] Referring to Figure 1 , according to the manufacturing method of the semiconductor structure of the embodiment of the present invention, step S2 is executed to form at least two polysilicon resistors with different thicknesses in the polysilicon resistor region 20. In this embodiment, MOS devices are planned to be fabricated in the device region 10, and the polysilicon resistors can be formed by etching the same polysilicon layer as the polysilicon gate of the MOS device.

[0048] Specifically, referring to Figure 2B , a polysilicon layer 110 is formed on the substrate 100, and the polysilicon layer 110 has a first thickness H1.

[0049] Then, the polysilicon layer 110 is selectively thinned to obtain the thickness of the polysilicon gate to be formed in the device region 10 and the thicknesses of the respective polysilicon resistors. As an example, selectively thinning the polysilicon layer 110 includes the following process:

[0050] First, as Figure 2C shown, a patterned first mask layer PR1 (which can be a photoresist or other suitable material) is formed on the polysilicon layer 110, and the openings in the first mask layer PR1 expose the first-conductivity-type MOS region 11, the second-conductivity-type MOS region 12, and part of the polysilicon resistor region 20;

[0051] Next, as Figure 2D shown, using the first mask layer PR1 as an etching mask, the polysilicon layer 110 is etched to thin the exposed polysilicon layer 110 from the first thickness H1 to the second thickness H2, and then the first mask layer PR1 is removed;

[0052] After that, as Figure 2EAs shown, a patterned second mask layer PR2 is formed on the polysilicon layer 110. The openings in the second mask layer PR2 expose the first-conductivity-type MOS region 11, a part of the polysilicon resistor region 20 covered with the polysilicon layer 110 of the second thickness H2, and a part of the polysilicon resistor region 20 covered with the polysilicon layer 110 of the first thickness H1. Optionally, in order to save the cost of manufacturing the photomask, the pattern of the second mask layer PR2 can be formed using the same photomask as the injection mask for well implantation into the first-conductivity-type MOS region 11 above. That is, the photomask used for well implantation into the first-conductivity-type MOS region 11 can be modified, and openings required are formed on the photomask corresponding to the polysilicon resistor region 20, so that the photomask is reused for the well implantation process and the polysilicon thinning process, thereby saving the development cost of a new photomask;

[0053] Next, as Figure 2F shown, using the second mask layer PR2 as an etching mask, the polysilicon layer 110 is etched, so that the exposed polysilicon layer 110 with the first thickness H1 is thinned from the first thickness H1 to the third thickness H3, and the exposed polysilicon layer 110 with the second thickness H2 is thinned from the second thickness H2 to the fourth thickness H4, and then the second mask layer PR2 is removed;

[0054] After that, as Figure 2G shown, a patterned third mask layer PR3 is formed on the polysilicon layer 110. The openings in the third mask layer PR3 expose the second-conductivity-type MOS region 12. Optionally, in order to save the development cost of a new photomask, the pattern of the third mask layer PR3 can be formed using the same photomask as the injection mask for well implantation into the second-conductivity-type MOS region 12 above;

[0055] Next, as Figure 2H shown, using the third mask layer PR3 as an etching mask, the polysilicon layer 110 is etched, so that the polysilicon layer 110 of the exposed second-conductivity-type MOS region 12 is thinned from the second thickness H2 to the fourth thickness H4, and then the third mask layer PR3 is removed.

[0056] In this embodiment, after thinning, the polysilicon layers 110 of the first-conductivity-type MOS region 11 and the second-conductivity-type MOS region 12 are both of the fourth thickness H4. However, the present invention is not limited thereto. In another embodiment, the thicknesses of the polysilicon layers 110 of the first-conductivity-type MOS region 11 and the second-conductivity-type MOS region 12 may also be different. In addition, in this embodiment, a patterned second mask layer PR2 is formed by using the mask for forming the implantation mask during well implantation of the first-conductivity-type MOS region 11. Herein, the opening on the mask also exposes a part of the polysilicon resistor region 20. And a patterned third mask layer PR3 is formed by using the mask for forming the implantation mask during well implantation of the second-conductivity-type MOS region 12. That is, the polysilicon layers 110 of the first-conductivity-type MOS region 11 and the second-conductivity-type MOS region 12 are thinned by an asynchronous etching process. However, the present invention is not limited thereto. In another embodiment, the polysilicon layers 110 of the first-conductivity-type MOS region 11 and the second-conductivity-type MOS region 12 may also be thinned by a synchronous etching process.

[0057] In this embodiment, after the above process, the polysilicon layers 110 of the first-conductivity-type MOS region 11 and the second-conductivity-type MOS region 12 are of the fourth thickness H4, while the polysilicon layer 110 of the polysilicon resistor region 20 includes regions with thicknesses of the first thickness H1, the second thickness H2, the third thickness H3, and the fourth thickness H4 respectively. These polysilicon regions with different thicknesses can be used to form polysilicon resistors with different thicknesses respectively. Optionally, by setting process parameters, the first thickness H1, the third thickness H3, the second thickness H2, and the fourth thickness H4 are sequentially decreased. That is, by borrowing the masks in other process steps, a relatively large number of polysilicon resistors with different thicknesses are formed in an interleaved manner, which not only saves costs but also arranges the thicknesses in sequence.

[0058] After selectively thinning the polysilicon layer 110, as Figure 2I shown, the polysilicon layer 110 is patterned. A first polysilicon gate P1 is formed in the first-conductivity-type MOS region 11, a second polysilicon gate P2 is formed in the second-conductivity-type MOS region 12, and at least two polysilicon resistors with different thicknesses are formed in the polysilicon resistor region 20. As an example, through etching, the polysilicon layer 110 regions with the first thickness H1, the third thickness H3, the second thickness H2, and the fourth thickness H4 in the polysilicon resistor region 20 are respectively formed into polysilicon resistors with corresponding thicknesses, as Figure 2IAs shown, a first polysilicon resistor R1 with a first thickness H1, a second polysilicon resistor R2 with a third thickness H3, a third polysilicon resistor R3 with a second thickness H2, and a fourth polysilicon resistor R4 with a fourth thickness H4 are formed in the polysilicon resistor region 20, and the thicknesses of the first polysilicon resistor R1, the second polysilicon resistor R2, the third polysilicon resistor R3, and the fourth polysilicon resistor R4 gradually decrease. It can be seen that the thicknesses of the first polysilicon gate P1 and the second polysilicon gate P2 are both smaller than the maximum thickness (the first thickness H1) of the polysilicon resistor and are equal to the minimum thickness (the fourth thickness H4) of the polysilicon resistor.

[0059] It should be noted that, as an example, in this embodiment, polysilicon layer 110 regions with four thicknesses are formed in the polysilicon resistor region 20 through a thinning process. However, the present invention is not limited thereto. In other embodiments, two, three, or more than five thickness regions may also be formed. After patterning the polysilicon layer 110, polysilicon resistors with two, three, or more than five thicknesses can be formed.

[0060] The cross-sectional shapes, lengths, and widths of the above-mentioned polysilicon resistors can be set as needed. For example, the number, shape, and size of the polysilicon resistors can be set according to the space of the polysilicon resistor region 20. The length direction of each of the polysilicon resistors is, for example, perpendicular to Figure 2I the paper surface direction shown. In this embodiment, not only are the heights of the polysilicon resistors different, but the net doping concentrations formed subsequently are also different. In order to obtain a polysilicon resistor that meets the design requirements while reducing the area of the substrate 100 occupied by the polysilicon resistor, the resistance value can be mainly adjusted by the thickness and the net doping concentration, and the lengths of the polysilicon resistors are set to be relatively small according to the area of the substrate 100 occupied by the polysilicon resistor region. As an example, it can be set such that the widths, lengths, or length-width ratios of at least two polysilicon resistors formed in the polysilicon resistor region 20 are the same.

[0061] Referring to Figure 1 , according to the manufacturing method of the semiconductor structure of the embodiment of the present invention, step S3 is executed to perform ion implantation of the first conductivity type on the device region 10 while exposing each of the polysilicon resistors, and ions of the first conductivity type with the same doping dose are formed in each of the polysilicon resistors.

[0062] In this embodiment, the ion implantation of the first conductivity type on the device region 10 is, for example, source-drain ion implantation for the first conductivity type MOS region 11, and more specifically, for example, P+ source-drain ion implantation. Before performing the P+ source-drain ion implantation, other processes required for manufacturing MOS devices, such as forming sidewalls and LDD implantation, can be performed on the first conductivity type MOS region 11 and the second conductivity type MOS region 12. For the sake of clarity, they are not described herein again.

[0063] Reference Figure 2J Figure 2J , before performing P+ source / drain ion implantation on the MOS region 11 of the first conductivity type, a first photoresist layer PR4 is first formed on the substrate 100 and patterned, and the MOS region 12 of the second conductivity type is protected by the patterned first photoresist layer PR4 to prevent P-type ions from being implanted into the MOS region 12 of the second conductivity type.

[0064]

[0064] In order to perform P-type implantation on the polysilicon resistors in the polysilicon resistor region 20 while performing P+ source / drain ion implantation on the MOS region 11 of the first conductivity type, the opening of the first photoresist layer PR4 exposes both the MOS region 11 of the first conductivity type and the polysilicon resistor region 20. Thus, by performing P+ source / drain ion implantation, while forming a source implantation region and a drain implantation region in the MOS region 11 of the first conductivity type, P-type ions with the same doping dose are also formed in each polysilicon resistor in the polysilicon resistor region 20 ( Figure 2J Figure 2J denoted as "p" in [[ ]], as the ions of the first conductivity type). After completing the P+ source / drain ion implantation, the first photoresist layer PR4 is removed. The "doping dose" refers to the number of implanted ions per unit area.

[0065] Reference Figure 1 Figure 1 , according to the manufacturing method of the semiconductor structure of the embodiment of the present invention, step S4 is performed to perform second conductivity type ion implantation on the device region 10, and at the same time, different ion blocking thicknesses are formed on each polysilicon resistor by using a photoresist layer, and second conductivity type ions with different doping doses are formed in each polysilicon resistor.

[0066] Specifically, in this embodiment, the second conductivity type ion implantation performed on the device region 10 is, for example, source / drain ion implantation for the MOS region 12 of the second conductivity type, and more specifically, for example, N+ source / drain ion implantation. Reference Figure 2K Figure 2K , before performing N+ source / drain ion implantation on the MOS region 12 of the second conductivity type, a second photoresist layer PR5 is first formed on the substrate 100 and patterned, and the MOS region 11 of the first conductivity type is protected by the second photoresist layer PR5 to prevent N-type ions from being implanted into the MOS region 11 of the first conductivity type. The thickness of the second photoresist layer PR5 of the MOS region 11 of the first conductivity type should be sufficient to block the passage of N-type ions.

[0067] In this embodiment, while performing N+ source / drain ion implantation on the MOS region 12 of the second conductivity type, the second photoresist layer PR5 also covers at least a part of the polysilicon resistor region 20, so that different ion blocking thicknesses are formed on each polysilicon resistor to perform N-type implantation on at least some of the polysilicon resistors in the polysilicon resistor region 20.

[0068] In this embodiment, the fourth polysilicon resistor R4 and the first polysilicon gate P1 both have the fourth thickness R4. Therefore, the thickness of the second photoresist layer PR5 above the fourth polysilicon resistor R4 and the first polysilicon gate P1 is the same. According to the process of the device region 10, the second photoresist layer PR5 blocks the N+ source / drain ion implantation into the first polysilicon gate P1. Therefore, the second photoresist layer PR5 can also block the N-type ion implantation into the fourth polysilicon resistor R4.

[0069] In order to use the second photoresist layer PR5 to form different ion blocking thicknesses on each polysilicon resistor, so as to form second-conductivity-type ions with different doping doses in each of the polysilicon resistors. As an example, the second photoresist layer PR5 covers each of the polysilicon resistors. Since the thicknesses of the polysilicon resistors are different, the thicknesses of the second photoresist layer PR5 located on the polysilicon resistors are also different. Specifically, by setting the thickness of the second photoresist layer PR5, it can be made that only part of the ions blocked by the N+ source / drain ion implantation can pass through the second photoresist layer PR5 located on the first polysilicon resistor R1, the second polysilicon resistor R2, and the third polysilicon resistor R3. Among them, the smaller the thickness of the second photoresist layer PR5, the smaller the blocking ability. That is, the blocking ability of the second photoresist layer PR5 decreases as the thickness of the polysilicon resistor increases.

[0070] As Figure 2K shown, after the above N+ source / drain ion implantation, the doping dose of the N-type ions (denoted as "n", as the second-conductivity-type ions) formed in the first polysilicon resistor R1 with the largest thickness (the first thickness H1) is the largest, the doping dose of the N-type ions formed in the second polysilicon resistor R2 with the third thickness H3 is smaller than that of the first polysilicon resistor R1, the doping dose of the N-type ions formed in the third polysilicon resistor R3 with the second thickness H2 is smaller than that of the second polysilicon resistor R2, and the doping dose of the N-type ions formed in the fourth polysilicon resistor R4 with the smallest thickness (the fourth thickness H4) is smaller than that of the third polysilicon resistor R3 (in this embodiment, there is no N-type ion implantation in the fourth polysilicon resistor R4, that is, the doping dose of the N-type ions is 0). In another embodiment, the second photoresist layer PR5 may also not cover the polysilicon resistor with a larger thickness, so that after the N+ source / drain ion implantation, N-type ions with a larger doping dose can be formed. After the above N+ source / drain ion implantation is completed, the second photoresist layer PR5 is removed.

[0071] Referring to Figure 1 and Figure 2L , according to the manufacturing method of the semiconductor structure of the embodiment of the present invention, step S5 is executed to perform heat treatment to make each of the polysilicon resistors form different net doping concentrations.

[0072] The heat treatment can select a suitable heating method and heating conditions according to specific requirements. This heat treatment can also be used to activate the ions implanted in the substrates of the source-drain ion implantation in the first-conductivity-type MOS region 11 and the second-conductivity-type MOS region 12.

[0073] In this embodiment, through the above step S3, each polysilicon resistor has first-conductivity-type ions (such as P-type ions) with the same doping dose. Through the above step S4, each polysilicon resistor also has second-conductivity-type ions (such as N-type ions) with different doping doses. Thus, after step S5, the first-conductivity-type doping ions and the second-conductivity-type doping ions in each polysilicon resistor are activated and partially electrically neutralized, finally forming different net doping doses. Since in step S4, the smaller the thickness of the polysilicon resistor, the smaller the dose of the second-conductivity-type ions implanted therein. After step S5, the net ion doping amount per unit volume is larger, and the net doping concentration of the corresponding polysilicon resistor after heat treatment is larger. As an example, the doping dose of the first-conductivity-type ions in each polysilicon resistor is greater than that of the second-conductivity-type doping. After heat treatment, each polysilicon resistor is net-doped with the first conductivity type, and as the thickness increases, the net doping concentration of the polysilicon resistor gradually decreases.

[0074] The resistivity of the polysilicon resistor is inversely proportional to its doping concentration, as shown in Equation (1):

[0075] ρ=a*(l*w*h / α) (1)

[0076] Where ρ represents the resistivity, a is a constant, l represents the length, w represents the width, h represents the thickness, l*w*h represents the volume of the polysilicon resistor, and α represents the net ion doping amount.

[0077] The resistance value R of the polysilicon resistor can be expressed by Equation (2):

[0078] R=ρ*l / (w*h) (2)

[0079] Substituting Equation (1) into Equation (2), Equation (3) can be obtained:

[0080] R=a*(l*w*h / α)*l / (w*h)=a*l 2 / α (3)

[0081] It can be seen that the resistance value R of the polysilicon resistor is inversely proportional to the net ion doping amount α, directly proportional to the length l, and independent of the height h and width w of the polysilicon resistor. Therefore, when the lengths l of all polysilicon resistors are set to be equal, the polysilicon resistor with a larger net ion doping amount α has a smaller resistance value. In this embodiment, the doping concentrations of the polysilicon resistors are different, and the sizes and process parameters of the polysilicon resistors can be adjusted as needed. For example, the doping dose of the second conductivity type in the polysilicon resistor can be adjusted by adjusting the thickness of the second photoresist layer PR5, so that the resistance values of the polysilicon resistors are different. Adjusting the resistance value of the polysilicon resistor does not require changing the ion implantation process in the device region 10.

[0082] In the manufacturing method of the semiconductor structure described in the above embodiment, ion implantation is performed on the polysilicon resistors in the polysilicon resistor region 20 by using the ion implantation process in the device region 10, so that polysilicon resistors with different thicknesses form different net doping concentrations and resistivities. These polysilicon resistors provide a wide range of selectable resistance values for the designer. One or more of them can be selected for use in specific applications, which provides great convenience and does not add an additional ion implantation process, facilitating the polysilicon resistors formed in the polysilicon resistor region 20 and the electronic components formed in the device region 10 to meet the design requirements.

[0083] An embodiment of the present invention further relates to a semiconductor structure, and the semiconductor structure can be formed by using the manufacturing method of the semiconductor structure described in the above embodiment. Referring to Figure 2L , the semiconductor structure includes a substrate 100 and at least two polysilicon resistors with different thicknesses. Among them, the substrate 100 has a device region 10 and a polysilicon resistor region 20, and the polysilicon resistors are formed on the substrate 100 in the polysilicon resistor region 20, and each of the polysilicon resistors has a different net doping concentration.

[0084] The polysilicon resistors can be formed with different net doping concentrations by using the process described in the above embodiment. As an example, the semiconductor structure includes a first polysilicon resistor R1 with a first thickness H1, a second polysilicon resistor R2 with a third thickness H3, a third polysilicon resistor R3 with a second thickness H2, and a fourth polysilicon resistor R4 with a fourth thickness H4 formed on the substrate 100 in the polysilicon resistor region 20, where the first thickness H1, the third thickness H3, the second thickness H2, and the fourth thickness H4 gradually decrease. Optionally, each of the polysilicon resistors is doped with a net doping of the first conductivity type, and as the thickness increases, the net doping concentration of the polysilicon resistor gradually decreases.

[0085] The length and width of each polysilicon resistor can be set as needed. Since the resistivity of a polysilicon resistor is inversely proportional to its doping concentration, each polysilicon resistor has a different resistivity. By setting appropriate dimensions, different resistances can be achieved for each polysilicon resistor without changing the ion implantation process in device region 10 or adding additional ion implantation to the polysilicon resistor region 20, thus avoiding a significant increase in production cost and complication of the production process. In the semiconductor structure, the formation of each polysilicon resistor does not affect the doping process in the device region, which helps to ensure that the electronic components in device region 10 and the polysilicon resistors in polysilicon resistor region 20 both meet the design requirements and helps to improve the quality of the semiconductor structure. Using the semiconductor structure and the manufacturing method of the semiconductor structure described in the embodiments of the present invention, as device sizes become smaller and smaller, it is still possible to fabricate multiple selectable resistance values with the least cost investment and process changes in the case of a decreasing ability to select the spatial dimensions of the resistor, and the process is simple.

[0086] It should be noted that the embodiments in this specification are described in a progressive manner, with the key points of each part highlighting the differences from other parts. For the same or similar parts, reference can be made for understanding.

[0087] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the rights of the present invention in any way. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention all fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, comprising: providing a substrate having a device region and a polysilicon resistor region; forming at least two polysilicon resistors with different thicknesses in the polysilicon resistor region; performing a first-conductivity-type ion implantation on the device region while exposing each of the polysilicon resistors, and forming first-conductivity-type ions with the same doping dose in each of the polysilicon resistors; performing a second-conductivity-type ion implantation on the device region while forming different ion blocking thicknesses on each of the polysilicon resistors using a photoresist layer, and forming second-conductivity-type ions with different doping doses in each of the polysilicon resistors; and performing a heat treatment to form different net doping concentrations for each of the polysilicon resistors.

2. The manufacturing method according to claim 1, characterized in that, the device region includes a first-conductivity-type MOS region and a second-conductivity-type MOS region; before performing the first-conductivity-type ion implantation on the device region, the manufacturing method further includes: forming a first polysilicon gate in the first-conductivity-type MOS region and a second polysilicon gate in the second-conductivity-type MOS region, wherein the thicknesses of the first polysilicon gate and the second polysilicon gate are both smaller than the maximum thickness of the polysilicon resistor.

3. The manufacturing method according to claim 2, characterized in that, performing the first-conductivity-type ion implantation on the device region includes: using a patterned first photoresist layer to protect the second-conductivity-type MOS region, and exposing the first-conductivity-type MOS region and the polysilicon resistor region, and performing a first-conductivity-type source / drain implantation.

4. The manufacturing method according to claim 2, characterized in that, performing the second-conductivity-type ion implantation on the device region includes: using a patterned second photoresist layer to protect the first-conductivity-type MOS region and at least a part of the polysilicon resistor region, and exposing the second-conductivity-type MOS region, and performing a second-conductivity-type source / drain implantation.

5. The manufacturing method according to claim 4, characterized in that, forming the first polysilicon gate, the second polysilicon gate, and each of the polysilicon resistors includes: forming a polysilicon layer on the substrate, the polysilicon layer having a first thickness; selectively thinning the polysilicon layer to form at least two regions with different thicknesses of the polysilicon layer in the polysilicon resistor region, and the minimum thickness of the polysilicon layer in the polysilicon resistor region is greater than or equal to the thickness of the polysilicon layer in the first-conductivity-type MOS region and the second-conductivity-type MOS region; and patterning the polysilicon layer to form the first polysilicon gate in the first-conductivity-type MOS region, the second polysilicon gate in the second-conductivity-type MOS region, and at least two polysilicon resistors with different thicknesses in the polysilicon resistor region.

6. The manufacturing method according to claim 5, characterized in that, selectively thinning the polysilicon layer includes: A patterned first mask layer is formed on the polysilicon layer, and the openings in the first mask layer expose the first-conductivity-type MOS regions, the second-conductivity-type MOS regions, and part of the polysilicon resistor regions; The polysilicon layer is etched using the first mask layer as an etching mask, so that the exposed polysilicon layer is thinned from a first thickness to a second thickness; A patterned second mask layer is formed on the polysilicon layer, and the openings in the second mask layer expose the first-conductivity-type MOS regions, part of the polysilicon resistor regions covered with the polysilicon layer of the second thickness, and part of the polysilicon resistor regions covered with the polysilicon layer of the first thickness; The polysilicon layer is etched using the second mask layer as an etching mask, so that the exposed polysilicon layer of the first thickness is thinned from the first thickness to a third thickness, and the exposed polysilicon layer of the second thickness is thinned from the second thickness to a fourth thickness; and A patterned third mask layer is formed on the polysilicon layer, and the openings in the third mask layer expose the second-conductivity-type MOS regions; and The polysilicon layer of the exposed second-conductivity-type MOS regions is etched using the third mask layer as an etching mask, so that the polysilicon layer of the exposed second-conductivity-type MOS regions is thinned from the second thickness to the fourth thickness.

7. The manufacturing method according to claim 6, wherein, the substrate includes isolation regions and active regions defined by the isolation regions, and the polysilicon resistor regions are located in the isolation regions.

8. The manufacturing method according to claim 7, wherein, before forming the polysilicon layer, the manufacturing method further includes: performing a second-conductivity-type well implantation on the substrate of the first-conductivity-type MOS regions and performing a first-conductivity-type well implantation on the substrate of the second-conductivity-type MOS regions; wherein, the mask pattern used for the second-conductivity-type well implantation is obtained using the same photomask as the pattern of the second mask layer, and the mask pattern used for the first-conductivity-type well implantation is obtained using the same photomask as the pattern of the third mask layer.

9. The manufacturing method according to claim 6, wherein, after selectively thinning and etching the polysilicon layer, four polysilicon resistors with thicknesses of the first thickness, the second thickness, the third thickness, and the fourth thickness are formed in the polysilicon resistor regions, and the first thickness, the third thickness, the second thickness, and the fourth thickness decrease in sequence.

10. The manufacturing method according to claim 6, wherein, the second photoresist layer covers each of the polysilicon resistors, and the second photoresist layer on the polysilicon resistor at the third thickness blocks the ions of the second-conductivity-type source / drain ion implantation from passing through, and the second photoresist layer on the polysilicon resistors at the first thickness, the fourth thickness, and the second thickness only partially blocks the ions of the second-conductivity-type source / drain ion implantation from passing through.

11. The manufacturing method according to claim 10, wherein, The second photoresist layer covers each of the polysilicon resistors. The second photoresist layer on the polysilicon resistor at the fourth thickness blocks ions of the second-conductivity-type source / drain ion implantation from passing through, and the second photoresist layer on the polysilicon resistors at the first thickness, the second thickness, and the third thickness only partially blocks ions of the second-conductivity-type source / drain ion implantation from passing through.

12. The manufacturing method according to any one of claims 1 to 11, characterized in that the first conductivity type is P-type and the second conductivity type is N-type.

13. A semiconductor structure, characterized in that it is formed by using the manufacturing method according to any one of claims 1 to 12, and the semiconductor structure includes: a substrate having a device region and a polysilicon resistor region; and at least two polysilicon resistors with different thicknesses, formed in the polysilicon resistor region, and each of the polysilicon resistors has a different net doping concentration.

14. The semiconductor structure according to claim 13, characterized in that at least two of the polysilicon resistors have the same width, the same length, or the same aspect ratio.

Images