Integrated circuit including island-like power tap cells

Abstract

An integrated circuit includes: a plurality of active patterns including a first active pattern and a second active pattern each extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a front wiring layer disposed over the front surface of the substrate; a rear wiring layer disposed on the back surface of the substrate; and an island power tap unit disposed over the front surface of the substrate. The island-shaped power tap unit includes a first termination unit and a second termination unit spaced apart from each other in the second direction, and a power tap unit disposed between the first termination unit and the second termination unit and electrically connecting the rear wiring layer to the front wiring layer. The first active pattern is cut over the first termination unit, and the second active pattern is cut over the second termination unit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0164839 filed on November 23, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to an integrated circuit, and more particularly to an integrated circuit including an island-shaped power tap unit. Background Art

[0004] Due to the demand for high integration and the advancement of semiconductor processes, the width, spacing and / or height of the wires included in the integrated circuit may be reduced, and the influence of the parasitic components of the wires may increase. In addition, the power supply voltage of the integrated circuit may be reduced to reduce power consumption and increase the operating speed, etc., and therefore, the influence of the parasitic components of the wires on the integrated circuit may be more significant. Therefore, the demand for a method of designing an integrated circuit for effectively routing wires and vias is increasing. Summary of the invention

[0005] The present disclosure provides an integrated circuit and a method of designing the integrated circuit, which can reduce wiring complexity by using a front wiring layer and a rear wiring layer and improve power performance area (PPA) by arranging an island-shaped power tap unit.

[0006] According to one aspect of the present disclosure, an integrated circuit includes: a plurality of active patterns, including a first active pattern and a second active pattern, each extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a front wiring layer, arranged above the front side of a substrate; a rear wiring layer, arranged on the rear side of the substrate; and an island-shaped power tap unit, arranged on the front side of the substrate, wherein the island-shaped power tap unit includes a first terminal unit and a second terminal unit spaced apart from each other in the second direction, and a power tap unit arranged between the first terminal unit and the second terminal unit and electrically connecting the rear wiring layer to the front wiring layer, and the first active pattern is cut above the first terminal unit, and the second active pattern is cut above the second terminal unit.

[0007] In addition, according to another aspect of the present disclosure, an integrated circuit includes: a plurality of active patterns, including a first active pattern and a second active pattern each extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a front wiring layer arranged above the front side of a substrate; a rear wiring layer arranged on the back side of the substrate; a first row of power tap units arranged in a row in the second direction; a second row of power tap units arranged in a row in the second direction and spaced apart from the first row of power tap units in the first direction; and an island-shaped power tap unit arranged between the first row of power tap units and the second row of power tap units, wherein the island-shaped power tap unit includes a first terminal unit and a second terminal unit spaced apart from each other in the second direction, and a power tap unit arranged between the first terminal unit and the second terminal unit and electrically connecting the rear wiring layer to the front wiring layer, and the first active pattern is cut above the first terminal unit, and the second active pattern is cut above the second terminal unit.

[0008] In addition, according to another aspect of the present disclosure, an integrated circuit includes: a front wiring layer, arranged above the front side of a substrate and including a front wiring line extending in a first direction; a rear wiring layer, arranged on the back side of the substrate; a first row of power tap cells, arranged in a row in a second direction intersecting the first direction; a second row of power tap cells, arranged in a row in the second direction and spaced apart from the first row of power tap cells in the first direction; a first island-shaped power tap cell, arranged between the first row of power tap cells and the second row of power tap cells; and a second island-shaped power tap cell, arranged between the first row of power tap cells and the second row of power tap cells, wherein a height of the first island-shaped power tap cell in the second direction is different from a height of the second island-shaped power tap cell in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 shows a layout of an integrated circuit according to some embodiments;

[0011] Figure 2 is a diagram showing a method according to some embodiments Figure 1 A perspective view of a portion of an integrated circuit;

[0012] Figure 3A According to some embodiments, Figure 1 An example of a cross-sectional view taken along line X1-X1', Figure 3B According to some embodiments, Figure 1 Another example of a cross-sectional view taken along line X1-X1', and Figure 3C According to some embodiments, Figure 1 Another example of a cross-sectional view taken along line X1-X1';

[0013] Figure 4 According to some embodiments, Figure 1 A cross-sectional view taken along line X2-X2';

[0014] Figure 5 According to some embodiments, Figure 1 A cross-sectional view taken along line X3-X3';

[0015] Figure 6 shows a layout of an integrated circuit according to some embodiments;

[0016] Figure 7 shows a layout of an integrated circuit according to some embodiments;

[0017] Figure 8 shows a layout of an integrated circuit according to some embodiments;

[0018] Fig. 9 shows a layout of an integrated circuit according to some embodiments;

[0019] Fig.10 shows a layout of an integrated circuit according to some embodiments;

[0020] Fig.11 shows a first layout and a second layout according to some embodiments;

[0021] Fig.12 shows a first layout and a second layout according to some embodiments;

[0022] FIG. 13A to FIG. 13D shows a device according to some embodiments;

[0023] Fig.14 is a flow chart illustrating a method of manufacturing an integrated circuit according to some embodiments;

[0024] Fig.15 is a block diagram illustrating a system on a chip according to some embodiments; and

[0025] Fig.16 is a block diagram illustrating a computing system including a memory for storing programs according to some embodiments. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions thereof are omitted.

[0027] In the present disclosure, the X-axis direction may be referred to as a first horizontal direction or a first direction, the Y-axis direction may be referred to as a second horizontal direction or a second direction, and the Z-axis direction may be referred to as a vertical direction. A plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, a component arranged in the +Z-axis direction relative to other components may be referred to as being above another component, and a component arranged in the -Z-axis direction relative to other components may be referred to as being below another component.

[0028] An integrated circuit can be designed by arranging multiple standard cells. A standard cell is a layout unit of an integrated circuit and may be referred to as a "cell" depending on the implementation. A standard cell may be designed to include multiple transistors to perform a predetermined function. A standard cell method for designing a large-scale integrated circuit only for a customer or user pre-prepares standard cells with various functions and combines the standard cells with each other. The standard cells are pre-designed and verified and registered in a standard cell library, and computer-aided design (CAD) is used to perform logic design, layout, and wiring by combining standard cells, and thus, an integrated circuit can be designed. When designing an integrated circuit, the length of the wire and / or via and the wiring complexity are reduced, and therefore, the performance of the integrated circuit can be further increased.

[0029] Figure 1 The layout of integrated circuit 10 is shown in accordance with some embodiments.

[0030] refer to Figure 1 , the integrated circuit 10 includes an island-type island power tap cell (PTC) 110. According to some embodiments, the island power tap cell 110 may be referred to as an island small power tap cell (small PTC or sPTC). The island power tap cell 110 may be implemented as a multi-height cell. For example, the island power tap cell 110 includes a power tap cell 111, a first termination cell or a first termination cell 112, and a second termination cell or a second termination cell 113, and may be implemented with a height corresponding to a three-cell height (CH) 3-CH. The power tap cell 111, and each of the first termination cell 112 and the second termination cell 113 may be defined by a cell boundary BD.

[0031] The integrated circuit 10 may be implemented by a semiconductor device, and a substrate formed with the semiconductor device may have a first surface or a first face (eg, Figure 3A FS in), and a second surface or second face (e.g., Figure 3ABS in ). For example, the first surface may be a surface on which circuit elements such as transistors are arranged, and in the present disclosure, the first surface may be referred to as a "front surface" or "front side". The second surface may be a surface opposite to the first surface, and the second surface may be referred to as a "rear surface" or "back side" in this disclosure.

[0032] The integrated circuit 10 includes a front wiring layer or a front wiring layer M1, and a back wiring layer or a back wiring layer BM1, and a power distribution network PDN can be formed by using the front wiring layer M1 and the back wiring layer BM1. In this case, the front wiring layer M1 can be above the island-shaped power tap unit 110 along the vertical direction Z, and the back wiring layer BM1 can be below the island-shaped power tap unit 110 along the vertical direction Z. Therefore, some signals and / or power applied to the integrated circuit 10 can be transmitted through the front wiring layer M1 (i.e., the front PDN (FSPDN)), and other signals and / or power applied to the integrated circuit 10 can be transmitted through the back wiring layer BM1 (i.e., the back PDN (BSPDN)). Therefore, according to the embodiment shown, compared with the structure in which the wires are arranged only above the front surface of the substrate, the wiring complexity can be greatly reduced, and the length of each wire or via can also be reduced, and therefore, the performance of the integrated circuit 10 can be increased.

[0033] For example, the front wiring layer M1 includes a first front wiring line M1a and a second front wiring line M1b, each extending in a first direction X and spaced apart from each other in a second direction Y. According to some embodiments, the first front wiring line M1a and the second front wiring line M1b may also be referred to as a first power rail and a second power rail, respectively. For example, the rear wiring layer BM1 includes a first rear wiring pattern BM1a and a second rear wiring pattern BM1b, each extending in a first direction X and spaced apart from each other in a second direction Y. However, the present disclosure is not limited thereto, and the extension direction and arrangement of the first front wiring line M1a and the second front wiring line M1b and / or the first rear wiring pattern BM1a and the second rear wiring pattern BM1b may be changed in various ways according to the embodiment.

[0034] The integrated circuit 10 may include a plurality of active patterns each extending in a first direction X and spaced apart from each other in a second direction Y. For example, the plurality of active patterns are diffusion regions doped with impurities that change the electrical properties of the substrate material, and may form source / drain regions of a transistor. In some embodiments, the plurality of active patterns may correspond to nanosheets NS, and in this case, the integrated circuit 10 may include a multi-bridge channel field effect transistor (MBCFET). However, the present disclosure is not limited thereto, and in some embodiments, the plurality of active patterns may correspond to nanowires, and in this case, the integrated circuit 10 may include a full-surround gate field effect transistor (GAAFET). In addition, in some embodiments, the plurality of active patterns may correspond to fin structures or fins, and in this case, the integrated circuit 10 may include a FinFET.

[0035] The integrated circuit 10 may further include a cutting area or a cutting layer FC for cutting some active patterns. The cutting layer FC may overlap with a partial area of ​​the first terminal unit 112, the power tap unit 111, and a partial area of ​​the second terminal unit 113. For example, the power tap unit 111 and the first terminal unit 112 and the second terminal unit 113 may each have a first height H1 in the second direction Y, and the cutting layer FC may have a height corresponding to twice the first height H1 in the second direction Y (i.e., 2×H1). For example, the cutting layer FC may overlap the first height H1 with the power tap unit 111, overlap the second height H2 with the first terminal unit 112, and overlap the second height H2 with the second terminal unit 113. For example, the second height H2 may be half of the first height H1, but is not limited thereto.

[0036] The nanosheet NS overlapping the power tap unit 111 may be cut by the cutting layer FC. Among the nanosheet NS overlapping the first terminal unit 112, the nanosheet NS adjacent to the power tap unit 111 may be cut by the cutting layer FC. Among the nanosheet NS overlapping the second terminal unit 113, the nanosheet NS adjacent to the power tap unit 111 may be cut by the cutting layer FC. In addition, the nanosheet NSa overlapping the first terminal unit 112 and the nanosheet NSb overlapping the second terminal unit 113 may be used as a dummy nanosheet or a dummy pattern. However, the present disclosure is not limited thereto, and in some embodiments, the nanosheets NSa and NSb may also be cut by the cutting layer FC.

[0037] The power tap unit 111 may electrically connect the rear wiring layer BM1 to the front wiring layer M1, and transmit a positive power supply voltage or a negative power supply voltage from the rear wiring layer BM1 to the front wiring layer M1. According to some embodiments, the power tap unit 111 may be referred to as a "power pickup unit", "pickup unit" or "tap unit". Figure 2The structure of the power tap unit 111 is described in more detail.

[0038] Figure 2 is a schematic diagram showing a method according to some embodiments Figure 1 A perspective view of a partial area of ​​integrated circuit 10 is shown.

[0039] Reference together Figure 1 and Figure 2 , the power tap unit 111 includes a via pattern or a via V extending in a vertical direction Z. The via V may extend along the vertical direction Z between the rear wiring layer BM1 and the front wiring layer M1, and electrically connect the rear wiring layer BM1 to the front wiring layer M1. According to some embodiments, the via V may be referred to as a through hole. For example, the via V may extend along the vertical direction Z between the first rear wiring pattern BM1a and the first front wiring line M1a, and may electrically connect the first rear wiring pattern BM1a to the first front wiring line M1a.

[0040] Figure 1 It is shown that the power tap unit 111 includes two vias V. For example, the first rear wiring pattern BM1a can receive a positive supply voltage (e.g., a power supply voltage), and the second rear wiring pattern BM1b can receive a negative supply voltage (e.g., a ground voltage). In this case, the power tap unit 111 can transmit the power supply voltage from the first rear wiring pattern BM1a to the first front wiring line M1a through the via V, and transmit the ground voltage from the second rear wiring pattern BM1b to the second front wiring line M1b through the via V. However, the present disclosure is not limited thereto, and in some embodiments, the power tap unit 111 may include one via V. In this case, the power tap unit 111 can transmit the power supply voltage or the ground voltage from the rear wiring layer BM1 to the front wiring layer M1 through the via V.

[0041] Figure 3A According to some embodiments, Figure 1 An example of a cross-sectional view taken along line X1-X1'.

[0042] Reference together Figure 1 and Figure 3A The substrate SUB may include a semiconductor substrate having a front side FS and a back side BS. For example, the semiconductor substrate may include any one of silicon, silicon on insulator (SOI), silicon on sapphire, germanium, silicon germanium, and gallium arsenide. The interlayer insulating layer ILD may be on the substrate SUB. The interlayer insulating layer ILD may include an insulating material, and for example, the insulating material may include any one of an oxide layer, a nitride layer, and an oxynitride layer.

[0043] In some embodiments, the substrate SUB may correspond to a volumeless substrate. During the process of manufacturing the integrated circuit 10a, a device wafer may be manufactured by forming gate lines, source / drain regions, contacts, vias, and / or wiring layers on the front side FS of the substrate SUB. Subsequently, the device wafer may be temporarily bonded to a carrier wafer, and a back grinding process may be performed on the device wafer to remove at least a portion of the substrate. In this way, a wafer that is back ground so that the height of the substrate is a reference height or less may be referred to as a "volumeless wafer" or "volumeless substrate".

[0044] The first rear wiring pattern BM1a may extend from the back side BS of the substrate SUB in the first direction X. The first front wiring line M1a may extend along the first direction X on the interlayer insulating layer ILD. However, the present disclosure is not limited thereto, and the extending directions of the first rear wiring pattern BM1a and the first front wiring line M1a may be changed according to the embodiment. The lower surface of the via V may contact the first rear wiring pattern BM1a, and the upper surface of the via V may contact the first front wiring line M1a.

[0045] Figure 3B According to some embodiments, Figure 1 Another example of a cross-sectional view taken along line X1 - X1 ′.

[0046] Reference together Figure 1 and Figure 3B , the integrated circuit 10b and Figure 3A The modified example of the integrated circuit 10a corresponds to the above referenced Figure 3A The description made may also be applied to the illustrated embodiment. For example, the power tap unit 111 includes a rear via BVA and a via V'. The rear via BVA may be on the first rear wiring pattern BM1a and may extend through the substrate SUB in the vertical direction Z. The via V' may be on the rear via BVA and may extend through the interlayer insulating layer ILD in the vertical direction Z. Therefore, the first rear wiring pattern BM1a may be electrically connected to the first front wiring line M1a through the rear via BVA and the via V'.

[0047] Figure 3C According to some embodiments, Figure 1 Another example of a cross-sectional view taken along line X1 - X1 ′.

[0048] Reference together Figure 1 and Figure 3C , the integrated circuit 10c can be connected with Figure 3A The modified example of the integrated circuit 10a corresponds to the above referenced Figure 3AThe description may also be applied to the illustrated embodiment. For example, the power tap unit 111 includes a rear via BVA, a via V”, and a first via VA. The rear via BVA may be on the first rear wiring pattern BM1a and extend through the substrate SUB in the vertical direction Z. The via V” may be on the rear via BVA and extend through the interlayer insulating layer ILD in the vertical direction Z. The first via VA may be on the via V” and extend through the interlayer insulating layer ILD in the vertical direction Z. Therefore, the first rear wiring pattern BM1a may be electrically connected to the first front wiring line M1a through the rear via BVA, the via V”, and the first via VA.

[0049] Figure 4 According to some embodiments, Figure 1 A cross-sectional view taken along line X2-X2'. Figure 5 According to some embodiments, Figure 1 A cross-sectional view taken along line X3-X3'.

[0050] Figure 4 and Figure 5 An example of a nanosheet formed on an active region is shown. For example, an MBCFET may be formed in which a plurality of nanosheets are stacked on an active region and a gate line surrounds the plurality of nanosheets. However, the integrated circuit according to the present disclosure is not limited to Figure 4 and Figure 5 For example, a FinFET including a fin formed on an active area and a gate line may also be formed. In another example, a GAAFET may also be formed in which a nanowire formed on an active area is surrounded by a gate line. FIG. 13A to FIG. 13D This is described in more detail.

[0051] Reference together Figure 1 , Figure 4 and Figure 5 , a nanosheet stack or nanosheet NS extending in a first direction X may be above the front side FS of a substrate SUB. The nanosheet stack or nanosheet NS may include a plurality of nanosheets overlapping in a vertical direction Z, for example, a first nanosheet, a second nanosheet, and a third nanosheet (NS1, NS2, and NS3). For example, the nanosheet NS above the N-well may be doped with N-type impurities and form an N-type transistor. In addition, the nanosheet NS above the P-type substrate may be doped with P-type impurities and form a P-type transistor. In some embodiments, the nanosheet NS may include Si, Ge, or SiGe. In some embodiments, the nanosheet NS may include InGaAs, InAs, GaSb, InSb, or a combination thereof.

[0052] like Figure 4As shown, the nanosheet NS may be cut by the cutting layer FC overlapping the power tap unit 111, and the via hole V may extend in the vertical direction Z in the region where the nanosheet NS is removed. Figure 5 As shown, the nanosheet NS may be cut by the cutting layer FC overlapping the second terminal unit 113. In this way, the nanosheet NS may be cut by the cutting layer FC overlapping the first terminal unit 112 and the second terminal unit 113, and thus, the standard cell or the logic cell may be freely placed on the top or bottom of the island-shaped power tap unit 110.

[0053] Figure 6 The layout of an integrated circuit 20 is shown according to some embodiments.

[0054] refer to Figure 6 , the integrated circuit 20 includes an island-shaped power tap unit 110a. The integrated circuit 20 can be connected to Figure 1 The modified example of the integrated circuit 10 corresponds to and refers to the above Figures 1 to 5 The description made may also be applied to the illustrated embodiment. For example, the island-shaped power tap unit 110a includes first and second power tap units 111a and 111b, and first and second terminal units 112 and 113, thereby being implemented with a height corresponding to 4-CH.

[0055] The front wiring layer M1 includes a first front wiring line M1a, a second front wiring line M1b, and a third front wiring line M1c extending in the first direction X. The rear wiring layer BM1 includes a first rear wiring pattern BM1a, a second rear wiring pattern BM1b, and a third rear wiring pattern BM1c extending in the first direction X. The cutting layer FC may overlap with a partial area of ​​the first terminal unit 112, the first power tap unit 111a and the second power tap unit 111b, and a partial area of ​​the second terminal unit 113. For example, the first power tap unit 111a and the second power tap unit 111b, and the first terminal unit 112 and the second terminal unit 113 may each have a first height H1 in the second direction Y, and the cutting layer FC may have a height corresponding to three times the first height H1 in the second direction Y (i.e., 3×H1).

[0056] The nanosheet NS overlapping with the first power tap unit 111a may be cut by the cutting layer FC. The nanosheet NS overlapping with the second power tap unit 111b may be cut by the cutting layer FC. Among the nanosheet NS overlapping with the first terminal unit 112, the nanosheet NS adjacent to the first power tap unit 111a may be cut by the cutting layer FC. Among the nanosheet NS overlapping with the second terminal unit 113, the nanosheet NS adjacent to the second power tap unit 111b may be cut by the cutting layer FC. In addition, the nanosheet NSa overlapping with the first terminal unit 112 and the nanosheet NSb overlapping with the second terminal unit 113 may be used as a dummy nanosheet or a dummy pattern. However, the present disclosure is not limited thereto, and in some embodiments, the nanosheets NSa and NSb may also be cut by the cutting layer FC.

[0057] Figure 7 A layout of an integrated circuit 30 is shown according to some embodiments.

[0058] refer to Figure 7 , the integrated circuit 30 includes an island-shaped power tap unit 110b. The integrated circuit 30 can be connected to Figure 1 The modified example of the integrated circuit 10 corresponds to and refers to the above Figures 1 to 5 The description may also be applied to the illustrated embodiment. For example, the island-shaped power tap unit 110b includes the first power tap unit 111a, the second power tap unit 111b and the third power tap unit 111c, and the first terminal unit 112 and the second terminal unit 113, thereby being configured with a height corresponding to 5-CH.

[0059] The front wiring layer M1 includes a first front wiring line M1a, a second front wiring line M1b, a third front wiring line M1c, and a fourth front wiring line M1d extending in the first direction X. The rear wiring layer BM1 includes a first rear wiring pattern BM1a, a second rear wiring pattern BM1b, a third rear wiring pattern BM1c, and a fourth rear wiring pattern BM1d extending in the first direction X. The cutting layer FC may overlap with a partial area of ​​the first terminal unit 112, the first power tap unit 111a, the second power tap unit 111b, and the third power tap unit 111c, and a partial area of ​​the second terminal unit 113. For example, the first power tap unit 111a, the second power tap unit 111b, and the third power tap unit 111c, and the first terminal unit 112 and the second terminal unit 113 may each have a first height H1 in the second direction Y, and the cutting layer FC may have a height corresponding to four times the first height H1 in the second direction Y (i.e., 4×H1).

[0060] The nanosheet NS overlapping with the first power tap unit 111a may be cut by the cutting layer FC. The nanosheet NS overlapping with the second power tap unit 111b may be cut by the cutting layer FC. The nanosheet NS overlapping with the third power tap unit 111c may be cut by the cutting layer FC. Among the nanosheet NS overlapping with the first terminal unit 112, the nanosheet NS adjacent to the first power tap unit 111a may be cut by the cutting layer FC. Among the nanosheet NS overlapping with the second terminal unit 113, the nanosheet NS adjacent to the third power tap unit 111c may be cut by the cutting layer FC. In addition, the nanosheet NSa overlapping with the first terminal unit 112 and the nanosheet NSb overlapping with the second terminal unit 113 may be used as a dummy nanosheet or a dummy pattern. However, the present disclosure is not limited thereto, and in some embodiments, the nanosheets NSa and NSb may also be cut by the cutting layer FC.

[0061] like Figure 1 , Figure 6 and Figure 7 As shown, the number of power tap units included in the island-shaped power tap unit may be changed according to the implementation, and therefore, the height of the island-shaped power tap unit may be changed in various ways according to the implementation. In this way, according to the implementation of the present disclosure, the number of power tap units included in the island-shaped power tap unit may be increased or decreased in consideration of the power consumption according to the function of the integrated circuit.

[0062] Figure 8 A layout of an integrated circuit 40 is shown according to some embodiments.

[0063] refer to Figure 8 , the integrated circuit 40 includes an island-shaped power tap unit 110, and a first logic unit 120 and a second logic unit 130. For example, the island-shaped power tap unit 110 includes a power tap unit 111, and a first terminal unit 112 and a second terminal unit 113. However, the present disclosure is not limited thereto, and the island-shaped power tap unit 110 may include a plurality of power tap units between the first terminal unit 112 and the second terminal unit 113. Figures 1 to 7 The description made may also be applied to the illustrated embodiment.For example, the first logic unit 120 and the second logic unit 130 may be implemented as various components (eg, standard cells, blocks, macros, or memories).

[0064] When only the power tap unit 111 is between the first logic unit 120 and the second logic unit 130, a design rule violation may occur. For example, due to the arrangement of the power tap unit 111, the lower active pattern among the active patterns included in the first logic unit 120 may need to be cut by the cutting layer, and the upper active pattern among the active patterns included in the first logic unit 120 may be used only as a dummy pattern. Similarly, due to the arrangement of the power tap unit 111, the upper active pattern among the active patterns included in the second logic unit 130 may need to be cut by the cutting layer, and the lower active pattern among the active patterns included in the second logic unit 130 may be used only as a dummy pattern. Therefore, in the related art, a plurality of power tap units can only be arranged in an in-row shape.

[0065] However, according to some embodiments, the integrated circuit 40 includes an island-shaped power tap unit 110 in which the first terminal unit 112 is arranged on the top of the power tap unit 111 and the second terminal unit 113 is arranged on the bottom of the power tap unit 111. In this way, the first terminal unit 112 is between the first logic unit 120 and the power tap unit 111, and therefore, it may not be necessary to arrange a cutting layer for the first logic unit 120. Likewise, the second terminal unit 113 is between the second logic unit 130 and the power tap unit 111, and therefore, it may not be necessary to arrange a cutting layer for the second logic unit 130. Therefore, a design rule violation for the integrated circuit 40 may not occur, and the first logic unit 120 and the second logic unit 130 may be freely placed on the top and bottom of the island-shaped power tap unit 110.

[0066] Fig. 9 A layout of an integrated circuit 50 is shown in accordance with some embodiments.

[0067] refer to Fig. 9 , the integrated circuit 50 includes a first intra-row power tap unit 51, a second intra-row power tap unit 52, and a third intra-row power tap unit 53, as well as a first island-shaped power tap unit 54 and a second island-shaped power tap unit 55. In addition, the integrated circuit 50 includes a front wiring layer M1 and a rear wiring layer BM1. In addition, the integrated circuit 50 may also include an active region, a gate line, a source / drain, and a contact portion, and the gate line and the source / drain may receive power and / or signals from the front wiring layer M1 and the rear wiring layer BM1 through the contact portion.

[0068] The first intra-row power tap unit 51, the second intra-row power tap unit 52, and the third intra-row power tap unit 53, and the first island-shaped power tap unit 54 and the second island-shaped power tap unit 55 may each include a via V, and the via V may extend in the vertical direction Z to electrically connect the front wiring layer M1 to the back wiring layer BM1. For example, the front wiring layer M1 may include alternately arranged front wiring lines that each receive a positive power supply voltage or power supply voltage VDD or a negative power supply voltage or ground voltage VSS, but the present disclosure is not limited thereto.

[0069] The first in-row power tapping unit 51 may include a plurality of power tapping units arranged in a row in the second direction Y. The second in-row power tapping unit 52 may include a plurality of power tapping units arranged in a row in the second direction Y. The third in-row power tapping unit 53 may include a plurality of power tapping units arranged in a row in the second direction Y. For example, the first in-row power tapping unit 51 and the second in-row power tapping unit 52 may be spaced apart from each other by a first spacing S1 in the first direction X, and the second in-row power tapping unit 52 and the third in-row power tapping unit 53 may be spaced apart from each other by a first spacing S1 in the first direction X.

[0070] A plurality of logic cells or a plurality of standard cells may be placed between the first in-row power tap cell 51 and the second in-row power tap cell 52, and the plurality of logic cells or the plurality of standard cells may receive a power supply voltage VDD or a ground voltage VSS through the rear wiring layer BM1, the first in-row power tap cell 51, and the front wiring layer M1, or receive a power supply voltage VDD or a ground voltage VSS through the rear wiring layer BM1, the second in-row power tap cell 52, and the front wiring layer M1. In this case, as the first spacing S1 increases, the voltage transmission path for some of the plurality of logic cells or the plurality of standard cells increases, and therefore, an IR drop problem may occur. According to some embodiments, the first island-shaped power tap cell 54 may be in an IR drop susceptible area or an IR drop hotspot (e.g., a portion where a larger IR drop is expected, or a larger IR drop portion). Therefore, the IR drop for the logic cells and / or standard cells adjacent to the first island-shaped power tap cell 54 can be reduced, and power can be stably supplied.

[0071] Similarly, a plurality of logic cells or a plurality of standard cells may be placed between the second row power tap unit 52 and the third row power tap unit 53, and the plurality of logic cells or the plurality of standard cells may receive a power supply voltage VDD or a ground voltage VSS through the rear wiring layer BM1, the second row power tap unit 52, and the front wiring layer M1, or receive a power supply voltage VDD or a ground voltage VSS through the rear wiring layer BM1, the third row power tap unit 53, and the front wiring layer M1. In this case, as the first spacing S1 increases, the voltage transmission path for some of the plurality of logic cells or the plurality of standard cells increases, and an IR drop problem may occur. According to some embodiments, the second island-shaped power tap unit 55 may be in a portion susceptible to IR drop or an IR drop hotspot (e.g., a portion where a larger IR drop is expected, or a larger IR drop portion). Therefore, the IR drop for the logic cells and / or standard cells adjacent to the second island-shaped power tap unit 55 can be reduced, and power can be stably supplied.

[0072] Fig.10 A layout of an integrated circuit 60 is shown in accordance with some embodiments.

[0073] refer to Fig.10 The integrated circuit 60 includes a first row power tap unit 61, a second row power tap unit 62, and a third row power tap unit 63, and a first island power tap unit 64, a second island power tap unit 65, and a third island power tap unit 66. In addition, the integrated circuit 60 includes a front wiring layer M1 and a rear wiring layer BM1. The integrated circuit 60 can be connected to Fig. 9 The modified example of the integrated circuit 50 corresponds to and refers to the above Fig. 9 The description given also applies to the illustrated embodiment.

[0074] The first intra-row power tap unit 61, the second intra-row power tap unit 62, and the third intra-row power tap unit 63, and the first island-shaped power tap unit 64, the second island-shaped power tap unit 65, and the third island-shaped power tap unit 66 may each include a via V, and the via V may extend in the vertical direction Z to electrically connect the front wiring layer M1 to the back wiring layer BM1. For example, the front wiring layer M1 may include alternately arranged front wiring lines each receiving a positive power supply voltage or power supply voltage VDD or a negative power supply voltage or ground voltage VSS, but is not limited thereto.

[0075] The first in-row power tap unit 61 may include a plurality of power tap units arranged in a row in the second direction Y. The second in-row power tap unit 62 may include a plurality of power tap units arranged in a row in the second direction Y. The third in-row power tap unit 63 may include a plurality of power tap units arranged in a row in the second direction Y. The heights of the first island-shaped power tap unit 64, the second island-shaped power tap unit 65, and the third island-shaped power tap unit 66 in the second direction Y may be different. For example, the first island-shaped power tap unit 64 may be composed of 3-CH including a power tap unit and two termination units. For example, the second island-shaped power tap unit 65 may be composed of 4-CH including two power tap units and two termination units. For example, the third island-shaped power tap unit 66 may be composed of 5-CH including three power tap units and two termination units. In this way, according to the embodiment shown, the integrated circuit 60 may include island-shaped power tap units with different heights.

[0076] For example, the first island-shaped power tapping unit 64 may be spaced apart from the first in-row power tapping unit 61 by a second interval S2 in the first direction X, and may be spaced apart from the second in-row power tapping unit 62 by a second interval S2 in the first direction X. In this way, the first island-shaped power tapping unit 64 may be in a central area or a middle area between the first in-row power tapping unit 61 and the second in-row power tapping unit 62, but the present disclosure is not limited thereto.

[0077] For example, the second island-shaped power tapping unit 65 may be spaced apart from the first in-row power tapping unit 61 by a second interval S2 in the first direction X, and may be spaced apart from the second in-row power tapping unit 62 by a second interval S2 in the first direction X. In this way, the second island-shaped power tapping unit 65 may be in a central area or a middle area between the first in-row power tapping unit 61 and the second in-row power tapping unit 62, but the present disclosure is not limited thereto.

[0078] For example, the third island-shaped power tap unit 66 may be spaced apart from the second in-row power tap unit 62 by a second interval S2 in the first direction X, and may be spaced apart from the third in-row power tap unit 63 by a second interval S2 in the first direction X. In this way, the third island-shaped power tap unit 66 may be in a central area or a middle area between the second in-row power tap unit 62 and the third in-row power tap unit 63, but the present disclosure is not limited thereto.

[0079] Fig.11 A first layout 70 and a second layout 70a are shown according to some embodiments.

[0080] refer to Fig.11, a method of manufacturing an integrated circuit including a standard cell SC may include a placement and routing (P&R) operation, which includes a placement operation of arranging the standard cell SC, and a routing operation of routing the pins of the standard cell SC. Before arranging the standard cells, a first layout 70 may be generated by arranging the first intra-row power tap cells 71 and the second intra-row power tap cells 72, and the island-shaped power tap cells 73. Subsequently, a second layout 70a may be generated by arranging the standard cells SC in the area between the first intra-row power tap cells 71 and the second intra-row power tap cells 72, the area between the first intra-row power tap cells 71 and the island-shaped power tap cells 73, and the area between the second intra-row power tap cells 72 and the island-shaped power tap cells 73, respectively.

[0081] In some embodiments, the island-shaped power tap unit 73 may be pre-arranged in a portion susceptible to an expected IR drop between the power tap unit 71 in the first row and the power tap unit 72 in the second row. For example, the portion susceptible to an IR drop may be anticipated based on the distance from the power tap unit 71 in the first row and / or the distance from the power tap unit 72 in the second row, and the island-shaped power tap unit may be arranged in the portion susceptible to an expected IR drop. For example, the portion susceptible to an IR drop may be anticipated based on the spacing between the power tap unit 71 in the first row and the power tap unit 72 in the second row, and the island-shaped power tap unit may be arranged in the portion susceptible to an expected IR drop. For example, the portion susceptible to an IR drop may be anticipated based on the number of power tap units included in the power tap unit 71 in the first row and / or the number of power tap units included in the power tap unit 72 in the second row, and the island-shaped power tap unit may be arranged in the portion susceptible to an expected IR drop.

[0082] In some embodiments, before arranging the standard cells SC, the island-shaped power tapping cells 73 may be pre-arranged at the center region or the middle region between the first intra-row power tapping cells 71 and the second intra-row power tapping cells 72. Fig.11 It is shown that one island-shaped power tap unit 73 is arranged between the first intra-row power tap unit 71 and the second intra-row power tap unit 72, but the present disclosure is not limited thereto, and the number of island-shaped power tap units arranged between the first intra-row power tap unit 71 and the second intra-row power tap unit 72 may vary according to the embodiment. Fig.11 The island-shaped power tap unit 73 is shown to be composed of 3-CH, but the present disclosure is not limited thereto, and the height of the island-shaped power tap unit 73 in the second direction Y (ie, the number of power tap units included in the island-shaped power tap unit 73) may vary depending on the implementation.

[0083] Fig.12 A first layout 80 and a second layout 80a are shown according to some embodiments.

[0084] refer to Fig.12 , the method of manufacturing an integrated circuit including a standard cell SC may include a P&R operation and a verification operation. Through the P&R operation, a first layout 80 including a first intra-row power tap cell 81 and a second intra-row power tap cell 82, and a standard cell SC between the first intra-row power tap cell 81 and the second intra-row power tap cell 82 may be generated. Thereafter, in a verification operation, an IR drop may be checked to check the power stability of the first layout 80. In this case, a second layout 80a may be generated by adding an island-shaped power tap cell 83 to a portion where the IR drop is large.

[0085] In some embodiments, the island power tap unit 83 may be arranged in a free space where no standard cell SC is arranged through an engineering change order (ECO). In some embodiments, when the layout space for the island power tap unit 83 is insufficient, the island power tap unit 83 may be arranged by adjusting the layout of some standard cells SC through an ECO. For example, space for the island power tap unit 83 may be obtained by moving the positions of some standard cells SC through an ECO.

[0086] In some embodiments, in the verification operation, an island-shaped power tap unit 83 may be added to the IR drop susceptible portion in the region between the first intra-row power tap unit 81 and the second intra-row power tap unit 82. Fig.12 It is shown that one island-shaped power tap unit 83 is added between the first intra-row power tap unit 81 and the second intra-row power tap unit 82, but the present disclosure is not limited thereto, and the number of island-shaped power tap units between the first intra-row power tap unit 81 and the second intra-row power tap unit 82 may vary according to the embodiment. Fig.12 The island-shaped power tap unit 83 is shown to be composed of 3-CH, but the present disclosure is not limited thereto, and the height of the island-shaped power tap unit 83 in the second direction Y (ie, the number of power tap units included in the island-shaped power tap unit 83) may vary depending on the implementation.

[0087] FIG. 13A to FIG. 13D Devices according to some embodiments are respectively shown.

[0088] For example, Fig.13A FinFET 90a is shown, Fig. 13B GAAFET 90b is shown, Fig. 13C MBCFET90c is shown, and Fig.13DA vertical field effect transistor (VFET) 90d is shown. For ease of illustration, FIG. 13A to FIG. 13C Each shows one of the two source / drain regions removed, and Fig.13D A cross section of the VFET 90 d cut in another plane parallel to a plane formed by the second direction Y and the vertical direction Z and passing through the channel CH of the VFET 90 d is shown.

[0089] refer to Fig.13A , the FinFET 90a may be formed of a fin-shaped active pattern extending in the first direction X between the device isolation layers STI, and a gate G extending in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, respectively, and thus, the source may be spaced apart from the drain in the first direction X. An insulating layer may be between the channel CH and the gate G. In some embodiments, the FinFET 90a may be formed of the gate G, and a plurality of active patterns spaced apart from each other in the second direction Y.

[0090] refer to Fig. 13B , the GAAFET 90b may be formed of active patterns (i.e., nanowires) spaced apart from each other in the vertical direction Z and extending in the first direction X, and a gate G extending in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, respectively, and thus the source may be spaced apart from the drain in the first direction X. An insulating layer may be between the channel CH and the gate G. The number of nanowires included in the GAAFET 90b is not limited to Fig. 13B Number of nanowires shown.

[0091] refer to Fig. 13C , the MBCFET 90c may be formed of active patterns (i.e., nanosheets) spaced apart from each other in the vertical direction Z and extending in the first direction X, and a gate G extending in the second direction Y. The source / drain S / D may be formed on both sides of the gate G, respectively, and thus the source may be spaced apart from the drain in the first direction X. An insulating layer may be between the channel CH and the gate G. The number of nanosheets included in the MBCFET 90c is not limited to Fig. 13C Number of nanosheets shown.

[0092] refer to Fig.13D , the VFET 90d includes a top source / drain T_S / D and a bottom source / drain B_S / D spaced apart from each other in the vertical direction Z, and a channel CH therebetween. The VFET 90d includes a gate G surrounding the periphery of the channel CH between the top source / drain T_S / D and the bottom source / drain B_S / D. An insulating layer may be between the channel CH and the gate G.

[0093] However, the transistor according to the embodiment is not limited to the above structure. For example, the integrated circuit may include a ForkFET having a structure in which a P-type transistor is close to an N-type transistor by separating a nanosheet for a P-type transistor from a nanosheet for an N-type transistor using a dielectric wall. In addition, the integrated circuit may include not only a bipolar junction transistor but also a FET (e.g., a complementary FET (CFET), a negative capacitance FET (NCFET), and a carbon nanotube (CNT) FET).

[0094] Fig.14 is a flow chart illustrating a method of fabricating an integrated circuit according to some embodiments.

[0095] refer to Fig.14 , the method according to the embodiment shown is a method for manufacturing an integrated circuit IC including a standard cell, and includes a plurality of operations S10, S30, S50, S70 and S90. The cell library (or standard cell library) D12 may include information related to the standard cell, for example, information related to functions, characteristics, layouts, etc. In some embodiments, the cell library D12 may define a tap cell and a dummy cell, and a functional cell that generates an output signal from an input signal. In some embodiments, the cell library D12 may define a storage cell and a dummy cell with the same occupied area. The design rule D14 may include requirements that must be followed in the layout of the integrated circuit IC. For example, the design rule D14 may include requirements for the spacing between patterns in the same layer, the minimum width of the pattern, the wiring direction of the wiring layer, etc. In some embodiments, the design rule D14 may define the minimum spacing in the same track of the wiring layer.

[0096] In operation S10, a logic synthesis operation of generating netlist data D13 according to RTL data D11 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis according to RTL data D11 generated as VHSIC hardware description language (VHDL) and hardware description language (HDL) (e.g., Verilog) with reference to cell library D12, and may generate netlist data D13 including a bitstream or a netlist. Netlist data D13 may correspond to inputs of placement and routing described below.

[0097] In operation S30, standard cells may be arranged. For example, a semiconductor design tool (e.g., a P&R tool) may arrange standard cells used in the netlist data D13 with reference to the cell library D12. In some embodiments, the semiconductor design tool may arrange the standard cells in a row extending along the X-axis direction or the Y-axis direction, and the arranged standard cells may receive power from a power rail extending along a boundary of the row.

[0098] In some embodiments, the intra-row power tap unit and the island power tap unit may be arranged before the standard unit is arranged. For example, the intra-row power tap unit may be arranged before the standard unit is arranged, and the island power tap unit may be arranged in the IR drop susceptible portion where the IR drop is expected to be larger. For example, the portion susceptible to IR drop may be expected based on the distance from the intra-row power tap unit, and the island power tap unit may be arranged in the portion susceptible to the expected IR drop. For example, the portion susceptible to IR drop may be expected based on the spacing between the intra-row power tap units, and the island power tap unit may be arranged in the portion susceptible to the expected IR drop. For example, the portion susceptible to IR drop may be expected based on the number of power tap units included in the intra-row power tap unit, and the island power tap unit may be arranged in the portion susceptible to the expected IR drop.

[0099] In operation S50, the pins of the standard cell can be wired. For example, the semiconductor design tool can generate an interconnection that electrically connects the output pin to the input pin of the arranged standard cell, and generates layout data D15 defining the arranged standard cell and the generated interconnection. The interconnection may include a via in a via layer and / or a pattern in a wiring layer. The wiring layer may include a front wiring layer in the upper portion of the front side of the substrate, and a rear wiring layer on the rear surface of the substrate. The layout data D15 may have a format such as GDSII, and may include geometric information of the cell and the interconnection. The semiconductor design tool may refer to the design rule D14 while wiring the pins of the cell. The layout data D15 may correspond to the output of the arrangement and wiring. Only operation S50, or both operation S30 and operation S50, may be referred to as a method for designing an integrated circuit.

[0100] In some embodiments, the integrated circuit may include an in-row power tap unit and an island power tap unit, and each power tap unit may include at least one via. At least one via may electrically connect the rear wiring layer to the front wiring layer. Since the island power tap unit includes a power tap unit and a termination unit, a logic unit or a standard unit may be freely arranged on the top and / or bottom of the island power tap unit. Therefore, the degree of freedom of unit arrangement in the integrated circuit may be increased, and performance may be increased by reducing IR drop.

[0101] In operation S70, an operation of manufacturing a mask may be performed. For example, in photolithography, optical proximity correction (OPC) for correcting distortion (e.g., refraction) caused by characteristics of light may be applied to the layout data D15. A pattern on a mask may be defined to form patterns on a plurality of layers based on data to which OPC is applied, and at least one mask (or photomask) for forming a pattern for each of the plurality of layers may be manufactured. In some embodiments, the layout of the integrated circuit IC may be limitedly modified in operation S70, and the limited modification of the integrated circuit IC in operation S70 is a post-processing for optimizing the structure of the integrated circuit IC, and may be referred to as design polishing.

[0102] In operation S90, an operation of manufacturing an integrated circuit IC may be performed. For example, an integrated circuit IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S70. The front end process (FEOL) may include, for example, planarizing and cleaning the wafer, forming a groove, forming a well, forming a gate line, and forming a source and a drain. Various components such as transistors, capacitors, and resistors may be formed in the substrate by the FEOL. In addition, the back end process (BEOL) may include, for example, performing silicide of the gate region, the source region, and the drain region, adding a dielectric, performing planarization, forming a hole, adding a metal layer, forming a via, forming a passivation layer, etc. Various components such as transistors, capacitors, and resistors may be interconnected to each other by the BEOL. In some embodiments, an intermediate process (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed on various components. Subsequently, the integrated circuit IC may be packaged in a semiconductor package and may be used as a component in various applications.

[0103] Fig.15 is a block diagram illustrating a system on chip (SoC) 210 according to some embodiments.

[0104] refer to Fig.15 , SoC 210 may refer to an integrated circuit in which components of a computing system or electronic system are integrated. For example, an application processor (AP) (e.g., SoC 210) may include a processor, and components for other functions. SoC 210 includes a core 211, a digital signal processor (DSP) 212, a graphics processing unit (GPU) 213, an embedded memory 214, a communication interface (I / F) 215, and a memory I / F 216. The components of SoC 210 may communicate with each other through a bus 217.

[0105] The core 211 may process instructions and control the operation of components included in the SoC 210. For example, the core 211 may drive an operating system by processing a series of instructions and execute an application of the operating system. The DSP 212 may generate useful data by processing digital signals (e.g., digital signals provided from the communication interface 215). The GPU 213 may generate data for an image output on a display device based on image data provided from the embedded memory 214 or the memory interface 216, and may encode the image data. In some embodiments, the integrated circuit described above with reference to the accompanying drawings may be included in the core 211, the DSP 212, the GPU 213, and / or the embedded memory 214.

[0106] The embedded memory 214 may store data required by the core 211, the DSP 212, and the GPU 213 for operation. The communication interface 215 may provide an interface for a communication network or one-to-one communication. The memory interface 216 may provide an interface to an external memory (e.g., a dynamic random access memory (DRAM) and a flash memory) of the SoC 210.

[0107] Fig.16 is a block diagram illustrating a computing system 220 including a memory for storing programs according to some embodiments.

[0108] refer to Fig.16 In the method of designing an integrated circuit according to some embodiments, for example, at least some operations in the above flowchart may be performed by a computing system 220. The computing system 220 includes a processor 221, an input / output (I / O) device 222, a network interface 223, a random access memory (RAM) 224, a read-only memory (ROM) 225, and a storage device 226. The processor 221, the I / O device 222, the network interface 223, the RAM 224, the ROM 225, and the storage device 226 may be connected to a bus 227 and may communicate with each other through the bus 227.

[0109] The processor 221 may be referred to as a processing unit and may include at least one core (e.g., a microprocessor, an AP, a DSP, or a GPU) that may execute any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, the processor 221 may access a memory (i.e., a RAM 224 or a ROM 225) via a bus 227 and may execute instructions stored in the RAM 224 and the ROM 225.

[0110] According to some embodiments, the RAM 224 may store a program 224_1 for a method of designing an integrated circuit or at least a portion of the program 224_1, and the program 224_1 may enable the processor 221 to execute the method of designing an integrated circuit (eg, Fig.14 That is, the program 224_1 may include a plurality of instructions that can be executed by the processor 221, and the plurality of instructions included in the program 224_1 may enable the processor 221 to perform, for example, at least some of the operations included in the above flowchart.

[0111] The storage device 226 may not lose the stored data even when the power supplied to the computing system 220 is disconnected. The storage device 226 may store the program 224_1 according to some embodiments, and before the program 224_1 is executed by the processor 221, the program 224_1 or at least a portion of the program 224_1 may be loaded from the storage device 226 into the RAM 224. Alternatively, the storage device 226 may store a file written in a programming language, and the program 224_1 or at least a portion of the program 224_1 generated from the file by a compiler or the like may be loaded into the RAM 224. In addition, the storage device 226 may store a database (DB) 226_1, and the database 226_1 may include information required for designing an integrated circuit, for example, information related to the designed blocks, Fig.14 The information related to the cell library D12 and / or the design rule D14.

[0112] The storage device 226 may also store data to be processed by the processor 221 or data processed by the processor 221. That is, the processor 221 may generate data by processing the data stored in the storage device 226 according to the program 224_1, and also store the generated data in the storage device 226. For example, the storage device 226 may store Fig.14 RTL data D11, netlist data D13 and / or layout data D15.

[0113] The I / O device 222 may include an input device (e.g., a keyboard or a pointing device) and an output device (e.g., a display device or a printer). For example, the user may also trigger the execution of the program 224_1 by using the processor 221 via the I / O device 222, and may also read the program 224_1. Fig.14 The RTL data D11 and / or netlist data D13 can also be checked Fig.14 The layout data D15. The network interface 223 may provide access to an external network of the computing system 220. For example, the external network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links.

[0114] As described above, embodiments are disclosed in the drawings and the specification. Although embodiments are described in the present disclosure by using specific terms, this is only for the purpose of describing the technical concept of the present disclosure and is not intended to limit the meaning or scope of the present disclosure as set forth in the claims. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments can be derived from these embodiments. Therefore, the true technical protection scope of the present disclosure should be determined by the technical concept of the attached patent claims.

[0115] Although the present disclosure includes many specific implementation details, these specific implementation details should not be interpreted as limiting the scope that can be claimed. In a single embodiment, the specific features described in the context of independent embodiments in the present disclosure can also be implemented in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any appropriate sub-combination. In addition, although features can be described above as working in a specific combination and even initially claimed as such, one or more features from the combination can be deleted from the combination in some cases, and the combination can be directed to a sub-combination or a variation of the sub-combination.

[0116] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: a plurality of active patterns, including a first active pattern and a second active pattern, wherein the first active pattern and the second active pattern each extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction; A front wiring layer, arranged above the front surface of the substrate; a rear wiring layer disposed on the back side of the substrate; and an island-shaped power tap unit, arranged on the front side of the substrate, wherein the island-shaped power tap unit comprises a first terminal unit and a second terminal unit spaced apart from each other in the second direction, and comprises a power tap unit arranged between the first terminal unit and the second terminal unit and electrically connecting the rear wiring layer to the front wiring layer, and The first active pattern is cut above the first terminal unit, and the second active pattern is cut above the second terminal unit.

2. The integrated circuit according to claim 1, wherein: The plurality of active patterns further include a third active pattern adjacent to the first active pattern and overlapping the first terminal unit, and a fourth active pattern adjacent to the second active pattern and overlapping the second terminal unit, and The third active pattern and the fourth active pattern are configured as dummy patterns.

3. The integrated circuit of claim 1 , further comprising: cutting the layer, cutting at least one active pattern among the plurality of active patterns, wherein the at least one active pattern overlaps with the island-shaped power tap unit, and The first active pattern and the second active pattern are cut by the cutting layer above the first terminal unit and the second terminal unit, respectively.

4. The integrated circuit according to claim 3, wherein: The cutting layer overlaps a partial area of ​​the first terminal unit, overlaps the power tap unit, and overlaps a partial area of ​​the second terminal unit.

5. The integrated circuit according to claim 3, wherein: A height of the cutting layer in the second direction corresponds to twice a height of the power tap unit in the second direction.

6. The integrated circuit according to claim 3, wherein: The plurality of active patterns further include at least one fifth active pattern overlapping the power tap unit, and The at least one fifth active pattern is cut by the cutting layer over the power tap unit.

7. The integrated circuit according to claim 1, wherein: The power tapping unit includes a plurality of power tapping units arranged in the second direction.

8. The integrated circuit of claim 1, wherein: Each of the plurality of active patterns includes at least one of a fin, a nanowire, and a nanosheet.

9. The integrated circuit of claim 1, wherein: The front wiring layer includes a first front wiring line and a second front wiring line, The rear wiring layer includes a first rear wiring pattern and a second rear wiring pattern, and The power tap unit includes at least one of a first via hole vertically extending between the first front wiring line and the first rear wiring pattern and a second via hole vertically extending between the second front wiring line and the second rear wiring pattern.

10. The integrated circuit of claim 1, wherein: The power tap unit is configured to transfer a positive supply voltage from the rear wiring layer to the front wiring layer.

11. The integrated circuit of claim 1 , wherein: The power tap unit is configured to transfer a negative power supply voltage from the rear wiring layer to the front wiring layer.

12. An integrated circuit comprising: a plurality of active patterns, including a first active pattern and a second active pattern, wherein the first active pattern and the second active pattern each extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction; A front wiring layer, arranged above the front surface of the substrate; A rear wiring layer arranged on the back side of the substrate; a plurality of first in-row power tap units arranged in a row in the second direction; a plurality of second in-row power tapping units arranged in a row in the second direction and spaced apart from the plurality of first in-row power tapping units in the first direction; and an island-shaped power tap unit, arranged between the plurality of first-row power tap units and the plurality of second-row power tap units, wherein the island-shaped power tap unit comprises a first terminal unit and a second terminal unit spaced apart from each other in the second direction, and comprises a power tap unit arranged between the first terminal unit and the second terminal unit and electrically connecting the rear wiring layer to the front wiring layer, and The first active pattern is cut above the first terminal unit, and the second active pattern is cut above the second terminal unit.

13. The integrated circuit of claim 12, further comprising: A plurality of standard cells are arranged between the plurality of first in-row power tap cells and the island-shaped power tap cells, and between the plurality of second in-row power tap cells and the island-shaped power tap cells.

14. The integrated circuit of claim 12, wherein: The plurality of active patterns further include a third active pattern adjacent to the first active pattern and overlapping the first terminal unit, and a fourth active pattern adjacent to the second active pattern and overlapping the second terminal unit, and The third active pattern and the fourth active pattern are configured as dummy patterns.

15. The integrated circuit of claim 12, further comprising: cutting the layer, cutting at least one active pattern among the plurality of active patterns, wherein the at least one active pattern overlaps with the island-shaped power tap unit, and The first active pattern and the second active pattern are cut by the cutting layer above the first terminal unit and the second terminal unit, respectively.

16. The integrated circuit of claim 15, wherein: The plurality of active patterns further include at least one fifth active pattern overlapping the power tap unit, and The at least one fifth active pattern is cut by the cutting layer over the power tap unit.

17. The integrated circuit of claim 12, wherein: The power tapping unit includes a plurality of power tapping units arranged in the second direction.

18. An integrated circuit comprising: a front wiring layer disposed above the front surface of the substrate, wherein the front wiring layer includes a plurality of front wiring lines extending in a first direction; A rear wiring layer arranged on the back side of the substrate; a plurality of first in-row power tap units arranged in a row in a second direction intersecting the first direction; a plurality of second in-row power tapping units arranged in a row in the second direction and spaced apart from the plurality of first in-row power tapping units in the first direction; a first island-shaped power tapping unit disposed between the plurality of first in-row power tapping units and the plurality of second in-row power tapping units; and a second island-shaped power tapping unit, arranged between the plurality of first in-row power tapping units and the plurality of second in-row power tapping units, Wherein, a height of the first island-shaped power tap unit in the second direction is different from a height of the second island-shaped power tap unit in the second direction.

19. The integrated circuit of claim 18, wherein: The first island-shaped power tap unit includes a first terminal unit and a second terminal unit spaced apart from each other in the second direction, and includes a power tap unit disposed between the first terminal unit and the second terminal unit and electrically connecting the rear wiring layer to the front wiring layer, and The second island-shaped power tap unit includes a third terminal unit and a fourth terminal unit spaced apart from each other in the second direction, and includes a plurality of power tap units arranged between the third terminal unit and the fourth terminal unit and electrically connecting the rear wiring layer to the front wiring layer.

20. The integrated circuit of claim 19, further comprising: a plurality of active patterns extending in the first direction and spaced apart from each other in the second direction; a first cutting layer for cutting at least one first active pattern among the plurality of active patterns, wherein the at least one first active pattern overlaps with the first island-shaped power tap unit; and The second cutting layer cuts at least one second active pattern among the plurality of active patterns, wherein the at least one second active pattern overlaps with the second island-shaped power tap unit.

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