Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a base insulating layer including a first surface and a second surface opposite to the first surface; the channel layer is located on the first surface of the base body insulating layer; source / drain patterns disposed in a first direction parallel to the first surface of the base insulating layer such that the channel layer is interposed between the source / drain patterns; a gate structure extending in a second direction crossing the first direction on the first surface of the base insulating layer and at least partially surrounding the channel layer; a gate separation pattern crossing the gate structure and penetrating the gate structure in a third direction perpendicular to the first direction and the second direction; and a through electrode penetrating the gate separation pattern in the third direction.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices with reduced parasitic capacitance and methods of manufacturing the same. Background Art

[0002] Semiconductor devices may be used in various electronic devices, such as, but not limited to, storage devices that may store data and processors that may calculate and / or process data. As the electronics industry develops, various methods for improving various characteristics such as, but not limited to, integration, reliability, speed, and functionality of semiconductor devices may be studied. For example, semiconductor devices having a three-dimensional (3D) structure may have been proposed to potentially overcome limitations that may result from reduced size of semiconductor devices.

[0003] Recently, research has been conducted to potentially improve routing congestion and reduce the size of semiconductor devices by placing a power delivery network on the back side of a substrate to route signals provided to the semiconductor devices. Summary of the invention

[0004] One or more example embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same, which are capable of reducing parasitic capacitance that may exist between an active region and a power delivery network.

[0005] According to one aspect of the present disclosure, a semiconductor device includes: a base insulating layer, the base insulating layer including a first surface and a second surface opposite to the first surface; a channel layer, the channel layer is located on the first surface of the base insulating layer; a source / drain pattern, the source / drain pattern is arranged along a first direction parallel to the first surface of the base insulating layer, so that the channel layer is between the source / drain patterns; a gate structure, the gate structure extends along a second direction intersecting the first direction on the first surface of the base insulating layer and at least partially surrounds the channel layer; a gate separation pattern, the gate separation pattern intersects the gate structure and penetrates the gate structure in a third direction perpendicular to the first direction and the second direction; and a through electrode, the through electrode penetrates the gate separation pattern in the third direction. The gate structure includes a first gate structure arranged on a first side of the gate separation pattern and a second gate structure arranged on a second side of the gate separation pattern. The gate separation pattern includes an air gap, the air gap is arranged between the first gate structure and the through electrode and between the second gate structure and the through electrode.

[0006] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device includes: forming a channel layer and a source / drain pattern on a first surface of a substrate, the source / drain pattern being arranged along a first direction parallel to the first surface of the substrate so that the channel layer is interposed between the source / drain patterns; forming a gate structure, the gate structure extending in a second direction intersecting the first direction and at least partially surrounding the channel layer in the second direction; forming a gate separation pattern, the gate separation pattern intersecting the gate structure and penetrating the gate structure in a third direction perpendicular to the first direction and the second direction; forming a through electrode, the through electrode penetrating the gate separation pattern in the third direction; and forming an air gap in the gate separation pattern, the air gap being located between the gate structure and a first side wall and a second side wall of the through electrode.

[0007] According to one aspect of the present disclosure, a semiconductor device includes: a base insulating layer, the base insulating layer including a first surface and a second surface opposite to the first surface; a channel layer, the channel layer is located on the first surface of the base insulating layer; a source / drain pattern, the source / drain pattern is arranged along a first direction parallel to the first surface of the base insulating layer, so that the channel layer is between the source / drain patterns; a gate structure, the gate structure extends on the first surface of the base insulating layer along a second direction intersecting the first direction and at least partially surrounds the channel layer; a gate separation pattern, the gate separation pattern and the gate The structure intersects and penetrates the gate structure in a third direction perpendicular to the first direction and the second direction; an interlayer insulating layer, the interlayer insulating layer at least partially covers the source / drain pattern, the gate structure and the gate separation pattern; an upper wire structure, the upper wire structure is located on the interlayer insulating layer; a lower wire structure, the lower wire structure is located on the second surface of the base insulation layer; a power rail, the power rail is located on the lower wire structure and penetrates the base insulation layer in the third direction; and a through electrode, the through electrode penetrates the gate separation pattern in the third direction and includes a first end coupled to the power rail. The gate separation pattern includes an air gap.

[0008] Additional aspects may be set forth in part in the description which follows and, in part, may be apparent from the description, and / or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure may be more clearly understood from the following description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a top view showing a semiconductor device according to an embodiment;

[0011] Figure 2 According to the embodiment along Figure 1 A cross-sectional view of the semiconductor device taken along line II';

[0012] Figure 3 According to the embodiment along Figure 1 A cross-sectional view of the semiconductor device taken along line II-II';

[0013] Figure 4 According to the embodiment along Figure 1 A cross-sectional view of the semiconductor device taken along line III-III';

[0014] Figure 5 According to the embodiment along Figure 1 A cross-sectional view of the semiconductor device taken along line IV-IV';

[0015] Figure 6 is a cross-sectional view of a semiconductor device according to an embodiment;

[0016] Fig. 7A and Figure 7B is a cross-sectional view of a semiconductor device according to an embodiment;

[0017] Figures 8 to 37 is a drawing showing a method of manufacturing a semiconductor device according to an embodiment;

[0018] Fig.38 is a top view showing a semiconductor device according to an embodiment;

[0019] Fig.39 According to the embodiment along Fig.38 A cross-sectional view of the semiconductor device taken along line II';

[0020] Fig.40 According to the embodiment along Fig.38 A cross-sectional view of the semiconductor device taken along line II-II';

[0021] Fig.41 According to the embodiment along Fig.38 A cross-sectional view of the semiconductor device taken along line III-III'; and

[0022] Fig.42 According to the embodiment along Fig.38 A cross-sectional view of the semiconductor device taken along line IV-IV'. DETAILED DESCRIPTION

[0023] The present disclosure is described hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0024] The drawings and description are to be regarded as illustrative in nature and not restrictive.Throughout the specification, like reference numerals may designate like elements.

[0025] For better understanding and ease of description, the size and thickness of each constituent element in the drawings may be arbitrarily illustrated, and therefore, the following embodiments are not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc. may be exaggerated for clarity and ease of description.

[0026] It should be understood that the singular form of a noun corresponding to an item may include one or more things unless the relevant context clearly indicates otherwise. As used herein, each of phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B or C" may include any one or all possible combinations of the items enumerated together in the corresponding phrases in these phrases. As used herein, terms such as "1st" and "2nd" or "first" and "second" may be used to simply distinguish a corresponding component from another component without limiting the component in other respects (e.g., importance or order). It should be understood that if an element (e.g., a first element) is referred to as being “coupled to another element (e.g., the second element)”, “coupled to another element (e.g., the second element)”, “connected to another element (e.g., the second element)” or “connected to another element (e.g., the second element)” when the terms “operably” or “communicatively” are used or when the terms “operably” or “communicatively” are not used, it means that the element can be coupled to the other element directly (e.g., by wire), wirelessly or via a third element.

[0027] Additionally, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being “over” or “on” another element, the element may be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there may be no intervening elements. Furthermore, when an element is referred to as being “over” or “on a reference element,” it may be located above or below the reference element, and it is not necessarily referred to as being “over” or “on” in a direction opposite to gravity.

[0028] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0029] Furthermore, throughout the specification, the phrase “in a top view” or “on a plane” may refer to observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” may refer to observing a cross section formed by vertically cutting the target portion from the side.

[0030] The terms "upper", "middle", "lower", etc. can be replaced with terms such as "first", "second", "third" to describe the relative position of elements. The terms "first", "second", "third" can be used to describe various elements, but these elements are not limited by these terms, and the "first element" can be referred to as the "second element". Alternatively or additionally, the terms "first", "second", "third", etc. can be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. may not necessarily refer to any form of order or numerical meaning.

[0031] As used herein, when an element or layer is referred to as "covering" another element or layer, the element or layer may cover at least a portion of the other element or layer, wherein the portion may include a small portion of the other element or may include the entirety of the other element. Similarly, when an element or layer is referred to as "penetrating" another element or layer, the element or layer may penetrate at least a portion of the other element or layer, wherein the portion may include a small portion of the other element or may include the entire size (e.g., length, width, depth) of the other element.

[0032] References throughout this disclosure to "one embodiment," "an embodiment," "an example embodiment," or similar language may indicate that a particular feature, structure, or characteristic described in conjunction with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment," "in an embodiment," "in an example embodiment," and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment. The embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto and may be implemented in various other forms.

[0033] As used herein, the terms “AlO”, “CoN”, “HfO”, “MoC”, “MoN”, “NbC”, “NbN”, “NiN”, “PtN”, “SiBN”, “SiC x N y ”, “SiN x”, “SiOBN”, “SiOC”, “SiOCN”, “SiON”, “SiO x ,"TaAlN," "TaC," "TaCN," "TaN," "TaO," "TaSiN," "TaTiN," "TiAl," "TiAlC," "TiAlC-N," "TiAlN," "TiC," "TiN," "TiSiN," "WC," "WN," etc. may refer to a material made of the elements included in each term, rather than a chemical formula expressing a stoichiometric relationship.

[0034] In the drawings of semiconductor devices, gate-all-around (GAA) and multi-bridge channel field effect transistor (MBCFET) are shown as illustrative examples. TM )(including nanowires or nanosheets), however, the present disclosure is not limited thereto. Depending on the embodiment, the semiconductor device may be and / or may include a fin field effect transistor (FinFET) having a channel region with a fin pattern shape, a tunnel field effect transistor (tunnel FET), a three-dimensional (3D) stacked field effect transistor (3D-SFET) structure, a complementary field effect transistor (CFET) structure, etc.

[0035] Hereinafter, semiconductor devices according to embodiments are described with reference to the accompanying drawings.

[0036] Figure 1 is a top view showing a semiconductor device according to an embodiment. Figures 2 to 4 is a cross-sectional view showing a semiconductor device according to an embodiment. Figure 2 According to the embodiment along Figure 1 A cross-sectional view of the semiconductor device taken along line II'. Figure 3 According to the embodiment along Figure 1 sectional view of the semiconductor device taken along line II-II'. Figure 4 According to the embodiment along Figure 1 1 is a cross-sectional view of the semiconductor device taken along line III-III'. Figure 5 According to the embodiment along Figure 1 A cross-sectional view of the semiconductor device taken along line IV-IV'.

[0037] refer to Figures 1 to 5 According to an embodiment, the semiconductor device may include a base insulating layer 100, a channel layer CH located on a first surface of the base insulating layer 100, a source / drain pattern 150 located on both sides of the channel layer CH, a gate structure GS surrounding the channel layer CH (e.g., a main gate structure M_GS and a sub-gate structure S_GS), and a gate separation pattern GC crossing the gate structure GS (e.g., M_GS and S_GS).

[0038] The base insulating layer 100 may include an insulating material. The base insulating layer 100 may include, but is not limited to, a layer of oxide, nitride, oxynitride, or a combination thereof. For example, the base insulating layer 100 may include silicon nitride (SiN x ). Although the base insulating layer 100 is illustrated as a single layer, this is only for ease of explanation, and the present disclosure is not limited thereto. The first surface and the second surface of the base insulating layer 100 may be formed as planes parallel to the first direction D1 and the second direction D2 intersecting the first direction D1. For example, the first surface of the base insulating layer 100 may be an upper surface, and the second surface may be a bottom surface. The upper surface of the base insulating layer 100 may be a surface opposite to the bottom surface of the base insulating layer 100 in the third direction D3. The third direction D3 may be a direction perpendicular to the first direction D1 and the second direction D2. The bottom surface of the base insulating layer 100 may be referred to as the back side of the base insulating layer 100. In some embodiments, the logic circuit in the cell area may be implemented on the upper surface of the base insulating layer 100.

[0039] The channel layer CH may be disposed on the base insulating layer 100. In an embodiment, a plurality of channel layers (e.g., a first channel layer 110a, a second channel layer 110b, a third channel layer 110c, and a fourth channel layer 110d) may be disposed on the base insulating layer 100. For example, each of the plurality of channel layers 110a to 110d may be and / or may include a sheet-shaped semiconductor layer. Each semiconductor layer may be and / or may include, for example, a nanosheet having a thickness of several nanometers (nm) along the third direction D3.

[0040] The channel layer CH may provide a path through which current may flow between the two source / drain patterns 150. Figures 2 to 4 , the first to fourth channel layers 110a to 110d may be disposed on the source / drain pattern 150 and connected to the source / drain pattern 150. The first to fourth channel layers 110a to 110d may penetrate a portion of the gate structure GS in a direction (e.g., a first direction D1) intersecting the direction along which the gate structure GS extends. The first to fourth channel layers 110a to 110d may be arranged to be spaced apart from the upper surface of the base insulating layer 100 in a vertical direction (e.g., a third direction D3). Although Figure 2 and Figure 4The four (4) channel layers 110a to 110d are illustrated as being arranged to be spaced apart, but the present disclosure is not limited thereto, and the number of stacked channel layers CH may be changed in various ways. The channel layer CH may include a semiconductor material. For example, the channel layer CH may include a group IV semiconductor, a group III-V compound semiconductor, a group II-VI compound semiconductor, etc., such as but not limited to silicon (Si) and germanium (Ge). In an embodiment, a lower pattern BP may be further disposed below the channel layer CH. For example, the lower pattern BP may be located between the base insulating layer 100 and the lowest sub-gate structure S_GS among the plurality of sub-gate structures S_GS. The upper surface of the lower pattern BP may contact the lower surface of the lowest sub-gate structure S_GS among the plurality of sub-gate structures S_GS. The lower pattern BP may include the same material as the channel layer CH. For example, the lower pattern BP may include a group IV semiconductor, a group III-V compound semiconductor, a group II-VI compound semiconductor, etc., such as but not limited to silicon (Si) and germanium (Ge). However, the present disclosure is not limited thereto, and the lower pattern BP may include a material different from the channel layer CH.

[0041] As another embodiment, the semiconductor device may not include the lower pattern BP. In such an embodiment, a lower surface of a lowermost sub-gate structure S_GS among the plurality of sub-gate structures S_GS may directly contact the base insulating layer 100 .

[0042] In an embodiment, a partial area of ​​the base insulating layer 100 overlapping the sub-gate structure S_GS in the third direction D3 may extend into the interior of the lower pattern BP and may directly contact the lower surface of the lowest sub-gate structure S_GS among the plurality of sub-gate structures S_GS. The lower pattern BP may be located in the lower portion of the source / drain pattern 150 located on both sides of the sub-gate structure S_GS, and the lower patterns BP located in the lower portions of different source / drain patterns 150 may be separated by the base insulating layer 100. The base insulating layer 100 may be positioned between the lower patterns BP located in the lower portions of different source / drain patterns 150.

[0043] According to an embodiment, the semiconductor device may further include a field insulating layer 105. The field insulating layer 105 may be located on the lower pattern BP. The field insulating layer 105 may be located on the sidewall of the lower pattern BP. The field insulating layer 105 may not be located on the upper surface of the lower pattern BP. The field insulating layer 105 may completely cover the side surface of the lower pattern BP. In an embodiment, the field insulating layer 105 may cover a portion of the sidewall of the lower pattern BP. In such an embodiment, a portion of the lower pattern BP may protrude from the upper surface of the field insulating layer 105 in the third direction D3. The field insulating layer 105 may include a layer of, for example, an oxide, a nitride, an oxynitride, or a combination thereof. Although the field insulating layer 105 is illustrated as a single layer, this is merely for ease of illustration, and the present disclosure is not limited thereto.

[0044] The source / drain pattern 150 may be located on the base insulating layer 100. The lower pattern BP may be located between the source / drain pattern 150 and the base insulating layer 100. However, the present disclosure is not limited thereto, and the lower pattern BP may not be located between the source / drain pattern 150 and the base insulating layer 100. The source / drain pattern 150 may be located on both sides of the channel layer CH or the sub-gate structure S_GS. That is, the two source / drain patterns 150 may be arranged along a direction (e.g., a first direction D1) that intersects the direction along which the gate structure GS extends, so that the channel layer CH or the sub-gate structure S_GS is between the two source / drain patterns 150. The source / drain pattern 150 may directly contact the channel layer CH or the sub-gate structure S_GS. The source / drain pattern 150 may directly contact the sub-interface insulating layer 133S of the sub-gate structure S_GS. In an embodiment, an inner spacer may be further disposed between the source / drain pattern 150 and the sub-interface insulating layer 133S. The inner spacer may include, but is not limited to, silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboride nitride (SiOBN), silicon oxycarbide (SiOC), combinations thereof, etc.

[0045] The source / drain pattern 150 may be formed on a sacrificial pattern (eg, Figure 8 sacrificial pattern SC_L) and active pattern (eg, Figure 8 The source / drain pattern 150 may be formed as an epitaxial layer formed by selective epitaxial growth (SEG) in a region where a portion of the sacrificial pattern SC_L and the active pattern ACT_L may be recessed. That is, the source / drain pattern 150 may fill a region where a portion of the sacrificial pattern SC_L and the active pattern ACT_L may be recessed.

[0046] The source / drain pattern 150 may include a liner layer 150a and a filling layer 150b, respectively. The liner layer 150a may be located on the side surface and the bottom surface of the source / drain pattern 150. The liner layer 150a may directly contact the sub-gate structure S_GS and the channel layer CH. That is, the liner layer 150a may be recessed along the source / drain (e.g., Fig.10 The filling layer 150b may be located on the liner layer 150a. The filling layer 150b and the liner layer 150a may have upper surfaces with substantially similar and / or identical heights. That is, the filling layer 150b may fill the inside of the source / drain recess RC1.

[0047] The source / drain pattern 150 may include a semiconductor material. The source / drain pattern 150 may include, for example, silicon (Si) or germanium (Ge). In addition, the source / drain pattern 150 may include, for example, a binary compound, or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge) or tin (Sn). For example, the source / drain pattern 150 may include silicon (Si), silicon germanium (Si-Ge), germanium (Ge), silicon carbide (SiC), etc. However, the present disclosure is not limited thereto. In an embodiment, the liner layer 150a and the filling layer 150b may have different concentrations of silicon (Si) or germanium (Ge). For example, the concentration of silicon (Si) or germanium (Ge) included in the liner layer 150a may be less than the concentration of silicon (Si) or germanium (Ge) included in the filling layer 150b.

[0048] In an embodiment, source / drain pattern 150 may be electrically connected to lower conductive line structure 220 through power rail PR and contact electrode 180. Source / drain pattern 150 may receive power from lower conductive line structure 220 through power rail PR and contact electrode 180.

[0049] The gate structure GS may be disposed on the base insulating layer 100. The lower pattern BP or the field insulating layer 105 may be located between the gate structure GS and the base insulating layer 100. The gate structure GS may include a sub-gate structure S_GS and a main gate structure M_GS. The sub-gate structure S_GS may be disposed on the base insulating layer 100, and the main gate structure M_GS may be disposed on the sub-gate structure S_GS. On the base insulating layer 100, the gate structure GS may extend in different directions other than the direction along which the source / drain pattern 150 is arranged. For example, on the base insulating layer 100, the gate structure GS may extend in a direction (e.g., a second direction D2) intersecting the direction along which the source / drain pattern 150 is arranged. The gate structure GS may be located on the base insulating layer 100. The gate structure GS may be arranged to be spaced apart in the first direction D1. The main gate structure M_GS may be located on the uppermost channel layer 110a. The main gate structure M_GS may also be located on the side surface of the structure in which the first to fourth channel layers 110a to 110d and the sub-gate structure S_GS are stacked. That is, the main gate structure M_GS may surround each of the channel layers 110a to 110d together with the sub-gate structure S_GS. However, the main gate structure M_GS may not be located on the surface of each of the channel layers 110a to 110d contacting the source / drain pattern 150. Although Figure 2 and Figure 4 Four (4) sub-gate structures S_GS arranged along the third direction are illustrated, but the number of arranged sub-gate structures S_GS is not limited thereto. For example, the gate structure GS may include three (3) sub-gate structures S_GS.

[0050] The sub-gate structure S_GS may contact the source / drain pattern 150. For example, the sub-gate structure S_GS may directly contact the source / drain pattern 150. The sub-gate structure S_GS may be located on both sides of the source / drain pattern 150. Each sub-gate structure S_GS may be formed in multiple layers. For example, each sub-gate structure S_GS may include a sub-gate electrode 131S, a sub-gate insulating layer 132S, and a sub-interface insulating layer 133S. The sub-gate structure S_GS and the first to fourth channel layers 110a to 110d may be alternately stacked along the third direction D3. The sub-gate structure S_GS may surround the surfaces of the first to fourth channel layers 110a to 110d except the surfaces connected to the source / drain pattern 150 together with the main gate structure M_GS.

[0051] The sub-gate electrode 131S may include, but is not limited to, at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal oxynitride, etc. The sub-gate electrode 131S may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or the like. The conductive metal oxide and the conductive metal oxynitride may include oxidized forms of the materials mentioned above, however, the present disclosure is not limited thereto.

[0052] The sub-interface insulating layer 133S may be positioned along the circumference of the channel layer CH. For example, the sub-interface insulating layer 133S may surround the surface of the channel layer CH except for the surface connected to the source / drain pattern 150. The sub-interface insulating layer 133S may directly contact the source / drain pattern 150 and the channel layer CH. The sub-interface insulating layer 133S may be between the channel layer CH and the sub-gate insulating layer 132S. The sub-interface insulating layer 133S may include, for example, silicon oxide (SiO x ).

[0053] The sub-gate insulating layer 132S may extend along the upper surface of the sub-interface insulating layer 133S. The sub-gate insulating layer 132S may surround the channel layer CH. For example, the sub-gate insulating layer 132S may surround the surface of the channel layer CH except the surface connected to the source / drain pattern 150. The sub-gate insulating layer 132S may be positioned along the circumference of the channel layer CH. The sub-gate insulating layer 132S may be between the sub-gate electrode 131S and the sub-interface insulating layer 133S. The sub-gate insulating layer 132S may include, for example, a high dielectric constant material. The high dielectric constant material may include a dielectric constant with silicon oxide (SiO x ) than materials with higher dielectric constants, such as but not limited to hafnium oxide (HfO), aluminum oxide (AlO), tantalum oxide (TaO), etc.

[0054] The main gate structure M_GS may be located on the sub-gate structure S_GS and the channel layer CH. The main gate structure M_GS may be located on the upper surface of the channel layer CH. Each main gate structure M_GS may be formed in multiple layers. For example, the main gate structure M_GS may include a main gate electrode 131M, a main interface insulating layer 133M, and a main gate insulating layer 132M. The main gate structure M_GS may surround the surface of at least one channel layer CH (e.g., the first channel layer 110a) in the channel layer CH together with the sub-gate structure S_GS except for the surface connected to the source / drain pattern 150.

[0055] The main gate electrode 131M may be located on the sub-gate structure S_GS and the channel layer CH. The main gate electrode 131M may be located on the upper surface of the channel layer CH. The main gate electrode 131M may include the same material as the sub-gate electrode 131S. For example, the main gate electrode 131M may include but is not limited to at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal oxynitride, and the like.

[0056] The main interface insulating layer 133M may extend along the upper surface of the channel layer CH. The main interface insulating layer 133M may include, for example, silicon oxide (SiO x ). The main gate insulating layer 132M may extend along the side surface and the bottom surface of the main gate electrode 131M. The main gate insulating layer 132M may include, for example, a high dielectric constant material.

[0057] In an embodiment, the gate structure GS may be electrically separated from an adjacent gate structure by the gate separation pattern GC. Figure 1 and Figure 4 , a partial region of the main gate structure M_GS may be penetrated by the gate separation pattern GC in the third direction D3 , and thus the main gate structure M_GS may be electrically separated from adjacent gate structures in the second direction D2 .

[0058] According to an embodiment, the semiconductor device may further include a capping layer 141 and a gate spacer 142. The gate spacer 142 may be located on the side surface of the main gate electrode 131M. The gate spacer 142 may not be disposed between the lower pattern BP and the channel layer CH. The gate spacer 142 may not be disposed between the channel layers CH adjacent along the third direction D3. Although the gate spacer 142 is illustrated as a single layer, this is only for ease of explanation, and the present disclosure is not limited thereto. The gate spacer 142 may include, for example, silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboride nitride (SiOBN), silicon oxycarbide (SiOC), combinations thereof, etc.

[0059] The capping layer 141 may be located on the main gate structure M_GS and the gate spacer 142. In an embodiment, the capping layer 141 may be located between the gate spacers 142. The capping layer 141 may include, for example, silicon nitride (SiN x ), silicon oxynitride (SiON), silicon carbide nitride (SiCN), silicon oxycarbonitride (SiOCN), a combination thereof, etc. The capping layer 141 may include a material having an etching selectivity with respect to the interlayer insulating layer 170 .

[0060] In embodiments, the capping layer 141 and the gate spacer 142 may be penetrated in the third direction D3 along the gate separation pattern GC and the through electrode 190. The capping layer 141 may have an upper surface having a height substantially similar and / or the same as that of an upper surface of the gate separation pattern GC.

[0061] The gate separation pattern GC may extend in a direction intersecting the gate structure GS (e.g., the first direction D1). The gate separation pattern GC may also extend in a third direction D3. That is, the gate separation pattern GC may extend in the third direction D3 and penetrate the main gate structure M_GS. Therefore, the gate separation pattern GC may electrically separate the gate structures arranged along the first direction D1. The gate separation pattern GC may have an upper surface with a height substantially similar and / or the same as that of the capping layer 141 and / or the contact electrode 180. The gate separation pattern GC may penetrate the main gate structure M_GS in the third direction and extend into the field insulation layer 105. Reference Figures 3 to 5 The lower surface of the gate separation pattern GC may contact the upper surface of the power rail PR. The gate separation pattern GC may include an insulating material. For example, the gate separation pattern GC may include silicon nitride (SiN x ), silicon oxide (SiO x ) and / or silicon carbonitride (SiC x N y). However, the present disclosure is not limited thereto, and the gate separation pattern GC may include various insulating materials for electrically separating the main gate structure M_GS from other gate structures. In an embodiment, the gate separation pattern GC may be penetrated by the through electrode 190 in the third direction D3. That is, the gate separation pattern GC may surround the sidewall of the through electrode 190. Therefore, the gate separation pattern GC may contact the sidewall of the through electrode 190. The gate separation pattern GC may have an upper surface having a height substantially similar and / or the same as that of the upper surface of the through electrode 190. The gate separation pattern GC may have a lower surface having a height substantially similar and / or the same as that of the lower surface of the through electrode 190.

[0062] refer to Figures 3 to 5 , the gate separation pattern GC may include a plurality of insulating patterns (e.g., a first insulating pattern DP1 and a second insulating pattern DP2) and an air gap ag between the first insulating pattern DP1 and the second insulating pattern DP2. For example, the gate separation pattern GC may include a first insulating pattern DP1, a second insulating pattern DP2, and an air gap ag between the first insulating pattern DP1 and the second insulating pattern DP2. The air gap ag may refer to an empty space between one layer and another layer. For example, the air gap ag may include air and / or gas used in a semiconductor device manufacturing process.

[0063] An upper surface of the first insulating pattern DP1 may contact the second interlayer insulating layer 172. A side surface of the first insulating pattern DP1 may contact the capping layer 141 and / or the first interlayer insulating layer 171. The first insulating pattern DP1 may not be located in a region where the gate separation pattern GC is penetrated by the contact electrode 180. Figure 3 , the lower surface of the first insulating pattern DP1 may be located at a level higher than or equal to the level of the upper surface of the source / drain pattern 150. That is, the first insulating pattern DP1 may not overlap the source / drain pattern 150 in the second direction D2. The first insulating pattern DP1 may include an insulating material. For example, the first insulating pattern DP1 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and / or silicon carbonitride (SiC x N y ). However, the present disclosure is not limited thereto, and the first insulating pattern DP1 may include various insulating materials for electrically separating the main gate structure M_GS from other gate structures. In an embodiment, the first insulating pattern DP1 may include an insulating material different from the insulating material included in the interlayer insulating layer 170. The first insulating pattern DP1 may include an insulating material having an etching selectivity relative to the interlayer insulating layer 170.

[0064] A lower surface of the second insulating pattern DP2 may contact the power rail PR. A side surface of the second insulating pattern DP2 may contact the field insulating layer 105. Figure 3 , the upper surface of the second insulating pattern DP2 may be located at a level lower than or equal to the level of the lower surface of the source / drain pattern 150. That is, the second insulating pattern DP2 may not overlap with the source / drain pattern 150 in the second direction D2. However, the present disclosure is not limited thereto, and the upper surface of the second insulating pattern DP2 may be located at a higher level than the lower surface of the source / drain pattern 150. The second insulating pattern DP2 may include an insulating material. For example, the second insulating pattern DP2 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and / or silicon carbonitride (SiC x N y ) in the base insulating layer 100. However, the present disclosure is not limited thereto, and the second insulating pattern DP2 may include various insulating materials for electrically separating the main gate structure M_GS from other gate structures. In an embodiment, the second insulating pattern DP2 may include the same insulating material as the insulating material included in the base insulating layer 100. In an embodiment, the second insulating pattern DP2 may be formed in the same process as the base insulating layer 100. However, the present disclosure is not limited thereto, and the second insulating pattern DP2 may be formed in a process separate from the process in which the base insulating layer 100 is formed. In such an embodiment, the second insulating pattern DP2 may include an insulating material different from the insulating material included in the base insulating layer 100.

[0065] The air gap ag may be located between the first insulation pattern DP1 and the second insulation pattern DP2. The air gap ag may refer to an empty space located between the first insulation pattern DP1 and the second insulation pattern DP2. Figure 3 , the air gap ag may include a portion that may overlap the source / drain pattern 150 in the second direction D2. In an embodiment, the dielectric constant of the air gap ag may be lower than the dielectric constant of the insulating material included in the first insulating pattern DP1 and / or the second insulating pattern DP2. In an embodiment, the air gap ag may be filled with air, and the dielectric constant of the air may be about 1.

[0066] In an embodiment, the width w of the gate separation pattern GC may be less than or equal to about 10 nm. In an embodiment, the width w of the gate separation pattern GC may be greater than or equal to about 2 nm, and may be less than or equal to about 8 nm. In another embodiment, the width w of the gate separation pattern GC may be greater than or equal to about 4 nm, and may be less than or equal to about 6 nm. However, the width w of the gate separation pattern GC is not limited thereto, and in some cases, may be greater than or equal to about 10 nm.

[0067] According to an embodiment, the semiconductor device may further include a through electrode 190 penetrating the gate separation pattern GC, a contact electrode 180 located between the source / drain pattern 150 and the through electrode 190, an interlayer insulating layer 170 covering the source / drain pattern 150, the gate structure GS and the gate separation pattern GC, an upper wire structure 210 located on the interlayer insulating layer 170, a lower wire structure 220 located on the lower surface of the base insulating layer 100, and a power rail PR located on the lower wire structure 220.

[0068] The through electrode 190 may interconnect the contact electrode 180 and the power rail PR. That is, a portion of the through electrode 190 may contact the contact electrode 180, and another portion may contact the power rail PR. Figures 1 to 5 According to an embodiment, the through electrode 190 may be located inside the gate separation pattern GC. That is, the through electrode 190 may be surrounded by the gate separation pattern GC. Therefore, the contact electrode 180 may penetrate a partial area of ​​the gate separation pattern GC and be connected to the through electrode 190. The width of the through electrode 190 in the second direction D2 may be narrower (e.g., reduced) as it is closer to the power rail PR. The through electrode 190 may penetrate the gate separation pattern GC in the third direction D3. Therefore, the two side walls of the through electrode 190 may contact the gate separation pattern GC. The air gap ag may be located between the gate structure GS and the two side walls of the through electrode 190. The air gap ag may be located between the first interlayer insulating layer 171 and the two side walls of the through electrode 190. The through electrode 190 may have an upper surface having a height substantially similar to and / or identical to the gate separation pattern GC. The through electrode 190 may extend in the first direction D1 parallel to the gate separation pattern GC and the gate structure GS. The through electrode 190 may include a conductive material. For example, the through electrode 190 may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, etc. Since the through electrode 190 is located inside the gate separation pattern GC, when the semiconductor device according to the embodiment is manufactured, the process margin can be improved, and a short circuit that may occur between the source / drain pattern 150 and the through electrode 190 can be potentially prevented.

[0069] The contact electrode 180 may interconnect the source / drain pattern 150 and the through electrode 190. That is, a portion of the contact electrode 180 may contact the source / drain pattern 150, and another portion may contact the through electrode 190. The contact electrode 180 may have an upper surface with a height substantially similar and / or the same as that of the through electrode 190 and the gate separation pattern GC. Figure 3, the lower surface of the contact electrode 180 is shown to be at a substantially similar and / or identical height to the upper surface of the filling layer 150b. However, the present disclosure is not limited in this regard, and in another embodiment, the lower surface of the contact electrode 180 may include a partial area having a height different from that of the upper surface of the filling layer 150b. For example, the area of ​​the entire area of ​​the lower surface of the contact electrode 180 that overlaps with the first interlayer insulating layer 171 in the third direction D3 may have a lower height than the upper surface of the filling layer 150b.

[0070] refer to Figure 1 and Figure 3 , the contact electrode 180 may extend in the second direction D2. In an embodiment, the contact electrode 180 may extend into the gate separation pattern GC. The contact electrode 180 may penetrate a partial region of the gate separation pattern GC and be connected to a portion of the through electrode 190.

[0071] The contact electrode 180 may include a conductive material. For example, the contact electrode 180 may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0072] The power rail PR may be located on the lower conductive line structure 220. The power rail PR may extend into the base insulating layer 100 along the third direction D3. Figure 3 and Figure 4 , the power rail PR may extend into the base insulating layer 100 along the third direction D3 and may contact the lower surfaces of the through electrode 190 and the gate separation pattern GC. As the power rail PR becomes closer to the lower surfaces of the through electrode 190 and the gate separation pattern GC along the third direction D3, the width of the power rail PR in the second direction D2 may become narrower. Figure 5 , the power rail PR may also extend in the first direction D1. The lower surface of the power rail PR may contact the lower conductive line structure 220. The power rail PR may include a conductive material. For example, the power rail PR may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, etc. The power rail PR may be connected to the lower conductive line structure 220, and may transmit power supplied from the lower conductive line structure 220 to the source / drain pattern 150.

[0073] The lower conductor structure 220 may be disposed on the bottom surface of the base insulating layer 100. In an embodiment, the lower conductor structure 220 may be and / or may include a component for supplying power to at least one source / drain pattern 150. For example, the lower conductor structure 220 may be and / or may include a power delivery network. The lower conductor structure 220 may include a lower conductor 221, a lower via 222, and a lower insulating layer 223. The lower conductor 221 and the lower via 222 may be located on the bottom surface of the base insulating layer 100. The lower conductor 221 and the lower via 222 may include a metal (e.g., copper (Cu)). The lower insulating layer 223 may be located on the bottom surface of the base insulating layer 100. The lower insulating layer 223 may be disposed between the bottom surface of the base insulating layer 100, the lower conductor 221, and the lower via 222 and insulate them. That is, the lower insulating layer 223 may cover the lower conductor 221 and the bottom surface of the base insulating layer 100. The lower conductive line 221 and the lower via 222 may be located in the lower insulating layer 223. The lower insulating layer 223 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiON) or at least one of a low dielectric layer.

[0074] The interlayer insulating layer 170 may include a first interlayer insulating layer 171 and a second interlayer insulating layer 172. The interlayer insulating layer 170 may cover the source / drain pattern 150, the gate structure GS, the contact electrode 180, and the gate separation pattern GC. That is, the first interlayer insulating layer 171 may cover the upper surface and side surfaces of the source / drain pattern 150, the side surface of the gate separation pattern GC, the side surface of the contact electrode 180, and the side surface of the gate structure GS. The second interlayer insulating layer 172 may cover the first interlayer insulating layer 171, the upper surface of the gate separation pattern GC, the upper surface of the contact electrode 180, and the upper surface of the capping layer 141. The interlayer insulating layer 170 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x), at least one of silicon oxynitride (SiON) and a low dielectric constant material. The low dielectric constant material may include, for example, tetraethyl fluoride orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxy di-tert-butyloxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), eastern silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but the present disclosure is not limited thereto. The first interlayer insulating layer 171 and the second interlayer insulating layer 172 may include different materials, or may include the same material. When the first and second interlayer insulating layers 171 and 172 include the same material, a boundary between the first and second interlayer insulating layers 171 and 172 may not be visible. In embodiments, the interlayer insulating layer 170 may include a different material from the base insulating layer 100 .

[0075] The upper conductor structure 210 may be located on the interlayer insulating layer 170. The upper conductor structure 210 may include an upper conductor 211, an upper via 212, and an upper insulating layer 213. The upper conductor 211 and the upper via 212 may include a metal (e.g., copper (Cu)). The upper insulating layer 213 may be disposed between the upper conductor 211 and the upper via 212 and insulate them. The upper insulating layer 213 may cover the interlayer insulating layer 170 and the upper conductor 211. The upper conductor 211 and the upper via 212 may be located within the upper insulating layer 213. The upper insulating layer 213 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x The upper conductive line structure 210 may be electrically connected to at least one of the main gate electrode 131M and the source / drain pattern 150 .

[0076] In a structure in which the through electrode 190 is located within the gate separation pattern GC, parasitic capacitance may exist between the source / drain pattern 150 and the through electrode 190. Figures 1 to 5As described, in the region of the gate separation pattern GC overlapping with the source / drain pattern 150 in the second direction D2, an air gap ag having a dielectric constant lower than that of the insulating material included in the first insulating pattern DP1 and / or the second insulating pattern DP2 may be positioned. In such an embodiment, compared with a case where the gate separation pattern GC is completely filled with the first insulating pattern DP1 and / or the second insulating pattern DP2, the parasitic capacitance between the source / drain pattern 150 and the through electrode 190 may be reduced, and thus, the performance degradation of the semiconductor device due to the parasitic capacitance may be potentially improved.

[0077] Figure 6 is a cross-sectional view of a semiconductor device according to an embodiment. Figure 6 , showing the Figure 1 sectional view of the semiconductor device taken along line II-II'. Figure 6 The semiconductor device shown may include and / or may be similar in many respects to the above-referenced Figures 1 to 5 The semiconductor device described above may include additional features not mentioned above. Therefore, for the sake of brevity, the above reference may be omitted. Figures 1 to 5 In addition, the following description may focus on Figure 6 The semiconductor device disclosed in Figures 1 to 5 The difference compared with the semiconductor device disclosed in.

[0078] like Figure 6 As shown, the lower surface of the first insulation pattern DP1 may be located at a level lower than or equal to the level of the upper surface of the source / drain pattern 150. In addition, the lower surface of the first insulation pattern DP1 may be located at a higher level than the lower surface of the source / drain pattern 150. That is, in an embodiment, the first insulation pattern DP1 may overlap a partial area of ​​the source / drain pattern 150 in the second direction D2.

[0079] In an embodiment, the first insulating pattern DP1 may also be located below the contact electrode 180. The first insulating pattern DP1 may be further located between the contact electrode 180 and the air gap ag. The lower surface of the first insulating pattern DP1 may be located at a level lower than or equal to the level of the upper surface of the source / drain pattern 150. In addition, the lower surface of the first insulating pattern DP1 may be located at a higher level than the lower surface of the source / drain pattern 150.

[0080] like Figure 6 As shown, with reference Figures 1 to 5 Compared with the semiconductor device described above, the area where the air gap ag is included in the gate separation pattern GC can be smaller. Figure 6In the case of the semiconductor device disclosed in the embodiment, the parasitic capacitance between the source / drain pattern 150 and the through electrode 190 can be maintained low, and at the same time, compared with the reference Figures 1 to 5 Compared with the semiconductor device described above, the structure can be more stable. Figure 6 As shown, the first insulating pattern DP1 may be further filled up to the region overlapping with the source / drain pattern 150 in the second direction, and thus, the first insulating pattern DP1 may be further filled up to the region overlapping with the source / drain pattern 150 in the second direction. Figures 1 to 5 The structure can be more robust compared to the semiconductor device described. Figure 6 Among the configurations shown, in the case of excluding other configurations of the gate separation pattern GC, the detailed configuration and connection relationship can be the same as those in reference Figures 1 to 5 The described semiconductor devices are substantially similar and / or identical, and thus, a detailed description thereof may be omitted for the sake of brevity.

[0081] Fig. 7A and Figure 7B is a cross-sectional view of a semiconductor device according to an embodiment. Fig. 7A and Figure 7B , showing the Figure 1 sectional view of the semiconductor device taken along line II-II'. Fig. 7A and Figure 7B The semiconductor device shown may include and / or may be similar in many respects to the above-referenced Figures 1 to 5 The semiconductor device described above may include additional features not mentioned above. Therefore, for the sake of brevity, the above reference may be omitted. Figures 1 to 5 In addition, the following description may focus on Fig. 7A and Figure 7B The semiconductor device disclosed in Figures 1 to 5 The difference compared with the semiconductor device disclosed in.

[0082] refer to Fig. 7A and Figure 7B , the semiconductor device may further include a metal pattern MP.

[0083] The metal pattern MP may be located in a region adjacent to a region where the gate separation pattern GC is penetrated by the contact electrode 180. That is, within the gate separation pattern GC, the metal pattern MP may be located in a portion of the region overlapping the contact electrode 180 in the third direction D3. Fig. 7A , an upper surface of the metal pattern MP may contact a lower surface of the contact electrode 180 . An air gap ag may be located between a lower surface of the metal pattern MP and the second insulating pattern DP2 . One aspect of the metal pattern MP may contact the through electrode 190 .

[0084] The metal pattern MP may include a conductive material. In an embodiment, the metal pattern MP may include a contact electrode 180 and the same or different material. For example, the metal pattern MP may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The metal may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitride may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0085] exist Fig. 7A , the metal pattern MP is shown as being separated from the contact electrode 180, but as shown in FIG. Figure 7B As shown, the metal pattern MP may be a part of the contact electrode 180. That is, the metal pattern MP may be formed together in the process of forming the contact electrode 180. In such an embodiment, the metal pattern MP may include the same material as the contact electrode 180.

[0086] In embodiments, the lower surface of the contact electrode 180 and the lower surface of the metal pattern MP may have various heights. Figure 7B , among the entire area of ​​the lower surface of the contact electrode 180, the lower surface of the metal pattern MP may be located at a lower height than the area a overlapping with the filling layer 150b of the source / drain pattern 150 in the third direction D3 and the area b overlapping with the first interlayer insulating layer 171 in the third direction D3. Figure 7B As shown, region a and region b may be located at the same height.

[0087] In another embodiment, region a and region b may have different heights. For example, region "b" may be located at a lower height than region a. The lower surface of the metal pattern MP may be located at a lower height than region b, may be located at a higher height than region b, or may be located at the same height as region b.

[0088] refer to Fig. 7A and Figure 7B , the metal pattern MP may be connected to the through electrode 190 together with the contact electrode 180, and provide a passage through which power may be supplied from the lower conductive line structure 220 to the source / drain pattern 150. According to an embodiment, a series resistance component between the through electrode 190 and the source / drain pattern 150 may be reduced, and thus, the electrical characteristics of the semiconductor device may be potentially improved. Fig. 7A and Figure 7B Among the configurations shown, in the case of excluding other configurations of the gate separation pattern GC, the detailed configuration and connection relationship can be the same as those in reference Figures 1 to 5 The described semiconductor devices are substantially similar and / or identical, and thus, a detailed description thereof may be omitted for the sake of brevity.

[0089] Figures 8 to 37 is a drawing illustrating a method of manufacturing a semiconductor device according to an embodiment.

[0090] like Figure 8 and Fig. 9 As shown, the field insulating layer 105, the lower pattern BP and the upper pattern structure U_AP may be formed on the substrate 10. The substrate 10 may be a silicon on insulator (SOI) or bulk silicon. Alternatively or additionally, the substrate 10 may be a silicon (Si) substrate, and may include other materials, for example, silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or indium antimonide, however, the present disclosure is not limited thereto. The lower pattern BP may be and / or may include a portion of the substrate 10.

[0091] The upper pattern structure U_AP may be located on the lower pattern BP. The upper pattern structure U_AP may include sacrificial patterns SC_L and active patterns ACT_L alternately stacked on the lower pattern BP. For example, the sacrificial patterns SC_L may include silicon germanium (SiGe). The active patterns ACT_L may include silicon (Si). The field insulating layer 105 may cover portions of the sidewalls of the lower pattern BP and the upper pattern structure U_AP.

[0092] On the upper pattern structure U_AP, a preliminary gate insulating layer 132P, a preliminary main gate electrode 131MP, and a preliminary capping layer 141P may be formed. The preliminary gate insulating layer 132P may also be located on the field insulating layer 105. The preliminary gate insulating layer 132P may include, for example, silicon oxide (SiOx), however, the present disclosure is not limited thereto. The preliminary main gate electrode 131MP may include, for example, polysilicon, however, the present disclosure is not limited thereto. The preliminary capping layer 141P may include, for example, silicon nitride (SiN), however, the present disclosure is not limited thereto. On both side surfaces of the preliminary main gate electrode 131MP, a preliminary gate spacer 142P may be formed.

[0093] like Fig.10 and Fig.11 As shown, by using the preliminary capping layer 141P and the preliminary gate spacer 142P as a mask, a source / drain recess RC1 may be formed by etching at least a portion of the upper pattern structure U_AP. As the source / drain recess RC1 is formed, at least a portion of the lower pattern BP may be etched. A portion of the source / drain recess RC1 may be formed in the substrate 10. Fig.10As shown, after forming the source / drain recess RC1, a dent process for the sacrificial layer SC_L may be performed. In the dent process, the sacrificial layer SC_L may be etched by a wet etching method and / or a dry etching method, and thus, the length of the sacrificial layer SC_L in the first direction D1 may be further reduced. Therefore, the surface of the sacrificial layer SC_L contacting the source / drain recess RC1 may be in a concave shape toward the source / drain recess RC1.

[0094] As the source / drain recess RC1 is formed, the active pattern ACT_L is separated so that the first to fourth channel layers 110a to 110d can be formed. The first to fourth channel layers 110a to 110d can be located on both sides of the source / drain recess RC1. The first to fourth channel layers 110a to 110d and the sacrificial pattern SC_L can be alternately stacked along the third direction D3. The lengths of the first to fourth channel layers 110a to 110d can be different, and / or the lengths can be the same.

[0095] like Fig.12 and Fig.13 As shown, the source / drain pattern 150 can be formed in the source / drain recess RC1. The source / drain pattern 150 can be formed on the substrate 10. The source / drain pattern 150 can be formed by using an epitaxial growth method. The inner wall of the source / drain recess can be used as a seed. The source / drain pattern 150 can directly contact the substrate 10 or the lower pattern BP. The source / drain pattern 150 can directly contact the first to fourth channel layers 110a to 110d and the sacrificial layer SC_L. The source / drain pattern 150 may include silicon (Si), germanium (Ge) or silicon germanium (SiGe). The source / drain pattern 150 can be formed of several regions with different concentrations. For example, referring to Fig.12 , the source / drain pattern 150 may include a liner layer 150a and a filling layer 150b. The liner layer 150a and the filling layer 150b may be formed sequentially. That is, first, a liner layer 150a may be formed along the sidewall and bottom surface of the source / drain recess RC1, and a filling layer 150b may be formed on each liner layer 150a. Each of the liner layer 150a and the filling layer 150b may be formed by using an epitaxial growth method. The liner layer 150a and the filling layer 150b may include a semiconductor material. For example, the liner layer 150a and the filling layer 150b may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. In an embodiment, the liner layer 150a and the filling layer 150b may have different concentrations of silicon (Si) or germanium (Ge). For example, the concentration of silicon (Si) or germanium (Ge) included in the liner layer 150 a may be lower than the concentration of silicon (Si) or germanium (Ge) included in the filling layer 150 b .

[0096] like Fig.14 and Fig.15 As shown, a first interlayer insulating layer 171 may be formed on the source / drain pattern 150. Subsequently, a portion of the first interlayer insulating layer 171 and the preliminary capping layer 141P may be removed so as to expose the upper surface of the preliminary main gate electrode 131MP. In an embodiment, a portion of the gate spacer 142P may be removed together, and the gate spacer 142 may be formed. Thereafter, by removing the remaining preliminary gate insulating layer 132P and the preliminary main gate electrode 131MP, the upper pattern structure U_AP between the gate spacers 142 may be exposed. Subsequently, the sacrificial pattern SC_L between the channel layer CH and the lower pattern BP may be removed so that the gate trench 130t may be formed.

[0097] like Fig.16 and Fig.17 As shown, the sub-interface insulating layer 133S, the sub-gate insulating layer 132S, and the sub-gate electrode 131S can be sequentially formed in the gate trench 130t. In addition, the main interface insulating layer 133M, the main gate insulating layer 132M, the main gate electrode 131M and the capping layer 141 can be sequentially formed. The sub-interface insulating layer 133S and the main interface insulating layer 133M can be formed simultaneously in the same process. The sub-gate insulating layer 132S and the main gate insulating layer 132M can be formed simultaneously in the same process (for example, at substantially similar times). The sub-gate electrode 131S and the main gate electrode 131M can be formed simultaneously in the same process.

[0098] like Fig.18 and Fig.19 As shown, by etching a portion of the main gate structure M_GS and filling the etched portion with an insulating material, a first insulating pattern DP1 may be formed. For example, by patterning the capping layer 141, the main gate electrode 131M, the main gate insulating layer 132M, and the main interface insulating layer 133M, a first insulating pattern DP1 extending in the first direction D1 may be formed. The capping layer 141, the main gate electrode 131M, the main gate insulating layer 132M, and the main interface insulating layer 133M may be sequentially etched. The first insulating pattern DP1 may intersect the capping layer 141, the main gate electrode 131M, the main gate insulating layer 132M, and the main interface insulating layer 133M. The first insulating pattern DP1 may penetrate the capping layer 141, the main gate electrode 131M, the main gate insulating layer 132M, and the main interface insulating layer 133M in the third direction D3. The first insulating pattern DP1 may penetrate the field insulating layer 105 located below the main gate electrode 131M in the third direction D3, and may contact the upper surface of the substrate 10. In embodiments, the first insulation pattern DP1 may include an insulation material having an etch selectivity compared to the interlayer insulation layer 170 .

[0099] like Fig. 20 and Fig.21 As shown, by etching a partial region of the first insulating pattern DP1, a first trench TR1 exposing a portion of the upper surface of the substrate 10 may be formed. A sidewall of the first trench TR1 may be surrounded by the first insulating pattern D1.

[0100] like Fig. 22 and Fig.23 As shown, the through electrode 190 may be formed by filling the first trench TR1 with a metal material. The upper surface of the through electrode 190 may be located on the same plane as the upper surface of the first insulating pattern DP1. The sidewall of the through electrode 190 may be surrounded by the first insulating pattern DP1. The lower surface of the through electrode 190 may contact the upper surface of the substrate 10.

[0101] like Fig.24 and Fig.25 As shown, by patterning a portion of the first insulating pattern DP1 and the first interlayer insulating layer 171, a contact electrode 180 that contacts the upper surface of the source / drain pattern 150 and the through electrode 190 may be formed. That is, by etching a portion of the first insulating pattern DP1 and the interlayer insulating layer 170, a portion of the sidewall of the through electrode 190 and the upper surface of the source / drain pattern 150 are exposed, and the contact electrode 180 may be formed by filling the etched portion with a metal material. In an embodiment, among the two sidewalls of the through electrode 190, a partial area of ​​the first insulating pattern DP1 that contacts one sidewall adjacent to the source / drain pattern 150 may be removed. Therefore, the contact electrode 180 may contact the source / drain pattern 150 and the through electrode 190 together. After the contact electrode 180 is formed, a second interlayer insulating layer 172 that covers the first interlayer insulating layer 171, the upper surface of the gate separation pattern GC, the upper surface of the contact electrode 180, and the upper surface of the gate structure GS may be formed.

[0102] like Fig.26 and Fig. 27As shown, the upper conductor structure 210 may be formed on the second interlayer insulating layer 172. The upper conductor structure 210 may include an upper conductor 211, an upper via 212, and an upper insulating layer 213. In an embodiment, the upper conductor structure 210 may include upper conductors 211 of various layers formed by a plurality of repeated processes. For example, after depositing a layer of the upper insulating layer 213 on the upper surface of the interlayer insulating layer 170, the upper insulating layer 213 is patterned, and the upper conductor 211 may be formed. Thereafter, after depositing a layer of the upper insulating layer 213 again, the upper insulating layer 213 is patterned, and an upper via 212 may be formed on the upper conductor 211. Thereafter, an upper conductor 211 connected to the second end of the upper via 212 may be formed. The upper conductor 211 and the upper via 212 may include a metal (e.g., copper (Cu)). The upper insulating layer 213 may be located on the upper surface of the interlayer insulating layer 170. The upper insulating layer 213 may cover the upper conductor 211 and the upper via 212. That is, the upper conductive line 211 and the upper via 212 may be disposed in the upper insulating layer 213. The upper insulating layer 213 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiON) or at least one of a low dielectric layer.

[0103] like Fig.28 and Fig.29 As shown, the substrate 10 may be removed by performing an etching process. A process of thinning the substrate 10 by performing a chemical mechanical polishing (CMP) process on the lower surface of the substrate 10 may be additionally performed. The etching process of removing the substrate 10 may be performed, for example, by a wet etching method. However, the present disclosure is not limited thereto, and the substrate 10 may be removed by a dry etching process. As a partial area of ​​the substrate 10 is removed, the lower surfaces of the through electrodes 190 and the first insulating pattern DP1 may be exposed. Another area of ​​the substrate 10 that is left by not being removed may form a lower pattern BP.

[0104] like Fig.30 and Fig.31As shown, the second trench TR2 may be formed by selectively etching a partial area of ​​the first insulating pattern DP1. The field insulating layer 105 and the first insulating pattern DP1 may be sequentially etched and may be etched together in the same process. In an embodiment, the field insulating layer 105 and the first insulating pattern DP1 may be etched by a dry etching process. However, the present disclosure is not limited thereto, and the field insulating layer 105 and the first insulating pattern DP1 may be etched by a wet etching process. In such an embodiment, a portion of the first insulating pattern DP1 may be etched by using an etchant having a higher etching selectivity relative to the first insulating pattern DP1 than the interlayer insulating layer 170. As the second trench TR2 is formed, a portion of the lower surface of the contact electrode 180 and the sidewall of the through electrode 190 may be exposed. In an embodiment, the first insulating pattern DP1 may be etched until the lower surface is located at a level higher than or equal to the upper surface of the source / drain pattern 150. However, the present disclosure is not limited thereto, and the first insulating pattern DP1 may be etched until a lower surface is lower than an upper surface of the source / drain pattern 150 and is located at a higher level than a lower surface of the source / drain pattern 150 .

[0105] like Fig.32 and Fig.33 As shown, in the region from which the substrate 10 is removed, a base insulating layer 100 covering the lower pattern BP, the field insulating layer 105 , the lower surface of the second trench TR2 , and the lower surface of the through electrode 190 may be formed.

[0106] In an embodiment, since the width of the second trench TR2 in the second direction D2 may be relatively narrow, the base insulating layer 100 may not be formed in a deep position of the second trench TR2 (e.g., a position adjacent to the lower surface of the first insulating pattern DP1 or the contact electrode 180). However, the base insulating layer 100 formed on the second trench TR2 may protrude into the second trench TR2 by gravity, and the second insulating pattern DP2 may be formed. In such an embodiment, the second insulating pattern DP2 may be controlled to have an upper surface having a level lower than or equal to that of the lower surface of the source / drain pattern 150. In another embodiment, the second insulating pattern DP2 may be controlled to have an upper surface having a level higher than that of the lower surface of the source / drain pattern 150. The air gap ag may be located between the second insulating pattern DP2 and the first insulating pattern DP1. Therefore, the first insulating pattern DP1, the second insulating pattern DP2, and the air gap ag may form a gate separation pattern GC.

[0107] In an embodiment, the second insulating pattern DP2 may be formed in a process separate and different from the process of forming the base insulating layer 100. For example, in a region from which the substrate 10 is removed, after forming the second insulating pattern DP2 protruding from the lower surface of the second trench TR2 into the second trench TR2, the base insulating layer 100 covering the lower pattern BP, the field insulating layer 105, the lower surface of the second insulating pattern DP2, and the lower surface of the through electrode 190 may be formed. In such an embodiment, the second insulating pattern DP2 may include an insulating material different from the insulating material included in the base insulating layer 100. However, the present disclosure is not limited thereto, and the second insulating pattern DP2 may include the same insulating material as the insulating material included in the base insulating layer 100.

[0108] like Fig.34 and Fig.35 As shown, by etching a partial region of the base insulating layer 100, a power rail PR penetrating the base insulating layer 100 in the third direction D3 may be formed. That is, the power rail PR may be formed in a partial region of the base insulating layer 100 overlapping the through electrode 190 and / or the gate separation pattern GC in the third direction D3. An upper surface of the power rail PR may contact the lower surface of the second insulating pattern DP2 and the through electrode 190. The power rail PR may extend in the first direction D1.

[0109] like Fig.36 and Fig.37 As shown, the lower conductor structure 220 may be formed on the lower surface of the base insulating layer 100. In an embodiment, the lower conductor structure 220 may include lower conductors 221 of various layers formed by a plurality of repeated processes. For example, after depositing a layer of the lower insulating layer 223 on the bottom surface of the base insulating layer 100, the lower insulating layer 223 may be patterned, and the lower conductor 221 connected to the lower conductive pattern 190b may be formed. Thereafter, after depositing a layer of the lower insulating layer 223 again, the lower insulating layer 223 may be patterned, and a lower via 222 may be formed on the lower conductor 221 connected to the lower conductive pattern 190b. Thereafter, a lower conductor 221 connected to the second end of the lower via 222 may be formed. The lower conductor 221 and the lower via 222 may include a metal (e.g., copper (Cu)). The lower insulating layer 223 may be located on the bottom surface of the base insulating layer 100. The lower insulating layer 223 may cover the lower conductor 221 and the lower via 222. That is, the lower conductive line 221 and the lower via 222 may be disposed in the lower insulating layer 223. The lower insulating layer 223 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiON) or at least one of a low dielectric layer.

[0110] Fig.38is a top view showing a semiconductor device according to an embodiment. Figure 39 to Figure 42 is a cross-sectional view showing a semiconductor device according to an embodiment. Fig.39 , showing the Fig.38 A cross-sectional view of the semiconductor device taken along line II'. Fig.40 It is along Fig.38 sectional view of the semiconductor device taken along line II-II'. Fig.41 It is along Fig.38 1 is a cross-sectional view of the semiconductor device taken along line III-III'. Fig.42 It is along Fig.38 A cross-sectional view of the semiconductor device taken along line IV-IV'.

[0111] In an embodiment, the semiconductor device may include a transistor of a complementary FET (CFET) structure. In an embodiment, the semiconductor device may include a transistor of a three-dimensional (3D) stacked FET (3DSFET) structure in which a plurality of transistors may be vertically stacked.

[0112] refer to Figures 38 to 42 According to an embodiment, a semiconductor device may include a base insulating layer 100, an active pattern AP located on the base insulating layer 100, a plurality of channel patterns 140 located on the active pattern AP and including a lower channel pattern 140A and an upper channel pattern 140B, an intermediate dielectric isolation structure MDI located between the lower channel pattern 140A and the upper channel pattern 140B, a field insulating layer 105 located on the base insulating layer 100, a gate structure 160 located on the active pattern AP, a source / drain pattern 300 located on at least a first side of the gate structure 160 and including a lower source / drain pattern 300A and an upper source / drain pattern 300B, a blocking structure 370 located between the lower source / drain pattern 300A and the upper source / drain pattern 300B, and a gate separation pattern GC intersecting the gate structure 160.

[0113] The base insulating layer 100 may include, for example, a layer of oxide, nitride, oxynitride, or a combination thereof. The base insulating layer 100 may include an insulating material. For example, the base insulating layer 100 may include, but is not limited to, silicon nitride (SiN x). Although the base insulating layer 100 is illustrated as a single layer, this is only for ease of explanation, and the present disclosure is not limited thereto. The first surface and the second surface of the base insulating layer 100 may be formed as planes parallel to the first direction D1 and the second direction D2 intersecting the first direction D1. For example, the first surface of the base insulating layer 100 may be an upper surface, and the second surface may be a bottom surface. The upper surface of the base insulating layer 100 is a surface opposite to the bottom surface of the base insulating layer 100 in the third direction D3. The third direction D3 may be a direction perpendicular to the first direction D1 and the second direction D2. The bottom surface of the base insulating layer 100 may be referred to as the back side of the base insulating layer 100. In some embodiments, the logic circuit in the cell region may be implemented on the upper surface of the base insulating layer 100. The base insulating layer 100 may include an upper surface and a bottom surface. The upper surface and the bottom surface of the base insulating layer 100 may be formed as planes parallel to the first direction D1 (X direction) and the second direction D2 intersecting the first direction D1 (X direction). The upper surface of the base insulating layer 100 may be a surface opposite to the bottom surface of the base insulating layer 100 in the third direction D3. The upper surface of the base insulating layer 100 may be referred to as a front surface. The bottom surface of the base insulating layer 100 may be referred to as a back surface. In some embodiments, a logic circuit in a cell region may be implemented on the upper surface of the base insulating layer 100.

[0114] The active pattern AP may be located on the base insulating layer 100. The active pattern AP may extend in the first direction D1. The active pattern AP may have a structure protruding from the base insulating layer 100. The upper surface of the active pattern AP may be positioned to protrude from the upper surface of the field insulating layer 105, however, the present disclosure is not limited thereto. The active pattern AP may be an active pattern AP formed by etching a portion of the base insulating layer 100, and may include an epitaxial layer grown from the base insulating layer 100. The active pattern AP may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. The active pattern AP may include an impurity or a doped region including an impurity.

[0115] According to an embodiment, the semiconductor device may include a plurality of transistor structures. For example, according to an embodiment, the semiconductor device may include a first transistor structure having a plurality of lower channel patterns 140A and a second transistor structure having a plurality of upper channel patterns 140B. According to an embodiment, the first transistor structure and the second transistor structure may be formed in a multi-bridge channel field effect transistor (MBCFET). TM ), in the MBCFET, multiple lower channel patterns 140A and multiple upper channel patterns 140B are surrounded by a gate structure 160.

[0116] In addition, according to an embodiment, the first transistor structure and the second transistor structure may be formed in a 3D stacked field effect transistor (3D-SFET) structure that may be stacked along a third direction D3. The first transistor structure may be one of an N-type MOSFET and a P-type MOSFET, and the second transistor structure may be the other of a P-type MOSFET and an N-type MOSFET. In an embodiment, the first transistor structure and the second transistor structure may be an N-type MOSFET and a P-type MOSFET, respectively, however, the present disclosure is not limited thereto. Hereinafter, an example is described in which a plurality of lower channel patterns 140A and a plurality of upper channel patterns 140B are stacked along a third direction D3 to form a 3D-SFET structure. However, the present disclosure is not limited thereto.

[0117] The plurality of channel patterns 140 may be located on the active pattern AP. In an embodiment, the plurality of channel patterns 140 may include a plurality of lower channel patterns 140A located on the active pattern AP and a plurality of upper channel patterns 140B located on the plurality of lower channel patterns 140A.

[0118] The plurality of lower channel patterns 140A may be located on an upper surface of the active pattern AP. The plurality of lower channel patterns 140A may be spaced apart from the active pattern AP in the third direction D3. Each of the plurality of lower channel patterns 140A may be spaced apart in the third direction D3.

[0119] In an embodiment, Fig.41 As shown, the widths of the plurality of lower channel patterns 140A along the second direction D2 may decrease away from the upper surface of the base insulating layer 100. Fig.39 As shown, the widths of the plurality of lower channel patterns 140A along the first direction D1 may decrease away from the upper surface of the base insulating layer 100. However, the present disclosure is not limited thereto, and the widths of the plurality of lower channel patterns 140A along the second direction D2 may be substantially similar and / or the same. In addition, the widths of the plurality of lower channel patterns 140A along the first direction D1 may be substantially similar and / or the same.

[0120] A plurality of upper channel patterns 140B may be located on a plurality of lower channel patterns 140A. That is, a plurality of upper channel patterns 140B may be located on the upper surface of an intermediate dielectric isolation structure MDI which is in turn located on a plurality of lower channel patterns 140A. A plurality of upper channel patterns 140B may be spaced apart from a plurality of lower channel patterns 140A in a third direction D3. For example, an intermediate dielectric isolation structure MDI may be located between a plurality of upper channel patterns 140B and a plurality of lower channel patterns 140A, and a plurality of upper channel patterns 140B may be positioned to be spaced apart from a plurality of lower channel patterns 140A in a third direction D3 by the intermediate dielectric isolation structure MDI. Each of a plurality of upper channel patterns 140B may be spaced apart in the third direction D3.

[0121] In an embodiment, Fig.41 As shown, the widths of the plurality of upper channel patterns 140B along the second direction D2 may decrease away from the upper surface of the base insulating layer 100. However, the present disclosure is not limited thereto, and the widths of the plurality of upper channel patterns 140B along the second direction D2 may be substantially similar and / or identical. Fig.39 As shown, widths of the plurality of upper channel patterns 140B along the first direction D1 may be substantially similar and / or identical, however, the present disclosure is not limited thereto.

[0122] The plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may be multi-channel active patterns. In embodiments, the active pattern AP, the plurality of lower channel patterns 140A, and the plurality of upper channel patterns 140B may be in a nanosheet shape and may be semiconductor patterns including a semiconductor material.

[0123] The plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may be channel patterns formed by etching a portion of the base insulating layer 100, and may include an epitaxial layer grown from the base insulating layer 100. The plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. In addition, the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0124] Each of the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B may include a material substantially similar to and / or the same as the active pattern AP, and may include a material different from the active pattern AP.

[0125] The Group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0126] The III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as III-group elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as V-group elements.

[0127] In an embodiment, the active pattern AP and the plurality of channel patterns 140 may include silicon (Si). As another example, the active pattern AP and the plurality of channel patterns 140 may include silicon germanium (SiGe). As yet another example, the active pattern AP may include silicon (Si), and the plurality of channel patterns 140 may include silicon germanium (SiGe).

[0128] exist Fig.39 and Fig.41 , although two lower channel patterns 140A and two upper channel patterns 140B are illustrated as being stacked to be spaced apart along the third direction D3, this is merely for better understanding and ease of description, and the present disclosure is not limited thereto. For example, three (3) or more lower channel patterns among the plurality of lower channel patterns 140A and / or three (3) or more upper channel patterns among the plurality of upper channel patterns 140B may be stacked to be spaced apart along the third direction D3. Alternatively or additionally, one lower channel pattern 140A and / or one upper channel pattern 140B may be stacked to be spaced apart along the third direction D3.

[0129] The intermediate dielectric isolation structure MDI may be located on the plurality of lower channel patterns 140A. The intermediate dielectric isolation structure MDI may be located between the uppermost lower channel pattern 140A and the lowermost upper gate structure 160B.

[0130] The intermediate dielectric isolation structure MDI may include an intermediate insulating pattern 230. The intermediate insulating pattern 230 may include various insulating materials. For example, the intermediate insulating pattern 230 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, etc. The intermediate dielectric isolation structure MDI may space the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B apart from each other.

[0131] In the embodiment, the intermediate dielectric isolation structure MDI has been described as including a single intermediate insulating pattern 230, however, the present disclosure is not limited thereto. For example, the intermediate dielectric isolation structure MDI may include a plurality of intermediate insulating patterns 230. Alternatively or additionally, the intermediate dielectric isolation structure MDI may include a semiconductor pattern located between the plurality of intermediate insulating patterns 230. In such an embodiment, the plurality of upper channel patterns 140B and the plurality of lower channel patterns 140A may be spaced apart by the intermediate dielectric isolation structure MDI.

[0132] The field insulating layer 105 may be located on the base insulating layer 100. The field insulating layer 105 may cover at least a portion of the side surface of the active pattern AP. Fig.41 As shown, the field insulation layer 105 may cover a portion of the side surface of the active pattern AP. That is, a portion of the side surface of the active pattern AP may be covered by the field insulation layer 105, and the remaining portion of the side wall of the active pattern AP may be covered by the gate structure 160. The field insulation layer 105 may overlap with the active pattern AP in the second direction D2. In addition, the field insulation layer 105 may not be located on the upper surface of the active pattern AP. In an embodiment, the upper surface of the field insulation layer 105 is illustrated as extending in a direction parallel to the upper surface of the base insulation layer 100, however, the present disclosure is not limited thereto. For example, the field insulation layer 105 may have a curved upper surface having a horizontal height that becomes higher as it is closer to the active pattern AP.

[0133] Fig.41 The field insulating layer 105 is illustrated to cover at least a portion of the side surface of the active pattern AP, however, the present disclosure is not limited thereto. For example, the field insulating layer 105 may completely cover the side surface of the active pattern AP. In such an embodiment, the side surface of the active pattern AP may be completely covered by the field insulating layer 105.

[0134] The field insulating layer 105 may include a layer of, for example, oxide, nitride, oxynitride, or a combination thereof. Although the field insulating layer 105 is illustrated as having a single layer, this is only for convenience of explanation and the present disclosure is not limited thereto.

[0135] The gate structure 160 may be located on the active pattern AP. The gate structure 160 may extend in the second direction D2. The gate structure 160 may be positioned to be spaced apart in the first direction D1. The gate structure 160 may be located on the active pattern AP. The gate structure 160 may intersect the active pattern AP. The gate structures 160 may each surround a plurality of channel patterns 140.

[0136] In an embodiment, the first transistor structure and the second transistor structure may be configured to share a gate structure 160. That is, the first transistor structure may include a plurality of lower channel patterns 140A, a gate structure 160 surrounding the plurality of lower channel patterns 140A, and a lower source / drain pattern 300A connected to the plurality of lower channel patterns 140A at one side of the gate structure 160. In addition, the second transistor structure may include a plurality of upper channel patterns 140B, a gate structure 160 surrounding the plurality of upper channel patterns 140B, and an upper source / drain pattern 300B connected to the plurality of upper channel patterns 140B at one side of the gate structure 160. Fig.41 As shown, since one gate structure 160 surrounds the plurality of lower channel patterns 140A and the plurality of upper channel patterns 140B together, the first transistor structure and the second transistor structure may be configured to share one gate structure 160 .

[0137] The gate structure 160 may include a lower gate structure 160A, an upper gate structure 160B, and a main gate structure 160M. The lower gate structure 160A may be located between a plurality of lower channel patterns 140A adjacent to each other in the third direction D3, between the active pattern AP and the lowest lower channel pattern 140A, and between the uppermost lower channel pattern 140A and the intermediate dielectric isolation structure MDI. The upper gate structure 160B may be located between a plurality of upper channel patterns 140B adjacent to each other in the third direction D3, and between the lowest upper channel pattern 140B and the intermediate dielectric isolation structure MDI. The main gate structure 160M may be located on the uppermost upper channel pattern 140B.

[0138] The lower gate structure 160A may be adjacent to the lower source / drain pattern 300A. The upper gate structure 160B may be adjacent to the upper source / drain pattern 300B. The main gate structure 160M may be located on the lower gate structure 160A, the upper gate structure 160B, and the plurality of upper channel patterns 140B.

[0139] According to an embodiment, each of the lower gate structure 160A and the upper gate structure 160B may include a plurality of layers, and the plurality of layers may be alternately stacked with the plurality of channel patterns 140. For example, Fig.39 and Fig.41 As shown, the lower gate structure 160A may include three (3) layers alternately stacked with the plurality of lower channel patterns 140A, and the upper gate structure 160B may include two (2) layers alternately stacked with the plurality of upper channel patterns 140B. However, the present disclosure is not limited thereto, and the number of layers of the lower gate structure 160A and the upper gate structure 160B may be changed in various ways.

[0140] Each of the lower gate structure 160A and the upper gate structure 160B may include gate electrodes 165A and 165B and gate insulating layers 162A and 162B.

[0141] The gate electrodes 165A and 165B may be located on the active pattern AP. For example, the lower gate electrode 165A may be located on the active pattern AP, and the upper gate electrode 165B may be located on the lower gate electrode 165A. The gate electrodes 165A and 165B may cross the active pattern AP. The gate electrodes 165A and 165B may surround a plurality of channel patterns 140. For example, the lower gate electrode 165A may surround a plurality of lower channel patterns 140A, and the upper gate electrode 165B may surround a plurality of upper channel patterns 140B.

[0142] In addition, at least a portion of the gate electrodes 165A and 165B may be located between the plurality of channel patterns 140. For example, the lower gate electrode 165A may be located between the plurality of lower channel patterns 140A, and the upper gate electrode 165B may be located between the plurality of upper channel patterns 140B. Another portion of the gate electrodes 165A and 165B may be positioned to cover both side surfaces of the stacked structure of the gate electrodes 165A and 165B and the plurality of channel patterns 140.

[0143] The gate electrodes 165A and 165B may include a conductive material. The gate electrodes 165A and 165B may include, but are not limited to, at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal oxynitride, and the like. The gate electrodes 165A and 165B may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W) , aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) at least one and their combinations, however, the present disclosure is not limited thereto. The conductive metal oxide and the conductive metal oxynitride may include oxidized forms of the materials mentioned above, however, the present disclosure is not limited thereto. The gate electrodes 165A and 165B may include the same material, however, the present disclosure is not limited thereto, and the gate electrodes 165A and 165B may include different materials.

[0144] The gate insulating layers 162A and 162B may be positioned along the circumference of the plurality of channel patterns 140. For example, the lower gate insulating layer 162A may be positioned along the circumference of the plurality of lower channel patterns 140A, and the upper gate insulating layer 162B may be positioned along the circumference of the plurality of upper channel patterns 140B. In addition, the lower gate insulating layer 162A may extend along the upper surface of the active pattern AP.

[0145] The lower gate insulating layer 162A may directly contact the active pattern AP, the plurality of lower channel patterns 140A, and the intermediate dielectric isolation structure MDI. The upper gate insulating layer 162B may directly contact the plurality of upper channel patterns 140B and the intermediate dielectric isolation structure MDI. The gate insulating layers 162A and 162B may be interposed between the plurality of channel patterns 140 and the gate electrodes 165A and 165B. The gate insulating layers 162A and 162B may include various insulating materials.

[0146] In the embodiment, the gate insulating layers 162A and 162B are shown as a single layer, however, the present disclosure is not limited thereto. For example, the gate insulating layers 162A and 162B may be formed on a layer including silicon oxide (SiO x) and a multilayer of a high dielectric constant material. The high dielectric constant material may include silicon oxide (SiO x ) than materials having a higher dielectric constant, such as, but not limited to, hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0147] The main gate structure 160M may be located on the upper gate structure 160B and the plurality of upper channel patterns 140B. The main gate structure 160M may be located on upper surfaces of the plurality of upper channel patterns 140B.

[0148] The main gate structure 160M may include a main gate electrode 165M and a main gate insulating layer 162M.

[0149] The main gate electrode 165M may be located on the upper gate structure 160B and the plurality of upper channel patterns 140B. The main gate electrode 165M may be located on the upper surface of the plurality of upper channel patterns 140B. Therefore, the four surfaces of the plurality of channel patterns 140 may be surrounded by the gate electrodes 165A and 165B and the main gate electrode 165M. The main gate electrode 165M may include a conductive material substantially similar and / or identical to the gate electrodes 165A and 165B. For example, the main gate electrode 165M may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0150] The main gate insulating layer 162M may extend along a side surface of the main gate electrode 165M. The main gate insulating layer 162M may extend along a side surface of the gate spacer 164. The main gate insulating layer 162M may include various insulating materials.

[0151] In the embodiment, the main gate insulating layer 162M is shown as a single layer, however, the present disclosure is not limited thereto. For example, the main gate insulating layer 162M may be formed on a layer including silicon oxide (SiO x ) and a multilayer of a high dielectric constant material. The high dielectric constant material may include silicon oxide (SiO x ) than materials having a higher dielectric constant, such as, but not limited to, hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0152] In an embodiment, the gate structure 160 may be electrically separated from adjacent gate structures by the gate separation pattern GC. Fig.38 and Fig.41 , a partial region of the main gate structure 160M may be penetrated by the gate separation pattern GC in the third direction D3 , and thus the main gate structure M_GS may be electrically separated from the adjacent gate structure in the second direction D2 .

[0153] According to an embodiment, the semiconductor device may further include a gate spacer 164 and a capping layer 166 .

[0154] The gate spacer 164 may be located on the side surface of the main gate electrode 165M. The gate spacer 164 may not be located between the active pattern AP and the plurality of channel patterns 140. The gate spacer 164 may not be located between the plurality of channel patterns 140 adjacent in the third direction D3.

[0155] The gate spacer 164 may include, for example, silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboride nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the gate spacer 164 is illustrated as a single layer, this is only for ease of explanation and the present disclosure is not limited thereto.

[0156] The capping layer 141 may be located on the main gate structure M_GS and the gate spacer 142. The upper surface of the capping layer 166 may be located on the same plane as the upper surface of the interlayer insulating layer 107. In an embodiment, the capping layer 166 may also be located between the gate spacers 164.

[0157] The capping layer 141 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The capping layer 166 may include a material having an etching selectivity with respect to the interlayer insulating layer 107 .

[0158] In embodiments, the capping layer 166 and the gate spacer 164 may be penetrated in the third direction D3 along the gate separation pattern GC and the through electrode 190. The capping layer 166 may have an upper surface having a height substantially similar and / or the same as that of an upper surface of the gate separation pattern GC.

[0159] The source / drain pattern 300 may be located at least on a first side of the gate structure 160. For example, the source / drain pattern 300 may be located on both sides of the gate structure 160. The source / drain pattern 300 may be located on the active pattern AP. The source / drain pattern 300 may contact the side surfaces of the plurality of channel patterns 140. The source / drain pattern 300 may be connected to the plurality of channel patterns 140.

[0160] According to an embodiment, the source / drain pattern 300 may include a lower source / drain pattern 300A and an upper source / drain pattern 300B. The lower source / drain pattern 300A may be located on the active pattern AP. The lower source / drain pattern 300A may be located on at least a first side of the lower gate structure 160A. For example, the lower source / drain pattern 300A may be located on both sides of the lower gate structure 160A. The lower source / drain pattern 300A may be connected to a plurality of lower channel patterns 140A.

[0161] The lower source / drain pattern 300A may be and / or may include an epitaxial pattern formed by a selective epitaxial growth process using the active pattern AP and the plurality of lower channel patterns 140A as seeds. The lower source / drain pattern 300A may be used as a source / drain of a first transistor structure using the plurality of lower channel patterns 140A as a channel region. In an embodiment, the first transistor structure may be an N-type MOSFET, however, the present disclosure is not limited thereto.

[0162] like Fig.40 As shown, on a cross section formed by the second direction D2 and the third direction D3, the lower source / drain pattern 300A may be in a trapezoidal shape whose width is wider as it is closer to the upper surface of the base insulating layer 100. That is, on a cross section formed by the second direction D2 and the third direction D3, the lower source / drain pattern 300A may include an inclined surface inclined from the upper surface of the base insulating layer 100. This may be due to the characteristics of a process of forming the lower source / drain pattern 300A in a space between gate spacers 164 facing each other. However, the present disclosure is not limited thereto, and for example, the width of the lower source / drain pattern 300A along the second direction D2 may be constant.

[0163] In an embodiment, in a cross section formed by the first direction D1 and the third direction D3, the lower source / drain pattern 300A may have an inclined side surface having a lower width narrower than an upper width according to an aspect ratio, however, the present disclosure is not limited thereto. For example, the lower width and the upper width of the lower source / drain pattern 300A may be substantially similar and / or identical.

[0164] In an embodiment, the lower source / drain pattern 300A is formed as a single layer, however, the present disclosure is not limited thereto, and the lower source / drain pattern 300A may be formed in a multi-layer structure including a semiconductor material.

[0165] According to embodiments, the upper source / drain pattern 300B of the semiconductor device may be located on the lower source / drain pattern 300A.

[0166] The upper source / drain pattern 300B may be positioned to be spaced apart from the lower source / drain pattern 300A in the third direction D3. For example, a blocking structure 370 may be located between the upper source / drain pattern 300B and the lower source / drain pattern 300A, and the upper source / drain pattern 300B and the lower source / drain pattern 300A may be spaced apart by the blocking structure 370. Therefore, the upper source / drain pattern 300B and the lower source / drain pattern 300A may be electrically insulated.

[0167] The upper source / drain pattern 300B may be located at least on a first side of the upper gate structure 160B. For example, the upper source / drain pattern 300B may be located on both sides of the upper gate structure 160B. The upper source / drain pattern 300B may be connected to the plurality of upper channel patterns 140B.

[0168] The upper source / drain pattern 300B may contact the side surfaces of the plurality of upper channel patterns 140B. In addition, unlike the lower source / drain pattern 300A, since the upper source / drain pattern 300B is positioned to be separated from the lower source / drain pattern 300A in the third direction D3, the upper source / drain pattern 300B may not contact the upper surface of the active pattern AP.

[0169] The upper source / drain pattern 300B may be an epitaxial pattern formed by a selective epitaxial growth process using a plurality of upper channel patterns 140B as seeds. The upper source / drain pattern 300B may be a pattern formed by using two side surfaces of a plurality of upper channel patterns 140B as seeds. That is, unlike the lower source / drain pattern 300, which is a pattern formed by using two side surfaces of the upper surface of the active pattern AP and a plurality of lower channel patterns 140A as seeds, the upper source / drain pattern 300B may be a pattern formed by using only two side surfaces of a plurality of upper channel patterns 140B as seeds. The upper source / drain pattern 300B may be used as a source / drain of a second transistor structure using a plurality of upper channel patterns 140B as a channel region. In an embodiment, the second transistor structure may be a P-type MOSFET, however, the present disclosure is not limited thereto.

[0170] like Fig.40As shown, on the cross section formed by the second direction D2 and the third direction D3, the upper source / drain pattern 300B may have a shape different from the lower source / drain pattern 300A. For example, on the cross section formed by the second direction D2 and the third direction D3, the upper source / drain pattern 300B may have a hexagonal shape, however, the present disclosure is not limited thereto. For example, the upper source / drain pattern 300B may be in a circular shape, an elliptical shape, a pentagonal shape, or a shape similar thereto. In an embodiment, the lower source / drain pattern 300A may be in a trapezoidal shape with a width that is wider as it is closer to the upper surface of the base insulating layer 100. This may be due to the characteristics of the process in which the upper source / drain pattern 300B is formed in an open space on the blocking structure 370, but the lower source / drain pattern 300A is formed in a space between gate spacers 164 facing each other.

[0171] The gate separation pattern GC may extend in a direction intersecting the gate structure 160 (e.g., the first direction D1). The gate separation pattern GC may also extend in a third direction D3. That is, the gate separation pattern GC may extend in the third direction D3 and penetrate the main gate structure 160M. Therefore, the gate separation pattern GC may electrically separate the gate structures 160 arranged along the first direction D1. The gate separation pattern GC may have an upper surface with a height substantially similar and / or the same as that of the capping layer 166 and / or the contact structure 380. The gate separation pattern GC may penetrate the main gate structure 160M in the third direction and extend into the active pattern AP. Reference Figure 40 to Figure 42 The lower surface of the gate separation pattern GC may contact the upper surface of the power rail PR. The gate separation pattern GC may include an insulating material. For example, the gate separation pattern GC may include silicon nitride (SiN x ) and / or silicon oxide (SiO x ). However, the present disclosure is not limited thereto, and the gate separation pattern GC may include various insulating materials for electrically separating the main gate structure 160M from other gate structures. In an embodiment, the gate separation pattern GC may be penetrated by the through electrode 190 in the third direction D3. That is, the gate separation pattern GC may surround the sidewall of the through electrode 190. Therefore, the gate separation pattern GC may contact the sidewall of the through electrode 190. The air gap ag included in the gate separation pattern GC may be located between portions of the two sidewalls of the through electrode 190 and the gate structure GS. The air gap ag included in the gate separation pattern GC may also be located between the interlayer insulating layer 107 and the two sidewalls of the through electrode 190. The gate separation pattern GC may have an upper surface having a height substantially similar and / or the same as the upper surface of the through electrode 190. The gate separation pattern GC may have a lower surface having a height substantially similar and / or the same as the lower surface of the through electrode 190.

[0172] refer to Figure 40 to Figure 42 The gate separation pattern GC may include a plurality of insulating layers DP1 and DP2 and an air gap ag between the insulating layers DP1 and DP2. For example, the gate separation pattern GC may include a first insulating pattern DP1, a second insulating pattern DP2 and an air gap ag between the first insulating pattern DP1 and the second insulating pattern DP2.

[0173] An upper surface of the first insulating pattern DP1 may contact the interlayer insulating layer 107. A side surface of the first insulating pattern DP1 may contact the capping layer 166. The first insulating pattern DP1 may not be located in a region where the gate separation pattern GC is penetrated by the contact structure 380. Fig.40 , the lower surface of the first insulating pattern DP1 may be located at a level higher than or equal to the level of the upper surface of the upper source / drain pattern 300B. That is, the first insulating pattern DP1 may not overlap with the upper source / drain pattern 300B and the lower source / drain pattern 300A in the second direction D2. The first insulating pattern DP1 may include an insulating material. For example, the first insulating pattern DP1 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and / or silicon carbonitride (SiC x N y ). However, the present disclosure is not limited thereto, and the first insulating pattern DP1 may include various insulating materials for electrically isolating the main gate structure 160M from other gate structures. In an embodiment, the first insulating pattern DP1 may include an insulating material different from the insulating material included in the interlayer insulating layer 107. The first insulating pattern DP1 may include an insulating material having an etching selectivity relative to the interlayer insulating layer 107.

[0174] A lower surface of the second insulating pattern DP2 may contact the power rail PR. A side surface of the second insulating pattern DP2 may contact the field insulating layer 105. Fig.40 , the upper surface of the second insulating pattern DP2 may be located at a level lower than or equal to the level of the lower surface of the lower source / drain pattern 300A. That is, the second insulating pattern DP2 may not overlap with the upper source / drain pattern 300B and the lower source / drain pattern 300A in the second direction D2. However, the present disclosure is not limited thereto, and the upper surface of the second insulating pattern DP2 may be located at a higher level than the lower surface of the lower source / drain pattern 300A. The second insulating pattern DP2 may include an insulating material. For example, the second insulating pattern DP2 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and / or silicon carbonitride (SiC x N y) in the base insulating layer 100. However, the present disclosure is not limited thereto, and the second insulating pattern DP2 may include various insulating materials for electrically isolating the main gate structure 160M from other gate structures. In an embodiment, the second insulating pattern DP2 may include the same insulating material as the insulating material included in the base insulating layer 100. In an embodiment, the second insulating pattern DP2 may be formed in the same process as the base insulating layer 100. However, the present disclosure is not limited thereto, and the second insulating pattern DP2 may be formed in a process separate from the process of forming the base insulating layer 100. In such an embodiment, the second insulating pattern DP2 may include an insulating material different from the insulating material included in the base insulating layer 100.

[0175] The air gap ag may be located between the first insulation pattern DP1 and the second insulation pattern DP2. The air gap ag may refer to an empty space located between the first insulation pattern DP1 and the second insulation pattern DP2. Fig.40 , the air gap ag may include a portion overlapping the upper source / drain pattern 300B and the lower source / drain pattern 300A in the second direction D2. In an embodiment, the dielectric constant of the air gap ag may be lower than the dielectric constant of the insulating material included in the first insulating pattern DP1 and / or the second insulating pattern DP2. In an embodiment, the air gap ag may be filled with air, and the dielectric constant of the air is about 1.

[0176] According to an embodiment, the semiconductor device may further include a through electrode 190 penetrating the gate separation pattern GC, a contact structure 380 located between the source / drain pattern 300 and the through electrode 190, an interlayer insulating layer 107 covering the source / drain pattern 300, the gate structure 160 and the gate separation pattern GC, a lower wire structure 220 located on the lower surface of the base insulating layer 100, and a power rail PR located on the lower wire structure 220.

[0177] The through electrode 190 may interconnect the contact structure 380 and the power rail PR. That is, a portion of the through electrode 190 may contact the contact structure 380, and another portion may contact the power rail PR. Figures 38 to 42According to an embodiment, the through electrode 190 may be located on the inside of the gate separation pattern GC. That is, the through electrode 190 may be surrounded by the gate separation pattern GC. Therefore, the contact structure 380 may penetrate a partial area of ​​the gate separation pattern GC and be connected to the through electrode 190. The width of the through electrode 190 in the second direction D2 may be narrower as it is closer to the power rail PR. The through electrode 190 may penetrate the gate separation pattern GC in the third direction D3. Therefore, both side walls of the through electrode 190 may contact the gate separation pattern GC. The air gap ag may be located between the gate structure GS and portions of both side walls of the through electrode 190. The air gap ag may be located between the first interlayer insulating layer 107 and both side walls of the through electrode 190. The through electrode 190 may have an upper surface having a height substantially similar to and / or identical to that of the gate separation pattern GC. The through electrode 190 may extend in the first direction D1 parallel to the gate separation pattern GC and the gate structure 160. The through electrode 190 may include a conductive material. For example, the through electrode 190 may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride. Since the through electrode 190 is located inside the gate separation pattern GC, when the semiconductor device according to the embodiment is manufactured, the process margin can be improved, and a short circuit that may occur between the source / drain pattern 300 and the through electrode 190 can be prevented.

[0178] The contact structure 380 may be located on the upper source / drain pattern 300B. The contact structure 380 may penetrate the interlayer insulating layer 107 and be electrically connected to the upper source / drain pattern 300B. The contact structure 380 may have an inclined side surface having a narrower lower width than an upper width according to the aspect ratio, however, the present disclosure is not limited thereto. The contact structure 380 may be positioned to be recessed into the upper source / drain pattern 300B to a predetermined depth. For example, the bottom surface of the contact structure 380 may be higher than the bottom surface of the topmost channel pattern among the plurality of upper channel patterns 140B. However, the present disclosure is not limited thereto, and the bottom surface of the contact structure 380 may be located at a similar horizontal height together with the bottom surface of the topmost upper channel pattern 140B among the plurality of upper channel patterns 140B, or may be lower than the bottom surface of the topmost upper channel pattern. Alternatively or additionally, the bottom surface of the contact structure 380 may be located between the bottom surface of the bottommost upper channel pattern and the bottom surface of the topmost upper channel pattern among the plurality of upper channel patterns 140B. According to an embodiment, the contact structure 380 of the semiconductor device may include a contact electrode 386, a first barrier layer 384 surrounding the contact electrode 386, and a first silicide layer 382 located between the first barrier layer 384 and the upper source / drain pattern 300B. The contact electrode 386 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The first barrier layer 384 may include, for example, a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The first silicide layer 382 may surround a portion of the contact electrode 386 recessed into the upper source / drain pattern 300B. The first silicide layer 382 may include a metal silicide. For example, the first silicide layer 382 may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. In an embodiment, the number and arrangement of the conductive layers forming the contact structure 380 may be changed in various ways. In an embodiment, the first barrier layer 384 and / or the first silicide layer 382 may be omitted.

[0179] In an embodiment, the contact structure 380 may extend in the second direction D2 and be connected to the through electrode 190. That is, a portion of the contact structure 380 may contact the upper source / drain pattern 300B, and another portion may contact the through electrode 190. The contact structure 380 may have an upper surface having a height substantially similar and / or the same as that of the through electrode 190 and the gate separation pattern GC. Fig.38 and Fig.40 The contact structure 380 may extend into the gate separation pattern GC. The contact structure 380 may penetrate a partial region of the gate separation pattern GC and be connected to a portion of the through electrode 190.

[0180] The power rail PR may be located on the lower conductive line structure 220. The power rail PR may extend into the base insulating layer 100 along the third direction D3. Fig.40 and Fig.41 , the power rail PR may extend into the base insulating layer 100 along the third direction D3 and may contact the lower surfaces of the through-electrode 190 and the gate separation pattern GC. The width of the power rail PR in the second direction D2 may be narrower as it is closer to the lower surfaces of the through-electrode 190 and the gate separation pattern GC. Fig.42 , the power rail PR may also extend in the first direction D1. The lower surface of the power rail PR may contact the lower conductive line structure 220. The power rail PR may include a conductive material. For example, the power rail PR may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride. The power rail PR may be connected to the lower conductive line structure 220 and transmit the power supplied from the lower conductive line structure 220 to the source / drain pattern 300.

[0181] The lower conductor structure 220 may be disposed on the bottom surface of the base insulating layer 100. In an embodiment, the lower conductor structure 220 may be a configuration for supplying power to the source / drain pattern 300. For example, the lower conductor structure 220 may be a power delivery network. The lower conductor structure 220 may include a lower conductor 221, a lower path 222, and a lower insulating layer 223. The lower conductor 221 and the lower path 222 may be located on the bottom surface of the base insulating layer 100. The lower conductor 221 and the lower path 222 may include a metal (e.g., copper (Cu)). The lower insulating layer 223 may be located on the bottom surface of the base insulating layer 100. The lower insulating layer 223 may be disposed between the bottom surface of the base insulating layer 100, the lower conductor 221, and the lower path 222 and insulate them. That is, the lower insulating layer 223 may cover the lower conductor 221 and the bottom surface of the base insulating layer 100. The lower conductor 221 and the lower path 222 may be located in the lower insulating layer 223. The lower insulating layer 223 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiON) or at least one of a low dielectric layer.

[0182] The blocking structure 370 may be located between the lower source / drain pattern 300A and the upper source / drain pattern 300B. The blocking structure 370 may overlap with the lower source / drain pattern 300A and the upper source / drain pattern 300B in the third direction (Z direction). The blocking structure 370 may be located between the intermediate dielectric isolation structure MDI. The upper surface and the bottom surface of the blocking structure 370 may be flat, however, the present disclosure is not limited thereto. For example, the upper surface and / or the bottom surface of the blocking structure 370 may be in a shape that is convex upward or convex downward.

[0183] The barrier structure 370 may include a first barrier pattern 371 extending along the side surface of the middle dielectric isolation structure MDI and the upper surface of the lower source / drain pattern 300A and a second barrier pattern 372 located on the first barrier pattern 371. The first barrier pattern 371 may be located on the side surface of the gate spacer 164, however, the present disclosure is not limited thereto. For example, the first barrier pattern 371 may not be located on the side surface of the gate spacer 164.

[0184] The first barrier pattern 371 and the second barrier pattern 372 may include various insulating materials. The first barrier pattern 371 and the second barrier pattern 372 may include different materials, however, the present disclosure is not limited thereto. For example, the first barrier pattern 371 may include silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof, and the second barrier pattern 372 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. The blocking structure 370 may space the lower source / drain pattern 300A and the upper source / drain pattern 300B apart from each other in a third direction (e.g., Z direction).

[0185] According to an embodiment, the semiconductor device may further include an interlayer insulating layer 107 .

[0186] The interlayer insulating layer 107 may be located on side surfaces of the gate spacer 164 , side surfaces of the capping layer 166 , and an upper surface of the upper source / drain pattern 300B. The interlayer insulating layer 107 may not cover an upper surface of the capping layer 166 .

[0187] The interlayer insulating layer 107 may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), at least one of silicon oxynitride (SiON) and a low dielectric constant material. The low dielectric constant material may include, for example, tetraethyl fluoride orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butyloxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), Toshin silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, however, the present disclosure is not limited thereto.

[0188] While the embodiments of the present disclosure have been described with respect to what are presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a base insulating layer, the base insulating layer comprising a first surface and a second surface opposite to the first surface; a channel layer, the channel layer being located on the first surface of the base insulating layer; source / drain patterns, the source / drain patterns being arranged along a first direction parallel to the first surface of the base insulating layer, so that the channel layer is interposed between the source / drain patterns; a gate structure extending on the first surface of the base insulating layer in a second direction intersecting the first direction and at least partially surrounding the channel layer; a gate separation pattern intersecting the gate structure and penetrating the gate structure in a third direction perpendicular to the first direction and the second direction; and a through electrode, wherein the through electrode penetrates the gate separation pattern in the third direction, The gate structure includes a first gate structure disposed on a first side of the gate separation pattern and a second gate structure disposed on a second side of the gate separation pattern, and The gate separation pattern includes an air gap, and the air gap is arranged between the first gate structure and the through electrode and between the second gate structure and the through electrode.

2. The semiconductor device according to claim 1, further comprising: a lower conductor structure, the lower conductor structure being located on the second surface of the base insulating layer; as well as a power rail located on the lower conductor structure and penetrating the base insulating layer in the third direction, The through electrode includes a first end portion coupled to the power rail.

3. The semiconductor device according to claim 1, wherein The gate separation pattern further includes a first insulating pattern disposed on the air gap and a second insulating pattern disposed between the air gap and the power rail, Wherein, the first insulating pattern comprises a first insulating material, and The second insulating pattern includes a second insulating material different from the first insulating material.

4. The semiconductor device according to claim 3, wherein: The base insulating layer includes the second insulating material.

5. The semiconductor device according to claim 3, wherein: A first level height of a lower surface of the first insulating pattern is higher than or equal to a second level height of an upper surface of the source / drain pattern, and The first level is lower than a third level of the upper surface of the gate structure.

6. The semiconductor device according to claim 3, wherein: A first level of an upper surface of the second insulating pattern is lower than or equal to a second level of a lower surface of the source / drain pattern.

7. The semiconductor device according to claim 3, wherein: A first level height of a lower surface of the first insulating pattern is lower than or equal to a second level height of an upper surface of the source / drain pattern, and The first level is higher than a third level of a lower surface of the source / drain pattern.

8. The semiconductor device according to claim 3, further comprising: a contact electrode disposed between an upper surface of the source / drain pattern and the through electrode, extending into the gate separation pattern, and including a first end portion contacting a portion of the through electrode; as well as A metal pattern includes an upper surface in contact with a lower surface of the contact electrode and a lower surface in contact with the air gap.

9. The semiconductor device according to claim 8, wherein: A first level of a lower surface of the first insulation pattern is higher than a second level of the upper surface of the metal pattern.

10. A method for manufacturing a semiconductor device, the method comprising: forming a channel layer and a source / drain pattern on a first surface of a substrate, wherein the source / drain pattern is arranged along a first direction parallel to the first surface of the substrate, so that the channel layer is interposed between the source / drain patterns; forming a gate structure extending in a second direction intersecting the first direction and at least partially surrounding the channel layer in the second direction; forming a gate separation pattern, the gate separation pattern intersecting the gate structure and penetrating the gate structure in a third direction perpendicular to the first direction and the second direction; forming a through electrode, wherein the through electrode penetrates the gate separation pattern in the third direction; as well as An air gap is formed in the gate separation pattern, the air gap being located between the gate structure and the first and second sidewalls of the through electrode.

11. The method according to claim 10, wherein: Forming the gate separation pattern includes: forming a first insulating pattern by etching a portion of the gate structure and filling the etched portion with an insulating material, and Wherein, forming the through electrode comprises: forming a first trench exposing the upper surface of the substrate by etching a portion of the first insulating pattern; and The interior of the first trench is filled with a conductive material.

12. The method according to claim 11, wherein: Forming the air gap comprises: exposing a lower surface of the first insulating pattern and a lower surface of the through electrode by etching a bottom surface of the substrate; forming a second trench inside the first insulating pattern by etching the first insulating pattern; and A base insulating layer is formed in the region where the substrate is removed, the base insulating layer at least partially covering the lower surface of the through electrode and the second trench.

13. The method according to claim 12, further comprising: forming a power rail penetrating the base insulating layer in the third direction and including an upper surface in contact with the lower surface of the through electrode, wherein the gate separation pattern further comprises a second insulation pattern located between the air gap and the power rail, and The second insulating pattern is formed as a portion of the base insulating layer at least partially overlapping the second trench in the third direction protrudes into the second trench.

14. The method according to claim 13, wherein: The first insulating pattern includes a first insulating material, and The second insulating pattern includes a second insulating material different from the first insulating material.

15. The method according to claim 13, wherein: A first level of the lower surface of the first insulating pattern is higher than or equal to a second level of the upper surface of the source / drain pattern, and The first level is lower than a third level of the upper surface of the gate structure.

16. The method according to claim 13, wherein: A first level of an upper surface of the second insulating pattern is lower than a second level of a lower surface of the source / drain pattern.

17. The method according to claim 13, wherein: A first level of the lower surface of the first insulating pattern is lower than or equal to a second level of the upper surface of the source / drain pattern, and The first level is higher than a third level of a lower surface of the source / drain pattern.

18. A semiconductor device, comprising: a base insulating layer, the base insulating layer comprising a first surface and a second surface opposite to the first surface; a channel layer, the channel layer being located on the first surface of the base insulating layer; source / drain patterns, the source / drain patterns being arranged along a first direction parallel to the first surface of the base insulating layer, so that the channel layer is interposed between the source / drain patterns; a gate structure extending on the first surface of the base insulating layer in a second direction intersecting the first direction and at least partially surrounding the channel layer; a gate separation pattern, the gate separation pattern intersecting the gate structure and penetrating the gate structure in a third direction perpendicular to the first direction and the second direction; an interlayer insulating layer, the interlayer insulating layer at least partially covering the source / drain pattern, the gate structure and the gate separation pattern; An upper conductor structure, the upper conductor structure being located on the interlayer insulating layer; a lower conductor structure, the lower conductor structure being located on the second surface of the base insulating layer; a power rail located on the lower conductor structure and penetrating the base insulating layer in the third direction; as well as a through electrode penetrating the gate separation pattern in the third direction and including a first end portion coupled to the power rail, and Wherein, the gate separation pattern includes an air gap.

19. The semiconductor device according to claim 18, wherein: The gate separation pattern further includes: a first insulating pattern, the first insulating pattern being located on the air gap; and a second insulating pattern, the second insulating pattern being disposed between the air gap and the power rail, Wherein, the first insulating pattern comprises a first insulating material, and The second insulating pattern includes a second insulating material different from the first insulating material.

20. The semiconductor device according to claim 19, wherein A first level height of a lower surface of the first insulating pattern is higher than or equal to a second level height of an upper surface of the source / drain pattern, and The first level is lower than a third level of the upper surface of the gate structure.

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