Integrated circuit device

Abstract

An integrated circuit device includes: a substrate provided with a fin-type active region disposed at a first surface of the substrate; a plurality of nanosheets disposed on a top surface of the fin-type active region and separated from the top surface of the fin-type active region; a gate line disposed on the fin-type active region, the gate line surrounding each of the plurality of nanosheets; a source / drain region disposed on the fin-type active region, a sidewall of the source / drain region being adjacent to the gate line and in contact with the plurality of nanosheets; a back contact extending from the second surface of the substrate toward a lower portion of the source / drain region; and the high-concentration doping layer is arranged at the lower part of the source electrode / drain electrode region. The high-concentration doped layer has a dopant concentration greater than a dopant concentration of the source / drain region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0161438 filed in the Korean Intellectual Property Office on November 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to integrated circuit devices and, more particularly, to integrated circuit devices including backside contacts. Background Art

[0004] As the demand for compact and multifunctional high-performance electronic products grows, higher capacity and higher integration of integrated circuit devices are required. Therefore, it is desirable to efficiently design interconnect structures to achieve higher integration while ensuring the required functions and operating speeds of integrated circuit devices. Summary of the invention

[0005] The present disclosure provides integrated circuit devices with improved performance and reliability.

[0006] According to one aspect of the present disclosure, an integrated circuit device includes: a substrate provided with a fin-type active region, wherein the fin-type active region is disposed at a first surface of the substrate and extends in a first horizontal direction parallel to the first surface of the substrate; a plurality of nanosheets disposed on and separated from the top surface of the fin-type active region; a gate line disposed on the fin-type active region, the gate line surrounds each of the plurality of nanosheets and extends in a second horizontal direction intersecting the first horizontal direction, wherein the second horizontal direction is parallel to the first surface of the substrate; a source / drain region disposed on the fin-type active region, the sidewall of the source / drain region being adjacent to the gate line and in contact with the plurality of nanosheets; a back contact extending from a second surface of the substrate toward a lower portion of the source / drain region, wherein the second surface of the substrate is opposite to the first surface of the substrate; and a high-concentration doping layer disposed at a lower portion of the source / drain region. The high-concentration doping layer has a dopant concentration greater than that of the source / drain region.

[0007] According to one aspect of the present disclosure, an integrated circuit device includes: a fin-type active region, which is arranged on a substrate and extends in a first horizontal direction, wherein the first horizontal direction is parallel to the upper surface of the substrate; a channel region arranged on the fin-type active region; a gate line arranged on the fin-type active region, the gate line surrounds the channel region and extends in a second horizontal direction intersecting the first horizontal direction, wherein the second horizontal direction is parallel to the upper surface of the substrate; a first source / drain region arranged on the fin-type active region, the sidewall of the first source / drain region is adjacent to the gate line and contacts the channel region; a first back contact, which extends from the lower surface of the substrate toward the lower part of the first source / drain region, wherein the lower surface of the substrate is opposite to the upper surface of the substrate; and a first high-concentration doped layer, which is arranged at the lower part of the first source / drain region. The first high-concentration doped layer and the first source / drain region include a first dopant, and the concentration of the first dopant in the first high-concentration doped layer is greater than the concentration of the first dopant in the first source / drain region.

[0008] According to one aspect of the present disclosure, an integrated circuit device includes: a fin-type active region, which is arranged on a substrate and extends in a first horizontal direction, wherein the first horizontal direction is parallel to the upper surface of the substrate; a plurality of nanosheets, which are arranged on the top surface of the fin-type active region, separated from the top surface of the fin-type active region, and have different distances from the top surface of the fin-type active region in a vertical direction perpendicular to the upper surface of the substrate; a gate line arranged on the fin-type active region, the gate line surrounds each of the plurality of nanosheets and extends longitudinally in a second horizontal direction intersecting the first horizontal direction, wherein the second horizontal direction is parallel to the upper surface of the substrate; a source / drain region, which is adjacent to the plurality of nanosheets in the first horizontal direction; a back contact, which extends from the lower surface of the substrate toward the lower part of the source / drain region, wherein the lower surface of the substrate is opposite to the upper surface of the substrate; a high-concentration doped layer, which is arranged at the lower part of the source / drain region; and a metal silicide film, between the upper part of the back contact and the high-concentration doped layer. The source / drain region includes a first semiconductor layer contacting the fin-type active region and a second semiconductor layer on the first semiconductor layer. The metal silicide film is in contact with the high-concentration doped layer. The high-concentration doped layer, the first semiconductor layer, and the second semiconductor layer include a first dopant. A first concentration of the first dopant in the first semiconductor layer is less than a second concentration of the first dopant in the second semiconductor layer. A third concentration of the first dopant in the high-concentration doped layer is greater than the second concentration of the first dopant in the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram showing a layout of a unit block of an integrated circuit device according to some embodiments;

[0011] Figure 2 is a layout diagram showing an integrated circuit device according to some embodiments;

[0012] FIG. 3A to FIG. 3C is a cross-sectional view showing an integrated circuit device according to some embodiments;

[0013] Figure 4 is an enlarged cross-sectional view showing an integrated circuit device according to some embodiments;

[0014] FIG. 5A to FIG. 5C is an enlarged cross-sectional view showing an integrated circuit device according to some embodiments;

[0015] Figure 6 and Figure 7 is an enlarged cross-sectional view showing an integrated circuit device according to some embodiments;

[0016] Figure 8 is a cross-sectional view showing an integrated circuit device according to some embodiments;

[0017] Fig. 9 is a cross-sectional view showing an integrated circuit device according to some embodiments;

[0018] Fig.10 is an enlarged cross-sectional view showing an integrated circuit device according to some embodiments;

[0019] Figures 11 to 13 is a cross-sectional view showing an integrated circuit device according to some embodiments; and

[0020] Figures 14 to 28 is a cross-sectional view of an integrated circuit device, which illustrates process steps of a method of manufacturing the integrated circuit device according to some embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments are described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals denote the same elements, and redundant descriptions thereof will be omitted.

[0022] Figure 1 is a diagram showing a layout of a cell block 12 of an integrated circuit device 10 according to some embodiments.

[0023] Reference Figure 1 The cell block 12 of the integrated circuit device 10 may include a plurality of logic cells LC, and the plurality of logic cells LC may include circuit patterns for forming various circuits on the upper surface of the substrate. The logic cells LC may be arranged in a matrix along a first horizontal direction (X direction) and a second horizontal direction (Y direction) in the cell block 12. The first horizontal direction and the second horizontal direction may be parallel to the upper surface of the substrate.

[0024] Each logic cell LC may include a circuit pattern having a layout designed according to a layout and routing (PnR) rule to perform at least one logic function. The logic cell LC may have various logic functions. In an embodiment, the logic cell LC may include a plurality of standard cells. In an embodiment, at least some of the logic cells LC may perform the same logic function. In some embodiments, at least some of the logic cells LC may perform different logic functions from each other.

[0025] The logic cell LC may include various logic cells having a plurality of circuit elements. Each logic cell LC may include, but is not limited to, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, an XNOR gate, an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), a multiplexer (MXT / MXIT), an OR / AND / Inverter (OAI) gate, an AND / OR (AO) gate, an AND / OR / Inverter (AOI) gate, a D flip-flop, a reset flip-flop, a master-slave flip-flop, a latch, or a combination thereof.

[0026] In the cell block 12, at least some of the logic cells LC forming one of the first to sixth rows R1, R2, R3, R4, R5, and R6 in the first horizontal direction (X direction) may have the same width. At least some of the logic cells LC forming one of the first to sixth rows R1, R2, R3, R4, R5, and R6 may have the same length. However, the present disclosure is not limited to Figure 1 At least some of the logic cells LC forming one of the first to sixth rows R1, R2, R3, R4, R5, and R6 may have different widths and lengths.

[0027] The area of ​​each logic cell LC of the cell block 12 of the integrated circuit device 10 may be defined by a cell boundary CBD. A cell contact portion CBC where the cell boundaries CBD meet each other may be between two logic cells LC adjacent to each other in the first horizontal direction (X direction) or the second horizontal direction (Y direction).

[0028] In some embodiments, among the logic cells LC forming one of the first to sixth rows R1, R2, R3, R4, R5, and R6, two logic cells LC adjacent to each other in the first horizontal direction (X direction) may contact each other at the cell contact portion CBC without a gap between the two logic cells LC. As used herein, the term "contact" or "in contact with..." refers to direct connection (i.e., physical contact) unless the context indicates otherwise. In some embodiments, among the logic cells LC forming one of the first to sixth rows R1, R2, R3, R4, R5, and R6, two logic cells LC adjacent to each other in the first horizontal direction (X direction) may be spaced apart from each other.

[0029] In an embodiment, among the logic cells LC forming one of the first to sixth rows R1, R2, R3, R4, R5, and R6, two adjacent logic cells LC may have the same structure and perform the same function. In some embodiments, among the logic cells LC forming one of the first to sixth rows R1, R2, R3, R4, R5, and R6, two adjacent logic cells LC may perform different functions.

[0030] In some embodiments, among the logic cells LC of the unit block 12 of the integrated circuit device 10, two logic cells LC adjacent to each other in the second horizontal direction (Y direction) may have a symmetrical structure with respect to a cell contact portion CBC between the two logic cells LC. For example, the reference logic cell LC_R in the third row R3 and the lower logic cell LC_L in the second row R2 may have a symmetrical structure with respect to a cell contact portion CBC therebetween. The reference logic cell LC_R in the third row R3 and the upper logic cell LC_H in the fourth row R4 may have a symmetrical structure with respect to a cell contact portion CBC therebetween.

[0031] exist Figure 1 In the embodiment, the cell block 12 may include six rows, namely, the first to sixth rows R1, R2, R3, R4, R5 and R6. The present disclosure is not limited thereto. In some embodiments, the cell block 12 may include various numbers of rows and each row may include various numbers of logic cells to achieve the desired function.

[0032] One of a plurality of ground lines VSS and a power line VDD may be arranged between two adjacent rows among the first to sixth rows R1, R2, R3, R4, R5, and R6, and each of the first to sixth rows R1, R2, R3, R4, R5, and R6 includes a plurality of logic cells LC arranged along a line extending in a first horizontal direction (X direction). The ground line VSS and the power line VDD may extend in the first horizontal direction (X direction), and may be alternately arranged and separated from each other in a second horizontal direction (Y direction). Therefore, each of the ground line VSS and the power line VDD may overlap a cell boundary CBD of the logic cell LC arranged in the second horizontal direction (Y direction).

[0033] Figure 2 is a diagram illustrating a layout of an integrated circuit device 100 according to some embodiments. FIG. 3A to FIG. 3C is a cross-sectional view illustrating an integrated circuit device 100 according to some embodiments. Figure 4 is an enlarged cross-sectional view illustrating an integrated circuit device 100 according to some embodiments. Figure 3A It is along Figure 2 A cross-sectional view taken along line X1-X1 in FIG. Figure 3B It is along Figure 2 A cross-sectional view taken along line Y1-Y1 in FIG. Figure 3C It is along Figure 2 A cross-sectional view taken along line Y2-Y2 in FIG. Figure 4 yes Figure 3A An enlarged cross-sectional view of area EX1 in FIG.

[0034] Refer to the following Figures 2 to 4 An integrated circuit device 100 is described that includes a field effect transistor with a fully surrounding gate, which includes an active region having a nanowire or nanosheet shape and a gate surrounding the active region. The integrated circuit device 100 may be formed Figure 1 Some of the logic cells LC in.

[0035] The integrated circuit device 100 may include a substrate 102 having a first surface 102_1 (i.e., upper surface) and a second surface 102_2 (i.e., lower surface) and a plurality of fin-type active areas FA protruding from the first surface 102_1 of the substrate 102. The fin-type active areas FA may longitudinally extend along a first horizontal direction (X direction) on the substrate 102 to be parallel to each other.

[0036] The substrate 102 may include a semiconductor material such as Si and Ge or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, and InP, or may be formed of the semiconductor material or the compound semiconductor. Each of the terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" used herein indicates a material composed of the elements included in each term, and is not a chemical formula representing a stoichiometric relationship. The substrate 102 may include a conductive region such as a well of a doped substance or a structure of a doped substance.

[0037] The isolation film 112 may be in a trench isolation structure defining the fin-type active area FA. The isolation film 112 may cover a portion of the sidewall of each fin-type active area FA. The isolation film 112 may be connected to the upper surface of the substrate 102, such as Figure 3B As shown. The present disclosure is not limited thereto. In some embodiments, the isolation film 112 may be spaced apart from the substrate 102 in a vertical direction (Z direction). The vertical direction may be perpendicular to the first surface 102_1 of the substrate 102. The isolation film 112 may include or may be a silicon oxide film. The isolation film 112 may include a material having an etching selectivity relative to a material of the substrate 102.

[0038] like Figure 2 , Figure 3A and Figure 3C As shown, a plurality of gate lines 160 may be disposed on the fin-type active area FA. Each gate line 160 may extend longitudinally in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). Each of the plurality of nanosheet stacks NSS may be disposed above the fin top FT (i.e., top surface) of the fin-type active area FA at the intersection of the fin-type active area FA and one of the gate lines 160. Each nanosheet stack NSS may include at least one nanosheet, the at least one nanosheet facing the fin top FT of the fin-type active area FA or adjacent to the fin top FT of the fin-type active area FA at a position separated from the fin top FT of the fin-type active area FA in a vertical direction (Z direction). It will be understood that the nanosheet includes a nanowire.

[0039] like Figure 3A and Figure 3C As shown, each nanosheet stack NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 that overlap each other in a vertical direction (Z direction) above the fin-type active area FA. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different vertical distances (Z direction distances) from the fin top FT of the fin-type active area FA. Each gate line 160 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 of the nanosheet stack NSS that overlap each other in a vertical direction (Z direction).

[0040] Although the planar shape of the nanosheet stack NSS is Figure 2 The nanosheet stack NSS is substantially rectangular in shape, but the embodiment is not limited thereto. The nanosheet stack NSS may have various planar shapes according to the planar shape of each of the fin-type active area FA and the gate line 160. The present embodiment shows a configuration in which a plurality of gate lines 160 are arranged on one fin-type active area FA and the nanosheet stack NSS is arranged in a row along a first horizontal direction (X direction) on the one fin-type active area FA. For example, the nanosheet stack NSS may be disposed on the upper surface of the fin-type active area FA and may extend longitudinally along the extension direction (e.g., the first horizontal direction) of the fin-type active area FA. There is no particular limitation on the number of nanosheet stacks NSS and gate lines 160 arranged on one fin-type active area FA.

[0041] Each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 of the nanosheet stack NSS can be used as a channel region. In some embodiments, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 can have a thickness selected from, but not limited to, a range of from about 4 nm to about 6 nm. The thickness of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 refers to the size in the vertical direction (Z direction). In some embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 can have substantially the same thickness as each other in the vertical direction (Z direction). In some embodiments, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 can have a different thickness from other nanosheets in the vertical direction (Z direction). In some embodiments, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 of the nanosheet stack NSS can include a Si layer, a SiGe layer, or a combination thereof, or can be formed by a Si layer, a SiGe layer, or a combination thereof.

[0042] like Figure 3A As shown, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 of a nanosheet stack NSS may have the same or similar size in the first horizontal direction (X direction). Figure 3A Differently, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 of a nanosheet stack NSS may have a size different from that of other nanosheets in the first horizontal direction (X direction). Each nanosheet stack NSS includes three nanosheets. The present disclosure is not limited thereto. For example, the nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets forming the nanosheet stack NSS is not particularly limited.

[0043] like Figure 3A and Figure 3CAs shown, each gate line 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M may extend longitudinally in a second horizontal direction (Y direction) to cover the top surface of the nanosheet stack NSS. The sub-gate portion 160S may be integrally connected to the main gate portion 160M and respectively between the third nanosheet N3 and the second nanosheet N2, between the second nanosheet N2 and the first nanosheet N1, and between the first nanosheet N1 and the fin-type active area FA. In the vertical direction (Z direction), the thickness of each sub-gate portion 160S may be less than the thickness of the main gate portion 160M.

[0044] Each gate line 160 may include a metal, a metal nitride, a metal carbide, or a combination thereof, or may be formed of a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may include TiAlC. However, the material of the gate line 160 is not limited to the above materials.

[0045] like Figure 3A and Figure 3B As shown, a plurality of first recesses R1 may be formed in the fin type active area FA. A vertical level of a bottommost surface of each first recess R1 may be lower than a vertical level of a fin top FT of the fin type active area FA.

[0046] like Figure 3A and Figure 3B As shown, a plurality of source / drain regions 130 may be respectively arranged in the first recess R1. Each source / drain region 130 may be adjacent to at least one of the gate lines 160. Each source / drain region 130 may have surfaces respectively facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the corresponding nanosheet stack NSS adjacent to each source / drain region 130. For example, each source / drain region 130 may have side surfaces adjacent to the first nanosheet N1 to the third nanosheet N3 of the corresponding nanosheet stack NSS. Each source / drain region 130 may contact the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS adjacent to each source / drain region 130.

[0047] The gate dielectric film 152 may be disposed in the space between the nanosheet stack NSS and the gate line 160. In some embodiments, the gate dielectric film 152 may include a stacked structure of an interface dielectric film and a high-k dielectric film. The interface dielectric film may include a low-k dielectric film (e.g., a silicon oxide film, a silicon oxynitride film, or a combination thereof) having a permittivity of about 9 or less, or may be formed by the low-k dielectric film. In some embodiments, the interface dielectric film may be omitted. The high-k dielectric film may include a material having a higher dielectric constant than the silicon oxide film, or may be formed by the material. For example, the high-k dielectric film may have a dielectric constant of about 10 to about 25. The high-k dielectric film may include hafnium oxide or may be formed by hafnium oxide, but is not limited thereto.

[0048] like Figure 3A and Figure 3C As shown, a top surface of each of the gate dielectric film 152 and the gate line 160 may be covered by a capping insulating pattern 168. The capping insulating pattern 168 may include or may be a silicon nitride film.

[0049] The opposite sidewalls of each of the gate line 160 and the capping insulating pattern 168 may be covered by the outer insulating spacer 118, respectively. The outer insulating spacer 118 may be disposed over the top surface of the nanosheet stack NSS to cover the opposite sidewalls of the main gate portion 160M, respectively. The outer insulating spacer 118 may be separated from the gate line 160 by the gate dielectric film 152.

[0050] like Figure 3B As shown, a plurality of recessed insulating spacers 119 may be disposed on the top surface of the isolation film 112 to respectively cover sidewalls of the source / drain regions 130. In some embodiments, each recessed insulating spacer 119 may be integrally connected to an outer insulating spacer 118 adjacent to each recessed insulating spacer 119.

[0051] The outer insulating spacer 118 and the recessed insulating spacer 119 may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof, or may be formed of silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. Each of the terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein indicates a material composed of the elements included in each term, and is not a chemical formula representing a stoichiometric relationship.

[0052] The first metal silicide film 172 may be disposed on the top surface of some of the source / drain regions 130. The first metal silicide film 172 may include a metal including Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd, or may be formed of the metal. For example, the first metal silicide film 172 may include titanium silicide or may be formed of titanium silicide, but is not limited thereto.

[0053] A plurality of source / drain regions 130, a plurality of first metal silicide films 172, and a plurality of outer insulating spacers 118 may be disposed on the substrate 102 and may be covered by an insulating liner 142. In some embodiments, the insulating liner 142 may be omitted. An inter-gate insulating film 144 may be disposed on the insulating liner 142. When the insulating liner 142 is omitted, the inter-gate insulating film 144 may be in contact with the source / drain regions 130.

[0054] The insulating liner 142 and the inter-gate insulating film 144 may be sequentially arranged on the source / drain region 130 and the first metal silicide film 172. The insulating liner 142 and the inter-gate insulating film 144 may form an insulating structure. In some embodiments, the insulating liner 142 may include silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, or may be formed of silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but is not limited to these materials. The inter-gate insulating film 144 may include or may be a silicon oxide film, but is not limited thereto.

[0055] Each of the opposite sidewalls of each sub-gate portion 160S of each gate line 160 may be separated from one of the source / drain regions 130 by a gate dielectric film 152. The gate dielectric film 152 may be disposed in a space between each sub-gate portion 160S of each gate line 160 and one of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and between the sub-gate portion 160S of the gate line 160 and the source / drain region 130.

[0056] Each nanosheet stack NSS may be disposed above a fin top FT of the fin active area FA where the fin active area FA intersects one of the gate lines 160, and may face or be adjacent to the fin top FT of the fin active area FA at a position separated from the fin active area FA. A plurality of nanosheet transistors may be formed above the substrate 102 where the fin active area FA intersects the gate line 160.

[0057] like Figure 3A and Figure 3BAs shown, the active contact CA may be disposed on the source / drain region 130. The active contact CA may pass through the inter-gate insulating film 144 and the insulating liner 142 in the vertical direction (Z direction), and may contact the first metal silicide film 172. The active contact CA may be electrically connected to the source / drain region 130 through the first metal silicide film 172.

[0058] The active contact CA may include a conductive barrier pattern 174 and a contact plug 176 sequentially stacked on the source / drain region 130. The conductive barrier pattern 174 may surround the bottom surface and the sidewall of the contact plug 176 and may be in contact with the bottom surface and the sidewall of the contact plug 176. The active contact CA may extend longitudinally in the vertical direction (Z direction) through the inter-gate insulating film 144 and the insulating liner 142. The conductive barrier pattern 174 may be disposed in a space between the first metal silicide film 172 and the contact plug 176. The conductive barrier pattern 174 may have a surface in contact with the first metal silicide film 172 and a surface in contact with the contact plug 176. In some embodiments, the conductive barrier pattern 174 may include a metal or a metal nitride, or may be formed of a metal or a metal nitride. For example, the conductive barrier pattern 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, or may be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited to these materials. The contact plug 176 may include molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), or a combination thereof, or may be formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), or a combination thereof, but is not limited to these materials.

[0059] like FIG. 3A to FIG. 3CAs shown, the top surfaces of the active contact CA, the cap insulating pattern 168, and the inter-gate insulating film 144 may be covered by an upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184 sequentially stacked on the active contact CA, the cap insulating pattern 168, and the inter-gate insulating film 144. The etch stop film 182 may include silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof, or may be formed of silicon carbide (SiC), silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating film 184 may include or may be an oxide film, a nitride film, an ultra-low-k (ULK) film having an ultra-low dielectric constant k of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating film 184 may include tetraethyl orthosilicate (TEOS) film, high-density plasma (HDP) oxide film, borophosphosilicate glass (BPSG) film, flowable chemical vapor deposition (FCVD) oxide film, SiON film, SiN film, SiOC film, SiCOH film or a combination thereof, or may be formed of TEOS film, HDP oxide film, BPSG film, FCVD oxide film, SiON film, SiN film, SiOC film, SiCOH film or a combination thereof, but is not limited to these materials.

[0060] like Figure 3A and Figure 3B As shown, the via contact VA may be disposed on the active contact CA. The via contact VA may pass through the upper insulating structure 180 and may contact the active contact CA. The source / drain region 130 may be electrically connected to the via contact VA through the first metal silicide film 172 and the active contact CA. The bottom surface of the via contact VA may contact the top surface of the active contact CA. The via contact VA may include W, Mo and / or Ru, or may be formed of W, Mo and / or Ru, but is not limited to these materials.

[0061] The interconnection line M1 may pass through the upper insulating film 192. The interconnection line M1 may be connected to the via contact VA thereunder. In some embodiments, the interconnection line M1 may extend in the first horizontal direction (X direction). The interconnection line M1 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, or a combination thereof, or may be formed of Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, or a combination thereof, but is not limited to these materials.

[0062] like Figure 3A and Figure 3BAs shown, the back contact BC may pass through the substrate 102 and may contact the source / drain region 130. The back contact BC may pass through the substrate 102 and the fin-type active area FA in the vertical direction (Z direction), and may contact the second metal silicide film 171. The back contact BC may be electrically connected to the source / drain region 130 through the second metal silicide film 171. In some embodiments, the back contact BC may extend from the second surface 102_2 of the substrate toward the lower portion of the source / drain region 130. The second metal silicide film 171 may be disposed in a space between the lower portion of the source / drain region 130 and the upper portion of the back contact BC. The upper portion of the back contact BC may contact the second metal silicide film 171 and may be connected to the source / drain region 130.

[0063] The back contact BC may include a barrier pattern 173 and a conductive plug 175 sequentially stacked. The barrier pattern 173 may surround the sidewall and top surface of the conductive plug 175 and may be in contact with the sidewall and top surface of the conductive plug 175. The barrier pattern 173 may be between the second metal silicide film 171 and the conductive plug 175. The barrier pattern 173 may have a surface in contact with the second metal silicide film 171 and a surface in contact with the conductive plug 175.

[0064] In some embodiments, the barrier pattern 173 may include or may be formed of a metal or a metal nitride. For example, the barrier pattern 173 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, or may be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited to these materials. The contact plug 175 may include Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, or a combination thereof, or may be formed of Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, or a combination thereof, but is not limited to these materials.

[0065] The high-concentration doped layer 177 may be disposed in a space between the source / drain region 130 and the back contact BC. The back contact BC may be inserted into the source / drain region 130. The high-concentration doped layer 177 may be disposed in a space between an inserted portion (i.e., an upper portion) of the back contact BC and the source / drain region 130. In some embodiments, the high-concentration doped layer 177 may correspond to a lower portion of the source / drain region 130 that is doped at a higher concentration than other portions of the source / drain region 130. Figure 4 The high-concentration doping layer 177 is described in detail.

[0066] In some embodiments, the second metal silicide film 171 may be disposed in a space between the high-concentration doped layer 177 and the back contact BC (e.g., the upper portion of the back contact BC). The second metal silicide film 171 may be in contact with the high-concentration doped layer 177. The second metal silicide film 171 may include a metal including Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd, or may be formed of the metal. For example, the second metal silicide film 171 may include titanium silicide or may be formed of titanium silicide, but is not limited thereto.

[0067] Reference Figure 4 , between the insertion portion of the back contact BC (i.e., the upper portion of the back contact BC) and the source / drain region 130, a second metal silicide film 171 and a high-concentration doping layer 177 may be sequentially arranged. The second metal silicide film 171 may be disposed between the back contact BC and the high-concentration doping layer 177, and may be in contact with the high-concentration doping layer 177. The second metal silicide film 171 and the high-concentration doping layer 177 may conformally cover the top surface of the upper portion of the back contact BC. The second metal silicide film 171 and the high-concentration doping layer 177 may have a convex shape that enters the source / drain region 130. In some embodiments, the high-concentration doping layer 177 may correspond to the lower portion of the source / drain region 130, and the second metal silicide film 171 may be disposed in the space between the upper portion of the back contact BC and the high-concentration doping layer 177.

[0068] In some embodiments, the source / drain region 130 may include a first semiconductor layer 130_1 and a second semiconductor layer 130_2 stacked in sequence. The first semiconductor layer 130_1 may be disposed on the bottom surface of the first recess R1 and may contact the fin-type active region FA and the channel region. The second semiconductor layer 130_2 may be disposed on the first semiconductor layer 130_1 and may completely fill the first recess R1. For example, the first semiconductor layer 130_1 and the second semiconductor layer 130_2 may contact the high-concentration doped layer 177.

[0069] In the source / drain region 130, each of the first semiconductor layer 130_1 and the second semiconductor layer 130_2 may include or may be Si doped with a p-type dopant. 1-x Ge x Layer, where x is a positive fraction greater than 0. The Ge content in the first semiconductor layer 130_1 may be less than the Ge content in the second semiconductor layer 130_2.

[0070] For example, the Ge content in the first semiconductor layer 130_1 may be greater than 0 at % and less than about 10 at %, and the Ge content in the second semiconductor layer 130_2 may be greater than about 45 at % and less than about 60 at %.

[0071] In some embodiments, the p-type dopant concentration in the first semiconductor layer 130_1 may be less than the p-type dopant concentration in the second semiconductor layer 130_2. For example, the p-type dopant concentration in the first semiconductor layer 130_1 may be about 1×10 18 atom / cm 3 About 1×10 19 atom / cm 3 The p-type dopant concentration in the second semiconductor layer 130_2 may be approximately 1×10 20 atom / cm 3 About 5×10 20 atom / cm 3 .

[0072] The p-type dopant included in the source / drain regions 130 may include, but is not limited to, boron (B), gallium (Ga), carbon (C), or a combination thereof.

[0073] In some embodiments, the high concentration doping layer 177 may include Si doped with a p-type dopant. 1-x Ge x layer, wherein x is a positive fraction greater than 0. For example, the Ge content in the high-concentration doping layer 177 may be about 45 at % to about 70 at %.

[0074] In an embodiment, the high-concentration doping layer 177 may have a p-type dopant concentration greater than that of the source / drain region 130. For example, the high-concentration doping layer 177 may have a p-type dopant concentration greater than that of the first semiconductor layer 130_1 and the second semiconductor layer 130_2. For example, the p-type dopant concentration in the high-concentration doping layer 177 may be about 5×10 20 atom / cm 3 About 1×10 22 atom / cm 3 .

[0075] In some embodiments, the p-type dopant included in the high-concentration doping layer 177 may include, but is not limited to, boron (B), gallium (Ga), carbon (C), or a combination thereof.

[0076] When the integrated circuit device 100 includes a high-concentration doping layer 177 that contacts the second metal silicide film 171 and has a greater dopant concentration than the source / drain region 130 (e.g., the first semiconductor layer 130_1 and the second semiconductor layer 130_2), the contact resistance between the source / drain region 130 and the back contact BC can be reduced. For example, since the high-concentration doping layer 177 has a greater dopant concentration than the source / drain region 130, the resistance of the back contact BC can be reduced by reducing the Schottky barrier at the interface between the second metal silicide film 171 and the high-concentration doping layer 177.

[0077] In some embodiments, the high-concentration doping layer 177 may further include a Ga dopant. For example, the Ga dopant concentration in the high-concentration doping layer 177 may be lower than the p-type dopant concentration in the high-concentration doping layer 177. For example, the high-concentration doping layer 177 may further include a Ga dopant having a concentration lower than that of the p-type dopant.

[0078] According to the present disclosure, since the high-concentration doping layer 177 of the integrated circuit device 100 further includes Ga dopants, the high-concentration doping layer 177 can further provide an anti-diffusion effect. For example, since the high-concentration doping layer 177 further includes Ga dopants having a size larger than that of B dopants, diffusion of Ga dopants in the high-concentration doping layer 177 can be prevented.

[0079] In some embodiments, the high concentration doping layer 177 of the integrated circuit device 100 may have a Ge content greater than or equal to the Ge content in the source / drain region 130. For example, the Ge content in the high concentration doping layer 177 may be about 45 at% to about 70 at%. In some embodiments, the high concentration doping layer 177 of the integrated circuit device 100 may include more Ge (whose size is larger than Si) content than the source / drain region 130, thereby further providing a stress enhancement effect. For example, the high concentration doping layer 177 with a higher Ge content may apply stress (e.g., compressive stress) to the first to third nanosheets N1, N2, and N3, thereby increasing the mobility of holes when the nanosheets are used as channel regions of p-type MOS transistors. Therefore, the channel resistance characteristics may be improved.

[0080] Figures 2 to 4 An integrated circuit device 100 having improved performance and reliability may be disclosed.

[0081] FIG. 5A to FIG. 5C 1 is an enlarged cross-sectional view showing integrated circuit devices 100A, 100B, and 100C according to some embodiments. The integrated circuit devices 100A, 100B, and 100C are described below, focusing on the above referenced Figures 2 to 4 The differences in the integrated circuit device 100 are described.

[0082] Reference Figure 5A , the integrated circuit device 100A may include a high concentration doping layer 177A between the source / drain region 130 and the back contact BCA. The back contact BCA may include a barrier pattern 173A and a conductive plug 175A stacked in sequence. The integrated circuit device 100A may further include a second silicide film 171A between the high concentration doping layer 177A and the back contact BCA. The second silicide film 171A may be in contact with the high concentration doping layer 177A.

[0083] In an embodiment, the high-concentration doping layer 177A may have a pointed shape. For example, the boundary between the high-concentration doping layer 177A and the source / drain region 130 may have a triangular shape. In order to form the pointed shape of the high-concentration doping layer 177A, the etching conditions may be adjusted in the process of etching a portion of the source / drain region 130 to form the high-concentration doping layer 177A. For example, the pointed shape of the high-concentration doping layer 177A may be formed by adjusting the etching rate according to the crystal plane.

[0084] exist Figure 5A In the embodiment, the top surface of each of the back contact BCA and the second silicide film 171A disposed on the high-concentration doping layer 177A has a triangular shape. The shape of the top surface of each of the second silicide film 171A and the back contact BCA is not limited thereto. For example, the second silicide film 171A and the back contact BCA may each conformally cover the high-concentration doping layer 177A.

[0085] Reference Figure 5B , the integrated circuit device 100B may include a high concentration doping layer 177B between the source / drain region 130 and the back contact BCB. The back contact BCB may include a barrier pattern 173B and a conductive plug 175B stacked in sequence. The integrated circuit device 100B may further include a second silicide film 171B between the high concentration doping layer 177B and the back contact BCB. The second silicide film 171B may be in contact with the high concentration doping layer 177B.

[0086] In some embodiments, the high-concentration doping layer 177B may have a trapezoidal shape. For example, a boundary between the high-concentration doping layer 177B and the source / drain region 130 may have a trapezoidal shape.

[0087] Reference Figure 5C, the integrated circuit device 100C may include a high-concentration doped layer 177C between the source / drain region 130 and the back contact BCC. The back contact BCC may include a barrier pattern 173C and a conductive plug 175C stacked in sequence. The integrated circuit device 100C may further include a second silicide film 171C between the high-concentration doped layer 177C and the back contact BCC. The second silicide film 171C may be in contact with the high-concentration doped layer 177C.

[0088] In some embodiments, the high-concentration doped layer 177C may overlap the gate line 160 in the first horizontal direction (X direction). Figures 2 to 4 Compared with the high concentration doping layer 177 of the integrated circuit device 100 described above, the back contact BCC may be further inserted into the source / drain region 130 so that the high concentration doping layer 177C may be arranged to overlap the gate line 160 in the first horizontal direction (X direction).

[0089] Figure 6 and Figure 7 1 and 100_2 according to some embodiments. The following describes the integrated circuit devices 100_1 and 100_2, focusing on the above referenced Figures 2 to 4 The differences in the integrated circuit device 100 are described.

[0090] Reference Figure 6 , the integrated circuit device 100_1 may include a high concentration doping layer 177_1 between the source / drain region 130 and the back contact BC. The integrated circuit device 100_1 may include a second metal silicide film 171 between the high concentration doping layer 177_1 and the back contact BC. The second metal silicide film 171 may contact the high concentration doping layer 177_1.

[0091] In some embodiments, the high-concentration doping layer 177_1 may have a stacked structure of a first sub-high-concentration doping layer 177_S1 and a second sub-high-concentration doping layer 177_S2. Each of the first sub-high-concentration doping layer 177_S1 and the second sub-high-concentration doping layer 177_S2 may include Si doped with a p-type dopant. 1-x Ge x Layer, where x is a positive fraction greater than 0.

[0092] In some embodiments, the first sub-high-concentration doping layer 177_S1 and the second sub-high-concentration doping layer 177_S2 may be different in at least one item selected from the group consisting of Ge content, the type of p-type dopant, and the concentration of the p-type dopant. For example, the first sub-high-concentration doping layer 177_S1 and the second sub-high-concentration doping layer 177_S2 may each include a B dopant (i.e., a boron dopant), but may have different concentrations of B dopant. For example, the first sub-high-concentration doping layer 177_S1 may include a B dopant, and the second sub-high-concentration doping layer 177_S2 may include a B dopant and a Ga dopant (i.e., a gallium dopant).

[0093] Reference Figure 7 , the integrated circuit device 100_2 may include a high concentration doping layer 177_2 between the source / drain region 130 and the back contact BC. The integrated circuit device 100_2 may include a second metal silicide film 171 between the high concentration doping layer 177_2 and the back contact BC. The second metal silicide film 171 may contact the high concentration doping layer 177_2.

[0094] In some embodiments, the high concentration doping layer 177_2 may contact the source / drain region 130 . For example, the high concentration doping layer 177_2 may contact the first semiconductor layer 130_1 of the source / drain region 130 but not the second semiconductor layer 130_2 of the source / drain region 130 .

[0095] Figure 8 1 is a cross-sectional view showing an integrated circuit device 100_3 according to some embodiments. The integrated circuit device 100_3 is described below, focusing on the integrated circuit device 100_3 as described above with reference to FIG. Figures 2 to 4 The differences in the integrated circuit device 100 are described.

[0096] Reference Figure 8 , the integrated circuit device 100_3 may include an insulating layer 110 and a back contact BC penetrating the insulating layer 110 and connected to the source / drain region 130. The insulating layer 110 of the integrated circuit device 100_3 may be formed by completely removing the semiconductor material of the substrate 102 and the fin-type active area FA of the integrated circuit device 100 and replacing the semiconductor material with an insulating material. For example, the insulating layer 110 may include the same material as the isolation film 112, or may be formed of the same material as the isolation film 112. For example, the insulating material 110 may include a material different from the isolation film 112, or may be formed of a material different from the isolation film 112. The insulating material 110 may include a material selected from silicon oxide (SiO 2), at least one of the group consisting of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxycarbide (SiOC) and silicon oxycarbon nitride (SiOCN), or can be formed by at least one of the above.

[0097] Fig. 9 is a cross-sectional view illustrating an integrated circuit device 200 according to some embodiments. Fig.10 is an enlarged cross-sectional view illustrating an integrated circuit device 200 according to some embodiments. Fig.10 yes Fig. 9 The following describes the integrated circuit device 200, focusing on the above referenced Figures 2 to 4 The differences in the integrated circuit device 100 are described.

[0098] Reference Fig. 9 and Fig.10 , the integrated circuit device 200 may include a substrate 202 and a fin-type active area FA protruding from the substrate 202 and extending in a first horizontal direction (X direction). A gate line 260 may be disposed above the fin-type active area FA and may extend in a second horizontal direction (Y direction). A nanosheet stack NSS including a plurality of nanosheets (e.g., first to third nanosheets N1, N2, and N3) may be disposed above a fin top FT of the fin-type active area FA. The gate line 260 may include a main gate portion 260M and a plurality of sub-gate portions 260S.

[0099] In some embodiments, a plurality of source / drain regions 230 may be disposed on the fin-type active region FA and arranged between the plurality of gate lines 260, such that each source / drain region 230 may have a surface facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the corresponding nanosheet stack NSS adjacent to each source / drain region 230. For example, each source / drain region 230 may have a side surface adjacent to the first nanosheet N1 to the third nanosheet N3 of the corresponding nanosheet stack NSS.

[0100] In some embodiments, the source / drain region 230 may include a first semiconductor layer 230_1 and a second semiconductor layer 230_2 stacked in sequence. The first semiconductor layer 230_1 may be in contact with the fin-type active region FA and the channel region. The second semiconductor layer 230_2 may be disposed on the first semiconductor layer 230_1. In some embodiments, the first semiconductor layer 230_1 may be disposed in a space between a side surface of the nanosheet stack NSS and the second semiconductor layer 230_2.

[0101] In the source / drain region 230 , each of the first semiconductor layer 230_1 and the second semiconductor layer 230_2 may include or may be formed of a Si layer doped with an n-type dopant.

[0102] In some embodiments, the n-type dopant concentration in the first semiconductor layer 230_1 may be less than the n-type dopant concentration in the second semiconductor layer 230_2. For example, the n-type dopant concentration in the first semiconductor layer 230_1 may be less than 10 21 atom / cm 3 The n-type dopant concentration in the second semiconductor layer 230_2 may be about 10 21 atom / cm 3 to about 10 22 atom / cm 3 .

[0103] The n-type dopant included in the source / drain regions 230 may include, but is not limited to, phosphorus (P), arsenic (As), or a combination thereof.

[0104] In some embodiments, the back contact BC may penetrate the substrate 202 and enter the source / drain region 230. In some embodiments, the back contact BC may extend from the lower surface of the substrate 202 toward the lower portion of the source / drain region 230. The back contact BC may include a barrier pattern 273 and a conductive plug 275 stacked in sequence. A high-concentration doped layer 277 may be between the back contact BC and the source / drain region 230. The high-concentration doped layer 277 may contact the first semiconductor layer 230_1 and the second semiconductor layer 230_2.

[0105] In some embodiments, the high-concentration doping layer 277 may include a Si layer doped with an n-type dopant, or may be formed of a Si layer doped with an n-type dopant. In some embodiments, the high-concentration doping layer 277 may correspond to a lower portion of the source / drain region 230, which is doped at a higher concentration than other regions of the source / drain region 230. The high-concentration doping layer 277 may have a greater n-type dopant concentration than the source / drain region 230. For example, the high-concentration doping layer 277 has a greater n-type dopant concentration than the first semiconductor layer 230_1 and the second semiconductor layer 230_2. For example, the n-type dopant concentration in the high-concentration doping layer 277 may be about 1.5×10 21 atom / cm 3 About 1×10 22 atom / cm 3 .

[0106] The n-type dopant included in the high-concentration doping layer 277 may include, but is not limited to, P, As, or a combination thereof.

[0107] For example, the high-concentration doping layer 277 may include SiP, and the P dopant concentration in the high-concentration doping layer 277 may be about 1.5×10 21 atom / cm 3 About 1×10 22 atom / cm 3 For example, the high-concentration doping layer 277 may include SiAs, and the As dopant concentration in the high-concentration doping layer 277 may be about 1.5×10 21 atom / cm 3 About 1×10 22 atom / cm 3 For example, the high-concentration doping layer 277 may include SiAsP, and the sum of the As dopant concentration and the P dopant concentration in the high-concentration doping layer 277 may be about 1.5×10 21 atom / cm 3 About 1×10 22 atom / cm 3 .

[0108] In some embodiments, the second silicide film 271 may be between the back contact BC and the high-concentration doping layer 277 , and may be in contact with the high-concentration doping layer 277 .

[0109] Figures 11 to 13 is a cross-sectional view illustrating integrated circuit devices 300 , 301 , and 302 according to some embodiments.

[0110] Reference Fig.11 , the integrated circuit device 300 may include a first region A1 in which a first source / drain region 331 is disposed and a second region A2 in which a second source / drain region 332 is disposed. In some embodiments, the first source / drain region 331 may correspond to a P-channel metal oxide semiconductor (PMOS) source / drain region. The second source / drain region 332 may correspond to an N-channel MOS (NMOS) source / drain region. In embodiments, the description of the elements of the first region A1 may refer to Figures 2 to 4 In the embodiment, for the description of the components of the second area A2, reference may be made to Fig. 9 and Fig.10 Components of the integrated circuit device 200 are described below.

[0111] In the first region A1, a first high-concentration doped layer 377 may be disposed in a space between the first source / drain region 331 and the first back contact BC1. The first high-concentration doped layer 377 may have a greater p-type dopant concentration than the first source / drain region 331. The second silicide film 371 may be disposed in a space between the first high-concentration doped layer 377 and the first back contact BC1, and may contact the first high-concentration doped layer 377. The first back contact BC1 may include a barrier pattern 373 and a conductive plug 375 sequentially stacked.

[0112] The first source / drain region 331 may include Si doped with a p-type dopant. 1-x Ge x layer, or can be made of Si doped with p-type dopants 1-x Ge x The first high-concentration doped layer 377 may have a p-type dopant concentration greater than that of the first source / drain region 331. For the description of the first source / drain region 331 and the first high-concentration doped layer 377, reference may be made to Figures 2 to 4 1 is a description of the source / drain region 130 and the high-concentration doped layer 177 of the integrated circuit device 100 .

[0113] In the second region A2, the second high-concentration doped layer 378 may be disposed in a space between the second source / drain region 332 and the second back contact BC2. The second high-concentration doped layer 378 may have a greater n-type dopant concentration than the second source / drain region 332. The second silicide film 371 may be disposed in a space between the second high-concentration doped layer 378 and the second back contact BC2, and may be in contact with the second high-concentration doped layer 378.

[0114] The second source / drain region 332 may include a Si layer doped with an n-type dopant, or may be formed of a Si layer doped with an n-type dopant. The second high-concentration doped layer 378 may have a greater n-type dopant concentration than the second source / drain region 332. For a description of the second source / drain region 332 and the second high-concentration doped layer 378, reference may be made to Fig. 9 and Fig.10 1 and 2. The source / drain regions 230 and the high-concentration doped layer 277 of the integrated circuit device 200 are described below.

[0115] Reference Fig.12 , the integrated circuit device 301 may include a first region A1 in which a first source / drain region 331 is arranged and a second region A2 in which a second source / drain region 332 is arranged.

[0116] In the first region A1, a first high-concentration doped layer 377 may be disposed in a space between the first source / drain region 331 and the first back contact BC1. The first high-concentration doped layer 377 may have a greater p-type dopant concentration than the first source / drain region 331. The second silicide film 371 may be disposed in a space between the first high-concentration doped layer 377 and the first back contact BC1, and may contact the first high-concentration doped layer 377.

[0117] Unlike the integrated circuit device 300, in the second region A2, the second high-concentration doping layer 378 may not exist between the second source / drain region 332 and the second back contact BC2. The second silicide film 371 may be disposed in a space between the second source / drain region 332 and the second back contact BC2, and may contact the second source / drain region 332.

[0118] Reference Fig.13 , the integrated circuit device 302 may include a first region A1 in which a first source / drain region 331 is arranged and a second region A2 in which a second source / drain region 332 is arranged.

[0119] Unlike the integrated circuit device 300, in the first region A1 of the integrated circuit device 302, the first high-concentration doping layer 377 may not exist between the first source / drain region 331 and the first back contact BC1. The second silicide film 371 may be disposed in a space between the first source / drain region 331 and the first back contact BC1 and may contact the first source / drain region 331.

[0120] In the second region A2 of the integrated circuit device 302, a second high-concentration doped layer 378 may be disposed in a space between the second source / drain region 332 and the second back contact BC2. The second high-concentration doped layer 378 may have a greater n-type dopant concentration than the second source / drain region 332. The second silicide film 371 may be disposed in a space between the second high-concentration doped layer 378 and the second back contact BC2, and may be in contact with the second high-concentration doped layer 378.

[0121] Figures 14 to 28 is a cross-sectional view of the integrated circuit device 100 , which illustrates process steps of a method of manufacturing the integrated circuit device 100 according to some embodiments.

[0122] Reference Fig.14 , a plurality of sacrificial semiconductor layers 103 and a plurality of nanosheet semiconductor layers NS may be alternately stacked on the substrate 102. The sacrificial semiconductor layers 103 may include or be formed of a semiconductor material having an etching selectivity relative to the semiconductor material of the nanosheet semiconductor layer NS.

[0123] Thereafter, a plurality of fin-type active areas FA extending in the first horizontal direction (X direction) may be formed by partially etching each of the sacrificial semiconductor layer 103, the nanosheet semiconductor layer NS, and the substrate 102. As a result, the first surface 102_1 of the substrate 102 may be formed, and the fin-type active area FA may be arranged on the first surface 102_1 of the substrate 102. In an embodiment, the fin-type active area FA may be formed using an epitaxial growth process in which the fin-type active area FA may be epitaxially grown from the first surface 102_1 of the substrate 102. The stacked structure of the sacrificial semiconductor layer 103 and the nanosheet semiconductor layer NS may remain on the fin top FT (i.e., top surface) of each fin-type active area FA.

[0124] Reference Fig.15 , a plurality of dummy gate structures DGS may be formed on the stacked structure of the sacrificial semiconductor layer 103 and the nanosheet semiconductor layer NS.

[0125] The dummy gate structure DGS may extend longitudinally in the second horizontal direction (Y direction). The dummy gate structures DGS may be spaced apart from each other in the first horizontal direction (X direction). Each dummy gate structure DGS may include an oxide film D122, a dummy gate layer D124, and a cap layer D126 stacked in sequence. In some embodiments, the dummy gate layer D124 may include or may be formed of polysilicon, and the cap layer D126 may include or may be a silicon nitride film.

[0126] Reference Fig.16 , outer insulating spacers 118 may be formed to cover opposite sidewalls of each dummy gate structure DGS, respectively. Thereafter, a portion of the sacrificial semiconductor layer 103 and a portion of the nanosheet semiconductor layer NS may be partially etched by using the dummy gate structure DGS and the outer insulating spacers 118 as etching masks. Thus, the nanosheet semiconductor layer NS may be divided into a plurality of nanosheet stacks NSS, each of which includes a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. The nanosheet stacks NSS may extend longitudinally in the second horizontal direction and may be spaced apart from each other in the first horizontal direction.

[0127] The plurality of first recesses R1 may be formed by the etching process as described above. To form the first recesses R1, dry etching, wet etching, or a combination thereof may be used.

[0128] Reference Fig.17, a plurality of source / drain regions 130 may be formed in the first recess R1, respectively. In some embodiments, the source / drain regions 130 may be formed by epitaxially growing a semiconductor material from a surface of the fin-type active area FA exposed at the bottom of the first recess R1, sidewalls of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in each nanosheet stack NSS, and a sidewall of the sacrificial semiconductor layer 103.

[0129] In an embodiment, in order to form the source / drain region 130, a first semiconductor layer 130_1 (in Figure 4 in) and the second semiconductor layer 130_2 (in Figure 4 middle).

[0130] Reference Fig.18 , an insulating liner 142 may be formed to cover Fig.17 The resulting structure including the source / drain regions 130 may be formed, and an inter-gate insulating film 144 may be formed on the insulating liner 142. Thereafter, the top surface of the cap layer D126 may be exposed by planarizing the insulating liner 142 and the inter-gate insulating film 144.

[0131] Thereafter, the top surface of the dummy gate layer D124 may be exposed by removing the cap layer D126. The insulating liner 142 and the inter-gate insulating film 144 may be partially removed so that the top surface of the inter-gate insulating film 144 may be substantially coplanar with the top surface of the dummy gate layer D124.

[0132] Reference Fig.19 , a main gate space GSM may be formed by removing the dummy gate layer D124 and the oxide film D122 under the dummy gate layer D124 , so that each nanosheet stack NSS may be exposed through the main gate space GSM.

[0133] Subsequently, by removing the sacrificial semiconductor layer 103 remaining on the fin type active area FA through the main gate space GSM, a sub gate space GSS may be formed between the first, second, and third nanosheets N1, N2, and N3 and the fin top FT of the fin type active area FA.

[0134] In some embodiments, the sacrificial semiconductor layer 103 having an etching selectivity with respect to the first nanosheet N1 , the second nanosheet N2 , and the third nanosheet N3 may be selectively removed.

[0135] Reference Fig. 20, a gate dielectric film 152 may be formed in the main gate space GSM and the sub-gate space GSS. The gate dielectric film 152 may be formed to cover the exposed surface of the third nanosheet N3 in the main gate space GSM. The gate dielectric film 152 may be formed to cover the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 in the sub-gate space GSS. The gate dielectric film 152 may be formed using atomic layer deposition (ALD).

[0136] Subsequently, a gate-forming conductive layer 160L may be formed on the gate dielectric film 152 to fill the main gate space GSM and the sub-gate space GSS and cover the top surface of the gate inter-insulating film 144. The gate-forming conductive layer 160L may include or be formed of a metal, a metal nitride, a metal carbide, or a combination thereof. The gate-forming conductive layer 160L may be formed using ALD or chemical vapor deposition (CVD).

[0137] Reference Fig.21 , the upper portion of the gate-forming conductive layer 160L may be removed to expose the top surface of the gate inter-insulating film 144 and clear the main gate space GSM (see Fig.19 As a result, a plurality of gate lines 160 may be formed from the gate forming conductive layer 160L.

[0138] During the time of removing the upper portion of the gate-forming conductive layer 160L filling the upper portion of the main gate space GSM, the upper portion of each of the gate dielectric film 152 and the outer insulating spacer 118 may be consumed in the main gate space GSM, and the height of each of the gate dielectric film 152 and the outer insulating spacer 118 may be reduced. Thereafter, a cap insulating pattern 168 may be formed on each gate line 160 to fill the main gate space GSM.

[0139] Reference Fig. 22, a source / drain contact hole may be formed through the insulating structure including the insulating liner 142 and the inter-gate insulating film 144 to expose one of the source / drain regions 130. Thereafter, by anisotropically etching the source / drain region 130 through the source / drain contact hole, the source / drain contact hole may be further extended toward the substrate 102. Thereafter, a first metal silicide film 172 may be formed on the exposed surface of the source / drain region 130 at the bottom of the source / drain contact hole. In some embodiments, the formation of the first metal silicide film 172 may include forming a metal liner (not shown) to conformally cover the exposed surface of the source / drain region 130, and inducing a reaction between the source / drain region 130 and the metal included in the metal liner by performing a heat treatment on the metal liner. After forming the first metal silicide film 172, the residue of the metal liner may be removed. During the process of forming the first metal silicide film 172, the source / drain region 130 may be partially consumed. In some embodiments, when the first metal silicide film 172 includes or is a titanium silicide film, the metal liner may include or be a Ti film.

[0140] Thereafter, an active contact CA including a conductive barrier pattern 174 and a contact plug 176 may be formed on the first metal silicide film 172 .

[0141] Reference Fig.23 , a back contact hole BCH may be formed through the substrate 102 and the fin type active area FA to connect to the source / drain region 130. In some embodiments, the process of forming the back contact hole BCH may include forming a placeholder (not shown) under the source / drain region 130 and using the placeholder as a mark.

[0142] Reference Fig.24 , the second recess R2 may be formed by further removing a portion of the source / drain region 130 through the back contact hole BCH. In some embodiments, the second recess R2 may be connected to the back contact hole BCH.

[0143] Reference Fig.25 , a high-concentration doping layer 177 may be formed at the source / drain region 130 exposed by the second recess R2. In an embodiment, the high-concentration doping layer 177 may have a p-type dopant concentration greater than that of the source / drain region 130. In some embodiments, a p-type dopant may be supplied to the source / drain region 130 via the second recess R2 and the back contact hole BCH, and the source / drain region 130 exposed by the second recess R2 may be doped with the p-type dopant. The doping region of the source / drain region 130 may be a high-concentration doping layer 177.

[0144] Reference Fig.26, a second metal silicide film 171 may be formed on the high concentration doping layer 177. The second metal silicide film 171 may be formed by a process similar to that of the first metal silicide film 172. In some embodiments, Fig.25 A portion of the high-concentration doped layer 177 may be converted into the second metal silicide film 171 by silicidation.

[0145] Reference Fig. 27 , a back side contact BC including a conductive barrier pattern 173 and a conductive plug 175 may be formed on the second metal silicide film 171 .

[0146] Reference Fig.28 , an upper insulating structure 180 may be formed on the inter-gate insulating film 144 and the active contact CA, and a via contact VA may be formed through the upper insulating structure 180 to be connected to the active contact CA. Subsequently, an upper insulating film 192 may be formed on the upper insulating structure 180 and the via contact VA, and an interconnection line M1 may be formed penetrating the upper insulating film 192. By the process described above, a Figures 2 to 4 An integrated circuit device 100.

[0147] Although the above reference Figures 14 to 28 Describes the manufacture as reference Figures 2 to 4 The method of the integrated circuit device 100 described above will be well appreciated by those skilled in the art. FIG. 5A to FIG. 13 The integrated circuit devices 100A, 100B, 100C, 100_1, 100_2, 100_3, 200, 300, 301 and 302 shown and other integrated circuit devices having various structures changed and modified from the integrated circuit devices 100A, 100B, 100C, 100_1, 100_2, 100_3, 200, 300, 301 and 302 can be implemented within the scope of the technical spirit of the present disclosure. Figures 14 to 28 Various changes and modifications can be made in the description.

[0148] While the present disclosure has been particularly shown and described with reference to certain embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: Providing a substrate having a fin-type active region, wherein the fin-type active region is disposed at a first surface of the substrate and extends in a first horizontal direction parallel to the first surface of the substrate; a plurality of nanosheets disposed on a top surface of the fin-type active region and separated from the top surface of the fin-type active region; A gate line disposed on the fin-type active region, the gate line surrounding each of the plurality of nanosheets and extending in a second horizontal direction intersecting the first horizontal direction, wherein the second horizontal direction is parallel to the first surface of the substrate; A source / drain region disposed on the fin-type active region, wherein a sidewall of the source / drain region is adjacent to the gate line and in contact with the plurality of nanosheets; a backside contact extending from a second surface of the substrate toward a lower portion of the source / drain region, wherein the second surface of the substrate is opposite to the first surface of the substrate; and A high concentration doping layer is arranged at the lower part of the source / drain region, The high-concentration doping layer has a dopant concentration greater than a dopant concentration of the source / drain region.

2. The integrated circuit device according to claim 1, further comprising: A metal silicide film is provided between an upper portion of the back contact and the high-concentration doping layer.

3. The integrated circuit device according to claim 2, in, The metal silicide film is in contact with the high-concentration doped layer.

4. The integrated circuit device according to claim 1, in, The high-concentration doped layer has a convex shape entering into the source / drain region.

5. The integrated circuit device according to claim 1, in, The high-concentration doping layer conformally covers a top surface of an upper portion of the back contact.

6. The integrated circuit device according to claim 1, in, The high-concentration doping layer has a stacked structure including a first sub-high-concentration doping layer and a second sub-high-concentration doping layer.

7. The integrated circuit device according to claim 6, in, The first high-concentration doping sub-layer and the second high-concentration doping sub-layer are different in at least one of a dopant and a dopant concentration.

8. An integrated circuit device comprising: A fin-type active region is disposed on a substrate and extends in a first horizontal direction, wherein the first horizontal direction is parallel to an upper surface of the substrate; A channel region disposed on the fin-type active region; A gate line disposed on the fin-type active region, the gate line surrounds the channel region and extends in a second horizontal direction intersecting the first horizontal direction, wherein the second horizontal direction is parallel to the upper surface of the substrate; A first source / drain region is disposed on the fin-type active region, wherein a sidewall of the first source / drain region is adjacent to the gate line and in contact with the channel region; a first backside contact extending from a lower surface of the substrate toward a lower portion of the first source / drain region, wherein the lower surface of the substrate is opposite to the upper surface of the substrate; and A first high-concentration doped layer is disposed at the lower portion of the first source / drain region, wherein the first high-concentration doped layer and the first source / drain region include a first dopant, and The concentration of the first dopant in the first high-concentration doping layer is greater than the concentration of the first dopant in the first source / drain region.

9. The integrated circuit device according to claim 8, in, The first source / drain region comprises: a first semiconductor layer contacting the channel region and the fin-type active region; and a second semiconductor layer, on the first semiconductor layer, wherein the first semiconductor layer is disposed in a space between the second semiconductor layer and the channel region, Wherein, each of the first semiconductor layer, the second semiconductor layer and the first high-concentration doped layer comprises Si doped with the first dopant 1-x Ge x layers, where x is a positive fraction, and Wherein, the first dopant is a p-type dopant.

10. The integrated circuit device according to claim 9, in, a p-type dopant concentration of the p-type dopant in the second semiconductor layer is greater than a p-type dopant concentration of the p-type dopant in the first semiconductor layer, and The p-type dopant concentration of the p-type dopant in the first high-concentration doping layer is greater than the p-type dopant concentration of the p-type dopant in the second semiconductor layer.

11. The integrated circuit device according to claim 10, in, The p-type dopant concentration of the p-type dopant in the first high-concentration doped layer is selected from about 5×10 20 atom / cm 3 to about 10 22 atom / cm 3 The value of the range.

12. The integrated circuit device according to claim 9, in, The Ge content in the first high-concentration doped layer is a value selected from the range of about 45 at % to about 70 at %.

13. The integrated circuit device according to claim 8, in, The first source / drain region comprises: a first semiconductor layer contacting the channel region and the fin-type active region, and a second semiconductor layer, on the first semiconductor layer, wherein the first semiconductor layer is disposed in a space between the second semiconductor layer and the channel region, wherein each of the first semiconductor layer, the second semiconductor layer and the first high-concentration doped layer comprises a Si layer doped with the first dopant, and Wherein, the first dopant is an n-type dopant.

14. The integrated circuit device according to claim 13, in, an n-type dopant concentration of the n-type dopant in the second semiconductor layer is greater than an n-type dopant concentration of the n-type dopant in the first semiconductor layer, and The n-type dopant concentration of the n-type dopant in the first high-concentration doping layer is greater than the n-type dopant concentration of the n-type dopant in the second semiconductor layer.

15. The integrated circuit device according to claim 14, in, The n-type dopant concentration of the n-type dopant in the first high-concentration doped layer is selected from about 1.5×10 21 atom / cm 3 to about 10 22 atom / cm 3 The value of the range.

16. The integrated circuit device according to claim 8, further comprising: a second source / drain region separated from the first source / drain region by the channel region; a second back contact extending from the lower surface of the substrate toward a lower portion of the second source / drain region; as well as A second high-concentration doped layer is disposed at the lower portion of the second source / drain region, wherein the second high-concentration doped layer and the second source / drain region include a second dopant, the second dopant having a conductivity type different from that of the first dopant, and The dopant concentration of the second dopant in the second high-concentration doping layer is greater than the dopant concentration of the second dopant in the second source / drain region.

17. An integrated circuit device comprising: A fin-type active region is disposed on a substrate and extends in a first horizontal direction, wherein the first horizontal direction is parallel to an upper surface of the substrate; a plurality of nanosheets disposed on the top surface of the fin-type active region, separated from the top surface of the fin-type active region, and having different distances from the top surface of the fin-type active region in a vertical direction perpendicular to the upper surface of the substrate; a gate line disposed on the fin-type active area, the gate line surrounding each of the plurality of nanosheets and extending longitudinally in a second horizontal direction intersecting the first horizontal direction, wherein the second horizontal direction is parallel to the upper surface of the substrate; a source / drain region adjacent to the plurality of nanosheets in the first horizontal direction; a back contact extending from a lower surface of the substrate toward a lower portion of the source / drain region, wherein the lower surface of the substrate is opposite to the upper surface of the substrate; a high concentration doping layer, disposed at the lower portion of the source / drain region; and a metal silicide film between an upper portion of the back contact and the high-concentration doping layer, Wherein, the source / drain region comprises: a first semiconductor layer contacting the fin-type active region, and a second semiconductor layer, on the first semiconductor layer, wherein the metal silicide film is in contact with the high-concentration doped layer, wherein the high-concentration doped layer, the first semiconductor layer and the second semiconductor layer include a first dopant, wherein a first concentration of the first dopant in the first semiconductor layer is less than a second concentration of the first dopant in the second semiconductor layer, and The third concentration of the first dopant in the high-concentration doping layer is greater than the second concentration of the first dopant in the second semiconductor layer.

18. The integrated circuit device according to claim 17, in, The first dopant is a p-type dopant, and Wherein, the p-type dopant includes boron (B).

19. The integrated circuit device according to claim 18, in, The high concentration doping layer further comprises: Gallium (Ga) having a concentration smaller than the third concentration of the first dopant in the high-concentration doping layer.

20. The integrated circuit device according to claim 17, in, The first dopant is an n-type dopant, and Wherein, the n-type dopant includes at least one of arsenic (As) and phosphorus (P).

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