Semiconductor device

Abstract

A semiconductor device according to a technical idea of the inventive concept includes: a first transistor including a first channel region extending in a first direction and a first source / drain region contacting the first channel region; a second transistor including a second channel region on the first transistor and spaced apart from the first transistor in a second direction perpendicular to the first direction and extending in the first direction, and a second source / drain region contacting the second channel region; a dummy layer under the first transistor; a protective layer under the dummy layer and including a recessed portion recessed in the first direction; and a spacer on the recessed portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0164857 filed in the Korean Intellectual Property Office on November 23, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Technical ideas of the inventive concept relate to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor. Background Art

[0004] As the size reduction of semiconductor devices is rapidly developing, it is necessary to ensure not only a high operating speed in semiconductor devices, but also an operating accuracy in semiconductor devices. In addition, as the integration of semiconductor devices increases and their size decreases, the possibility of process defects during the process of manufacturing field effect transistors will increase. Therefore, it is necessary to develop a semiconductor device with a new structure that can eliminate the possibility of process defects and improve the performance and reliability of field effect transistors. Summary of the invention

[0005] A task to be solved by the technical idea of ​​the present inventive concept is to provide an improved semiconductor device having improved electrical characteristics by preventing stacking errors.

[0006] Tasks to be solved by the technical idea of ​​the present inventive concept are not limited to the above-mentioned tasks, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] The semiconductor device of the technical idea conceived by the present invention includes: a first transistor, which includes a first channel region extending in a first direction and a first source / drain region contacting the first channel region; a second transistor, which includes a second channel region and a second source / drain region contacting the second channel region, the second channel region is on the first transistor and is spaced apart from the first transistor in a second direction perpendicular to the first direction, and extends in the first direction; a dummy layer, which is below the first transistor; a protective layer, which is below the dummy layer and includes a recessed portion recessed in the first direction; and a spacer, which is on the recessed portion.

[0008] The semiconductor device of the technical idea conceived by the present invention includes: a first transistor, which includes a first channel region extending in a first direction and a first source / drain region contacting the first channel region; a second transistor, which includes a second channel region and a second source / drain region contacting the second channel region, the second channel region is on the first transistor and is spaced apart from the first transistor in a second direction perpendicular to the first direction, and extends in the first direction; a dummy layer, which is below the first transistor and includes a sidewall recessed in the first direction; a protective layer, which is below the dummy layer and includes a sidewall recessed in the first direction; and a spacer, which is on the sidewall of the protective layer and on the sidewall of the dummy layer.

[0009] A semiconductor device of the technical idea conceived by the present invention includes: a first transistor, which includes a first channel region, a first source / drain region and a plurality of first gate lines, the first channel region includes a plurality of first nanosheets extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, the first source / drain region contacts the first channel region, and the plurality of first gate lines surround the plurality of first nanosheets; a second transistor, which includes a second channel region, a second source / drain region and a plurality of second gate lines, the second channel region is on the first transistor and spaced apart from the first transistor in the second direction, and includes a plurality of second nanosheets spaced apart from each other in the second direction, the second source / drain region contacts the second channel region, the plurality of second gate lines are spaced apart from each other, and the second nanosheets are located between the plurality of second gate lines; an insulating layer, which is located between the first transistor and the second transistor and insulates the first transistor and the second transistor from each other; a contact electrode, which is below the first source / drain region; a dummy layer, which is below the first transistor; a protective layer, which is below the dummy layer and includes a sidewall recessed in the first direction; and a spacer, which is on the sidewall. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0011] In the figure:

[0012] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment;

[0013] Figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment;

[0014] FIG. 3A to FIG. 3L A method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0015] A cross-sectional view of the process sequence; and

[0016] FIG. 4A to FIG. 4CA method for manufacturing a semiconductor device according to another embodiment is shown.

[0017] Cross-sectional view of the process sequence of the method. DETAILED DESCRIPTION

[0018] Embodiments of the technical ideas of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0019] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0020] Reference Figure 1 , the semiconductor device 100 may include a protection layer 121, a dummy layer 140 formed on the protection layer 121, a first transistor TR1 formed on the dummy layer 140, and a second transistor TR2. For example, the first transistor TR1 may include a PMOS transistor, and the second transistor TR2 may include an NMOS transistor.

[0021] The first transistor TR1 may include a first nanosheet stack NSS1. The first nanosheet stack NSS1 may include a plurality of first nanosheets NS1 overlapping each other in a vertical direction (Z direction). The nanosheet should be understood to include a nanowire. The plurality of first nanosheets NS1 may be spaced apart from each other in a vertical direction (Z direction) and may have different vertical distances (Z direction distances) from the dummy layer 140.

[0022] The second transistor TR2 may include a second nanosheet stack NSS2. The second nanosheet stack NSS2 may include a plurality of second nanosheets NS2 overlapping each other in a vertical direction (Z direction). The plurality of second nanosheets NS2 may be spaced apart from each other in a vertical direction (Z direction) and may have different vertical distances (Z direction distances) from the dummy layer 140.

[0023] Figure 1The case where the first nanosheet stack NSS1 and the second nanosheet stack NSS2 include two first nanosheets NS1 and two second nanosheets NS2, respectively, is shown, but the technical idea of ​​the present invention is not limited thereto. The number of nanosheets constituting the first nanosheet stack NSS1 and the second nanosheet stack NSS2 is not particularly limited. For example, the first nanosheet stack NSS1 and the second nanosheet stack NSS2 may also include one, three, four or more nanosheets, respectively. A plurality of first nanosheets NS1 and a plurality of second nanosheets NS2 may each have / provide a channel region. For example, a plurality of first nanosheets NS1 and a plurality of second nanosheets NS2 may each have a thickness selected from a range of about 5 nanometers (nm) to about 10 nm, but is not limited thereto. Here, the thickness of a plurality of first nanosheets NS1 and a plurality of second nanosheets NS2 refers to the size shown in the vertical direction (Z direction). In some embodiments, a plurality of first nanosheets NS1 and a plurality of second nanosheets NS2 may have substantially the same thickness in the vertical direction (Z direction). In other embodiments, at least some of the plurality of first nanosheets NS1 and the plurality of second nanosheets NS2 may have different thicknesses in the vertical direction (Z direction).

[0024] In some embodiments, each of the plurality of first nanosheets NS1 included in the first nanosheet stack NSS1 may have the same size in the first horizontal direction (X direction). In other embodiments, at least some of the plurality of first nanosheets NS1 included in the first nanosheet stack NSS1 may have different sizes in the first horizontal direction (X direction). The X direction and the Z direction may be perpendicular to each other.

[0025] In some embodiments, each of the plurality of second nanosheets NS2 included in the second nanosheet stack NSS2 may have the same size in the first horizontal direction (X direction). In other embodiments, at least some of the plurality of second nanosheets NS2 included in the second nanosheet stack NSS2 may have different sizes in the first horizontal direction (X direction).

[0026] In this specification, the plurality of first nanosheets NS1 of the first nanosheet stack NSS1 included in the first transistor TR1 may be referred to as a first channel region, and the plurality of second nanosheets NS2 of the second nanosheet stack NSS2 included in the second transistor TR2 may be referred to as a second channel region.

[0027] The plurality of first nanosheets NS1 may be made of a semiconductor layer made of the same element. In some embodiments, the plurality of first nanosheets NS1 may each be made of an undoped silicon layer. In other embodiments, the plurality of first nanosheets NS1 may each be made of a doped silicon layer.

[0028] The plurality of second nanosheets NS2 may be made of a semiconductor layer made of the same element. In some embodiments, the plurality of second nanosheets NS2 may each be made of an undoped silicon layer. In other embodiments, the plurality of second nanosheets NS2 may each be made of a doped silicon layer.

[0029] For example, in the first transistor TR1, the plurality of first nanosheets NS1 may be made of a silicon layer doped with an n-type dopant, and in the second transistor TR2, the plurality of second nanosheets NS2 may be made of a silicon layer doped with a p-type dopant, but is not limited thereto. The n-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb). The p-type dopant may be selected from boron (B) and gallium (Ga).

[0030] The first transistor TR1 may include a first source / drain region 160. The first source / drain region 160 may contact each of a plurality of first nanosheets NS1 disposed adjacent to the first source / drain region 160. The second transistor TR2 may include a second source / drain region 170. The second source / drain region 170 may contact each of a plurality of second nanosheets NS2 disposed adjacent to the second source / drain region 170.

[0031] The first source / drain region 160 may include silicon germanium (SiGe) formed by an epitaxial growth method. The first source / drain region 160 may include a first semiconductor layer 160a and a second semiconductor layer 160b disposed inside the first semiconductor layer 160a. In some embodiments, the first semiconductor layer 160a may include silicon germanium (SiGe) formed by an epitaxial growth method, and the second semiconductor layer 160b may also include silicon germanium (SiGe) formed by an epitaxial growth method. In this case, the germanium (Ge) content ratio of the second semiconductor layer 160b may be less than the germanium (Ge) content ratio of the first semiconductor layer 160a.

[0032] The first semiconductor layer 160a and the second semiconductor layer 160b may include a material obtained by doping silicon germanium (SiGe) formed by an epitaxial growth method with a p-type dopant. In some embodiments, the first semiconductor layer 160a may include a material obtained by doping silicon germanium (SiGe) formed by an epitaxial growth method with boron (B), and the second semiconductor layer 160b may also include a material obtained by doping silicon germanium (SiGe) formed by an epitaxial growth method with boron (B). In this case, the boron (B) doping concentration of the second semiconductor layer 160b may be lower than the boron (B) doping concentration of the first semiconductor layer 160a.

[0033] The second source / drain region 170 may include silicon formed by an epitaxial growth method. The second source / drain region 170 may include a third semiconductor layer 170a and a fourth semiconductor layer 170b disposed inside the third semiconductor layer 170a. The third semiconductor layer 170a and the fourth semiconductor layer 170b may include silicon doped with an n-type dopant. In some embodiments, the third semiconductor layer 170a and the fourth semiconductor layer 170b may include silicon doped with phosphorus (P). The third semiconductor layer 170a may be doped with a dopant with a lower concentration than the fourth semiconductor layer 170b, and a short channel effect may be blocked / prevented.

[0034] exist Figure 1 In the embodiment, the second source / drain region 170 is shown to include two semiconductor layers, but is not limited thereto. In some embodiments, the second source / drain region 170 may include a plurality of semiconductor layers.

[0035] In some embodiments, the third semiconductor layer 170a may include a material obtained by doping silicon formed by an epitaxial growth method with phosphorus (P), and the fourth semiconductor layer 170b may also include a material obtained by doping silicon formed by an epitaxial growth method with phosphorus (P).

[0036] The first transistor TR1 may include a plurality of first gate lines 132 spaced apart from the first nanosheet NS1 therebetween. The second transistor TR2 may include a plurality of second gate lines 134 spaced apart from the second nanosheet NS2 therebetween.

[0037] The first gate line 132 and the second gate line 134 can be made of metal, metal nitride, metal carbide or a combination thereof independently. The metal can be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er) and palladium (Pd). The metal nitride can be selected from titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide can be titanium aluminum carbide (TiAlC). In some embodiments, the first gate line 132 and the second gate line 134 each independently have a structure in which a metal nitride film, a metal film, a conductive capping film and a gap filling metal film are sequentially stacked. The metal nitride film and the metal film may include at least one metal selected from titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo) and hafnium (Hf). The gap filling metal film may be made of a tungsten (W) film or an aluminum (Al) film. The plurality of first gate lines 132 and the plurality of second gate lines 134 may include at least one work function containing metal film. The at least one work function containing metal film may include at least one metal selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er) and palladium (Pd). In some embodiments, the first gate line 132 and the second gate line 134 may include a stacked structure of titanium aluminum carbide / titanium nitride / tungsten (TiAlC / TiN / W), a stacked structure of titanium nitride / tantalum nitride / titanium aluminum carbide / titanium nitride / tungsten (TiN / TaN / TiAlC / TiN / W), or a stacked structure of titanium nitride / tantalum nitride / titanium nitride / titanium aluminum carbide / titanium nitride / tungsten (TiN / TaN / TiN / TiAlC / TiN / W), but are not limited to the above examples. In some embodiments, the first gate line 132 and the second gate line 134 may have different thicknesses, different materials, or different stacked structures.

[0038] In the first transistor TR1, the first nanosheet NS1 may be surrounded by the first gate dielectric film 133, and the first gate dielectric film 133 may be surrounded by the first gate line 132. In the second transistor TR2, the second nanosheet NS2 may be surrounded by the second gate dielectric film 135, and the second gate dielectric film 135 may be surrounded by the second gate line 134. Therefore, the first gate line 132 may surround the first nanosheet NS1, and the second gate line 134 may surround the second nanosheet NS2. In addition, the first gate dielectric film 133 may be between the first gate line 132 and the first nanosheet NS1, and the second gate dielectric film 135 may be between the second gate line 134 and the second nanosheet NS2.

[0039] In some embodiments, the first gate dielectric film 133 and the second gate dielectric film 135 may be made of a high dielectric film. The high dielectric film may be made of a material having a dielectric constant greater than that of a silicon oxide film. For example, the high dielectric film may have a dielectric constant of about 10 to 25. The high dielectric film may be made of hafnium oxide, but is not limited thereto. In some embodiments, the first gate dielectric film 133 and the second gate dielectric film 135 may have different thicknesses, different materials, or different stacked structures.

[0040] In the first transistor TR1, the upper surface of the first source / drain region 160 may be covered with a semiconductor capping layer 161. In some embodiments, the semiconductor capping layer 161 may be made of undoped silicon, silicon doped with a p-type dopant, or silicon germanium (SiGe) having a germanium (Ge) content ratio less than that in the second semiconductor layer 160b.

[0041] The first source / drain region 160 of the first transistor TR1 and the second source / drain region 170 of the second transistor TR2 may have different shapes and sizes. The shapes and sizes of the first source / drain region 160 of the first transistor TR1 and the second source / drain region 170 of the second transistor TR2 are not limited to Figure 1 The shapes and sizes shown in , and the sizes and shapes of the first source / drain region 160 and the second source / drain region 170 may be modified in various ways.

[0042] The insulating layer 150 may be disposed between the first transistor TR1 and the second transistor TR2 and insulate the first transistor TR1 and the second transistor TR2 from each other. In some embodiments, the insulating layer 150 may be made of a silicon nitride film, a silicon oxide film, a silicon oxynitride (SiON) film, a silicon oxycarbon nitride (SiOCN) film, or a combination thereof.

[0043] The first source / drain region 160 may be spaced apart from the second source / drain region 170 with a first insulating film 151 and a second insulating film 152 disposed therebetween. In some embodiments, the first insulating film 151 and the second insulating film 152 may each independently be made of a silicon nitride film, a silicon oxide film, a silicon oxynitride (SiON) film, a silicon oxycarbon nitride (SiOCN) film, or a combination thereof.

[0044] When etching the silicon layer in the process of manufacturing the semiconductor device 100, the protective layer 121 can be used to protect the first source / drain region 160. The thickness of the protective layer 121 can be, for example, about 5 nm or more and about 10 nm or less. The thickness of the protective layer 121 can be, for example, about 1 nm or more and about 20 nm or less.

[0045] The protective layer 121 may be made of a semiconductor material layer formed by an epitaxial growth method. The protective layer 121 may include silicon germanium or a material obtained by adding carbon to silicon germanium. For example, the protective layer 121 may include silicon germanium and carbon.

[0046] In addition, since the protective layer 121 includes silicon germanium or a material obtained by adding carbon to silicon germanium, the protective layer 121 may have the same thickness as the substrate including silicon (refer to Figure 3A The first source / drain region 160 may be formed in the same crystal structure as the first source / drain region 110 and / or the dummy layer 140 including silicon. When the first source / drain region 160 is grown in the same crystal structure, the occurrence of stacking errors may be reduced / prevented.

[0047] A recessed structure ID may be formed in the protective layer 121. The recessed structure ID may be, for example, an opening in the protective layer 121. The recessed structure ID formed in the protective layer 121 may have a spacer 191 therein (for example, the recessed structure ID may be filled with the spacer 191). The protective layer 121 may be recessed relative to the dummy layer 140 (and relative to the gap-filling oxide layer 190) in the X direction (due to / because of the recessed structure ID). For example, the inner sidewall of the protective layer 121 may be recessed relative to the inner sidewall of the dummy layer 140 (and relative to the inner sidewall of the gap-filling oxide layer 190) in the X direction. The inner sidewall of the protective layer 121 may therefore be a part of the recessed portion of the protective layer 121. The spacer 191 may be on the recessed portion of the protective layer 121 (for example, may contact the inner sidewall of the protective layer 121). The spacer 191 may include silicon nitride (SiN), but is not limited thereto. The spacer 191 may include, for example, silicon nitride (SiN), silicon dioxide (SiO 2 ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon oxynitride (SiON). A portion of the spacer 191 may protrude toward the recessed portion (eg, inner sidewall) of the protective layer 121 in the X direction.

[0048] The dummy layer 140 may be disposed on the protective layer 121. The dummy layer 140 may include silicon. For example, the thickness of the dummy layer 140 may be about 10 nm or more and about 20 nm or less. As another example, the thickness of the dummy layer 140 may be about 5 nm or more and about 50 nm or less.

[0049] The gap-fill oxide layer 190 may be disposed under the protective layer 121. The gap-fill oxide layer 190 may fill a space where the silicon layer is etched away during a process of manufacturing the semiconductor device 100. The gap-fill oxide layer 190 may include, for example, silicon dioxide (SiO 2 ).

[0050] The contact electrode 192 may be disposed below the first source / drain region 160. The contact electrode 192 may be surrounded by a spacer 191. The contact electrode 192 may be made of a metal, a conductive metal nitride, or a combination thereof. The contact electrode 192 may be made of, for example, tungsten (W), molybdenum (Mo), copper (Cu), Al, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), alloys thereof, or combinations thereof.

[0051] The main gate line 134M and the second gate dielectric film 135 contacting the main gate line 134M can be arranged on the uppermost second nanosheet NS2. The main gate line 134M can be made of metal, metal nitride, metal carbide or a combination thereof. The metal can be selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er) and palladium (Pd). The metal nitride can be selected from titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide can be titanium aluminum carbide (TiAlC). In some embodiments, the main gate line 134M can have a structure in which a metal nitride film, a metal film, a conductive capping film and a gap filling metal film are stacked sequentially. The metal nitride film and the metal film may include at least one metal selected from titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), and hafnium (Hf). The gap filling metal film may be made of a tungsten (W) film or an aluminum (Al) film. The main gate line 134M may include at least one work function metal-containing film. The at least one work function metal-containing film may include at least one metal selected from titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). In some embodiments, the main gate line 134M may include a stacked structure of titanium aluminum carbide / titanium nitride / tungsten (TiAlC / TiN / W), a stacked structure of titanium nitride / tantalum nitride / titanium aluminum carbide / titanium nitride / tungsten (TiN / TaN / TiAlC / TiN / W), or a stacked structure of titanium nitride / tantalum nitride / titanium nitride / titanium aluminum carbide / titanium nitride / tungsten (TiN / TaN / TiN / TiAlC / TiN / W), but is not limited to the above examples. The upper surface of each of the plurality of main gate lines 134M may be covered with a capping insulating pattern 183. The capping insulating pattern 183 may be made of a silicon nitride film. The sidewall of the main gate line 134M may be covered by an insulating spacer 184. The insulating spacer 184 may be spaced apart from the main gate line 134M, and the second gate dielectric film 135 is located between the insulating spacer 184 and the main gate line 134M. The insulating spacer 184 may be made of silicon nitride (SiN), silicon oxide (SiO), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOC), or a combination thereof.As used in this specification, the terms "silicon nitride (SiN)", "silicon oxide (SiO)", "silicon carbonitride (SiCN)", "silicon boron nitride (SiBN)", "silicon oxynitride (SiON)", "silicon oxycarbonitride (SiOCN)", "silicon boron carbonitride (SiBCN)", and "silicon oxycarbide (SiOC)" refer to materials composed of the elements included in each term, but they are not chemical formulas expressing a stoichiometric relationship.

[0052] The second source / drain region 170 may be covered with an insulating liner 154. The insulating liner 154 may be made of silicon nitride (SiN), silicon oxide (SiO), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron carbonitride (SiBCN), silicon oxycarbon (SiOC), or a combination thereof. In some embodiments, the insulating liner 154 may be omitted. An inter-gate insulating film 155 may be disposed on the insulating liner 154. The inter-gate insulating film 155 may be made of a silicon nitride film, a silicon oxide film, a silicon oxynitride (SiON) film, a silicon oxycarbonitride (SiOCN) film, or a combination thereof. When the insulating liner 154 is omitted, the inter-gate insulating film 155 may contact a plurality of second source / drain regions 170.

[0053] Figure 1 The semiconductor device 100 shown in FIG. 1 may include a protective layer 121 having a recessed structure ID, and the protective layer 121 may include silicon germanium or a material obtained by adding carbon to silicon germanium. Due to the strain compensation effect of germanium (Ge) and carbon (C), the possibility of plastic relaxation caused by adding the protective layer 121 can be reduced / minimized, and when the first source / drain region 160 is grown, the occurrence of a stacking error can be reduced / prevented.

[0054] Figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0055] Reference Figure 2 , the semiconductor device 101 may include a protection layer 121 having a first recessed structure ID1 , a dummy layer 140 formed on the protection layer 121 and including a second recessed structure ID2 , a first transistor TR1 formed on the dummy layer 140 , and a second transistor TR2 .

[0056] In addition to the second recessed structure ID2 formed in the dummy layer 140, the semiconductor device 101 and Figure 1 The semiconductor device 100 is the same as that of FIG. Figure 2 When Figure 1 The content overlaps the content.

[0057] The first recessed structure ID1 may be formed in the protective layer 121. The first recessed structure ID1 formed in the protective layer 121 may be filled with a spacer 191. The spacer 191 may include silicon nitride, but is not limited thereto. The spacer 191 may include, for example, silicon nitride (SiN), silicon dioxide (SiO 2 ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) or silicon oxynitride (SiON).

[0058] The second recessed structure ID2 may be formed in the dummy layer 140. The second recessed structure ID2 may be, for example, an opening in the dummy layer 140. The second recessed structure ID2 formed in the dummy layer 140 may have a spacer 191 therein (e.g., may be filled with the spacer 191). The spacer 191 may include silicon nitride, but is not limited thereto. The spacer 191 may include, for example, silicon nitride (SiN), silicon dioxide (SiO 2 ), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) or silicon oxynitride (SiON).

[0059] The depth d1 (in the direction X) of the first recessed structure ID1 formed in the protective layer 121 may be greater than the depth d2 (in the direction X) of the second recessed structure ID2 formed in the dummy layer 140. However, the embodiment is not limited thereto, and the depth d1 of the first recessed structure ID1 formed in the protective layer 121 may be the same as or smaller than the depth d2 of the second recessed structure ID2 formed in the dummy layer 140. The spacer 191 may contact both (i) the inner sidewall of the recessed depth d1 of the protective layer 121 and (ii) the inner sidewall of the recessed depth d2 of the dummy layer 140. The depths d1, d2 may each be a distance (e.g., a recess) in the X direction relative to the inner sidewall of the gap-filling oxide layer 190 that may contact the spacer 191. As used herein, the term "recessed" may refer to a portion (e.g., a sidewall) of a layer that is laterally recessed / offset relative to another layer.

[0060] The semiconductor devices 100 and 101 of the embodiments may include a complementary field effect transistor (CFET) including a first transistor TR1 and a second transistor TR2 that are vertically stacked.

[0061] FIG. 3A to FIG. 3L 1 is a cross-sectional view showing a process sequence of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3A to FIG. 3L Describe manufacturing reference Figure 1 An example method of a semiconductor device 100 is described. FIG. 3A to FIG. 3L In, with Figure 1 The same reference numerals in the drawings denote the same elements, and a detailed description thereof is omitted here.

[0062] Reference Figure 3A , an etch stop layer 120 , a silicon layer 111 , a protection layer 121 , and a dummy layer 140 may be sequentially formed on a substrate 110 .

[0063] The substrate 110 may include a material having semiconductor properties (e.g., silicon, germanium), an insulating material (e.g., glass, quartz), a semiconductor covered by an insulating material, and one of a conductor. Here, the substrate 110 may include a wafer containing silicon (Si). In some embodiments, the substrate 110 may include a wafer including a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). At the same time, the substrate 110 may include a silicon on insulator (SOI) structure.

[0064] The etch stop layer 120 may be made of a semiconductor material layer formed by an epitaxial growth method. The etch stop layer 120 may include silicon germanium or a material obtained by adding carbon to silicon germanium. The silicon layer 111 may include silicon (Si).

[0065] A plurality of first sacrificial semiconductor layers 130 and a plurality of first nanosheets NS1 may be alternately stacked one layer at a time on the dummy layer 140 , and then, the insulating layer 150 may be stacked on the uppermost first sacrificial semiconductor layer 130 .

[0066] Thereafter, a plurality of second sacrificial semiconductor layers 131 and a plurality of second nanosheets NS2 may be alternately stacked one layer at a time on the insulating layer 150 .

[0067] Figure 3B is a diagram showing the state of the image when viewed from the X-axis (ie, viewed in the YZ plane). Figure 3A See Figure 1. Figure 3B , an oxide film 125 covering the silicon layer 111 may be formed. The oxide film 125 may be formed so that the protective layer 121 is not removed when the first sacrificial semiconductor layer 130 and the second sacrificial semiconductor layer 131 are removed. The vertical height of the upper surface of the oxide film 125 may be formed to be greater than the vertical height of the upper surface of the protective layer 121.

[0068] The dummy layer 140 may have a sufficient thickness to block / prevent the protective layer 121 from being removed when the first sacrificial semiconductor layer 130 and the second sacrificial semiconductor layer 131 are removed. For example, the thickness of the dummy layer 140 may be about 10 nm or more and about 20 nm or less. As another example, the thickness of the dummy layer 140 may be about 5 nm or more and about 50 nm or less.

[0069] Reference Figure 3C, a dummy gate layer 180 and a dummy capping layer 181 may be sequentially stacked on the uppermost second nanosheet NS2 , and a spacer film 182 may be formed to surround the dummy gate layer 180 and the dummy capping layer 181 .

[0070] The dummy gate layer 180 , the dummy capping layer 181 , and the spacer film 182 may be used to etch a portion of each of the plurality of first sacrificial semiconductor layers 130 , the plurality of first nanosheets NS1 , the plurality of second sacrificial semiconductor layers 131 , the plurality of second nanosheets NS2 , the dummy layer 140 , the protection layer 121 , and the silicon layer 111 .

[0071] Thereafter, a first insulating film 151 may be formed to conformally cover the etched surfaces of the plurality of second sacrificial semiconductor layers 131 and the plurality of second nanosheets NS2, and a second insulating film 152 may be formed to conformally cover the etched surfaces of the plurality of first sacrificial semiconductor layers 130 and the plurality of first nanosheets NS1. To form the first insulating film 151 and the second insulating film 152, an atomic layer deposition (ALD) process may be used.

[0072] Reference Figure 3D , a placeholder 153 (ie, a sacrificial layer) may be formed on the silicon layer 111. The placeholder 153 may be made of silicon germanium (SiGe) grown using an epitaxial growth method.

[0073] Reference Figure 3E , a first source / drain region 160 may be formed on the placeholder 153. The upper surface of the first source / drain region 160 may be covered with a semiconductor capping layer 161. A second source / drain region 170 electrically insulated from the first source / drain region 160 may be formed above the first source / drain region 160.

[0074] In a structure including the substrate 110 , the etch stop layer 120 , the silicon layer 111 , and the protection layer 121 having the same crystallinity, epitaxial growth of the placeholder 153 and the first source / drain region 160 may be performed, thereby reducing / preventing stacking errors.

[0075] Reference Figure 3F , the first sacrificial semiconductor layer 130 and the second sacrificial semiconductor layer 131 including silicon germanium (SiGe) may be removed. Figure 3B The oxide film 125 , the protective layer 121 may not be removed.

[0076] A first gate line 132 may be formed in a portion / region where the first sacrificial semiconductor layer 130 has been removed, and a first gate dielectric film 133 may be formed to surround the first gate line 132. A second gate line 134 may be formed in a portion / region where the second sacrificial semiconductor layer 131 has been removed, and a second gate dielectric film 135 may be formed to surround the second gate line 134. Thereafter, the wafer may be flipped to form a contact electrode 192 described later.

[0077] Reference Figure 3G and Figure 3H After flipping the wafer, the substrate 110 , the etch stop layer 120 , and the silicon layer 111 may be etched away.

[0078] Reference Fig. 3I , a gap-fill oxide layer 190 may be formed in a portion / region where the silicon layer 111 has been removed. The formed gap-fill oxide layer 190 may be planarized by a chemical mechanical polishing (CMP) process.

[0079] Reference Figure 3J , a recessed structure ID may be formed by etching a portion of the gap-filling oxide layer 190 and etching a portion of the protection layer 121 .

[0080] Reference Figure 3K , a spacer 191 may be formed (eg, filled) in the recessed structure ID of the protection layer 121. The spacer 191 may be formed to contact the gap-filling oxide layer 190. Thereafter, a contact electrode 192 may be formed under the first source / drain region 160. The contact electrode 192 may be surrounded by the spacer 191.

[0081] Reference Figure 3L , the dummy gate layer 180, the dummy capping layer 181, and the spacer film 182 may be removed, and the main gate line 134M and the second gate dielectric film 135 contacting the main gate line 134M may be formed in the removed portion. The plurality of main gate lines 134M may be covered with a capping insulating pattern 183, and the sidewalls of the main gate lines 134M may be covered with an insulating spacer 184. The insulating spacer 184 may be spaced apart from the main gate line 134M, and the second gate dielectric film 135 is located between the insulating spacer 184 and the main gate line 134M. The second source / drain region 170 may be covered with an insulating liner 154. An inter-gate insulating film 155 may be provided on the insulating liner 154.

[0082] FIG. 4A to FIG. 4C is a cross-sectional view showing a process sequence of a method for manufacturing a semiconductor device according to another embodiment. For example, this process sequence can be used to form Figure 2 The semiconductor device 101 shown in FIG. FIG. 4A to FIG. 4C In, with Figure 1 and Figure 2 The same reference numerals in the drawings denote the same elements, and a detailed description thereof is omitted here.

[0083] Can be FIG. 4A to FIG. 4C The process is performed before reference FIG. 3A to FIG. 3I Describe the process.

[0084] Reference Figure 4A , a first recessed structure ID1 may be formed by etching a portion of the gap-filling oxide layer 190 and etching a portion of the protection layer 121 , and a second recessed structure ID2 may be formed by etching a portion of the dummy layer 140 .

[0085] Reference Figure 4B , a spacer 191 may be formed to fill the first recessed structure ID1 of the protection layer 121 and the second recessed structure ID2 of the dummy layer 140. The spacer 191 may be formed to contact the gap-filling oxide layer 190. Thereafter, a contact electrode 192 may be formed under the first source / drain region 160. The contact electrode 192 may be surrounded by the spacer 191.

[0086] Reference Figure 4C , the dummy gate layer 180, the dummy capping layer 181, and the spacer film 182 may be removed, and the main gate line 134M and the second gate dielectric film 135 contacting the main gate line 134M may be formed in the removed portion. The plurality of main gate lines 134M may be covered with a capping insulating pattern 183, and the sidewalls of the main gate lines 134M may be covered with an insulating spacer 184. The insulating spacer 184 may be spaced apart from the main gate line 134M, and the second gate dielectric film 135 is located between the insulating spacer 184 and the main gate line 134M. The second source / drain region 170 may be covered with an insulating liner 154. The inter-gate insulating film 155 may be disposed on the insulating liner 154.

[0087] Above, exemplary embodiments have been described with reference to the accompanying drawings, but those skilled in the art will appreciate that the inventive concept can be implemented in other specific forms without changing the technical ideas or essential features. Therefore, it should be understood that the above embodiments are illustrative and non-restrictive in all aspects.

[0088] While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device comprising: a first transistor including a first channel region extending in a first direction and a first source / drain region contacting the first channel region; a second transistor including a second channel region and a second source / drain region contacting the second channel region, the second channel region being on the first transistor and spaced apart from the first transistor in a second direction perpendicular to the first direction and extending in the first direction; a dummy layer below the first transistor; a protection layer, which is below the dummy layer and includes a concave portion concave in the first direction; as well as A spacer is on the recessed portion.

2. The semiconductor device according to claim 1, wherein The protective layer includes carbon and silicon germanium, and The recessed portion of the protection layer includes an inner sidewall of the protection layer, and the inner sidewall of the protection layer is recessed relative to the inner sidewall of the dummy layer in the first direction.

3. The semiconductor device according to claim 1, wherein The spacer includes silicon nitride, and Wherein, a portion of the spacer protrudes toward the recessed portion of the protection layer in the first direction.

4. The semiconductor device according to claim 1, wherein The first source / drain region includes epitaxial silicon germanium.

5. The semiconductor device according to claim 1, wherein The second source / drain region includes epitaxial silicon.

6. The semiconductor device according to claim 1, wherein The first channel region includes a plurality of first nanosheets spaced apart from each other in the second direction, and The first transistor further includes a plurality of first gate lines spaced apart from each other, and the plurality of first nanosheets are located between the plurality of first gate lines.

7. The semiconductor device according to claim 6, wherein: The first source / drain region contacts each of the plurality of first nanosheets.

8. The semiconductor device according to claim 1, wherein The second channel region includes a plurality of second nanosheets spaced apart from each other in the second direction, and The second transistor further includes a plurality of second gate lines spaced apart from each other, and the plurality of second nanosheets are located between the plurality of second gate lines.

9. The semiconductor device according to claim 1, further comprising: a contact electrode below the first source / drain region, Wherein, the contact electrode is surrounded by the spacer.

10. The semiconductor device according to claim 1, wherein The dummy layer comprises silicon and has a thickness between 10 nanometers and 20 nanometers.

11. The semiconductor device according to claim 1, wherein The first source / drain region includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, and Wherein, the first semiconductor layer and the second semiconductor layer include silicon germanium.

12. The semiconductor device according to claim 11, wherein A germanium content ratio of the first semiconductor layer is greater than a germanium content ratio of the second semiconductor layer.

13. The semiconductor device according to claim 1, further comprising: An insulating layer is between the first transistor and the second transistor and insulates the first transistor and the second transistor from each other.

14. A semiconductor device comprising: a first transistor including a first channel region extending in a first direction and a first source / drain region contacting the first channel region; a second transistor including a second channel region and a second source / drain region contacting the second channel region, the second channel region being on the first transistor and spaced apart from the first transistor in a second direction perpendicular to the first direction and extending in the first direction; a dummy layer below the first transistor and including a sidewall recessed in the first direction; a protection layer, which is below the dummy layer and includes a sidewall recessed in the first direction; as well as A spacer is on a sidewall of the protection layer and on a sidewall of the dummy layer.

15. The semiconductor device according to claim 14, wherein: A sidewall of the protection layer is more recessed than a sidewall of the dummy layer in the first direction.

16. The semiconductor device according to claim 14, wherein: The protective layer includes carbon and silicon germanium.

17. The semiconductor device according to claim 14, wherein: The first channel region includes a plurality of first nanosheets spaced apart from each other in the second direction, and The first transistor further includes a plurality of first gate lines spaced apart from each other, and the plurality of first nanosheets are located between the plurality of first gate lines.

18. A semiconductor device comprising: a first transistor including a first channel region, a first source / drain region, and a plurality of first gate lines, wherein the first channel region includes a plurality of first nanosheets extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, the first source / drain region contacts the first channel region, and the plurality of first gate lines surround the plurality of first nanosheets; a second transistor including a second channel region, a second source / drain region, and a plurality of second gate lines, the second channel region being on the first transistor and spaced apart from the first transistor in the second direction and including a plurality of second nanosheets spaced apart from each other in the second direction, the second source / drain region contacting the second channel region, the plurality of second gate lines being spaced apart from each other, and the plurality of second nanosheets being located between the plurality of second gate lines; an insulating layer located between the first transistor and the second transistor and insulating the first transistor and the second transistor from each other; a contact electrode below the first source / drain region; a dummy layer below the first transistor; a protection layer below the dummy layer and including a sidewall recessed in the first direction; as well as A spacer is on the side wall.

19. The semiconductor device according to claim 18, wherein: The protective layer includes carbon and silicon germanium, Wherein, the semiconductor device further comprises a gap-filling oxide layer, wherein the protection layer is located between the gap filling oxide layer and the dummy layer in the second direction, wherein the sidewall of the protection layer is recessed relative to the sidewall of the gap filling oxide layer in the first direction, and Wherein, the spacer is on the sidewall of the gap filling oxide layer.

20. The semiconductor device according to claim 18, wherein The first transistor includes a PMOS transistor, and the second transistor includes an NMOS transistor.

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