A solar cell and photovoltaic module
By setting metal crystals in the electrode overlap region of the passivation antireflection layer, the contact area between the electrode and the doped semiconductor layer is expanded, solving the problems of electrode current collection capability and connection reliability, and improving current collection efficiency and battery photoelectric conversion efficiency.
Patent Information
- Application Number
- CN202510096222.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2045-01-21
AI Technical Summary
How to improve the electrode current collection capability and electrode connection reliability of solar cells, especially at the contact between the collector grid line and the doped semiconductor layer.
Metal crystals are placed in the electrode overlap region of the passivation antireflection layer to expand the contact area between the current collector grid and the doped semiconductor layer. At the same time, metal crystals are placed in the electrode overlap region at the electrical junction to enhance the bonding force between the electrode and the doped semiconductor layer, reduce current loss, and connect the battery in series through electrical connection lines.
It improves the current collection efficiency of the electrodes and the reliability of the electrode connections, reduces current loss, and enhances the photoelectric conversion efficiency of the battery and the power of the module.
Smart Images
Figure CN120051010B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar cell technology, and more particularly to a solar cell and a photovoltaic module. Background Technology
[0002] Solar cells mainly consist of a substrate and electrodes. The substrate includes a silicon substrate and a doped layer and a passivation antireflection layer sequentially disposed on one side of the silicon substrate. The electrodes include current collector lines disposed on the silicon substrate and in contact with the doped layer for collecting current. The current collector lines are connected to conductive interconnects through electrical junctions, and the collected current is then discharged. Improving the current collection capability of the electrodes and the reliability of the electrode connections has become a problem urgently needing to be solved by those skilled in the art. Summary of the Invention
[0003] The purpose of this invention is to provide a solar cell and a photovoltaic module to improve the current collection capability of the electrodes and the reliability of the electrode connections.
[0004] In a first aspect, the present invention provides a solar cell, comprising:
[0005] A silicon substrate has two opposing sides;
[0006] A doped semiconductor layer is disposed on at least one side of a silicon substrate;
[0007] A passivation antireflection layer is disposed on the surface of the doped semiconductor layer away from the silicon substrate. The passivation antireflection layer includes an electrode overlap region and a non-electrode overlap region.
[0008] The electrical junction is disposed on the surface of the passivation antireflection layer away from the silicon substrate;
[0009] Collector gate line, a portion of the collector gate line covers the surface of the electrical junction away from the silicon substrate;
[0010] Among them, the electrode overlap region corresponds to the part where the electrical junction overlaps with the collector grid line, and the non-electrode overlap region corresponds to the part where the electrical junction does not overlap with the collector grid line. Metal crystals exist in the electrode overlap region.
[0011] When the above technical solution is adopted,
[0012] The function of the electrical junction is to collect the current collected in the collector grid line. Therefore, it is usually not necessary to place a metal crystal in the electrical junction line that contacts the doped semiconductor layer. In this application, placing a metal crystal in the electrode overlap region of the passivation antireflection layer will, on the one hand, increase the contact area between the collector grid line and the doped semiconductor layer, thereby improving the efficiency of the collector grid line in collecting current; on the other hand, forming a metal crystal in the passivation antireflection layer below the electrical junction line can improve the bonding force between the electrode and the doped semiconductor layer, thereby improving the reliability of the electrode connection. In addition, during module-end string bonding, since the collector grid line covers the surface of the electrical junction line away from the silicon substrate, the interconnect and the collector grid line can be directly connected. Compared with the traditional conductive structure of "collector grid line-pad-current guide bar", this reduces the intermediate conductive process through the electrical junction line, reduces current loss, and can effectively improve module power.
[0013] In some possible implementations, the number of metal crystals in the electrode overlap region is greater than the number of metal crystals in the non-electrode overlap region.
[0014] With the above technical solution, the number of metal crystals in the electrode overlap region is relatively large, which allows the current collector grid line to form an ohmic contact with the doped semiconductor layer in the electrode overlap region, thereby collecting charge carriers in the corresponding electrode overlap region of the doped semiconductor layer and improving the photoelectric conversion efficiency of the battery. The number of metal crystals in the non-electrode overlap region is relatively small, resulting in less damage to the passivation and antireflection layer in this region, less passivation loss, and a slight impact on the photoelectric conversion efficiency of the battery.
[0015] In some possible implementations, the orthogonal projection area of the metal crystal in the electrode overlap region on the electrode overlap region accounts for 10% to 60% of the area of the electrode overlap region.
[0016] And / or, the orthogonal projection area of the metal crystal in the non-electrode overlap region on the non-electrode overlap region accounts for 0% to 10% of the area of the non-electrode overlap region.
[0017] When the area ratio of the metal crystal in the electrode overlap region is less than 10%, it is not conducive to the formation of ohmic contacts between the current collector grid line and the doped semiconductor layer in the corresponding electrode overlap region, which is detrimental to the current collection efficiency in this region. If the area ratio of the metal crystal in the electrode overlap region is greater than 60%, the bonding area between the electrode overlap region and the electrical junction will be too small, reducing the bonding reliability between the electrical junction and the electrode overlap region. If the area ratio of the metal crystal in the non-electrode overlap region is greater than 10%, it will increase the damage to the passivation and antireflection layer in this region, reduce the passivation effect, and affect the photoelectric conversion efficiency of the battery.
[0018] In some possible implementations, the doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer, wherein the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types;
[0019] The passivation antireflection layer includes a first passivation antireflection layer located on a first doped semiconductor layer and a second passivation antireflection layer located on a second doped semiconductor layer. Both the first passivation antireflection layer and the second passivation antireflection layer include an electrode overlap region and a non-electrode overlap region.
[0020] The number of metal crystals in the electrode overlap region of the first passivation antireflection layer is greater than the number of metal crystals in the electrode overlap region of the second passivation antireflection layer.
[0021] When the above technical solution is adopted, the number of metal crystals in the passivation and antireflection layer of the doped semiconductor layer corresponding to different conductivity types is different. The number of metal crystals in the electrode overlap area of the first passivation and antireflection layer is greater than the number of metal crystals in the electrode overlap area of the second passivation and antireflection layer. This can enhance the contact effect between the first doped semiconductor layer and the corresponding electrode, and is more conducive to the current collection efficiency of the corresponding electrode overlap area of the first doped semiconductor layer.
[0022] In some possible implementations, the number of metal crystals in the electrode overlap region is less than the number of metal crystals in the passivation antireflection layer that overlap with the collector grid lines and are located outside the electrode overlap region.
[0023] With the above technical solution, since some collector grid lines cover part of the surface of the electrical junction and some cover part of the surface of the passivation antireflection layer other than the electrical junction, the collector grid lines covering the passivation antireflection layer are used to collect the current of the underlying doped semiconductor layer. Therefore, the metal crystals of the collector grid lines covering the passivation antireflection layer need to penetrate more of the passivation antireflection layer to contact the underlying doped semiconductor layer, thereby improving the current collection capability. As for the collector grid lines covering the electrical junction, since the main function of the electrical junction is to collect the current of the collector grid lines, metal crystals that contact the doped semiconductor layer are usually not required in the electrical junction. Therefore, there are fewer metal crystals in the electrode overlap area of the electrical junction. This improves the contact performance of the electrical junction without damaging the bonding force between the electrical junction and the passivation antireflection layer, reducing the risk of the electrical junction detaching.
[0024] In some possible implementations, the electrical junction is provided intermittently along the direction perpendicular to the extension of the collector grid line.
[0025] With the above technical solution, the electrical junction can be connected to the current collector grid line without a main grid. In this case, the contact area between the electrical junction and the passivation antireflection layer is reduced. Therefore, setting a metal crystal in the electrode overlap area can compensate for the loss of contact performance and electrode pull caused by the intermittent setting of the electrical junction, thereby improving the battery efficiency.
[0026] In some possible implementations, the height of the electrical junction in the electrode overlap region is less than the height of the electrical junction in the non-electrode overlap region.
[0027] When the above technical solution is adopted, since the height of the part of the electrical junction that overlaps with the current collector line is lower than the height of the rest of the electrical junction, the distance between the current collector line covering the electrical junction and the passivation anti-reflection layer is reduced, which can reduce the difficulty of forming a metal crystal in the area of the lower electrode overlap of the current collector line.
[0028] In some possible implementations, the surface of the electrode overlap region has a corrosion zone;
[0029] The doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types.
[0030] The passivation antireflection layer includes a first passivation antireflection layer located on a first doped semiconductor layer and a second passivation antireflection layer located on a second doped semiconductor layer. Both the first passivation antireflection layer and the second passivation antireflection layer include an electrode overlap region and a non-electrode overlap region.
[0031] The ratio of the corrosion zone of the first passivation antireflection layer to the area of the corresponding electrode overlap region is greater than the ratio of the corrosion zone of the second passivation antireflection layer to the area of the corresponding electrode overlap region.
[0032] When the above technical solution is adopted, the area ratio of the etched region in the passivation antireflection layer of the doped semiconductor layer corresponding to different conductivity types is different. The area ratio of the etched region in the first passivation antireflection layer is greater than that in the second passivation antireflection layer. This allows the collector grid line to have more direct or indirect contact with the first doped semiconductor layer, enhances the contact effect between the first doped semiconductor layer and the corresponding electrode, and is more conducive to the current collection efficiency of the overlapping area of the first doped semiconductor layer and the corresponding electrode.
[0033] In some possible implementations, the area of the etched region in the first passivation antireflection layer accounts for 80% to 100%;
[0034] And / or, the area of the corrosion zone in the second passivation antireflection layer accounts for 10% to 70%.
[0035] When the area ratio of the etched region in the first passivation antireflection layer is less than 80% using the above technical solution, it is detrimental to the contact performance of the first doped semiconductor layer in the overlapping area between the collector gate line and the corresponding electrode, thus negatively impacting the current collection efficiency in that area. If the area ratio of the etched region in the first passivation antireflection layer is less than 80%, the bonding area between the electrode overlapping area of the first passivation antireflection layer and the electrical junction will be too small, reducing the bonding reliability between the electrical junction and the electrode overlapping area of the first passivation antireflection layer. Similarly, considering the same reasons as for the etched region of the first passivation antireflection layer, the area ratio of the etched region in the second passivation antireflection layer is selected to be between 10% and 70%.
[0036] In some possible implementations, the etched region has a contact hole penetrating the passivation antireflection layer, and the metal crystal located within the contact hole contacts the doped semiconductor layer and / or the collector gate line.
[0037] When the above technical solution is adopted, the current collection grid line covering the electrical junction can contact the doped semiconductor layer through the metal crystal in the contact hole of the passivation antireflection layer to form an ohmic contact, thereby improving the contact performance between the electrode and the doped semiconductor layer and improving the current collection efficiency in this area.
[0038] In some possible implementations, the surface of the non-electrode overlap region away from the silicon substrate has blind holes that do not penetrate the passivation antireflection layer;
[0039] Alternatively, the surface of the non-electrode overlap region away from the silicon substrate has blind holes that do not penetrate the passivation antireflection layer, and the blind holes contain metal crystals.
[0040] When the above technical solution is adopted, for cases where there are metal crystals in the blind hole, the bonding force between the electrical junction and the passivation antireflection layer can be improved, and the risk of the electrical junction falling off can be reduced.
[0041] In a second aspect, the present invention also provides a photovoltaic module, the photovoltaic module including a plurality of battery strings, the battery strings including solar cells and electrical connecting wires as described in any of the above claims, the electrical connecting wires being disposed on an electrical junction portion and covering at least a portion of the electrical junction portion; the electrical connecting wires being electrically connected to the electrical junction portion by a bonding material.
[0042] When the above technical solution is adopted, the solar cells of the battery string are connected in series through the connection of the electrical connection wire and the electrical junction. Since the photovoltaic module uses the same solar cells as in the first aspect and any of the above implementations, the photovoltaic module has the same beneficial effects as in the first aspect and any of the above implementations, which will not be elaborated further. Attached Figure Description
[0043] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0044] Figure 1 This is a schematic diagram of the structure of a solar cell provided in an embodiment of the present invention;
[0045] Figure 2 This is a schematic diagram of the topography of the overlapping region of the N-region electrodes in a solar cell provided in an embodiment of the present invention;
[0046] Figure 3 This is a schematic diagram of the topography of the overlapping region of the P-region electrodes in a solar cell provided in an embodiment of the present invention.
[0047] Reference numerals in the figures: 1 is silicon substrate, 2 is doped semiconductor layer, 21 is first doped semiconductor layer, 22 is second doped semiconductor layer, 3 is passivation antireflection layer, 31 is first passivation antireflection layer, 32 is second passivation antireflection layer, 4 is electrical junction, 41 is first electrical junction, 42 is second electrical junction, 5 is collector gate line, 51 is first collector gate line, 52 is second collector gate line, 101 is electrode overlap region, 102 is non-electrode overlap region. Detailed Implementation
[0048] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
[0049] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.
[0051] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0052] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0053] Solar cells mainly consist of a substrate and electrodes. The substrate includes a silicon substrate and a doped layer and a passivation antireflection layer sequentially disposed on one side of the silicon substrate. The electrodes include current collector lines disposed on the silicon substrate and in contact with the doped layer for collecting current. The current collector lines are connected to conductive interconnects through electrical junctions, and the collected current is then discharged. Improving the current collection capability of the electrodes and the reliability of the electrode connections has become a problem urgently needing to be solved by those skilled in the art.
[0054] In view of this, such as Figure 1 As shown, an embodiment of the present invention provides a solar cell, including a silicon substrate 1, a doped semiconductor layer 2, a passivation antireflection layer 3, an electrical junction portion 4, and a current collector grid line 5; wherein, the silicon substrate 1 has two opposing sides; the doped semiconductor layer 2 is disposed on at least one side of the silicon substrate 1; the passivation antireflection layer 3 is disposed on the surface of the doped semiconductor layer 2 away from the silicon substrate 1, and the passivation antireflection layer 3 includes an electrode overlap region 101 and a non-electrode overlap region 102; the electrical junction portion 4 is disposed on the surface of the passivation antireflection layer 3 away from the silicon substrate 1; a portion of the current collector grid line 5 covers the portion of the electrical junction portion 4 away from the silicon substrate 1; wherein, the electrode overlap region 101 corresponds to the portion where the electrical junction portion 4 and the current collector grid line 5 overlap, the non-electrode overlap region 102 corresponds to the portion where the electrical junction portion 4 and the current collector grid line 5 do not overlap, and the electrode overlap region 101 contains a metal crystal.
[0055] It should be noted that the electrode overlap region 101 and the non-electrode overlap region 102 include not only the region on the passivation antireflection layer 3, but also the corresponding regions in the doped semiconductor layer 2 and the electrical junction 4. The presence of metal crystals in the electrode overlap region 101 means that metal crystals may exist only in the electrode overlap region 101 of the passivation antireflection layer 3, or simultaneously in the electrode overlap regions 101 corresponding to the passivation antireflection layer 3 and the doped semiconductor layer 2, or simultaneously in the electrode overlap regions 101 corresponding to the passivation antireflection layer 3, the doped semiconductor layer 2, and the electrical junction 4.
[0056] For example, the printing sequence is controlled as "electrical junction - N-region or P-region collector grid line printing - P-region or N-region collector grid line printing," with each printing pass followed by drying to solidify the paste. After three printing passes, sintering and photoinjection are performed together to form a contact. Alternatively, the printing sequence can be controlled as "electrical junction - N-region and P-region collector grid line printing," with each printing pass followed by drying to solidify the paste. After two printing passes, sintering and photoinjection are performed together to form a contact. This allows the collector grid line 5 to be printed or overlapped above the electrical junction 4, forming a contact structure of collector grid line - electrical junction - doped semiconductor layer.
[0057] It should be noted that, depending on the surface structural characteristics of the solar cell to be observed, the surface of the area to be observed is obtained by cleaning with a cleaning solution once, twice, or multiple times. For example, the detection of metal crystals can be carried out as follows: First, the metal grid lines and glass phase on the surface of the solar cell are cleaned and removed with a cleaning solution (such as HNO3 and / or HF), leaving the passivation antireflection layer 3. Then, the area of the electrostatic junction 4 of the cleaned solar cell is observed and imaged using an electron microscope to observe the metal crystals in this area, which can be observed at a depth of 25 μm. 2 Within the calculation, the area ratio of metal crystals (such as silver-silicon crystals, nickel crystals, copper crystals, etc., determined according to the metal used in the electrode) is calculated. To reduce the impact of image acquisition resolution and software statistical errors, metal crystals with a particle size of less than 45nm are not included in the statistical range.
[0058] In the case of the above technical solution, the function of the electrical junction 4 is to collect the current collected in the collector grid line 5. Therefore, it is generally not necessary to provide a metal crystal in the electrical junction 4 that contacts the doped semiconductor layer 2. In this application, providing a metal crystal in the electrode overlap region 101 of the passivation antireflection layer 3 will, on the one hand, increase the contact area between the collector grid line 5 and the doped semiconductor layer 2, thereby improving the efficiency of current collection by the collector grid line 5; on the other hand, forming a metal crystal in the passivation antireflection layer 3 below the electrical junction 4 can improve the bonding force between the electrode and the doped semiconductor layer 2, thereby improving the reliability of the electrode connection. Furthermore, during the serial bonding of the modules, since the current collector grid 5 covers the part of the electrical junction 4 that is away from the silicon substrate 1, the electrical junction 4 blocks the large-area corrosion of the passivation and antireflection layer 3 by the highly corrosive glass material in the current collector grid 5 paste. This can maintain the bonding strength between the electrical junction 4 and the cell, ensuring excellent welding pull. Moreover, since the current collector grid 5 covers the part of the electrical junction 4 that is away from the silicon substrate 1, conductive interconnects (such as solder strips) can be directly connected to the current collector grid 5. Compared with the traditional conductive structure of "current collector grid-pad-current guide strip", this reduces the intermediate conductive process through the electrical junction, reduces current loss, and can effectively improve the module power.
[0059] In some embodiments, the number of metal crystals in the electrode overlap region 101 is greater than the number of metal crystals in the non-electrode overlap region 102. The relatively larger number of metal crystals in the electrode overlap region 101 allows the current collector grid 5 to form an ohmic contact with the doped semiconductor layer 2 in the electrode overlap region 101, thereby collecting charge carriers within the corresponding electrode overlap region 101 of the doped semiconductor layer 2 and improving the battery's photoelectric conversion efficiency. The relatively smaller number of metal crystals in the non-electrode overlap region 102 results in less damage to the passivation and antireflection layer 3 in this region, less passivation loss, and a minor impact on the battery's photoelectric conversion efficiency.
[0060] In some embodiments, the projected area of the metal crystal in the electrode overlap region 101 accounts for 10% to 60% of the area of the electrode overlap region 101, specifically 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, etc. If the area ratio of the metal crystal in the electrode overlap region 101 is less than 10%, it is not conducive to the formation of ohmic contact between the collector grid line 5 and the doped semiconductor layer 2 of the corresponding electrode overlap region 101, which is not conducive to the current collection efficiency of this region. If the area ratio of the metal crystal in the electrode overlap region 101 is greater than 60%, the bonding area between the electrode overlap region 101 and the electrical junction 4 will be too small, reducing the bonding reliability between the electrical junction 4 and the electrode overlap region 101. Therefore, in order to improve the current collection efficiency of the electrode overlap region and the bonding reliability of the electrical junction, the positive projection area of the metal crystal in the electrode overlap region 101 in this embodiment accounts for 10% to 60% of the area of the electrode overlap region 101.
[0061] In some embodiments, the projected area of the metal crystal in the non-electrode overlap region 102 onto the non-electrode overlap region 102 accounts for 0% to 10% of the area of the non-electrode overlap region 102, specifically 0%, 2%, 4%, 6%, 0.8%, 10%, etc. If the area of the metal crystal in the non-electrode overlap region 102 is greater than 10%, it will increase the damage to the passivation and antireflection layer 3 in this region, reduce the passivation effect, and affect the photoelectric conversion efficiency of the battery.
[0062] like Figure 1 As shown, in some embodiments, for a back-contact solar cell, the doped semiconductor layer 2 includes a first doped semiconductor layer 21 and a second doped semiconductor layer 22, with opposite conductivity types; the passivation antireflection layer 3 includes a first passivation antireflection layer 31 located on the first doped semiconductor layer 21 and a second passivation antireflection layer 32 located on the second doped semiconductor layer 22, both the first passivation antireflection layer 31 and the second passivation antireflection layer 32 including an electrode overlap region 101 and a non-electrode overlap region 102; a first electrical junction 41 and a first collector grid line 51 are provided on the first passivation antireflection layer 31, and a second electrical junction 42 and a second collector grid line 52 are provided on the second passivation antireflection layer 32; the number of metal crystals in the electrode overlap region 101 of the first passivation antireflection layer 31 is greater than the number of metal crystals in the electrode overlap region 101 of the second passivation antireflection layer 32.
[0063] When the above technical solution is adopted, the number of metal crystals in the passivation and antireflection layer 3 of the doped semiconductor layer 2 corresponding to different conductivity types is different. The number of metal crystals in the electrode overlap region 101 of the first passivation and antireflection layer 31 is greater than the number of metal crystals in the electrode overlap region 101 of the second passivation and antireflection layer 32. This can enhance the contact effect between the first doped semiconductor layer 21 and the corresponding first collector grid line 51, and is more conducive to the current collection efficiency of the electrode overlap region 101 of the first doped semiconductor layer 21.
[0064] For example, the first doped semiconductor layer 21 can be a P-type doped semiconductor layer, corresponding to the P-region, and the second doped semiconductor layer 22 can be an N-type doped semiconductor layer, corresponding to the N-region; or, the first doped semiconductor layer 21 can be an N-type doped semiconductor layer, corresponding to the N-region, and the second doped semiconductor layer 22 can be a P-type doped semiconductor layer, corresponding to the P-region. For example, the paste used for the collector grid line 5 on the P-region has a relatively high content of metal components and corrosive glass frit, while the paste used for the collector grid line 5 on the N-region has a relatively low content of metal components and corrosive glass frit. The highly corrosive glass frit in the collector grid line 5 has a corrosive effect on the passivation antireflection layer 3, causing the metal components in the collector grid line 5 to enter the corroded structure of the passivation antireflection layer 3 under the action of gravity, forming metal crystals. Because the paste used for the collector grid lines 5 in the P-region has a relatively high metal content and glass frit content, the glass frit of the collector grid lines 5 in the electrode overlap region 101 of the passivation and antireflection layer 3 in the P-region corrodes the passivation and antireflection layer 3 in this region more strongly and has a higher metal content. Therefore, the number and density of metal crystals formed within the corrosion structure are relatively greater than in the N-region. This enhances the contact effect between the P-type doped semiconductor layer and the corresponding electrode, and is more conducive to the current collection efficiency of the electrode overlap region 101 of the P-type doped semiconductor layer.
[0065] It should be noted that the process of achieving different numbers of metal crystals in the passivation and antireflection layer 3 of semiconductor layers 2 with different conductivity types can be achieved by using different electrode pastes in conductive regions with different doping types, or by adjusting process parameters such as sintering temperature and sintering time, which are not limited here.
[0066] For non-back-contact solar cells, the doped semiconductor layers 2 on the same surface of the silicon substrate 1 have the same conductivity type, which can be either P-type or N-type doped semiconductor layers. Doped semiconductor layers with different doping types are located on the light-receiving and back-light-receiving surfaces of the silicon substrate 1, respectively. Wherever electrical junctions 4 and collector grid lines 5 are provided, there exists an electrode overlap region 101 and a non-electrode overlap region 102. Metal crystals exist within the electrode overlap region 101, or the number of metal crystals within the electrode overlap region 101 is greater than the number of metal crystals within the non-electrode overlap region 102. The technical effects are described in the above embodiments and will not be repeated here.
[0067] In some embodiments, the number of metal crystals within the electrode overlap region 101 is less than the number of metal crystals in the passivation antireflection layer 3 that overlap with the collector gate line 5 and are located outside the electrode overlap region 101. Since a portion of the collector gate line 5 covers a portion of the surface of the electrical junction 4, and another portion of the collector gate line 5 covers the surface of the passivation antireflection layer 3 excluding the electrical junction 4 (i.e., directly covering the passivation antireflection layer 3), the collector gate line 5 directly covering the passivation antireflection layer 3 is used to collect current from the underlying doped semiconductor layer 2. Therefore, more metal crystals of the collector gate line 5 covering the passivation antireflection layer 3 need to penetrate the passivation antireflection layer 3 to contact the underlying doped semiconductor layer 2, thereby improving current collection capability. Since the main function of the electrical junction 4 is to collect the current of the collector grid line 5, it is generally not necessary to place metal crystals in the electrical junction 4 to contact the doped semiconductor layer 2. Therefore, the number of metal crystals in the electrode overlap region 101 of the passivation antireflection layer 3 corresponding to the electrical junction 4 is greater than the number of metal crystals in the part of the passivation antireflection layer 3 that directly covers the collector grid line 5. This is to improve the contact performance between the collector grid line 5 and the doped semiconductor layer 2 at the electrical junction 4 without damaging the bonding force between the electrical junction 4 and the passivation antireflection layer 3, thereby reducing the risk of the electrical junction 4 falling off.
[0068] It should be noted that the portion of the passivation antireflection layer 3 that overlaps with the collector gate line 5 and includes not only the region on the passivation antireflection layer 3, but also the corresponding regions in the doped semiconductor layer 2 and the collector gate line 5. The presence of metal crystals in this portion means that metal crystals may exist only in this portion of the passivation antireflection layer 3, or simultaneously in the portions corresponding to the passivation antireflection layer 3 and the doped semiconductor layer 2, or simultaneously in the portions corresponding to the passivation antireflection layer 3, the doped semiconductor layer 2, and the collector gate line 5.
[0069] In some embodiments, the electrical connection portion 4 is provided intermittently along the extension direction perpendicular to the collector grid line 5. That is, the electrical connection portion 4 at this time corresponds to the pad on the collector grid line 5, corresponds to the end line near both ends of the collector grid line 5, or corresponds to the thickened section on the collector grid line 5. As long as it can be electrically connected to the collector grid line 5 and can be electrically connected to conductive interconnects, such as solder strips, it is acceptable.
[0070] When the above technical solution is adopted, the electrical junction 4 does not need to use the main grid line. Instead, it is connected to the current collector grid line 5 through discontinuous electrical junctions 4 (such as pads, end lines, or thickened sections of current collector grid lines). In this case, the contact area between the electrical junction 4 and the passivation anti-reflection layer 3 is reduced. Therefore, by setting a metal crystal in the electrode overlap region 101, the loss of conductive contact performance and electrode pull caused by the discontinuous setting of the electrical junction 4 can be compensated, thereby improving the battery efficiency.
[0071] Of course, in some other embodiments, the electrical connection portion 4 may also include continuous busbar lines, i.e., main busbar lines, whose extension direction intersects with the extension direction of the collector busbar lines, specifically, they may be perpendicular. One main busbar line connects to multiple collector busbar lines. At the locations where the main busbar lines connect to the corresponding collector busbar lines, pads, end lines, or thickened sections of the main busbar lines may be provided to facilitate connection with conductive interconnects. Of course, the electrical connection portion 4 may also only include busbar lines. During fabrication, the electrical connection portion 4 (such as pads and busbar lines) can be printed first, dried and cured, and then the collector busbar lines 5 can be printed and cured again. Finally, they are sintered together and photoinjected to form a contact, so that the electrical connection portion 4 can block the highly corrosive glass material in the collector busbar lines 5 from corroding the passivation and antireflection layer 3 below the electrical connection portion 4, maintain the bonding strength between the electrical connection portion 4 and the cell, ensure good welding pull force, and make it difficult for the conductive interconnects to fall off.
[0072] In some embodiments, the surface of the electrical junction 4 overlapping with the collector gate line 5 on the electrode overlap region 101 is recessed towards the silicon substrate 1 relative to the surface of the electrical junction 4 not overlapping with the collector gate line 5. That is, in the thickness direction of the silicon substrate 1, the height of the portion of the electrical junction 4 overlapping with the collector gate line 5 is less than the height of the rest of the electrical junction 4. This configuration reduces the distance between the collector gate line 5 covering the electrical junction 4 and the passivation antireflection layer 3, making it easier for the glass frit of the collector gate line 5 at this location to etch through the underlying electrical junction 4 and passivation antireflection layer 3 to contact the doped semiconductor layer 2, thereby reducing the difficulty of forming a metal crystal in the underlying electrode overlap region 101 for the collector gate line 5.
[0073] like Figure 2 and Figure 3 As shown, in some possible implementations, the surface of the electrode overlap region 101 has a corrosion zone, that is, the surface of the passivation antireflection layer 3 has a corrosion zone corroded by the highly corrosive glass frit in the current collector grid line 5. The area on the surface of the passivation antireflection layer 3 that shows corrosion pits or corrosion penetration is the corrosion zone. It should be noted that, depending on the surface structural characteristics of the solar cell to be observed, the surface of the electrical junction to be observed is obtained by cleaning with a cleaning solution once, twice, or multiple times. For example, the corrosion zone can be observed in the following ways:
[0074] First, the metal grid lines, glass phase, and metal crystals on the surface of the solar cell are removed using a cleaning solution (such as HNO3), leaving the passivation and antireflection layer 3 intact. Then, the area corresponding to the electrical junction of the cleaned solar cell is observed and imaged using an electron microscope, yielding results as shown below. Figure 2 and Figure 3 As shown in the image, there are corrosion pits on the surface of the passivation antireflection layer 3, and in some areas the underlying doped semiconductor layer 2 is exposed.
[0075] For example, in a back-contact solar cell, the doped semiconductor layer 2 includes a first doped semiconductor layer 21 and a second doped semiconductor layer 22, with opposite conductivity types. The passivation antireflection layer 3 includes a first passivation antireflection layer 31 on the first doped semiconductor layer 21 and a second passivation antireflection layer 32 on the second doped semiconductor layer 22. Both the first passivation antireflection layer 31 and the second passivation antireflection layer 32 include an electrode overlap region 101 and a non-electrode overlap region 102. The area ratio of the etched region of the first passivation antireflection layer 31 to the corresponding electrode overlap region 101 is greater than the area ratio of the etched region of the second passivation antireflection layer 32 to the corresponding electrode overlap region 101.
[0076] With the above technical solution, the area ratio of the etched region in the passivation and antireflection layer 3 varies for different conductivity types of doped semiconductor layers 2. The area ratio of the etched region in the first passivation and antireflection layer 31 is larger than that in the second passivation and antireflection layer 32. This allows the collector grid line 5 to have more direct or indirect contact with the first doped semiconductor layer 21, enhancing the contact effect between the first doped semiconductor layer 21 and the corresponding electrode, and is more conducive to the current collection efficiency of the overlapping region 101 of the first doped semiconductor layer 2 and the corresponding electrode. For example, the first doped semiconductor layer 21 is a P-type doped semiconductor layer, corresponding to the P-region, and the second doped semiconductor layer 22 is an N-type doped semiconductor layer, corresponding to the N-region. Since the paste used for the collector grid line 5 in the P-region contains more highly corrosive glass material, it has a higher corrosiveness to the passivation and antireflection layer 3 in the P-region. Therefore, the area ratio of the etched region in the passivation and antireflection layer 3 in the P-region is larger than that in the passivation and antireflection layer 3 in the N-region, which enhances the contact effect between the P-type doped semiconductor layer and the corresponding electrode, and is more conducive to the current collection efficiency of the overlapping region 101 of the P-type doped semiconductor layer and the corresponding electrode.
[0077] It should be noted that the different areas of the etched regions in the passivation and antireflection layer 3 of the semiconductor layer 2 with different conductivity types can be achieved by using different electrode pastes in the conductive regions with different doping types, or by adjusting process parameters such as sintering temperature and sintering time, which are not limited here.
[0078] For example, such as Figure 3 As shown, the area ratio of the etched region in the first passivation antireflection layer 31 is 80% to 100%, specifically 80%, 85%, 90%, 95%, 100%, etc.; for example... Figure 2 As shown, the area ratio of the corrosion zone of the second passivation antireflection layer 32 is 10% to 70%, specifically 10%, 20%, 30%, 40%, 50%, 60%, 70%, etc.
[0079] When the area ratio of the etched region of the first passivation antireflection layer 31 is less than 80%, it is detrimental to the contact performance between the collector gate line 5 and the first doped semiconductor layer 21 of the corresponding electrode overlap region 101, and thus detrimental to the current collection efficiency in this region. If the area ratio of the etched region of the first passivation antireflection layer 31 is less than 80%, the bonding area between the electrode overlap region 101 of the first passivation antireflection layer 31 and the first electrical junction 41 will be too small, reducing the bonding reliability between the electrical junction 41 and the electrode overlap region 101 of the first passivation antireflection layer 31. Similarly, considering the same reasons as for the etched region of the first passivation antireflection layer 31, the area ratio of the etched region of the second passivation antireflection layer 32 is selected to be 10% to 70%.
[0080] In some embodiments, the etched region has a contact hole penetrating the passivation antireflection layer 3, and a metal crystal located within the contact hole contacts the doped semiconductor layer 2 and / or the current collector line 5. That is, in the region where the passivation antireflection layer 3 is etched, a portion penetrates the passivation antireflection layer 3 to form a contact hole. This contact hole is formed by etching with highly corrosive glass frit from the current collector line 5, allowing the metal frit in the current collector line 5 to enter the contact hole and form a metal crystal. The current collector line 5 covering the electrical junction 4 can contact the doped semiconductor layer 2 through the metal crystal located within the contact hole of the passivation antireflection layer 3 to form an ohmic contact, improving the contact performance between the electrode and the doped semiconductor layer 2 and enhancing the current collection efficiency in this region. Of course, when a contact hole exists, a metal crystal may or may not be present in the contact hole. If a metal crystal is present in the contact hole, the metal crystal in the contact hole may only contact the current collector grid line 5, or only contact the doped semiconductor layer 2, or contact both the current collector grid line 5 and the doped semiconductor layer 2, or not contact either the current collector grid line 5 or the doped semiconductor layer 2. Any combination of these situations can occur on the solar cell.
[0081] It should be noted that the contact holes can be observed in the following ways:
[0082] First, the metal grid lines, glass phase, and metal crystals on the surface of the solar cell are removed using a cleaning solution, leaving the passivation antireflection layer 3, which has been corroded by the glass frit. Then, the area of the contact points 4 of the cleaned solar cell is observed and imaged using an electron microscope to examine the contact holes. To minimize the impact of image acquisition resolution and software statistical errors, holes with a diameter less than 45 nm are not included in the contact hole statistics. The cleaning solution can be a corrosive solution such as HNO3 or HF.
[0083] In some embodiments, the surface of the non-electrode overlap region 102 of the passivation antireflection layer 3, away from the silicon substrate 1, has a blind hole that does not penetrate the passivation antireflection layer 3. The opening of the blind hole faces away from the silicon substrate 1, and this blind hole may not contain a metal crystal. Alternatively, the blind hole may contain a metal crystal. Since the non-electrode overlap region 102 does not overlap with the collector grid line 5, this region is not subject to corrosion by the corrosive glass frit in the collector grid line 5, or the corrosion is very weak. After corrosion, a non-penetrating blind hole is formed. Furthermore, the electrical bonding portion 4 does not need to have a metal crystal in contact with the underlying doped semiconductor layer 2. Therefore, the blind hole may not contain a metal crystal, or may contain a small number of metal crystals. The roughness of the passivation antireflection layer 3 can be increased through the blind hole, which facilitates the entry of some material of the electrical bonding portion 4 into the blind hole to increase the bonding strength between the electrical bonding portion 4 and the passivation antireflection layer 3 and reduce the risk of the electrical bonding portion 4 falling off.
[0084] In some possible implementations, the surface of the overlapping region 101 of the electrodes corresponding to the doped semiconductor layer 2 has etched pits. These etched pits on the doped semiconductor layer 2 are also formed by etching with highly corrosive glass frit in the collector grid line 5, indicating that the passivation antireflection layer 3 above the etched pit region of the doped semiconductor layer 2 is also etched away. The etched pit region on the doped semiconductor layer 2 directly contacts the collector grid line 5, forming an ohmic contact, achieving carrier collection and improving the photoelectric conversion efficiency of the battery.
[0085] In some embodiments, the doped semiconductor layer 2 includes a first doped semiconductor layer 21 and a second doped semiconductor layer 22, the first doped semiconductor layer 21 and the second doped semiconductor layer 22 having opposite conductivity types; the passivation antireflection layer 3 includes a first passivation antireflection layer 31 located on the first doped semiconductor layer 21 and a second passivation antireflection layer 32 located on the second doped semiconductor layer 22, both the first passivation antireflection layer 31 and the second passivation antireflection layer 32 including an electrode overlap region 101 and a non-electrode overlap region 102; both the first doped semiconductor layer 21 and the second doped semiconductor layer 22 have etched pits, and the first doped semiconductor layer 21 has an electrode overlap region 102. The area ratio of the etched pits of the conductor layer 21 on the corresponding electrode overlap region 101 is greater than the area ratio of the etched pits of the second doped semiconductor layer 22 on the corresponding electrode overlap region 101. Specifically, the area ratio of the etched pits of the first doped semiconductor layer 21 on the corresponding electrode overlap region 101 is 0% to 30%, for example, it can be 0%, 5%, 10%, 15%, 20%, 25%, 30%, etc.; the area ratio of the etched pits of the second doped semiconductor layer 22 on the corresponding electrode overlap region 101 is 0% to 15%, for example, it can be 0%, 5%, 10%, 15%, etc.
[0086] When the above technical solution is adopted, the area ratio of the etched pits in the first doped semiconductor layer 21 is greater than that in the second doped semiconductor layer 22, which can enhance the contact effect between the first doped semiconductor layer 21 and the first collector grid line 51. For example, the first doped semiconductor layer 21 is a P-type doped semiconductor layer, corresponding to the P region, and the second doped semiconductor layer 22 is an N-type doped semiconductor layer, corresponding to the N region. Since the paste used for the collector grid line 5 in the P region contains more highly corrosive glass material, it has a higher corrosiveness to the passivation antireflection layer 3 and the doped semiconductor layer 2 in the P region. Therefore, the area ratio of the etched region in the P-type doped semiconductor layer is greater than that in the N-type doped semiconductor layer, which can enhance the contact effect between the P-type doped semiconductor layer and the corresponding electrode, and is more conducive to the current collection efficiency of the overlapping area of the corresponding electrode of the P-type doped semiconductor layer.
[0087] In some embodiments, the glass layer formed at the intersection of the electrical junction 4 and the collector grid line 5 is thicker, while the glass layer formed at the non-overlapping area of the electrical junction 4 is thinner. The thickness of the glass layer can be characterized using 8-bit grayscale values, where 0–255 represents a continuous change from black to white. A higher grayscale value indicates greater image brightness and a thicker glass layer. For example, the average grayscale value at the intersection of the electrical junction 4 and the collector grid line 5 in the N region is 5–15 higher than the non-overlapping area, and the average grayscale value at the intersection of the electrical junction 4 and the collector grid line 5 in the P region is 15–50 higher than the non-overlapping area, indicating that the glass layer at the intersection of the electrical junction 4 and the collector grid line 5 in the P region is thicker than that in the N region. Since both electrical junction paste and collector grid paste are present at the intersection of the electrical junction 4 and the collector grid line 5, the metal content and glass frit content are higher. Therefore, after sintering, the glass layer in this region is thicker, with a greater number and density of precipitated metal crystals. Furthermore, because the metal consumption in the P region is higher than in the N region, the glass layer in the P region is thicker than that in the N region.
[0088] In some embodiments, the silicon substrate 1 can be N-type or P-type monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, etc. The material of the doped semiconductor layer 2 can include doped polycrystalline silicon, doped microcrystalline silicon, doped nanocrystalline silicon, doped amorphous silicon, etc. The material of the passivation and antireflection layer 3 can include silicon oxide, silicon carbide, aluminum oxide, or titanium oxide, etc., and the passivation and antireflection layer can be a single-layer or stacked structure composed of one or more of the above materials. The materials and doping types of the silicon substrate 1 and the doped semiconductor layer 2 are selected appropriately according to the type of battery. For example, when the doped semiconductor layer 2 is doped polycrystalline silicon, it can form a tunneling passivation contact structure with the tunneling oxide layer; when the doped semiconductor layer 2 is doped amorphous silicon, it can form a heterojunction contact structure with intrinsic amorphous silicon. The resulting solar cell can be a back-contact solar cell or a bifacial solar cell with a tunneling passivation contact structure and / or a heterojunction contact structure, without specific limitations.
[0089] In some embodiments, the doped semiconductor layer 2 is a tunneling passivation contact structure composed of doped polycrystalline silicon and a tunneling oxide layer, with the tunneling oxide layer located between the silicon substrate 1 and the doped semiconductor layer 2. The tunneling oxide layer can prevent metal crystals from penetrating the doped semiconductor layer and entering the silicon substrate 1, thus preventing damage to the passivation of the solar cell surface and resulting in a loss of cell efficiency. The dielectric layer material includes materials such as silicon oxide and titanium oxide.
[0090] Based on the solar cells described in any of the above embodiments, this invention also provides a photovoltaic module. The photovoltaic module includes multiple cell strings, each cell string including the solar cells described in any of the above embodiments and electrical connecting wires. The electrical connecting wires are disposed on the electrical connection portion 4, and the electrical connecting wires at least cover a portion of the electrical connection portion 4. The electrical connecting wires are electrically connected to the electrical connection portion 4 through a bonding material. The electrical connecting wires are conductive interconnects and can be wires capable of conductive connection, such as solder strips.
[0091] When the above technical solution is adopted, the solar cells of the battery string are connected in series through the connection of the electrical connection line and the electrical junction 4. Since the photovoltaic module uses the solar cells described in any of the above embodiments, the photovoltaic module has the same beneficial effects as any of the above embodiments. The metal crystal in the electrode overlap area 101 of the passivation antireflection layer 3 will, on the one hand, increase the contact area between the current collector grid line 5 and the doped semiconductor layer 2, and improve the current collection efficiency of the current collector grid line 5; on the other hand, the metal crystal formed in the passivation antireflection layer 3 below the electrical junction 4 can improve the bonding force between the electrode and the doped semiconductor layer 2, improve the electrode connection pull force, and thus improve the reliability of the electrode connection. In addition, when the module end is wired, since the current collector grid line 5 covers the part of the surface of the electrical junction 4 away from the silicon substrate 1, the electrical connection line and the current collector grid line 5 can be directly connected. Compared with the traditional conductive structure "current collector grid line-pad-electrical connection line", the intermediate conductive process through the electrical junction is reduced, the current loss is reduced, and the module power can be effectively improved.
[0092] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0093] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A solar cell, characterized in that, include: A silicon substrate has two opposing sides; A doped semiconductor layer is disposed on at least one side of the silicon substrate; A passivation antireflection layer is disposed on the surface of the doped semiconductor layer away from the silicon substrate, and the passivation antireflection layer includes an electrode overlap region and a non-electrode overlap region; An electrical junction is disposed on the surface of the passivation antireflection layer away from the silicon substrate; A collector gate line, a portion of which covers the electrical junction on a portion of the surface away from the silicon substrate; The electrode overlapping region corresponds to the portion where the electrical junction overlaps with the current collector grid line, and the non-electrode overlapping region corresponds to the portion where the electrical junction does not overlap with the current collector grid line. Metal crystals are present in the electrode overlapping region.
2. The solar cell according to claim 1, characterized in that, The number of metal crystals in the electrode overlap region is greater than the number of metal crystals in the non-electrode overlap region.
3. The solar cell according to claim 2, characterized in that, The projected area of the metal crystal within the electrode overlap region accounts for 10% to 60% of the area of the electrode overlap region. And / or, the area of the metal crystal in the non-electrode overlap region projected onto the non-electrode overlap region accounts for 0% to 10% of the area of the non-electrode overlap region.
4. The solar cell according to claim 1, characterized in that, The doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer, wherein the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. The passivation antireflection layer includes a first passivation antireflection layer located on the first doped semiconductor layer and a second passivation antireflection layer located on the second doped semiconductor layer. Both the first passivation antireflection layer and the second passivation antireflection layer include the electrode overlap region and the non-electrode overlap region. The number of metal crystals in the electrode overlap region of the first passivation antireflection layer is greater than the number of metal crystals in the electrode overlap region of the second passivation antireflection layer.
5. The solar cell according to claim 1, characterized in that, The number of metal crystals in the electrode overlap region is less than the number of metal crystals in the passivation antireflection layer that overlap with the collector grid line outside the electrode overlap region.
6. The solar cell according to claim 1, characterized in that, The electrical connection portion is discontinuously arranged along the direction perpendicular to the extension of the collector grid line.
7. The solar cell according to claim 1, characterized in that, The height of the electrical junction in the electrode overlap region is less than the height of the electrical junction in the non-electrode overlap region.
8. The solar cell according to claim 1, characterized in that, The surface of the electrode overlap region has a corrosion zone; The doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer, wherein the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. The passivation antireflection layer includes a first passivation antireflection layer located on the first doped semiconductor layer and a second passivation antireflection layer located on the second doped semiconductor layer. Both the first passivation antireflection layer and the second passivation antireflection layer include the electrode overlap region and the non-electrode overlap region. The ratio of the area of the corrosion zone of the first passivation antireflection layer to the area of the corresponding electrode overlap region is greater than the ratio of the area of the corrosion zone of the second passivation antireflection layer to the area of the corresponding electrode overlap region.
9. The solar cell according to claim 8, characterized in that, The area of the etched region in the first passivation antireflection layer accounts for 80% to 100%; And / or, the area of the etched region in the second passivation antireflection layer accounts for 10% to 70%.
10. The solar cell according to claim 8, characterized in that, The etched region has a contact hole that penetrates the passivation antireflection layer, and the metal crystal located in the contact hole is in contact with the doped semiconductor layer and / or the collector gate line.
11. The solar cell according to claim 1, characterized in that, The surface of the non-electrode overlap region away from the silicon substrate has blind holes that do not penetrate the passivation antireflection layer; Alternatively, the surface of the non-electrode overlap region away from the silicon substrate has a blind hole that does not penetrate the passivation antireflection layer, and the blind hole contains a metal crystal.
12. A photovoltaic module, characterized in that, The photovoltaic module includes a plurality of battery strings, each battery string including a solar cell as described in any one of claims 1 to 11 and an electrical connection wire, the electrical connection wire being disposed on the electrical junction portion and the electrical connection wire covering at least a portion of the electrical junction portion; The electrical connection wire is electrically connected to the electrical junction via a bonding material.
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