Multi-mode neuromorphic transistor and preparation method thereof

Abstract

The invention relates to a multi-mode neuromorphic transistor and a preparation method thereof, the multi-mode neuromorphic transistor comprises a MoS2 channel layer and a gate electrode which are arranged on a SiO2 / Si substrate at an interval, a 2H-MoTe2 sensitization layer located on the MoS2 channel layer, a heterojunction formed between the MoS2 channel layer and the 2H-MoTe2 sensitization layer, an h-BN gate dielectric layer located on the 2H-MoTe2 sensitization layer, a source electrode and a drain electrode which are respectively arranged at two ends of the MoS2 channel layer, the h-BN gate dielectric layer is provided with a graphene top gate, and the graphene top gate is connected to a gate electrode; due to the existence of bipolar MoTe2 in the vertical heterojunction, the transistor integrates an optical detector, an optical memory and a visual synapse mode into a whole, the transistor which effectively integrates all main functions of an artificial visual system is obtained, and further development and commercial application of a memory and optical synapse integrated visual chip are expected to be promoted.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a multimodal neuromorphic transistor and a preparation method thereof. Background Art

[0002] Neuromorphic computing can perform parallel information processing, which paves the way for breaking the constraints of the traditional von Neumann computing architecture. As the core part of the human brain for perceiving and preprocessing light stimuli, the visual system contributes more than 80% of the information input. To simulate the functions of the visual system, an artificial visual system usually integrates a sensitive photosensor to perceive multiple visual inputs, a storage unit for retaining visual information, and a processing unit for performing complex image processing tasks. In commercial artificial visual systems, due to the structural and performance gaps between the sensing, storage, and computing units, these different functional modules are usually physically separated and independently configured. This results in a large system volume, high manufacturing cost, low data transmission efficiency, and also requires complex circuits and algorithms. Summary of the Invention

[0003] Aiming at the technical problems existing in the prior art, the primary object of the present invention is to provide a multimodal neuromorphic transistor and a preparation method thereof. This transistor integrates three different modules, namely a photodetector, an optical memory, and an optical synapse, into one body, and uses a gate-tunable out-of-plane electric field to achieve multimodal integration of the three major components of the artificial visual system.

[0004] On the one hand, the present invention provides a multimodal neuromorphic transistor, including: a MoS 2 channel layer and a gate electrode disposed at intervals on the SiO 2 / Si substrate, a 2H-MoTe 2 sensitization layer located on the MoS 2 channel layer, a heterojunction formed between the MoS 2 channel layer and the 2H-MoTe 2 sensitization layer, an h-BN gate dielectric layer located on the 2H-MoTe 2 sensitization layer, a source electrode and a drain electrode are respectively disposed at both ends of the MoS 2 channel layer, and the source electrode and the drain electrode do not contact the 2H-MoTe 2 sensitization layer, a graphene top gate is disposed on the h-BN gate dielectric layer, and the graphene top gate is connected to the gate electrode.

[0005] On the one hand, the present invention provides a preparation method of a multimodal neuromorphic transistor, including the following steps:

[0006] Transfer the MoS 2 channel layer on the SiO 2 / Si substrate by mechanical exfoliation method;

[0007] Transfer the 2H-MoTe 2 sensitization layer to the middle section area of the MoS 2 channel layer, and the MoS 2 channel layer and the 2H-MoTe 2 sensitization layer form a heterojunction;

[0008] Fabricate source and drain electrodes at both ends of the MoS 2 channel layer and fabricate a gate electrode on the SiO 2 / Si substrate, and the source and drain electrodes do not contact the 2H-MoTe 2 sensitization layer;

[0009] Transfer the h-BN gate dielectric layer to the 2H-MoTe 2 sensitization layer and the MoS 2 channel layer by mechanical exfoliation method;

[0010] Transfer a graphene thin layer to the h-BN gate dielectric layer by mechanical exfoliation method to form a graphene top gate. On the projection plane, the graphene top gate covers the h-BN gate dielectric layer, and the graphene top gate is connected to the gate electrode; anneal in an inert atmosphere.

[0011] Furthermore, the thickness of the MoS 2 channel layer is 20 nm to 40 nm.

[0012] Furthermore, the thickness of the 2H-MoTe 2 sensitization layer is 25 nm to 55 nm.

[0013] Furthermore, the thickness of the h-BN gate dielectric layer is 5 nm to 15 nm.

[0014] Furthermore, the thickness of the graphene top gate is 5 nm to 20 nm.

[0015] Furthermore, the annealing temperature is 80 - 120 °C and the annealing time is 0.5 - 2 hours.

[0016] Furthermore, when a gate voltage less than 0 V is applied to the graphene top gate, this multi-modal neuromorphic transistor has photodetection and optical storage performance.

[0017] By adjusting the top gate voltage, the sensitization layer MoTe 2 can be configured from p-type to n-type, in MoTe 2 / MoS 2The interface forms a gate-tunable built-in electric field, thereby determining the conductivity of the molybdenum disulfide channel and enabling multi-mode integration. Under a negative gate voltage, that is, when a gate voltage greater than or equal to 0V is applied to the graphene top gate, the multimodal neuromorphic transistor has a visual synaptic mode. Under a negative gate voltage, the out-of-plane electric field at the p-n interface can promote the separation of photoexcited electrons and holes, generating a significant optical gating effect, thereby producing a highly sensitive light sensing ability. After turning off the laser, the holes generated by light are stored in the second material layer 2H-MoTe 2 and exhibit persistent photoconductivity, endowing the device with the ability of non-volatile optical memory. Under zero or positive gate voltage, the reduction or even reversal of the interface electric field weakens the charge storage capacity, thereby switching the device to a visual synaptic mode with neuromorphic computing ability. By effectively regulating the light and dark currents and storage characteristics of the device through the top gate, a transistor that effectively integrates all the main functions of an artificial vision system is obtained.

[0018] On the one hand, the present invention also provides the application of the multimodal neuromorphic transistor in image recognition and classification. Through the integration with a synaptic neural network, the multifunctional neuromorphic transistor achieves accurate image recognition and classification with an accuracy rate as high as 95.26%.

[0019] The present invention relates to a multimodal neuromorphic transistor and a preparation method thereof. The structure is based on a vertical heterojunction of MoS 2 and MoTe 2 and integrates optical storage and optical synaptic functions; due to the existence of bipolar MoTe 2 in the vertical heterojunction, the optoelectronic transistor of the present invention exhibits excellent light response performance in Mode 1 (top gate voltage <0V) and can be used as an efficient photodetector and optical memory. Specifically, the device has a responsivity as high as about 6.515 kA / W to a 635 nm infrared laser, and the detectivity reaches about 3.92×10 14 Jones. In addition, due to its charge storage effect, the device can also be used as a non-volatile multi-level (>4 bits) optical memory with a storage time exceeding 10,000 seconds and a high write / erase ratio of up to 10 6 . In Mode 2 (top gate voltage ≥0V), the transistor transforms into a visual synaptic mode with neuromorphic computing ability, providing a new approach for simulating complex biological learning and synaptic plasticity. By combining synaptic plasticity with an artificial neural network (ANN), the present invention achieves accurate image recognition and classification with an accuracy rate of 95.26%; as a multimodal neuromorphic transistor, the present invention solves the challenges of integrated integration and manufacturing complexity of an artificial vision system, and the preparation process is simple, the technology is mature, the equipment is easy to obtain, and the cost is low, which is expected to promote the further development and commercial application of memory and opto-synaptic integrated vision chips. Brief Description of the Drawings

[0020] Figure 1 This is a schematic diagram of the device structure of the multimodal neuromorphic transistor of the present invention.

[0021] Figure 2 This is an optical microscope image of the device of the multimodal neuromorphic transistor of the present invention.

[0022] Figure 3 This is a graph showing the evolution of current over time after the same light pulse stimulation under different gate voltages for the multimodal neuromorphic transistor of the present invention.

[0023] Figure 4 These are two erasing and writing cycles of storing under a voltage and erasing under a mode 1 light pulse for the multimodal neuromorphic transistor of the present invention.

[0024] Figure 5 This is the synaptic plasticity exhibited by the multimodal neuromorphic transistor of the present invention for different power light pulses in mode 2.

[0025] Figure 6 These are the number of training cycles and the correct rate of image recognition when the multimodal neuromorphic transistor of the present invention is combined with a neural network in mode 2. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings of the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention. The experimental methods described in the following embodiments are conventional methods unless otherwise specified; the reagents and materials are commercially available from public sources unless otherwise specified.

[0027] Spatial relative terms such as "beneath", "below", "lower", "above", "upper" are used in this specification to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device in addition to those shown in the figures.

[0028] In addition, terms such as "first", "second" are used to describe each element, layer, region, section, etc., and are not intended to be limiting. The terms "having", "containing", "including", "comprising" are open-ended terms indicating the presence of the stated element or feature, but do not exclude additional elements or features unless the context clearly dictates otherwise.

[0029] The structure of the multimodal neuromorphic transistor of the present invention is as Figure 1 shown, MoS 2The channel layer and the gate electrode are arranged at intervals on SiO 2 / Si substrate, and MoS 2 The thickness of the channel layer is 20 nm to 40 nm. MoS 2 A 2H-MoTe 2 sensitization layer is arranged on the channel layer, and the thickness of the 2H-MoTe 2 sensitization layer is 25 nm to 55 nm; MoS 2 A heterojunction is formed between the channel layer and the 2H-MoTe 2 sensitization layer. An h-BN gate dielectric layer is arranged on the 2H-MoTe 2 sensitization layer, and the thickness of the h-BN gate dielectric layer is 5 nm to 15 nm; The source electrode and the drain electrode are respectively arranged at both ends of the MoS 2 channel layer. A graphene top gate is arranged on the h-BN gate dielectric layer, and the graphene top gate is connected to the gate electrode. The thickness of the graphene top gate is 5 nm to 20 nm; Among them, the source electrode and the drain electrode do not contact the 2H-MoTe 2 sensitization layer. The drain electrode is a Au electrode of ~50 nm, the source electrode is a Au electrode of ~50 nm, and the gate electrode is a Au electrode of ~50 nm

[0030] In order to make the neuromorphic transistor of the present invention clearer, the following embodiments introduce in detail the preparation method of the transistor.

[0031] First, ultrasonically clean the SiO 2 / Si substrate with acetone solution, ethanol, and deionized water respectively. The ultrasonic time for each time is 5 minutes. Acetone is used to remove residual glue and dust, ethanol is used to dissolve the residual acetone, and finally deionized water is used to remove the residual chemicals.

[0032] Then, adopt the mechanical exfoliation method. Use tape to stick the target single crystal to obtain a single crystal tape, and use PDMS to stick the MoS 2 single crystal tape to obtain MoS 2 / PDMS. Cover the PDMS with the adhered MoS 2 on the surface of the SiO 2 / Si substrate, and gently press for 45 seconds. Then, select a 20 - 40 nm thin layer of MoS 2 under an optical microscope as the current channel.

[0033] Then, use the ultraviolet laser lithography process to lithograph the source and drain electrodes at both ends of the MoS 2 and reserve the gate electrode at an appropriate blank distance. Use the electron beam evaporation and thermal evaporation processes to evaporate a 50 nm Au layer, and the evaporation rate is 0.01 nm / s. After the evaporation is completed, place it in acetone for ten minutes to dissolve the photoresist, so as to remove the excess Au layer. Then, obtain MoTe through the same mechanical exfoliation method 2Nanosheets, MoTe bonded with PDMS 2 Single crystal tape to obtain 2H-MoTe 2 / PDMS, containing MoS 2 One side of the PDMS faces up, and then a 25-45 nm thin layer of MoTe is selected under an optical microscope. 2 As the second layer material. After the material is selected, it is precisely covered on the MoS through the transfer platform. 2 In order to realize the gate control function, h-BN and graphene nanosheets were obtained by the same mechanical exfoliation method and then transferred to the MoTe covered nanosheets through the transfer platform. 2 / MoS 2 Finally, the graphene nanosheet is covered with MoTe through the gate dielectric. 2 The region is connected to the reserved gate, completing the construction of the phototransistor structure. The device is placed in a glove box and annealed in argon at 100°C for 30 minutes. The optical microscope image of the prepared transistor structure is shown in Figure 2. Figure 2 shown.

[0034] Figure 3 The It graph shows the removal of a 2s light pulse at different bias voltages from -5V to 0V. When the top gate voltage is -5V, the device exhibits a dark current as low as 197fA and persistent photoconductivity, indicating that it has strong light storage capabilities. As the top gate voltage increases to 0V, the dark current gradually increases, and the persistent photoconductivity disappears with the release of stored holes. As a non-volatile device at a top gate voltage of -5V, Figure 4 The optical writing and electrical erasing processes by applying optical pulses and top gate voltage pulses are shown. Figure 5 Shows the mode 2 (V TG ≥0V), the second material layer 2H-MoTe 2 Configured as n-type, the built-in electric field is weakened or reversed, thereby switching the device to a visual synaptic mode with neuromorphic computing capabilities. That is, by increasing the power of the light pulse, the value of the excitatory postsynaptic current gradually increases, and the retention time gradually prolongs, achieving synaptic plasticity behavior and switching between long-term plasticity and short-term plasticity. Figure 6 The invention shows that the invention can achieve accurate image recognition and classification with an accuracy rate of up to 95.26% through integration with synaptic neural networks. The invention integrates all three key components required for the visual system into a single device to obtain a multifunctional neuromorphic transistor.

[0035] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A multimodal neuromorphic transistor, characterized in that include: A MoS2 channel layer and a gate electrode are arranged at intervals on a SiO2 / Si substrate, a 2H-MoTe2 sensitizing layer is located on the MoS2 channel layer, a heterojunction is formed between the MoS2 channel layer and the 2H-MoTe2 sensitizing layer, an h-BN gate dielectric layer is located on the 2H-MoTe2 sensitizing layer, a source and a drain are arranged at both ends of the MoS2 channel layer, respectively, the source and the drain are not in contact with the 2H-MoTe2 sensitizing layer, a graphene top gate is arranged on the h-BN gate dielectric layer, and the graphene top gate is connected to the gate electrode.

2. A method for preparing a multimodal neuromorphic transistor, characterized in that: The following steps are involved: The MoS2 channel layer was transferred on SiO2 / Si substrate by mechanical exfoliation; The 2H-MoTe2 sensitizing layer is transferred to the middle region of the MoS2 channel layer by a mechanical stripping method, and the MoS2 channel layer and the 2H-MoTe2 sensitizing layer form a heterojunction; A source electrode and a drain electrode are prepared at both ends of the MoS2 channel layer, and a gate electrode is prepared on a SiO2 / Si substrate, wherein the source electrode and the drain electrode are not in contact with the 2H-MoTe2 sensitizing layer; The h-BN gate dielectric layer is transferred to the 2H-MoTe2 sensitizing layer and the MoS2 channel layer by mechanical stripping; A graphene thin layer is transferred onto the h-BN gate dielectric layer by a mechanical stripping method to form a graphene top gate, wherein the graphene top gate covers the h-BN gate dielectric layer on a projection surface, and the graphene top gate is connected to a gate electrode; Anneal in an inert atmosphere.

3. The multimodal neuromorphic transistor according to claim 1, or the preparation method according to claim 2, characterized in that: The thickness of the MoS2 channel layer is 20nm to 40nm.

4. The multimodal neuromorphic transistor according to claim 1, or the preparation method according to claim 2, characterized in that: The thickness of the 2H-MoTe2 sensitizing layer is 25nm-55nm.

5. The multimodal neuromorphic transistor according to claim 1, or the preparation method according to claim 2, characterized in that: The thickness of the h-BN gate dielectric layer is 5nm to 15nm.

6. The multimodal neuromorphic transistor according to claim 1, or the preparation method according to claim 2, characterized in that: The thickness of the graphene top gate is 5nm-20nm.

7. The preparation method according to any one of claims 2 to 6, characterized in that: The annealing temperature is 80-120° C., and the annealing time is 0.5-2 hours.

8. The multimodal neuromorphic transistor according to any one of claims 1 to 6, characterized in that: When a gate voltage less than 0V is applied to the graphene top gate, the multimodal neuromorphic transistor has light detection and light storage performance.

9. The multimodal neuromorphic transistor according to any one of claims 1 to 6, characterized in that: When a gate voltage greater than or equal to 0V is applied to the graphene top gate, the multimodal neuromorphic transistor has a visual synaptic mode.

10. Application of the multimodal neuromorphic transistor according to any one of claims 1 to 6 and claims 8 to 9 in image recognition and classification.

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