Laminated cell and preparation method thereof

Abstract

The invention discloses a laminated cell and a preparation method thereof. The laminated cell comprises a crystalline silicon bottom cell and a perovskite cell layer, the crystalline silicon bottom battery comprises a silicon substrate, and a first tunneling passivation structure is arranged on the front face of the silicon substrate. First areas and second areas are alternately arranged on the back face of the silicon substrate in the first direction. A second tunneling passivation structure, a passivation layer and a first electrode are sequentially arranged on the first region in the direction far away from the back surface of the silicon substrate; the perovskite cell layer comprises a perovskite layer, the front surface of the perovskite layer is provided with a third area, the third area is provided with a top cell electrode, and the projections of the first area and the third area along the thickness direction of the cell are partially overlapped. According to the invention, passivation contact of the emitter is realized by adopting the P-type doped polycrystalline silicon layer for the crystalline silicon bottom cell, compounding with slurry can be reduced, and good metal-semiconductor contact can be realized through the heavily doped P-type doped polycrystalline silicon layer.

Description

Technical Field

[0001] The present disclosure relates to the field of solar cell manufacturing, and particularly to a tandem cell and a method for preparing the same. Background Art

[0002] Tandem solar cells are a type of cell technology designed to improve solar conversion efficiency. Such cells typically consist of two or more photovoltaic layers that absorb different wavelengths of the solar spectrum and are stacked in series. Each photovoltaic layer is optimized to absorb a specific range of the solar spectrum, enabling more efficient utilization of the entire solar spectrum and thus enhancing the overall energy conversion efficiency.

[0003] In the preparation of tandem solar cells, pure silver paste or silver-aluminum paste is usually used. However, the following problems exist in the actual preparation process: If pure silver paste is used, there are few electrons in the emitter, and it is difficult to reduce silver ions, making it impossible to achieve good Schottky contact; if silver-aluminum paste is used, aluminum spikes can achieve good electrical conductivity between the metal and the silicon substrate. On the other hand, aluminum spikes will cause severe recombination, affecting the Voc of the cell. Therefore, the current industry uses the LECO process, which can prepare the emitter with pure silver paste and, through the bias voltage of the LECO process, enable sufficient electrons to accumulate at the Schottky contact of the emitter to reduce silver ions and achieve good Schottky contact. At the same time, the heat of the laser also helps the pure silver paste to achieve good Schottky contact.

[0004] However, for perovskite / silicon tandem cells, only one pole in the bottom cell structure has grid lines. Since the bias voltage of the LECO process requires the grid lines on both the front and back sides to be conductive, perovskite / silicon tandem cells cannot undergo the LECO process. Therefore, only the silver-aluminum paste used for printing before the LECO technology can be adopted, but as mentioned above, this method has a high recombination rate.

[0005] Therefore, how to reduce the recombination of the emitter and improve the Schottky contact of the emitter in tandem cells to enhance the efficiency of tandem cells is an urgent problem to be solved. Summary of the Invention

[0006] The present disclosure aims to provide a tandem cell and a method for preparing the same, solve the difficulty that the bottom cell of the tandem cell is difficult to undergo the LECO process, and provide a high cell conversion efficiency.

[0007] To solve the above technical problems, the technical solution adopted by the present disclosure is as follows:

[0008] A tandem cell includes a crystalline silicon bottom cell and a perovskite cell layer.

[0009] The crystalline silicon bottom cell includes a silicon substrate and opposite front and back sides.

[0010] The perovskite cell is stacked on the front side of the silicon substrate;

[0011] A first tunneling passivation structure is provided on the front side of the crystalline silicon bottom cell, and the first tunneling passivation structure includes an N-type doped polysilicon layer;

[0012] On the back side of the silicon substrate, a first region and a second region are alternately arranged along a first direction, and the first direction intersects with the thickness direction of the silicon substrate;

[0013] On the first region, a second tunneling passivation structure, a passivation layer, and a first electrode are sequentially provided along the direction away from the back side of the silicon substrate;

[0014] The second tunneling passivation structure includes a P-type doped polysilicon layer;

[0015] On the second region, a textured structure and a passivation layer are sequentially provided along the direction away from the back side of the silicon substrate;

[0016] The thickness of the N-type doped polysilicon layer is less than 100 nm;

[0017] The perovskite cell layer includes a perovskite layer. On the front side of the perovskite layer, a third region is provided, and a top cell electrode is provided on the third region. The projections of the first region and the third region in the cell thickness direction partially overlap.

[0018] Preferably, the perovskite cell layer is a p-i-n type inverted perovskite cell layer.

[0019] Preferably, the projected area of the first region is larger than the projected area of the third region. The first electrode on the back side of the crystalline silicon bottom cell forms a Poly-finger structure, that is, a local TOPCon structure, which can reduce the parasitic absorption of long-wavelength light by the P-type doped polysilicon layer in the non-metal contact region. And the Poly-finger corresponds to the top cell electrode. Due to the light shielding of the top cell electrode, the parasitic absorption of the P-type doped polysilicon layer in the metal contact region on the back side of the crystalline silicon bottom cell to long wavelengths can be further reduced, and the light loss caused by the parasitic absorption of the P-type doped polysilicon layer can be minimized.

[0020] Preferably, the first region is the metal contact region on the back side of the crystalline silicon bottom cell; the second region is the other region on the back side of the crystalline silicon bottom cell except the metal contact region; the third region is the metal contact region on the front side of the perovskite cell layer.

[0021] Preferably, the passivation layer includes a stack of alumina and silicon nitride.

[0022] Preferably, an electrical insulation layer is provided around the stacked cell.

[0023] This application also claims to protect a method for preparing a tandem cell for preparing the tandem cell described above, including preparing a perovskite cell layer on the front surface of a crystalline silicon bottom cell to complete the production of the tandem cell.

[0024] Preferably, it also includes laser edge isolation around the tandem cell to electrically insulate the periphery of the crystalline silicon bottom cell.

[0025] Preferably, the method for preparing the crystalline silicon bottom cell in the tandem cell includes the following steps:

[0026] Step S1, primary polishing: perform double-sided polishing on the silicon substrate.

[0027] Step S2, preparation of P-type doped polysilicon layer: adopt single insertion to prepare a P-type doped polysilicon layer and borosilicate glass on both sides of the silicon substrate.

[0028] Step S3, P1 laser: use P1 laser to pattern the back surface of the crystalline silicon bottom cell prepared in step S2, retain the borosilicate glass in the first region, and remove the borosilicate glass in the second region.

[0029] Step S4, front surface removal of borosilicate glass: pass the crystalline silicon bottom cell prepared in step S3 through a chain acid pickling machine to remove the borosilicate glass on the front surface of the crystalline silicon bottom cell.

[0030] Step S5, P1 cleaning: remove the P-type doped polysilicon layer on the crystalline silicon bottom cell without borosilicate glass protection through P1 cleaning.

[0031] Step S6, preparation of N-type doped polysilicon layer: adopt single insertion to prepare phosphosilicate glass and an N-type doped polysilicon layer with a thickness of less than 100 nm on both sides of the crystalline silicon bottom cell to reduce parasitic absorption.

[0032] Step S7, back surface removal of PSG: remove the phosphosilicate glass on the back surface of the crystalline silicon bottom cell.

[0033] Step S8, P2 cleaning: remove the N-type doped polysilicon layer on the back surface of the crystalline silicon bottom cell, and at the same time remove the borosilicate glass and phosphosilicate glass on both sides, and form a textured structure on the silicon substrate in the second region by means of trough alkaline texturing.

[0034] Step S9, ALD: deposit aluminum oxide on both sides of the crystalline silicon bottom cell; the aluminum oxide deposited on the front surface of the crystalline silicon bottom cell serves as a sacrificial layer for passivation. Since it is insulating, it needs to be removed. The hydrogen released during the deposition of aluminum oxide on the front surface, saturates the defects at the interface between the silicon substrate and the tunneling layer, and the dangling bonds of the silicon substrate, which can help passivate the front surface of the bottom cell.

[0035] Step S10, coating: deposit SiNx on the back surface of the crystalline silicon bottom cell.

[0036] Step S11, cleaning: removing aluminum oxide on the N-type doped polysilicon layer with hydrochloric acid;

[0037] Step S12, printing: printing Poly-finger on the P-type doped polysilicon layer to form the first electrode of the bottom cell.

[0038] Preferably, in step S2, before preparing the P-type doped polysilicon layer, a tunneling layer needs to be prepared on both sides of the crystalline silicon bottom cell.

[0039] Preferably, in step S2, replacing the single insertion with double insertion, the P-type doped polysilicon layer is only prepared on the back side of the crystalline silicon bottom cell.

[0040] Preferably, the method for preparing the N-type doped polysilicon layer with a thickness less than 100 nm in step S6 includes at least one of reducing the lamination time or adopting a thinning process.

[0041] Due to the application of the above technical solutions, the beneficial effects of the present disclosure compared with the prior art are as follows:

[0042] (1) By designing the P-type doped polysilicon layer structure, the present application improves the crystalline silicon bottom cell of the perovskite / crystalline silicon tandem cell. The P-type doped polysilicon layer is adopted for the crystalline silicon bottom cell to achieve the passivating contact of the emitter, solving the problem that the crystalline silicon bottom cell of the perovskite / crystalline silicon tandem cell is difficult to perform the LECO process. At the same time, a high passivation effect is provided, which can reduce its recombination with the paste and can also achieve good Schottky contact through the heavily doped P-type doped polysilicon layer.

[0043] (2) By correspondingly arranging the Poly-finger of the first electrode on the back side of the bottom cell and the top cell electrode, on the one hand, the P-type doped polysilicon layer in the non-metal contact area on the back side of the bottom cell is removed, and on the other hand, by using the light-shielding effect of the top cell electrode, the problem of optical loss caused by the parasitic absorption of the P-type doped polysilicon layer for long-wavelength light is further reduced, the process difficulty is reduced, and the production efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0045] Figure 1 It is a schematic structural diagram of a tandem cell in Embodiment 1 of the present disclosure;

[0046] Figure 2Schematic diagram of the preparation process of the crystalline silicon bottom cell in a tandem cell in Embodiment 2 of the present disclosure.

[0047] Explanation of reference numerals:

[0048] 1 - crystalline silicon bottom cell; 2 - perovskite cell layer; 3 - silicon substrate; 4 - N-type doped polysilicon layer; 5 - first region; 6 - second region; 7 - P-type doped polysilicon layer; 8 - Poly-finger; 9 - perovskite layer; 10 - third region; 11 - top cell electrode. Detailed implementation manners

[0049] In order to enable those skilled in the art to better understand the solution of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present disclosure.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so as to describe the embodiments of the present disclosure here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0051] In the present disclosure, the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the accompanying drawings. These terms are mainly used to better describe the present disclosure and its embodiments, and are not used to limit that the indicated devices, elements or components must have a specific orientation or be constructed and operated in a specific orientation.

[0052] Moreover, in addition to being able to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present disclosure can be understood according to specific circumstances.

[0053] It should be noted that, without conflict, the embodiments and features in the present disclosure may be combined with each other. The following will describe the present disclosure in detail with reference to the accompanying drawings and in combination with embodiments.

[0054] Embodiment 1

[0055] Please refer to Figure 1 , a stacked battery, comprising a crystalline silicon bottom cell 1 and a perovskite cell layer 2;

[0056] The crystalline silicon bottom cell 1 includes a silicon substrate 3 and opposite front and back surfaces; among them, by way of example, the silicon substrate is an N-type single-crystalline silicon substrate, and the N-type doping is doping with group VA elements such as phosphorus, arsenic or antimony, having a high carrier mobility (>1400 cm 2 / Vs) and a low bulk resistivity (0.001 - 10 Ω·cm).

[0057] The perovskite cell layer is stacked on the front surface of the silicon substrate 3; preferably, the perovskite cell layer is a p-i-n type inverted perovskite cell layer, where the p-i-n type inverted perovskite cell layer is composed of three parts. The bottom layer is a p-type hole transport layer for collecting and transporting holes; the middle is an intrinsic (i) perovskite light-absorbing layer that can absorb photons to generate electron-hole pairs; the top is an n-type electron transport layer responsible for collecting and transporting electrons.

[0058] A first tunneling passivation structure is provided on the front surface of the crystalline silicon bottom cell, and the first tunneling passivation structure includes an N-type doped polysilicon layer 4; by way of example, the first tunneling passivation structure on the front surface of the crystalline silicon bottom cell is composed of an N-type doped polysilicon layer (n-poly) and an ultra-thin silicon oxide layer between the silicon substrate and the N-type doped polysilicon. The ultra-thin oxide layer allows majority carriers electrons to tunnel into the polysilicon layer while blocking the recombination of minority carriers holes, thereby improving the open-circuit voltage and short-circuit current of the battery.

[0059] Preferably, the thickness of the N-type doped polysilicon layer is less than 100 nm, preferably <40 nm, for example, any value from 20 - 40 nm. In this embodiment, a thinner n-poly layer is prepared, which can reduce the parasitic absorption of n-poly. The thinner polysilicon layer reduces the absorption of incident light, enabling more photons to reach the base silicon of the battery, thereby generating more photo-generated carriers, and further increasing the short-circuit current (Isc). At the same time, the ultra-thin polysilicon layer can improve the contact performance of the battery and reduce the contact resistance (Rs), thereby reducing the loss during the power transmission process, improving the overall efficiency of the battery. Reducing parasitic absorption and optimizing the contact resistance contribute to increasing the fill factor (FF) of the battery, further enhancing the photoelectric conversion efficiency of the battery. In addition, the thinner polysilicon layer can reduce the recombination current density (J0) while maintaining good passivation performance, thereby reducing the carrier recombination rate and further increasing the open-circuit voltage (Voc) of the battery.

[0060] On the back surface of the silicon substrate, a first region 5 and a second region 6 are alternately arranged along a first direction, and the first direction intersects with the thickness direction of the silicon substrate;

[0061] On the first region, a second tunneling passivation structure, a passivation layer, and a first electrode 8 are sequentially arranged along a direction away from the back surface of the silicon substrate;

[0062] The second tunneling passivation structure includes a P-type doped polysilicon layer 9; Exemplarily, the second tunneling passivation structure is composed of a P-type doped polysilicon layer and an ultra-thin silicon oxide layer between the silicon substrate and the P-type doped polysilicon. The ultra-thin oxide layer allows majority carrier electrons to tunnel into the polysilicon layer while blocking minority carrier hole recombination, thereby improving the open-circuit voltage and short-circuit current of the battery;

[0063] On the second region, a textured structure and a passivation layer are sequentially arranged along a direction away from the back surface of the silicon substrate;

[0064] The perovskite battery layer includes a perovskite layer 9. On the front surface of the perovskite layer, a third region 10 is provided, and a top cell electrode 11 is arranged on the third region. Part of the projections of the first region and the third region in the battery thickness direction overlap.

[0065] Preferably, the projected area of the first region is larger than that of the third region. The back surface first electrode of the crystalline silicon bottom cell forms a Poly-finger structure, that is, the polysilicon in the non-metal contact area is removed or thinned, which can avoid or reduce the parasitic absorption of long-wavelength light by the P-type doped polysilicon layer in the non-metal contact area. And the Poly-finger corresponds to the top cell electrode. Due to the light shielding of the top cell electrode, the parasitic absorption of the P-type doped polysilicon layer in the back surface metal contact area of the crystalline silicon bottom cell to long-wavelength light can be further reduced, maximizing the reduction of light loss caused by the parasitic absorption of the P-type doped polysilicon layer.

[0066] Preferably, the first region is the metal contact area on the back surface of the crystalline silicon bottom cell; the second region is other regions on the back surface of the crystalline silicon bottom cell except the metal contact area; the third region is the metal contact area on the front surface of the perovskite battery layer.

[0067] Preferably, an electrical insulation layer is provided around the stacked cell. The insulation layer can be composed of insulating materials in the prior art, and this embodiment does not make any limitations.

[0068] Embodiment 2

[0069] This embodiment provides a method for manufacturing a stacked cell for manufacturing the stacked cell described in Embodiment 1, including preparing a perovskite battery layer on the front surface of the crystalline silicon bottom cell to complete the production of the stacked cell.

[0070] In one embodiment, the perovskite cell layer is a p-i-n type inverted perovskite cell layer. Exemplarily, its preparation process may include the preparation of a hole transport layer (HTL): placing the crystalline silicon cell in a vacuum coating equipment and depositing a layer of p-type semiconductor material, such as nickel oxide (NiO), as the hole transport layer on the surface of the crystalline silicon cell by physical vapor deposition methods, such as thermal evaporation or sputtering, and precisely controlling the deposition rate and thickness; the preparation of the perovskite light-absorbing layer: using the solution spin-coating method to drop the perovskite precursor solution on the crystalline silicon cell on which the hole transport layer has been deposited, and forming a uniform perovskite thin film by controlling the spin-coating speed, time, and solution concentration, and then annealing at a certain temperature to make the precursor fully react to form a high-quality perovskite light-absorbing layer; the preparation of the electron transport layer (ETL): preparing the electron transport layer on the perovskite layer by solution spin-coating or atomic layer deposition method. First, prepare a C60 thin film by evaporation method, and then deposit tin oxide (SnO) by atomic layer deposition technology, and control the process parameters to ensure the uniformity and performance of the thin film; the preparation of the electrode: depositing a metal electrode, such as evaporating gold (Au) or silver (Ag), etc. as the top electrode on the electron transport layer by thermal evaporation or other methods, and then performing packaging treatment, using packaging materials such as glass cover plates and encapsulation adhesives to seal the battery to prevent damage to the battery caused by moisture and oxygen, etc. It can be understood that other materials and other process flows can also be used for the preparation of the perovskite cell layer, and this application does not make any restrictions.

[0071] Preferably, it further includes laser edge isolation around the stacked cell to electrically insulate the periphery of the crystalline silicon bottom cell.

[0072] Please refer to Figure 2 , the preparation method of the crystalline silicon bottom cell in the stacked cell includes the following steps:

[0073] Step S1, primary polishing: perform double-sided polishing on the silicon substrate;

[0074] Step S2, preparation of P-type doped polysilicon layer: adopt single insertion to prepare a P-type doped polysilicon layer and borosilicate glass on both sides of the silicon substrate;

[0075] Step S3, P1 laser: perform battery backside patterning on the crystalline silicon bottom cell prepared in step S2 by using P1 laser, retain the borosilicate glass in the first region, and remove the borosilicate glass in the second region;

[0076] Step S4, front-side removal of borosilicate glass: pass the crystalline silicon bottom cell prepared in step S3 through a chain acid pickling machine to remove the borosilicate glass on the front side of the crystalline silicon bottom cell;

[0077] Step S5, P1 cleaning: remove the P-type doped polysilicon layer on the crystalline silicon bottom cell without borosilicate glass protection by P1 cleaning;

[0078] Step S6, Preparation of N-type doped polysilicon layer: By single insertion, phosphosilicate glass and an N-type doped polysilicon layer with a thickness less than 100 nm, preferably <40 nm, such as any value from 0 to 40 nm, are prepared on both sides of the crystalline silicon bottom cell to reduce parasitic absorption;

[0079] Step S7, Removal of PSG on the back: Remove the phosphosilicate glass on the back of the crystalline silicon bottom cell;

[0080] Step S8, P2 cleaning: Remove the N-type doped polysilicon layer on the back of the crystalline silicon bottom cell, and at the same time remove the borosilicate glass and phosphosilicate glass on both sides. A textured structure is formed on the silicon substrate in the second region by means of trough-type alkaline texturing;

[0081] Step S9, ALD: Deposit aluminum oxide on both sides of the crystalline silicon bottom cell; The aluminum oxide deposited on the front of the crystalline silicon bottom cell serves as a sacrificial layer for passivation. Since it is insulating, it needs to be removed. The hydrogen released during the deposition of aluminum oxide on the front, the defects at the interface between the saturated silicon substrate and the tunneling layer, and the dangling bonds at the bottom of the silicon substrate can help passivate the front of the bottom cell;

[0082] Step S10, Coating: Deposit SiNx on the back of the crystalline silicon bottom cell;

[0083] Step S11, Cleaning: Remove the aluminum oxide on the N-type doped polysilicon layer with hydrochloric acid;

[0084] Step S12, Printing: Print Poly-finger on the P-type doped polysilicon layer to form the positive electrode of the bottom cell.

[0085] Preferably, in step S2, before the preparation of the P-type doped polysilicon layer, a tunneling layer also needs to be prepared on both sides of the crystalline silicon bottom cell.

[0086] Preferably, the method for preparing the N-type doped polysilicon layer with a thickness less than 100 nm in step S6 includes at least one of reducing the deposition time or using a thinning process.

[0087] In other preferred embodiments, in step S2, the single insertion is replaced by double insertion, and only the P-type doped polysilicon layer is prepared on the back of the crystalline silicon bottom cell.

[0088] Finally, it should be noted that the above are only preferred embodiments of the present disclosure and are not used to limit the present disclosure. Although the present disclosure has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A laminated battery, characterized in that: Including crystalline silicon bottom cell and perovskite cell layer, The crystalline silicon bottom cell comprises a silicon substrate and a front side and a back side opposite to each other; The perovskite cell is stacked on the front side of the silicon substrate; A first tunnel passivation structure is disposed on the front side of the crystalline silicon bottom cell, wherein the first tunnel passivation structure comprises an N-type doped polysilicon layer; The back side of the silicon substrate is alternately arranged with a first area and a second area along a first direction, and the first direction intersects with a thickness direction of the silicon substrate; A second tunneling passivation structure, a passivation layer, and a first electrode are sequentially arranged on the first region in a direction away from the back side of the silicon substrate; The second tunnel passivation structure includes a P-type doped polysilicon layer; The second region is provided with a suede structure and a passivation layer in sequence along a direction away from the back side of the silicon substrate; The thickness of the N-type doped polysilicon layer is less than 100 nm; The perovskite battery layer comprises a perovskite layer, a third region is provided on the front side of the perovskite layer, a top battery electrode is provided on the third region, and projections of the first region and the third region along the battery thickness direction partially overlap.

2. A laminated battery as claimed in claim 1, characterized in that: The projection area of ​​the first region is greater than the projection area of ​​the third region.

3. A laminated battery as claimed in claim 1, characterized in that: The passivation layer includes a stack of aluminum oxide and silicon nitride.

4. A laminated battery as claimed in claim 1, characterized in that: An electrical insulation layer is arranged around the stacked battery.

5. A method for preparing a laminated battery, for preparing the laminated battery according to any one of claims 1 to 4, characterized in that: This includes preparing a perovskite cell layer on the front side of a silicon-based cell to complete the production of a stacked cell.

6. A method for preparing a laminated battery according to claim 5, characterized in that: The method also includes performing laser edge isolation around the stacked battery to electrically insulate the four sides of the crystalline silicon bottom battery.

7. The method for preparing a laminated battery according to claim 5, characterized in that: The method for preparing the crystalline silicon bottom cell in the stacked cell comprises the following steps: Step S1, primary polishing: double-sided polishing of the silicon substrate; Step S2, preparation of a P-type doped polysilicon layer: adopting a single insertion method to prepare a P-type doped polysilicon layer and borosilicate glass on both sides of a silicon substrate; Step S3, P1 laser: using P1 laser to pattern the back side of the crystalline silicon bottom cell prepared in step S2, retaining the borosilicate glass in the first area and removing the borosilicate glass in the second area; Step S4, removing borosilicate glass from the front: passing the crystalline silicon bottom battery prepared in step S3 through a chain pickling machine to remove the borosilicate glass on the front of the crystalline silicon bottom battery; Step S5, P1 cleaning: P1 cleaning is used to remove the P-type doped polysilicon layer on the crystalline silicon bottom cell that is not protected by borosilicate glass; Step S6, preparation of N-type doped polysilicon layer: adopting single insertion, preparing phosphorus silicon glass and N-type doped polysilicon layer with thickness less than 100nm on both sides of the crystalline silicon bottom cell; Step S7, removing PSG from the back: removing the phosphorus silicon glass on the back of the crystalline silicon bottom cell; Step S8, P2 cleaning: remove the N-type doped polysilicon layer on the back of the crystalline silicon bottom cell, and remove the borosilicate glass and phosphorus silicon glass on both sides, and form a velvet structure on the silicon substrate in the second area by trough alkali texturing; Step S9, ALD: depositing aluminum oxide on both sides of the crystalline silicon bottom cell; the aluminum oxide deposited on the front side of the crystalline silicon bottom cell is used as a sacrificial layer for passivation; Step S10, coating: depositing SiNx on the back side of the crystalline silicon bottom cell; Step S11, cleaning: using hydrochloric acid to remove the aluminum oxide on the N-type doped polysilicon layer; Step S12, printing: printing a Poly-finger on the P-type doped polysilicon layer to form a first electrode of the bottom cell.

8. The method for preparing a laminated battery according to claim 7, characterized in that: In step S2, before preparing the P-type doped polysilicon layer, a tunneling layer needs to be prepared on both sides of the crystalline silicon bottom cell.

9. The method for preparing a laminated battery according to claim 7, characterized in that: In step S2, the single insertion is replaced by the double insertion, and a P-type doped polysilicon layer is prepared only on the back side of the crystalline silicon bottom cell.

10. The method for preparing a laminated battery according to claim 7, characterized in that: The method for preparing the N-type doped polysilicon layer with a thickness less than 100 nm in step S6 includes at least one of reducing the deposition time or adopting a thinning process.

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