Electronic device

Abstract

The invention relates to an electronic device. The electronic device comprises a display panel, a display panel including a first region, a bending region at which the display panel is bent, a second region overlapping the first region, a first electrode arranged in a first direction in the first region, a second electrode arranged in a second direction in the first region and intersecting the first electrode, and a third electrode in the first region and overlapping the first electrode; a circuit board coupled to the display panel at the second area and including connecting lines arranged in the first direction and electrically connected to the third electrodes, respectively; the metal lower plate is arranged between the display panel and the circuit board; a first magnetic field shielding layer between the third electrode and the metal lower plate; and the second magnetic field shielding layer is arranged between the connecting line of the circuit board and the metal lower plate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0167244 filed on November 27, 2023, Korean Patent Application No. 10-2023-0192905 filed on December 27, 2023, and Korean Patent Application No. 10-2024-0098453 filed on July 25, 2024, filed in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] The present disclosure herein relates to an electronic device capable of sensing an input of a pen. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, laptop computers, navigators, game consoles, etc. include display devices for displaying images. In addition to common input methods such as buttons, keyboards, mice, etc., such electronic devices may include a sensor layer (or input sensor) that can provide a touch-based input method that allows users to easily, intuitively and conveniently input information or commands. The sensor layer can sense the user's touch or pressure. For users who are familiar with using writing tools to input information or specific applications (e.g., applications for mapping or drawing), there is an increasing demand for fine touch input using a pen. Summary of the invention

[0005] The present disclosure provides an electronic device capable of sensing an input of a pen.

[0006] One or more embodiments of the present disclosure provide an electronic device, which includes: a display panel, including a first area, a curved area at which the display panel is curved, a second area overlapping the first area, a first electrode arranged in a first direction in the first area, a second electrode arranged in a second direction crossing the first direction and crossing the first electrode in the first area, and a third electrode in the first area and overlapping the first electrode; a circuit board connected to the display panel at the second area and including connecting lines arranged in the first direction and electrically connected to the third electrodes, respectively; a metal lower plate between the display panel and the circuit board; a first magnetic field shielding layer between the third electrode of the display panel and the metal lower plate; and a second magnetic field shielding layer between the connecting lines of the circuit board and the metal lower plate.

[0007] The connection line may be electrically connected to the third electrode at the first region, at the bent region, or at the second region, respectively.

[0008] The display panel may further include a display layer and a sensor layer including first annular traces electrically connected to first ends of the third electrodes and arranged in the first direction, and second annular traces electrically connected to second ends of the third electrodes, respectively.

[0009] The first loop traces may be spaced apart from connection lines respectively electrically connected thereto in the first direction.

[0010] The second annular trace may include a first line portion electrically connected to the third electrode, a second line portion extending from a first end of the first line portion in the second direction, and a third line portion extending from the second end of the first line portion in the second direction, wherein the second line portion, the first annular trace, and the third line portion are arranged sequentially in the first direction.

[0011] At least one of the display panel and the circuit board may further include bridge lines electrically connecting the connection lines and the third electrodes, respectively.

[0012] The bridging line may extend in a first direction.

[0013] The bridging line may be in the first region.

[0014] The first region may include a sensing region for sensing an external input and a peripheral region adjacent to the sensing region, wherein at least some of the bridge lines are in the peripheral region.

[0015] The bridging line may be separated from the bending region.

[0016] Some of the bridge lines may be in the first region, wherein other of the bridge lines are in the circuit board.

[0017] One or more embodiments of the present disclosure provide an electronic device, which includes: a display panel, including a first area, a curved area at which the display panel is curved, a second area overlapping the first area, a first electrode portion arranged in a first direction in the first area, a second electrode portion arranged in the first direction in the curved area and electrically connected to the first electrode portion, and a third electrode portion arranged in the first direction in the second area and electrically connected to the second electrode portion; a circuit board, connected to the display panel at the second area, and including a connecting line arranged in the first direction and electrically connected to the third electrode portion; a metal lower plate, between the first electrode portion and the connecting line; a first magnetic field shielding layer, between the first electrode portion and the metal lower plate; and a second magnetic field shielding layer, between the connecting line and the metal lower plate.

[0018] The connection lines may have an arrangement order in the first direction that is different from an arrangement order in the first direction of the third electrode parts respectively connected thereto.

[0019] The arrangement order of the third electrode portions may be opposite to the arrangement order of the connection lines.

[0020] One or more embodiments of the present disclosure provide an electronic device, which includes: a display panel, including a first area, a curved area at which the display panel is curved, a second area overlapping the first area, a first electrode portion arranged in a first direction in the first area, a second electrode portion arranged in the first direction in the curved area and electrically connected to the first electrode portion, and a third electrode portion arranged in the first direction in the second area and electrically connected to the second electrode portion; a circuit board, connected to the display panel at the second area, and including a connecting line electrically connected to the third electrode portion at a first layer, an extended connecting line connected to the connecting line at a second layer different from the first layer, a first conductive shielding layer between the first electrode portion and the connecting line, and a second conductive shielding layer between the connecting line and the extended connecting line; a metal lower plate, between the display panel and the circuit board; and a magnetic field shielding layer, between the display panel and the metal lower plate.

[0021] The first conductive shielding layer or the second conductive shielding layer may be grounded.

[0022] The first conductive shield layer or the second conductive shield layer may be configured to receive a constant voltage.

[0023] The circuit board may be below the display panel at the first region, and may further include a first conductive layer having a connection line and a second conductive layer having an extended connection line, with the first conductive layer being between the second conductive layer and the first region of the display panel.

[0024] The first conductive layer may be below the first conductive shielding layer and may partially overlap the second area of ​​the display panel.

[0025] The second conductive layer may be below the second conductive shielding layer and may partially overlap the second region of the display panel.

[0026] One or more embodiments of the present disclosure provide an electronic device, which includes: a substrate, including a first area, a bent area where the substrate is bent, and a second area overlapping the first area; a circuit layer, which is above the substrate and includes a transistor; a light-emitting element layer, which is above the circuit layer and includes a light-emitting element electrically connected to the transistor; a sensor layer, which is above the light-emitting element layer and includes electrodes arranged in a first direction in the first area; a sensor driver, configured to use the electrodes to generate a magnetic field for charging a pen including an RLC resonant circuit; a circuit board, which is connected to the substrate at the second area and includes a connecting line electrically connected to the electrode; a metal lower plate, which is between the electrode and the connecting line; a first magnetic field shielding layer, which is between the electrode and the metal lower plate; and a second magnetic field shielding layer, which is between the connecting line and the metal lower plate.

[0027] The sensor driver may be configured to selectively operate in a first mode in which the sensor layer is driven to sense a touch input or in a second mode in which the sensor layer is driven to sense a pen input, the second mode comprising a charging drive mode.

[0028] The sensor layer may be configured to sense the pen input by applying a first signal to at least one of the electrodes and by applying a second signal to at least another one of the electrodes.

[0029] The sensor layer may further include a first mesh line having a first width, a second mesh line above the first mesh line and having a second width equal to or greater than the first width, and an intermediate insulating layer between the first mesh line and the second mesh line.

[0030] The connection lines may have an arrangement order in the first direction that is different from an arrangement order in the first direction of the electrodes respectively connected thereto.

[0031] The electronic device may further include bridge wires in the first region of the substrate and / or in the circuit board, the bridge wires electrically connecting the electrodes to the connection wires, respectively.

[0032] The bridging line may be within a finite distance from a bending edge defined in the bending region.

[0033] The electronic device may further include a display driver in the second area and configured to control the circuit layer, wherein the circuit board overlaps the first area.

[0034] The second magnetic field shielding layer may overlap the circuit board and the second region of the substrate.

[0035] The surface area of ​​the first magnetic field shielding layer may be equal to or greater than the surface area of ​​the second magnetic field shielding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0037] Figure 1A is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0038] Figure 1B is a rear perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0039] Figure 2 is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0040] Figure 3 is a perspective view of an electronic device according to one or more embodiments of the present disclosure;

[0041] Figure 4 is a schematic cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0042] Figure 5 is a view for explaining the operation of the electronic device according to one or more embodiments of the present disclosure;

[0043] Fig. 6A is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure;

[0044] Figure 6B is a cross-sectional view of a sensor layer according to one or more embodiments of the present disclosure;

[0045] Figure 7 is a plan view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0046] Fig. 8A is a plan view showing a first conductive layer of a sensing unit according to one or more embodiments of the present disclosure;

[0047] Figure 8B is a plan view showing a second conductive layer of a sensing unit according to one or more embodiments of the present disclosure;

[0048] Fig. 9 According to one or more embodiments of the present disclosure, Fig. 8A and Figure 8B A cross-sectional view of the sensor layer taken along line II';

[0049] Fig. 10A yes Fig. 8A An enlarged plan view of area AA';

[0050] Fig. 10B yes Figure 8B An enlarged plan view of area BB';

[0051] Fig.11 is a view showing the operation of the sensor driver according to one or more embodiments of the present disclosure;

[0052] Fig.12 is a view showing the operation of the sensor driver according to one or more embodiments of the present disclosure;

[0053] Fig.13 is a plan view for explaining a first mode according to one or more embodiments of the present disclosure;

[0054] Fig.14 is a plan view for explaining a second mode according to one or more embodiments of the present disclosure;

[0055] Fig.15A is a diagram showing a waveform of a first signal according to one or more embodiments of the present disclosure;

[0056] Fig. 15B is a diagram showing a waveform of a second signal according to one or more embodiments of the present disclosure;

[0057] Fig.16 is a view of a pen according to one or more embodiments of the present disclosure;

[0058] Fig.17A is a view for explaining the operation of the pen according to one or more embodiments of the present disclosure;

[0059] Fig. 17B is a view for explaining the operation of a sensor layer according to one or more embodiments of the present disclosure;

[0060] Fig.18A is a plan view for explaining a second mode according to one or more embodiments of the present disclosure;

[0061] Fig.18B is a view for explaining a second mode based on a sensing unit according to one or more embodiments of the present disclosure;

[0062] Fig.19 is a plan view showing a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0063] Fig. 20 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0064] Fig.21 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0065] Fig. 22 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0066] Fig.23 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0067] Fig.24 is a view of a display panel and a circuit board according to one or more embodiments of the present disclosure;

[0068] Fig.25Ais a view showing a result of simulating a magnetic field on a surface of a display panel according to a comparative example of the present disclosure;

[0069] Fig.25B is a view showing a result of simulating a magnetic field on a surface of a display panel according to an embodiment of the present disclosure;

[0070] Fig.26 According to one or more embodiments of the present disclosure, Fig.19 A cross-sectional view of the electronic device taken along line II-II';

[0071] Fig. 27 According to one or more embodiments of the present disclosure, Fig.19 A cross-sectional view of the electronic device taken along line II-II';

[0072] Fig.28 According to one or more embodiments of the present disclosure, Fig.19 A cross-sectional view of the electronic device taken along line II-II';

[0073] Fig.29 is a cross-sectional view of a circuit board according to one or more embodiments of the present disclosure;

[0074] Fig. 30A is a cross-sectional view of a circuit board according to one or more embodiments of the present disclosure;

[0075] Fig. 30B is a plan view of a circuit board according to one or more embodiments of the present disclosure;

[0076] Fig.31 is a cross-sectional view of a circuit board according to one or more embodiments of the present disclosure;

[0077] Fig.32A is a plan view of a first shielding layer according to one or more embodiments of the present disclosure;

[0078] Fig.32B is a plan view of a first line layer according to one or more embodiments of the present disclosure;

[0079] Fig.32C is a plan view of a second shielding layer according to one or more embodiments of the present disclosure;

[0080] Fig.32D is a plan view of a third shielding layer according to one or more embodiments of the present disclosure;

[0081] Fig.32E is a plan view of a second line layer according to one or more embodiments of the present disclosure; and

[0082] Fig.32F is a plan view of a fourth shielding layer according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0083] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing them. The embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0084] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. When describing an embodiment, the use of "can", "may", or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents, and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in its entirety, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0085] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading is often provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise indicated.

[0086] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Thus, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are anticipated. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but rather include deviations in shapes due to, for example, manufacturing.

[0087] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0088] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper", "upper side" etc. may be used herein to describe the relationship between an element or feature and another (multiple) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as being "below", "below" or "below" other elements or features will then be oriented to be "above" other elements or features. Therefore, the exemplary terms "below" and "below" may include both the orientations of the upper and lower parts. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being arranged "on" a second portion, this means that the first portion is arranged at the upper or lower side of the second portion, without being limited to its upper side based on the direction of gravity.

[0089] In addition, the phrase "in a plan view" means observing the object portion from above, and the phrase "in a schematic cross-sectional view" means observing the schematic cross-section intercepted by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" can include stacking, facing or facing, extending throughout..., covering or partially covering, or any other suitable term as will be understood and appreciated by ordinary technicians in the art. The statement "non-overlapping" can include meanings such as "separated from..." or "set side by side with..." or "offset with..." and any other suitable equivalents as will be understood and appreciated by ordinary technicians in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, although still facing each other.

[0090] It will be understood that when an element, layer, region, or component is referred to as being "formed" "on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may refer collectively to direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, capacitors, etc. When describing the embodiments, unless explicitly described as directly connected, the expression of connection means electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component or on another component without intermediate components.

[0091] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the situation that the part is "directly" "below" another part, but also includes the situation that there is another other part between the part and the other part. On the other hand, other expressions such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." that describe the relationship between components can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0092] For the purposes of this disclosure, expressions such as "at least one of..." or "any of..." or "one or more of...", when following a list of elements, modify the entire list of elements, rather than modifying individual elements in the list. For example, "at least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of," "one of...", and other prepositional phrases, when following a list of elements, modify the entire list of elements, rather than modifying individual elements in the list.

[0093] It will be understood that, although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or sections in this article, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section, without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish elements of different categories or different groups in this article. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0094] In the example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0095] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "include", "comprise", "have", "have", "include" and "include" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0096] When one or more embodiments can be implemented differently, the specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in the reverse order of the described order.

[0097] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of ±5% of the corresponding value. In view of the measurement discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within the acceptable deviation range of the particular value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure".

[0098] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such in this article.

[0099] The terms "part" and "unit" refer to software components or hardware components that perform a specific function. Hardware components may include, for example, field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Software components may refer to executable code in an addressable storage medium and / or data used by the executable code. Thus, software components may be, for example, object-oriented software components, class components and task components, processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables.

[0100] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0101] Figure 1A is a perspective view of an electronic device 1000 according to one or more embodiments of the present disclosure. Figure 1B is a rear perspective view of an electronic device 1000 according to one or more embodiments of the present disclosure.

[0102] refer to Figure 1A and Figure 1B , the electronic device 1000 may be a device activated according to an electrical signal. For example, the electronic device 1000 may display an image and sense an input applied from the outside. The external input may be an input from a user. The user's input may include various types of external inputs, such as a part of the user's body, a pen PN, light, heat, or pressure.

[0103] The electronic device 1000 may include a first display panel DP1 and a second display panel DP2. The first display panel DP1 and the second display panel DP2 may be separate panels separated from each other. The first display panel DP1 may be referred to as a main display panel, and the second display panel DP2 may be referred to as an auxiliary display panel, or referred to as an external display panel.

[0104] The first display panel DP1 may include a first display portion DA1-F, and the second display panel DP2 may include a second display portion DA2-F. The surface area of ​​the second display panel DP2 may be smaller than that of the first display panel DP1. The surface area of ​​the first display portion DA1-F may be larger than that of the second display portion DA2-F to correspond to the size of each of the first display panel DP1 and the second display panel DP2.

[0105] In a state in which the electronic device 1000 is unfolded, the first display portion DA1-F may have a plane substantially parallel to the first direction DR1 and the second direction DR2. A thickness direction of the electronic device 1000 may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Therefore, a front surface (or top surface) and a rear surface (or bottom surface) of each of the members constituting the electronic device 1000 may be defined based on the third direction DR3.

[0106] The first display panel DP1 or the first display portion DA1-F may include a foldable and expandable folding area FA and a plurality of non-folding areas NFA1 and NFA2 spaced apart from each other, and the folding area FA is between the plurality of non-folding areas NFA1 and NFA2. The second display panel DP2 may overlap one of the plurality of non-folding areas NFA1 and NFA2. For example, the second display panel DP2 may overlap the first non-folding area NFA1.

[0107] The display direction of the first image IM1a displayed on a portion of the first display panel DP1 (for example, in the second non-folding area NFA2) and the display direction of the second image IM2a displayed on the second display panel DP2 may be opposite to each other. For example, the first image IM1a may be displayed in a third direction DR3, and the second image IM2a may be displayed in a fourth direction DR4 opposite to the third direction DR3.

[0108] In one or more embodiments of the present disclosure, the folding area FA may be bent relative to a folding axis extending in a direction parallel to the long side of the electronic device 1000, for example, extending in a direction parallel to the second direction DR2. When the electronic device 1000 is folded, the folding area FA may have a curvature and a radius of curvature (for example, a predetermined curvature and radius of curvature). The first non-folding area NFA1 and the second non-folding area NFA2 may face each other, and the electronic device 1000 may be folded inwardly so that the first display portion DA1-F is not exposed to the outside.

[0109] In one or more embodiments of the present disclosure, the electronic device 1000 may be folded outwardly so that the first display portion DA1-F is exposed to the outside. In one or more embodiments of the present disclosure, the electronic device 1000 may be capable of being both folded inwardly and outwardly from an unfolded state, but is not limited thereto.

[0110] exist Figure 1A, an example is shown in which one folding area FA is defined in the electronic device 1000, but the present disclosure is not limited thereto. For example, the electronic device 1000 may define a plurality of folding axes and a plurality of folding areas corresponding thereto, and the electronic device 1000 may be in an inner folding, outer folding or unfolding state at each of the folding areas.

[0111] According to one or more embodiments of the present disclosure, even if at least one of the first display panel DP1 and the second display panel DP2 does not include a digitizer, at least one of the first display panel DP1 and the second display panel DP2 can sense the input of the pen PN. Therefore, since the digitizer for sensing the pen PN is omitted, the increase in thickness, the increase in weight, and the decrease in flexibility of the electronic device 1000 due to the addition of the digitizer can be avoided. Therefore, not only the first display panel DP1 but also the second display panel DP2 can be designed to sense the pen PN.

[0112] Figure 2 is a perspective view of an electronic device 1000 - 1 according to one or more embodiments of the present disclosure. Figure 3 is a perspective view of an electronic device 1000 - 2 according to one or more embodiments of the present disclosure.

[0113] Figure 2 An example is shown in which the electronic device 1000 - 1 is a mobile phone and the electronic device 1000 - 1 may include a display panel DP. Figure 3 An example is shown in which the electronic device 1000-2 is a laptop computer and the electronic device 1000-2 may include a display panel DP. Figure 3 is a perspective view of electronic device 1000-2, but Figure 3 The coordinate axes included in are displayed based on the display panel DP in the electronic device 1000-2.

[0114] In one or more embodiments of the present disclosure, the display panel DP may sense an input applied from the outside. The external input may be an input of a user. The input of the user may include various types of external inputs, such as a part of the user's body, a pen PN (see Figure 1A ), light, heat or pressure.

[0115] According to one or more embodiments of the present disclosure, even if the display panel DP does not include a digitizer, the display panel DP can sense the input of the pen PN. Therefore, since the digitizer for sensing the pen PN is omitted, the increase in thickness, weight, and reduction in flexibility of the electronic device 1000-1 or 1000-2 due to the addition of the digitizer may not occur.

[0116] exist Figure 1AIn the embodiment, the foldable electronic device 1000 may be shown as an example, and in Figure 2 In the embodiment, the bar-type electronic device 1000-1 may be shown as an example. However, the present disclosure to be described below is not limited thereto. For example, the description described below may be applied to various electronic devices, such as a rollable electronic device, a slidable electronic device, and a stretchable electronic device.

[0117] Figure 4 is a schematic cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure.

[0118] refer to Figure 4 , the display panel DP may include a display layer 100 and a sensor layer 200 .

[0119] The display layer 100 may be configured to substantially generate an image. The display layer 100 may be an emissive display layer. For example, the display layer 100 may be an organic light-emitting display layer, an inorganic light-emitting display layer, an organic-organic light-emitting display layer, a quantum dot display layer, a micro-LED display layer, or a nano-LED display layer. The display layer 100 may include a base layer 110, a circuit layer 120, a light-emitting element layer 130, and an encapsulation layer 140.

[0120] The base layer 110 may be a member providing a base surface on which the circuit layer 120 is positioned. The base layer 110 may have a single layer structure or a multi-layer structure. The base layer 110 may be a glass substrate, a metal substrate, a silicon substrate, or a polymer substrate, but the present disclosure is not particularly limited thereto.

[0121] The circuit layer 120 may be located on the base layer 110 (e.g., "on" may mean "above" as used herein). The circuit layer 120 may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base layer 110 in a manner such as coating or vapor deposition, and then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a plurality of photolithography processes.

[0122] The light emitting element layer 130 may be located on the circuit layer 120. The light emitting element layer 130 may include a light emitting element. For example, the light emitting element layer 130 may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED or a nano-LED.

[0123] The encapsulation layer 140 may be located on the light emitting element layer 130. The encapsulation layer 140 may protect the light emitting element layer 130 from moisture, oxygen, and impurities such as dust particles.

[0124] The sensor layer 200 may be located on the display layer 100. The sensor layer 200 may sense an external input applied from the outside. The sensor layer 200 may be an integrated sensor continuously formed during a process of manufacturing the display layer 100, or the sensor layer 200 may be an external sensor attached to the display layer 100. The sensor layer 200 may be referred to as a sensor, an input sensing layer, an input sensing panel, or an electronic device for sensing input coordinates.

[0125] According to one or more embodiments of the present disclosure, the sensor layer 200 can sense both inputs from a passive input unit (such as a user's body) and an input device that generates a magnetic field having a resonant frequency (e.g., a predetermined resonant frequency). The input device can be referred to as a pen, an input pen, a magnetic pen, a stylus, or an electromagnetic resonance pen.

[0126] Figure 5 is a view for explaining the operation of the electronic device 1000 according to one or more embodiments of the present disclosure.

[0127] refer to Figure 5 , the electronic device 1000 may include a display layer 100, a sensor layer 200, a display driver 100C (e.g., a first driver circuit), a sensor driver 200C (e.g., a second driver circuit), a main driver 1000C (e.g., a third driver circuit), and a power circuit 1000P.

[0128] The sensor layer 200 may sense a first input 2000 or a second input 3000 applied from the outside. Each of the first input 2000 and the second input 3000 may be an input unit capable of providing a capacitance change of the sensor layer 200, or an input unit capable of causing an induced current in the sensor layer 200. For example, the first input 2000 may be a passive input unit such as a user's body. The second input 3000 may be an input using a pen PN or a radio frequency integrated circuit (RFIC) tag. For example, the pen PN may be a passive pen or an active pen.

[0129] In one or more embodiments of the present disclosure, the pen PN may be a device that generates a magnetic field having a resonant frequency (e.g., a predetermined resonant frequency). The pen PN may be configured to transmit an output signal based on electromagnetic resonance. The pen PN may be referred to as an input device, an input pen, a magnetic pen, a stylus, or an electromagnetic resonance pen.

[0130] The pen PN may include an RLC resonant circuit, and the RLC resonant circuit may include an inductor L and a capacitor C. In one or more embodiments of the present disclosure, the RLC resonant circuit may be a variable resonant circuit whose resonant frequency varies. In this case, the inductor L may be a variable inductor, and / or the capacitor C may be a variable capacitor, but neither of them is particularly limited thereto.

[0131] The inductor L can generate a current by a magnetic field generated in the electronic device 1000 (e.g., the sensor layer 200). However, the present disclosure is not particularly limited to this. For example, if the pen PN operates as an active type, the pen PN can generate a current even if it does not receive a magnetic field from the outside. The generated current can be transferred to the capacitor C. The capacitor C can charge the current input from the inductor L, and can release the charged current to the inductor L. Thereafter, the inductor L can emit a magnetic field at a resonant frequency. Due to the magnetic field emitted by the pen PN, the induced current can flow in the sensor layer 200, and the induced current can be transmitted to the sensor driver 200C as a received signal (or a sensing signal, a signal, etc.).

[0132] The main driver 1000C may control the overall operation of the electronic device 1000. For example, the main driver 1000C may control the operation of the display driver 100C and the sensor driver 200C. The main driver 1000C may include at least one microprocessor and may also include a graphics controller. The main driver 1000C may be referred to as an application processor, a central processing unit, or a main processor.

[0133] The display driver 100C may control the display layer 100. The display driver 100C may receive image data and control signals from the main driver 1000C. The control signals may include various signals. For example, the control signals may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock signal, and a data enable signal.

[0134] The sensor driver 200C may control the sensor layer 200. The sensor driver 200C may receive a control signal from the main driver 1000C. The control signal may include a clock signal of the sensor driver 200C. In addition, the control signal may also include a mode determination signal that determines a driving mode of the sensor driver 200C and the sensor layer 200.

[0135] The sensor driver 200C may be implemented as an integrated circuit (IC) and may be electrically connected to the sensor layer 200. For example, the sensor driver 200C may be directly mounted on an area (e.g., a predetermined area) of the display panel, or may be mounted on a separate printed circuit board using a chip on film (COF) method and may be electrically connected to the sensor layer 200.

[0136] The sensor driver 200C and the sensor layer 200 may selectively operate in a first mode or a second mode. For example, the first mode may be a mode for sensing a touch input (e.g., the first input 2000). The second mode may be a mode for sensing a pen PN input (e.g., the second input 3000). The first mode may be referred to as a touch sensing mode, and the second mode may be referred to as a pen sensing mode.

[0137] The switching between the first mode and the second mode can be implemented in various ways. For example, the sensor driver 200C and the sensor layer 200 are driven in the first mode and the second mode in time division, and the first input 2000 and the second input 3000 can be sensed. Alternatively, the switching between the first mode and the second mode can occur due to the user's selection or the user's corresponding action (or input), or one of the first mode and the second mode can be activated or deactivated by activating or deactivating the corresponding application, or can be switched from one to the other. Alternatively, if the first input 2000 is sensed while the sensor driver 200C and the sensor layer 200 are operating alternately in the first mode and the second mode, the sensor driver 200C and the sensor layer 200 can remain in the first mode, and if the second input 3000 is sensed, the sensor driver 200C and the sensor layer 200 can remain in the second mode.

[0138] The sensor driver 200C may calculate input coordinate information based on the signal received from the sensor layer 200, and may provide a coordinate signal having the input coordinate information to the main driver 1000C. The main driver 1000C may perform an operation corresponding to the user input based on the coordinate signal. For example, the main driver 1000C may operate the display driver 100C to display a new application image on the display layer 100.

[0139] The power circuit 1000P may include a power management integrated circuit (PMIC). The power circuit 1000P may generate a plurality of driving voltages for driving the display layer 100, the sensor layer 200, the display driver 100C, and the sensor driver 200C. For example, the plurality of driving voltages may include a gate high voltage, a gate low voltage, a first driving voltage, a second driving voltage, an initialization voltage, etc., but the present disclosure is not particularly limited thereto.

[0140] Fig. 6A is a cross-sectional view of a display panel DP according to one or more embodiments of the present disclosure.

[0141] refer to Fig. 6A, at least one buffer layer BFL may be located on the top surface of the base layer 110. The buffer layer BFL may improve the bonding force between the base layer 110 and the semiconductor pattern. The buffer layer BFL may be provided as a multilayer. Alternatively, the display layer 100 may further include a barrier layer. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0142] The semiconductor patterns SC, AL, DR, and SCL may be located on the buffer layer BFL. Each of the semiconductor patterns SC, AL, DR, and SCL may include polycrystalline silicon. However, each of the semiconductor patterns SC, AL, DR, and SCL is not limited thereto and may include amorphous silicon, low temperature polycrystalline silicon, or oxide semiconductor.

[0143] Fig. 6A Only some semiconductor patterns SC, AL, DR and SCL are shown, and other semiconductor patterns may also be located in one or more other regions. The semiconductor patterns SC, AL, DR and SCL may be arranged in a corresponding arrangement throughout the pixel. Depending on whether the semiconductor patterns SC, AL, DR and SCL are doped, the semiconductor patterns SC, AL, DR and SCL may have different electrical characteristics. The semiconductor patterns SC, AL, DR and SCL may include a first region SC, DR and SCL having high conductivity and a second region AL having low conductivity. The first region SC, DR and SCL may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a doped region doped with a P-type dopant, and the N-type transistor may include a doped region doped with an N-type dopant. The second region AL may be a non-doped region, or may be doped with a concentration lower than that of the first region SC, DR and SCL.

[0144] The conductivity of the first region SC, DR and SCL may be greater than that of the second region AL and may be substantially used as an electrode or a signal line. The second region AL may substantially correspond to the active region AL (or channel) of the transistor 100PC. In other words, a portion AL of the semiconductor pattern SC, AL, DR and SCL may be the active region AL of the transistor 100PC, and the other portions SC and DR may be the source region SC or the drain region DR of the transistor 100PC, respectively, and another portion SCL may be a connection electrode or a connection signal line SCL.

[0145] Each of the pixels may have an equivalent circuit including a plurality of transistors, at least one capacitor, and at least one light emitting element. The equivalent circuit diagram of the pixel may be modified in various forms. Fig. 6A , one transistor 100PC and one light emitting element 100PE provided in a pixel are shown as an example.

[0146] The source region SC, the active region AL, and the drain region DR of the transistor 100PC may be formed of the semiconductor patterns SC, AL, DR, and SCL. The source region SC and the drain region DR may extend from the active region AL in opposite directions, respectively, in cross section. Fig. 6A A portion of a connection signal line SCL formed of the semiconductor patterns SC, AL, DR, and SCL is shown. In one or more embodiments, the connection signal line SCL may be connected to the drain region DR of the transistor 100PC on a plane.

[0147] The first insulating layer 10 may be located on the buffer layer BFL. The first insulating layer 10 may overlap with a plurality of pixels in common and may cover the semiconductor patterns SC, AL, DR and SCL. The first insulating layer 10 may include an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and hafnium oxide. The first insulating layer 10 may include a single-layer silicon oxide layer. The insulating layer other than the first insulating layer 10 of the circuit layer 120 to be described later may also be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but is not limited thereto.

[0148] The gate GT of the transistor 100PC is located on the first insulating layer 10. The gate GT may be a part of the metal pattern. The gate GT overlaps the active area AL. The gate GT may be used as a mask in the process of doping or reducing the semiconductor patterns SC, AL, DR, and SCL.

[0149] The second insulating layer 20 may be located on the first insulating layer 10 to cover the gate electrode GT. The second insulating layer 20 may overlap with the pixel in common. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0150] The third insulating layer 30 may be located on the second insulating layer 20. The third insulating layer 30 may have a single layer structure or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0151] The first connection electrode CNE1 may be located on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0152] The fourth insulating layer 40 may be located on the third insulating layer 30. The fourth insulating layer 40 may be a single silicon oxide layer. The fifth insulating layer 50 may be located on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer.

[0153] The second connection electrode CNE2 may be located on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0154] The sixth insulating layer 60 may be located on the fifth insulating layer 50 to cover the second connection electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0155] The light emitting element layer 130 may be located on the circuit layer 120. The light emitting element layer 130 may include a light emitting element 100PE. For example, the light emitting element layer 130 may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED. Hereinafter, the light emitting element 100PE is described as an example of an organic light emitting element, but the present disclosure is not particularly limited thereto.

[0156] The light emitting element 100PE may include a first electrode AE, an emission layer EL, and a second electrode CE.

[0157] The first electrode AE ​​may be located on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a contact hole CNT-3 passing through the sixth insulating layer 60.

[0158] The pixel defining layer 70 may be positioned on the sixth insulating layer 60 to cover a portion of the first electrode AE. An opening 70-OP is defined in the pixel defining layer 70. The opening 70-OP of the pixel defining layer 70 exposes at least a portion of the first electrode AE.

[0159] The first display part DA1-F (see Figure 1A ) may include an emission region PXA and a non-emission region NPXA adjacent to the emission region PXA. The non-emission region NPXA may surround the emission region PXA (eg, in a plan view). The emission region PXA may be defined as a portion of a region corresponding to the first electrode AE ​​exposed by the opening 70-OP.

[0160] The emission layer EL may be located on the first electrode AE. The emission layer EL may be located in a region corresponding to the opening 70 -OP. Fig. 6A An example is shown in which the emission layer EL is located within the opening 70 -OP, but the present disclosure is not particularly limited thereto. For example, the emission layer EL may extend to cover some of the top surface of the pixel defining layer 70 and the side surface of the pixel defining layer 70 defining the opening 70 -OP.

[0161] According to one or more embodiments of the present disclosure, the emission layer EL may be positioned individually for each of the pixels. When the emission layer EL is positioned individually for each of the pixels, each of the emission layers EL may emit light having at least one color of blue, red, and green. However, the present disclosure is not limited thereto. For example, the emission layer EL may be commonly included in a plurality of pixels while having an integral shape. In this case, the emission layer EL may provide blue light or white light.

[0162] The second electrode CE may be located on the emission layer EL. The second electrode CE may be commonly included in a plurality of pixels while having an integral shape.

[0163] In one or more embodiments of the present disclosure, the hole control layer may be located between the first electrode AE ​​and the emission layer EL. The hole control layer may be located in common in the emission region PXA and the non-emission region NPXA. The hole control layer may include a hole transport layer and may also include a hole injection layer. The electron control layer may be located between the emission layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may also include an electron injection layer. The hole control layer and the electron control layer may be commonly disposed in the pixel by using an open mask or an inkjet process.

[0164] The encapsulation layer 140 may be located on the light emitting element layer 130. The encapsulation layer 140 may include an inorganic layer, an organic layer, and another inorganic layer stacked sequentially, but the layers constituting the encapsulation layer 140 are not limited thereto. The inorganic layer may protect the light emitting element layer 130 from moisture and oxygen, and the organic layer may protect the light emitting element layer 130 from impurities such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an acrylic-based organic layer, but the present disclosure is not limited thereto.

[0165] The sensor layer 200 may include a base layer 201 , a first conductive layer 202 , an intermediate insulating layer 203 , a second conductive layer 204 , and a cover insulating layer 205 .

[0166] The base layer 201 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the base layer 201 may be an organic layer including epoxy resin, acrylic resin, or imide-based resin. The base layer 201 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3. In one or more embodiments of the present disclosure, the sensor layer 200 may omit the base layer 201.

[0167] Each of the first conductive layer 202 and the second conductive layer 204 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3.

[0168] In one or more embodiments, each of the first conductive layer 202 and the second conductive layer 204 has a single-layer structure and may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, graphene, etc.

[0169] In one or more embodiments, each of the first conductive layer 202 and the second conductive layer 204 has a multi-layer structure and may include a metal layer. The metal layer may have a three-layer structure of titanium / aluminum / titanium. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0170] In one or more embodiments of the present disclosure, the thickness of the first conductive layer 202 may be equal to or greater than the thickness of the second conductive layer 204. When the thickness of the first conductive layer 202 is greater than the thickness of the second conductive layer 204, the resistance of components (e.g., electrodes, sensing patterns, or bridge patterns, etc.) included in the first conductive layer 202 may be reduced. In addition, because the first conductive layer 202 is located below the second conductive layer 204, the visible recognition probability of the components may be lower than the visible recognition probability of the second conductive layer 204 even if the thickness of the first conductive layer 202 increases.

[0171] At least one of the intermediate insulating layer 203 and the capping insulating layer 205 may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0172] At least one of the intermediate insulating layer 203 and the cover insulating layer 205 may include an organic layer. The organic layer may include at least one of acrylic-based resin, methacrylic-based resin, polyisoprene-based resin, vinyl-based resin, epoxy-based resin, urethane-based resin, cellulose-based resin, siloxane-based resin, polyimide-based resin, polyamide-based resin, and perylene-based resin.

[0173] Previously, as an example, it is described that the sensor layer 200 includes the first conductive layer 202 and the second conductive layer 204, that is, two conductive layers in total, but it is not particularly limited thereto. For example, the sensor layer 200 may include three or more conductive layers.

[0174] Figure 6B is a cross-sectional view of a sensor layer 200 according to one or more embodiments of the present disclosure.

[0175] refer to Fig. 6A and Figure 6B , the second width 204wt of the second mesh line MS2 included in the second conductive layer 204 may be equal to or greater than the first width 202wt of the first mesh line MS1 included in the first conductive layer 202. When the user USR views the first mesh line MS1 and the second mesh line MS2 from the side, since the width of the first mesh line MS1 is smaller than the width of the second mesh line MS2, the probability of the first mesh line MS1 being visibly recognized may be reduced.

[0176] Each of the first mesh line MS1 and the second mesh line MS2 may include a first metal layer M1 and a second metal layer M2 located between the first metal layers M1. For example, each of the first metal layers M1 may include titanium (Ti), and the second metal layer M2 may include aluminum (Al). However, this is only an example, and the present disclosure is not particularly limited thereto.

[0177] In one or more embodiments of the present disclosure, the first thickness TK1 of the second metal layer M2 of the first mesh line MS1 and the second thickness TK2 of the second metal layer M2 of the second mesh line MS2 may be substantially the same, but the present disclosure is not particularly limited thereto. For example, the first thickness TK1 may be greater than the second thickness TK2. Alternatively, the second thickness TK2 may be greater than the first thickness TK1. In one or more embodiments of the present disclosure, each of the first thickness TK1 and the second thickness TK2 may be about 1,000 angstroms or more, for example, about 6,000 angstroms.

[0178] Figure 7 is a plan view of a display panel DP and a circuit board MFPC according to one or more embodiments of the present disclosure.

[0179] refer to Figure 7 , the display panel DP may include a first area AA1, a bending area BA, and a second area AA2. The bending area BA may be located between the first area AA1 and the second area AA2, and the first area AA1 and the second area AA2 are spaced apart from each other in the second direction DR2. Each of the bending area BA and the second area AA2 extending parallel to the first direction DR1 may have a width (or length) smaller than that of the first area AA1 in the first direction DR1. An area having a short length in the direction of the bending axis may be more easily bent.

[0180] Figure 7The display panel DP shown in FIG. 1 is a plan view of the display panel DP in an unfolded state before being assembled with other components (i.e., before being modularized). A portion of the display panel DP may be bent and modularized. For example, the bending area BA may be bent so that the second area AA2 is located below the first area AA1 (e.g., in the third direction DR3).

[0181] The display driver 100C may be mounted on the second area AA2 of the display panel DP. The display driver 100C may be referred to as a first driving chip. The display driver 100C may include a chip for driving the display layer 100 (see FIG. 1 ) included in the display panel DP. Figure 5 ) in the pixel driving element, such as a data driving circuit.

[0182] The circuit board MFPC may be coupled to the second area AA2 of the display panel DP. The circuit board MFPC may be electrically connected to the pad PD of the display panel DP through an anisotropic conductive adhesive layer. However, one or more embodiments of the present disclosure are not particularly limited thereto. For example, the pad PD-M of the circuit board MFPC may be directly coupled to the pad PD of the display panel DP. The circuit board MFPC may be referred to as a flexible circuit board, a flexible circuit film, a multi-layer flexible substrate, or a multi-layer flexible film.

[0183] The sensor driver 200C may be mounted on the circuit board MFPC. The sensor driver 200C may be referred to as a second driver chip. Figure 7 A structure is shown in which the display driver 100C is mounted on the display panel DP and in which the sensor driver 200C is mounted on the circuit board MFPC, but the present disclosure is not limited thereto. For example, the display driver 100C may also be mounted on the circuit board MFPC.

[0184] The display panel DP includes a sensor layer 200. A sensing area 200A and a peripheral area 200NA adjacent to the sensing area 200A may be defined on the sensor layer 200. The first area AA1 may overlap some of the sensing area 200A and the peripheral area 200NA. The bending area BA and the second area AA2 may overlap another portion of the peripheral area 200NA.

[0185] The sensor layer 200 may include a plurality of first electrodes 210 , a plurality of second electrodes 220 , a plurality of third electrodes 230 , and a plurality of fourth electrodes 240 located in the first area AA1 and the sensing area 200A.

[0186] Each of the first electrodes 210 may cross the second electrode 220. Each of the first electrodes 210 may extend in the second direction DR2, and the first electrodes 210 may be arranged to be spaced apart from each other in the first direction DR1. Each of the second electrodes 220 may extend in the first direction DR1, and the second electrodes 220 may be arranged to be spaced apart from each other in the second direction DR2. The sensing unit SU of the sensor layer 200 may be a region where one of the first electrodes 210 and one of the second electrodes 220 cross each other.

[0187] exist Figure 7 , six first electrodes 210 and ten second electrodes 220 may be illustrated as an example, and sixty sensing units SU may be illustrated as an example. However, the number of the first electrodes 210 and the second electrodes 220 is not limited thereto.

[0188] Each of the third electrodes 230 may extend in the second direction DR2, and the third electrodes 230 may be arranged to be spaced apart from each other in the first direction DR1. One third electrode 230 may at least partially overlap one first electrode 210. According to one or more embodiments of the present disclosure, the overlapping area between one first electrode 210 and one third electrode 230 may be adjusted to adjust the capacitance (or coupling capacitance) between one first electrode 210 and one third electrode 230. The third electrode 230 may also be referred to as a ring electrode.

[0189] The fourth electrode 240 may be arranged along the second direction DR2, and the fourth electrode 240 may extend along the first direction DR1. One fourth electrode 240 may at least partially overlap with one second electrode 220. According to one or more embodiments of the present disclosure, the overlapping area between one second electrode 220 and one fourth electrode 240 may be adjusted to adjust the capacitance (or coupling capacitance) between one second electrode 220 and one fourth electrode 240.

[0190] In one or more embodiments of the present disclosure, at least some of the fourth electrodes 240 may be electrically connected to each other to form an electrode group. Figure 7 In the embodiment, five of the fourth electrodes 240 can be connected to the same single trace, such as the auxiliary trace 240t, to form an electrode group. Figure 7 , two electrode groups arranged along the second direction DR2 are shown. However, the number of fourth electrodes 240 constituting one electrode group is not limited thereto. For example, the number of fourth electrodes 240 constituting one electrode group may be 10, and in this case, the sensor layer 200 may include one electrode group.

[0191] The sensor layer 200 may further include a plurality of first traces 210t and a plurality of second traces 220t located in the peripheral area 200NA. The first traces 210t may correspond to the first electrodes 210 one-to-one and be electrically connected to the first electrodes 210. The second traces 220t may correspond to the second electrodes 220 one-to-one and be electrically connected to the second electrodes 220.

[0192] The sensor layer 200 may further include a plurality of first annular traces 230rt1 , a second annular trace 230rt2 , and a plurality of auxiliary traces 240t in the peripheral area 200NA.

[0193] The first loop traces 230rt1 may be connected to the third electrodes 230 in a one-to-one correspondence. That is, the number of the first loop traces 230rt1 may correspond to the number of the third electrodes 230. Figure 7 , six first annular traces 230rt1 and six third electrodes 230 are shown as examples.

[0194] In one or more other embodiments of the present disclosure, a first annular trace may be electrically connected to a plurality of third electrodes. A plurality of third electrodes connected to a first annular trace may be referred to as an electrode group. In this case, as the number of third electrodes connected in parallel included in an electrode group increases, the resistance of an electrode group may be reduced to improve power efficiency and sensing sensitivity. Conversely, as the number of third electrodes included in an electrode group decreases, the annular coil pattern formed using an electrode group may be implemented in a more diverse form.

[0195] The second loop trace 230rt2 may be electrically connected to the third electrode 230. In one or more embodiments of the present disclosure, the second loop trace 230rt2 may be electrically connected to all of the third electrodes 230. The second loop trace 230rt2 may include a first line portion 231t extending in the first direction DR1 and electrically connected to the third electrode 230, a second line portion 232t extending from a first end of the first line portion 231t in the second direction DR2, and a third line portion 233t extending from a second end of the first line portion 231t in the second direction DR2.

[0196] It should be noted that the third electrode 230, the first annular trace 230rt1, and the second line portion 232t and the third line portion 233t of the second annular trace 230rt2 may each have a first electrode portion, a second electrode portion, and / or a third electrode portion. For example, each of the electrodes or each of the lines described herein may have a first electrode portion in the first area AA1, a second electrode portion in the bending area BA, and a third electrode portion in the second area AA2.

[0197] Each of the third electrodes 230, the first portion of the first annular trace 230rt1, the first portion of the second line portion 232t, and the first portion of the third line portion 233t are respectively disposed in the first area AA1 and may correspond to the first electrode portions, respectively. The second portion of the first annular trace 230rt1, the second portion of the second line portion 232t, and the second portion of the third line portion 233t are respectively disposed in the bending area BA and may correspond to the second electrode portions, respectively. The third portion of the first annular trace 230rt1, the third portion of the second line portion 232t, and the third portion of the third line portion 233t are respectively disposed in the second area AA2 and may correspond to the third electrode portions, respectively. In one or more embodiments of the present disclosure, each of the resistance of the second line portion 232t and the resistance of the third line portion 233t may be substantially equal to the resistance of one of the third electrodes 230. Therefore, there may be an effect in which the second line portion 232t and the third line portion 233t are effectively used as the third electrode 230 located in the peripheral area 200NA. For example, one of the second wire portion 232t and the third wire portion 233t and one of the third electrodes 230 may form a coil. Therefore, a pen located on an area adjacent to the peripheral area 200NA may also be sufficiently charged through a loop including the second wire portion 232t or the third wire portion 233t.

[0198] In one or more embodiments of the present disclosure, in order to adjust the resistance of the second line portion 232t and the resistance of the third line portion 233t, the width of each of the second line portion 232t and the third line portion 233t in the first direction DR1 may be adjusted. However, this is only an example, and the first line portion 231t, the second line portion 232t, and the third line portion 233t may have substantially the same width.

[0199] The auxiliary traces 240 t may be spaced apart from each other with the sensing region 200A between the auxiliary traces 240 t . Figure 7 An example in which two electrode groups are arranged is shown. The auxiliary traces 240t connected to the five fourth electrodes 240 located at the upper side and the auxiliary traces 240t connected to the five fourth electrodes 240 located at the lower side may be spaced apart from each other, and the sensing area 200A is between the auxiliary traces 240t. However, the present disclosure is not particularly limited thereto.

[0200] According to one or more embodiments of the present disclosure, at least a portion of each of the first trace 210t, the second trace 220t, the first annular trace 230rt1, the second annular trace 230rt2, and the plurality of auxiliary traces 240t may have a multi-layer structure. For example, portions of the first trace 210t, the second trace 220t, the first annular trace 230rt1, the second annular trace 230rt2, and the plurality of auxiliary traces 240t extending in the second direction DR2 may have a multi-layer structure. For example, these portions may be located in the bending area BA and the second area AA2. Each of these portions may include a conductive layer included in the first conductive layer 202 (see Fig. 6A ) and the first line portion contained in the second conductive layer 204 (see Fig. 6A ) in the second line portion.

[0201] Fig. 8A is a plan view showing a first conductive layer 202SU of a sensing unit according to one or more embodiments of the present disclosure. Figure 8B is a plan view showing a second conductive layer 204SU of a sensing unit according to one or more embodiments of the present disclosure. Fig. 9 According to one or more embodiments of the present disclosure, Fig. 8A and Figure 8B FIG. 2 is a cross-sectional view of the sensor layer 200 taken along line II′.

[0202] refer to Fig. 8A and Figure 8B The described shape of the sensing unit SU is only an example, and the shape of the sensing unit SU is not limited thereto.

[0203] refer to Fig. 8A , Figure 8B and Fig. 9 , the first electrode 210 may include a first sensing pattern 210-sp and a first bridge pattern 210-bp. The first sensing pattern 210-sp and the first bridge pattern 210-bp may be electrically connected to each other through the first contact portion CNa. The second electrode 220 may be located on the same layer as the first sensing pattern 210-sp. For example, the first sensing patterns 210-sp may be spaced apart from each other, and the second electrode 220 may be between them. The first bridge pattern 210-bp may be located on a different layer from the second electrode 220, and may be insulated from the second electrode 220 and may intersect with the second electrode 220.

[0204] The third electrode 230 may be located on the same layer as the first bridge pattern 210-bp. An opening surrounding the first bridge pattern 210-bp may be defined in the third electrode 230. The third electrode 230 may overlap the first sensing pattern 210-sp. Therefore, a coupling capacitor may be defined between the first electrode 210 and the third electrode 230.

[0205] The fourth electrode 240 may include a second sensing pattern 240-sp and a second bridge pattern 240-bp. The second sensing pattern 240-sp and the second bridge pattern 240-bp may be electrically connected to each other through a second contact CNb. The third electrode 230 may be located on the same layer as the second sensing pattern 240-sp. For example, the second sensing patterns 240-sp may be spaced apart from each other, and the third electrode 230 is between them. The second bridge pattern 240-bp is located on a different layer from the third electrode 230, and may be insulated from the third electrode 230 and may intersect with the third electrode 230.

[0206] In one or more embodiments of the present disclosure, the first conductive layer 202SU may include a first bridge pattern 210-bp, a third electrode 230, and a second sensing pattern 240-sp. The second conductive layer 204SU may include a first sensing pattern 210-sp, a second electrode 220, and a second bridge pattern 240-bp.

[0207] In one or more embodiments of the present disclosure, the first conductive layer 202SU may further include a dummy pattern DMP. Since the dummy pattern DMP is located in an empty space, the visible recognition probability of the corresponding pattern due to reflection of external light may be reduced. In other words, an electronic device 1000 having improved visibility due to reflection of external light may be provided (see Figure 1A ). Each of the dummy patterns DMP may be electrically floating or electrically grounded. In one or more embodiments of the present disclosure, the dummy pattern DMP may be omitted.

[0208] refer to Fig. 8A and Figure 8B , the area occupied by the components in the first electrode 210 and the second electrode 220 included in the second conductive layer 204SU in one sensing unit SU may be larger than the area occupied by the components in the third electrode 230 and the fourth electrode 240. Figure 5 ) can increase as the distance becomes shorter. Therefore, the capacitance change caused by sensing the first input 2000 (see Figure 5 ) can be located in the electronic device 1000 (see Figure 1A ) is within a relatively large area on a layer adjacent to the surface of the ). Therefore, the touch performance can be improved.

[0209] previously, FIG. 6A to FIG. 9A structure is shown in which the first electrode 210, the second electrode 220, the third electrode 230 and the fourth electrode 240 are respectively located in two conductive layers 202SU and 204SU, but the present disclosure is not particularly limited thereto. For example, the first electrode 210, the second electrode 220, the third electrode 230 and the fourth electrode 240 can be divided into three or four conductive layers.

[0210] In one or more embodiments of the present disclosure, the third electrode 230 to which a signal is applied in the charging driving mode may be included in a third conductive layer located below the first conductive layer 202SU and the second conductive layer 204SU. For example, the third conductive layer may be disposed below the base layer 201. The third conductive layer may be located between the base layer 201 and the display layer 100, may be located below the display layer 100, or may be included in the display layer 100.

[0211] The first electrode 210, the second electrode 220, and the fourth electrode 240 may be included in the first conductive layer 202SU and the second conductive layer 204SU. For example, if the third electrode 230 is implemented as a separate conductive layer, such as a third conductive layer, the shape of the third electrode 230 can be designed more freely. For example, the third electrode 230 can be arranged in a form including a plurality of coils. In addition, the third electrode 230 can be arranged more densely by using the third conductive layer, and in this case, the pen sensing sensitivity can be improved. In one or more other embodiments of the present disclosure, the third conductive layer may include the fourth electrode 240 instead of the third electrode 230.

[0212] Fig. 10A yes Fig. 8A An enlarged plan view of area AA'. Fig. 10B yes Figure 8B An enlarged plan view of area BB'.

[0213] refer to Fig. 8A , Figure 8B , Fig. 10A and Fig. 10B , each of the first electrode 210, the second electrode 220, the third electrode 230, the fourth electrode 240 and the dummy pattern DMP may have a mesh structure. Each of the mesh structures may include a plurality of mesh lines. Each of the plurality of mesh lines may have a shape extending in one direction (e.g., a predetermined direction), and the plurality of mesh lines may be connected to each other. The mesh lines may have various shapes, such as a straight line, a line with a protrusion, or an uneven line. An opening in which a mesh structure is not provided may be defined (e.g., provided or formed) in each of the first electrode 210, the second electrode 220, the third electrode 230, the fourth electrode 240 and the dummy pattern DMP.

[0214] Fig. 10A and Fig. 10B An example is shown in which the mesh structure includes mesh lines extending in a first crossing direction CDR1 and mesh lines extending in a second crossing direction CDR2, the first crossing direction CDR1 intersecting the first direction DR1 and the second direction DR2, and the second crossing direction CDR2 intersecting the first crossing direction CDR1. However, the extending directions of the mesh lines constituting the mesh structure are not particularly limited to Fig. 10A and Fig. 10B For example, the mesh structure may include only mesh lines extending in the first direction DR1 and the second direction DR2, or may include mesh lines extending in the first direction DR1, the second direction DR2, the first crossing direction CDR1, and the second crossing direction CDR2. That is, the mesh structure may be changed into various forms.

[0215] Fig.11 is a view illustrating the operation of the sensor driver according to one or more embodiments of the present disclosure.

[0216] refer to Figure 5 and Fig.11 , the sensor driver 200C may be configured to be selectively driven in one of the first operation mode DMD1 , the second operation mode DMD2 , and the third operation mode DMD3 .

[0217] The first operation mode DMD1 may be referred to as a touch and pen standby mode, the second operation mode DMD2 may be referred to as a touch activation and pen standby mode, and the third operation mode DMD3 may be referred to as a pen activation mode. The first operation mode DMD1 may be a mode for waiting for the first input 2000 and the second input 3000. The second operation mode DMD2 may be a mode for sensing the first input 2000 and waiting for the second input 3000. The third operation mode DMD3 may be a mode for sensing the second input 3000.

[0218] In one or more embodiments of the present disclosure, the sensor driver 200C may be first driven in the first operating mode DMD1. When the first input 2000 is sensed in the first operating mode DMD1, the sensor driver 200C may be switched (or changed) to the second operating mode DMD2. Alternatively, if the second input 3000 is sensed in the first operating mode DMD1, the sensor driver 200C may be switched (or changed) to the third operating mode DMD3.

[0219] In one or more embodiments of the present disclosure, if the second input 3000 is sensed in the second operating mode DMD2, the sensor driver 200C may be switched to the third operating mode DMD3. When the first input 2000 is released (or no longer detected) in the second operating mode DMD2, the sensor driver 200C may be switched to the first operating mode DMD1. When the second input 3000 is released (or no longer detected) in the third operating mode DMD3, the sensor driver 200C may be switched to the first operating mode DMD1.

[0220] Fig.12 is a view illustrating the operation of the sensor driver according to one or more embodiments of the present disclosure.

[0221] refer to Figure 5 , Fig.11 and Fig.12 , operations in the first operation mode DMD1 , the second operation mode DMD2 , and the third operation mode DMD3 are shown in the order of time t.

[0222] In the first operation mode DMD1, the sensor driver 200C may be repeatedly driven in the second mode MD2-d and the first mode MD1-d. During the second mode MD2-d, the sensor layer 200 may be scan-driven to detect the second input 3000. During the first mode MD1-d, the sensor layer 200 may be scan-driven to detect the first input 2000. Fig.12 An example is shown in which the sensor driver 200C operates in the first mode MD1 - d continuously (eg, immediately) after the second mode MD2 - d , but the order is not limited thereto.

[0223] In the second operation mode DMD2, the sensor driver 200C may be repeatedly driven in the second mode MD2-d and the first mode MD1. During the second mode MD2-d, the sensor layer 200 may be scan-driven to detect the second input 3000. During the first mode MD1, the sensor layer 200 may be scan-driven to detect the coordinates of the first input 2000.

[0224] In the third operation mode DMD3, the sensor driver 200C may be driven in the second mode MD2. During the second mode MD2, the sensor layer 200 may be scan-driven to detect the coordinates of the second input 3000. In the third operation mode DMD3, the sensor driver 200C may not operate in the first mode MD1-d or MD1 until the second input 3000 is released (or not detected).

[0225] Fig.13 is a plan view for explaining a first mode according to one or more embodiments of the present disclosure.

[0226] refer to Figure 5 , Fig.12 and Fig.13 , the first mode MD1 - d of the first operation mode DMD1 and the first mode MD1 of the second operation mode DMD2 may include a mutual capacitance detection mode. Fig.13 1 is a view for explaining a mutual capacitance detection mode in the first mode MD1 - d of the first operation mode DMD1 and / or the first mode MD1 of the second operation mode DMD2 .

[0227] In the mutual capacitance detection mode, the sensor driver 200C may sequentially provide a transmission signal TX to the first electrode 210, and may detect the coordinates of the first input 2000 by using a reception signal RX detected by the second electrode 220. For example, the sensor driver 200C may be configured to calculate the input coordinates by sensing a change in mutual capacitance between the first electrode 210 and the second electrode 220.

[0228] Fig.13 FIG. 2 shows an example in which a transmission signal TX is supplied to one first electrode 210 and a reception signal RX is output from a second electrode 220. In order to clarify the representation of the signal, Fig.13 Only one first electrode 210 to which the transmission signal TX is provided is shown in bold in FIG. The sensor driver 200C may detect the input coordinates of the first input 2000 by sensing a change in capacitance between each of the second electrodes 220 and the first electrode 210 .

[0229] In one or more other embodiments of the present disclosure, at least one of the first mode MD1-d of the first operating mode DMD1 and the first mode MD1 of the second operating mode DMD2 may further include a self-capacitance detection mode. In the self-capacitance detection mode, the sensor driver 200C may be configured to output a drive signal to the first electrode 210 and the second electrode 220, and may be configured to calculate the input coordinates by sensing a capacitance change of each of the second electrodes 220.

[0230] In the first mode MD1 - d of the first operation mode DMD1 and the first mode MD1 of the second operation mode DMD2 , all third electrodes 230 and fourth electrodes 240 may be grounded. Therefore, touch noise may be reduced or prevented from flowing through the third electrodes 230 and fourth electrodes 240 .

[0231] Fig.14 is a plan view for explaining a second mode according to one or more embodiments of the present disclosure. Fig.15A is a diagram showing a waveform of a first signal according to one or more embodiments of the present disclosure. Fig. 15Bis a diagram showing a waveform of a second signal according to one or more embodiments of the present disclosure.

[0232] refer to Fig.14 , Fig.15A and Fig. 15B The second mode MD2 may include a charging driving mode. The charging driving mode may include a searching charging driving mode and a tracking charging driving mode.

[0233] The search charge driving mode may be a driving mode before sensing the position of the pen. Therefore, the first signal SG1 and / or the second signal SG2 may be provided to all channels included in the sensor layer 200. That is, the entire area of ​​the sensor layer 200 may be scanned in the search charge driving mode. When the pen PN (see FIG. 1 ) is sensed in the search charge driving mode, the first signal SG1 and / or the second signal SG2 may be provided to all channels included in the sensor layer 200. Figure 5 ), the sensor layer 200 may be driven for tracking charging. For example, in the tracking charging driving mode, the sensor driver 200C may sequentially output the first signal SG1 and the second signal SG2 to an area overlapping with a point where the pen PN is sensed, rather than to the entire sensor layer 200.

[0234] In the charging driving mode, the sensor driver 200C may apply a first signal SG1 to one pad and may apply a second signal SG2 to another pad. The second signal SG2 may be an opposite signal of the first signal SG1. For example, the first signal SG1 may be a sine wave signal.

[0235] Because the first signal SG1 and the second signal SG2 are applied to at least two pads, the current RFS can have a current path flowing from one pad to another pad. In addition, because the first signal SG1 and the second signal SG2 are sinusoidal wave signals having an opposite relationship to each other, the direction of the current RFS can be periodically changed. In one or more other embodiments of the present disclosure, the first signal SG1 and the second signal SG2 can be square wave signals having an anti-phase relationship to each other.

[0236] When the first signal SG1 and the second signal SG2 have an anti-phase relationship, the first signal SG1 is Figure 4 ) can be offset by the noise caused by the second signal SG2. Therefore, a flicker phenomenon may not occur in the display layer 100, and the display quality of the display layer 100 may be improved.

[0237] In one or more other embodiments of the present disclosure, the first signal SG1 may be a sine wave signal. However, the present disclosure is not limited thereto, and the first signal SG1 may be a square wave signal. In addition, the second signal SG2 may have a constant voltage V (e.g., a predetermined constant voltage V). For example, the second signal SG2 may be a ground voltage. In other words, the pad to which the second signal SG2 is applied may be regarded as being grounded. Even in this case, the current RFS may flow from one pad to another. In addition, even if the other pad is grounded, since the first signal SG1 is a sine wave signal or a square wave signal, the direction of the current RFS may be periodically changed.

[0238] refer to Fig.14 , the first signal SG1 may be provided to a pad connected to a first ring trace 230rt1, and the second signal SG2 may be provided to a pad connected to a second ring trace 230rt2. The current RFS may flow through a current path defined by a first ring trace 230rt1, a third electrode 230 connected to a first ring trace 230rt1, and a portion of the second ring trace 230rt2. The current path may have a coil shape. That is, the first signal SG1 may be provided to a third electrode 230 connected to a first ring trace 230rt1, and the second signal SG2 may be provided to at least another third electrode 230 connected to the second ring trace 230rt2. Therefore, in the charging drive mode of the second mode, the RLC resonant circuit of the pen PN may be charged through the current path.

[0239] According to one or more embodiments of the present disclosure, the current path of the loop coil pattern may be implemented by components included in the sensor layer 200. Figure 1A ) The pen PN may be charged using the sensor layer 200. Therefore, since a coil for charging the pen PN does not need to be separately added, the electronic device 1000 may not increase in thickness and weight, and may not reduce flexibility.

[0240] In the charging drive mode, the first electrode 210, the second electrode 220 and the fourth electrode 240 may be grounded, may have a constant voltage applied, or may be electrically floating. For example, the first electrode 210, the second electrode 220 and the fourth electrode 240 may be floating. In this case, the current RFS may not flow through the first electrode 210, the second electrode 220 and the fourth electrode 240.

[0241] Fig.16 is a diagram of a pen PN according to one or more embodiments of the present disclosure.

[0242] refer to Fig.16, the pen PN may include a housing PN-H, a pen tip PN-T, an inductor L, a capacitor C, a resistor R, an elastic body PN-ED, a pressure capacitor CP, a switch SW-B, and a button capacitor CB. The pen PN may not include active elements such as a power supply, a transistor, or a diode, but the switch SW-B is connected to the button capacitor CB. The components included in the pen PN are not limited to the above components. At least a part of the above components may be omitted, and other components may be added.

[0243] In one or more embodiments of the present disclosure, the pen tip PN-T may include a non-conductive material. The pen tip PN-T may have a structure protruding to the outside of the housing PN-H. The pen tip PN-T may be detachably connected to the housing PN-H and may be a replaceable component.

[0244] In one or more embodiments of the present disclosure, the resistor R, the inductor L, and the capacitor C may be connected in series with each other. Therefore, the pen PN may have a structure having a resonant frequency and selectivity, which is a characteristic of an RLC series circuit. In this case, the frequency of each of the signals provided to the sensor layer 200 (for example, if the sensor layer 200 is driven for charging) may correspond to the resonant frequency of the pen PN. The capacitor C, the pressure capacitor CP, and the button capacitor CB may have a structure connected in parallel with each other. For reference, if the switch SW-B is turned on, the button capacitor CB may be connected in parallel to the capacitor C.

[0245] In one or more embodiments of the present disclosure, when the switch SW-B is turned on and off, the button capacitor CB can be electrically connected to the capacitor C, or disconnected from the capacitor C. That is, the switch SW-B can be turned on and off to enable the pen PN to respond to other resonant frequencies. For example, a button can be provided on the outer peripheral surface of the housing PN-H. When the button is pressed, the switch SW-B can be turned on, and the button capacitor CB can be electrically connected to the capacitor C, and therefore, the capacitance of the entire pen PN can be increased.

[0246] In one or more embodiments of the present disclosure, the capacitor C may be provided by cutting some of the plurality of capacitors connected in parallel to each other. For example, during the process of manufacturing the pen PN, the pen PN may tune the capacitor C by cutting or disabling some of the plurality of capacitors to match the target resonant frequency.

[0247] In one or more embodiments of the present disclosure, if the pen tip PN-T is partially inserted into the housing PN-H by pen pressure, the area, distance, or area and distance corresponding to the capacitance of the pressure capacitor CP can be changed. Therefore, the capacitance of the pressure capacitor CP can be changed. For example, if pen pressure is applied to the pen PN, the capacitance of the pressure capacitor CP can be increased, and the resonant frequency of the pen PN can be reduced accordingly. Thereafter, if the pen pressure is removed, the capacitance of the pressure capacitor CP can return to its original state due to the elastic body PN-ED.

[0248] Fig.17A is a view for explaining the operation of the pen PN according to one or more embodiments of the present disclosure. Fig. 17B 2 is a view for explaining the operation of the sensor layer 200 according to one or more embodiments of the present disclosure.

[0249] refer to Fig.14 , Fig.16 , Fig.17A and Fig. 17B , the second mode MD2 may include a charging part MD2-ch and a discharging part MD2-dc. The charging part MD2-ch may correspond to the charging driving mode, and the discharging part MD2-dc may correspond to the pen sensing driving mode.

[0250] The first signal SG1 and the second signal SG2 may be provided to the sensor layer 200 during a first time period. The first time period may correspond to a charging portion MD2-ch. During the first time period, the pen PN adjacent to the sensor layer 200 may be charged. For example, the inductor L may generate a current through a magnetic field generated in the sensor layer 200. The generated current may be transferred to the capacitor C. The capacitor C may charge the current input from the inductor L. Thereafter, the capacitor C may release the charged current to the inductor L, and the inductor L may emit a magnetic field at a resonant frequency.

[0251] The portion where the magnetic field is emitted from the pen PN may correspond to the discharge portion MD2-dc. Due to the magnetic field emitted by the pen PN, an induction current may flow in the sensor layer 200, and the induction current may be transmitted to the sensor driver 200C as a reception signal (eg, a sensing signal, a signal, etc.).

[0252] In one or more embodiments of the present disclosure, the charging driving voltage of the sensor layer 200 may have a sine wave or a square wave, and Fig. 17B An example in which the charging driving voltage has a sine wave is shown. A voltage charged to the pen PN or a voltage discharged from the pen PN may have a sine wave.

[0253] Fig.18Ais a plan view for explaining a second mode according to one or more embodiments of the present disclosure. Fig.18B is a view for explaining the second mode based on one sensing unit SU according to one or more embodiments of the present disclosure.

[0254] refer to Fig.18A and Fig.18B , the second mode may include a charging driving mode and a pen sensing driving mode. Fig.18A and Fig.18B is a view for explaining a pen sensing driving mode.

[0255] refer to Fig.18A , in the pen sensing driving mode, a first reception signal PRX1 may be output from the first electrode 210 , and a second reception signal PRX2 may be output from the second electrode 220 . Fig.18B A sensing unit SU is shown, through which the first sensing current Ia, the second sensing current Ib, the third sensing current Ic, and the fourth sensing current Id generated by the pen PN flow.

[0256] refer to Fig.18A and Fig.18B , the wiring directions of one electrode and another electrode of the sensor layer 200 that overlap each other may be different from each other. For example, the wiring direction of the first electrode 210 and the wiring direction of the third electrode 230 may be different from each other. In addition, the wiring direction of the second electrode 220 and the wiring direction of the fourth electrode 240 may be different from each other. The wiring direction may be a direction in which the trace protrudes and extends from the position where the electrode and the trace are connected to each other.

[0257] For example, in Fig.18B , the first electrode 210 and the first trace 210t may be connected at the lower portion of the sensing unit SU, and the first trace 210t may protrude and extend from the lower portion of the first electrode 210. The third electrode 230 and the second ring-shaped trace 230rt2 may be connected at the upper portion of the sensing unit SU, and the second ring-shaped trace 230rt2 may protrude and extend from the upper portion of the third electrode 230. The second electrode 220 and the second trace 220t may be connected at the right side of the sensing unit SU, and the second trace 220t may protrude and extend from the right side of the second electrode 220, and the fourth electrode 240 and the auxiliary trace 240t may be connected at the left side of the sensing unit SU, and the auxiliary trace 240t may protrude and extend from the left side of the fourth electrode 240.

[0258] The RLC resonant circuit of the pen PN may emit a magnetic field at a resonant frequency while discharging the charged charge. By the magnetic field provided from the pen PN, a first induced current Ia may be generated in the first electrode 210, and a second induced current Ib may be generated in the second electrode 220. In addition, a third induced current Ic may be generated in the third electrode 230, and a fourth induced current Id may be generated in the fourth electrode 240.

[0259] The first coupling capacitor Ccp1 may be located between the third electrode 230 and the first electrode 210, and the second coupling capacitor Ccp2 may be located between the fourth electrode 240 and the second electrode 220. The third sense current Ic may be transmitted to the first electrode 210 through the first coupling capacitor Ccp1, and the fourth sense current Id may be transmitted to the second electrode 220 through the second coupling capacitor Ccp2.

[0260] The sensor driver 200C may receive a first reception signal PRX1a based on the first sensing current Ia and the third sensing current Ic from the first electrode 210, and may receive a second reception signal PRX2a based on the second sensing current Ib and the fourth sensing current Id from the second electrode 220. The sensor driver 200C may detect input coordinates of the pen PN based on the first reception signal PRX1a and the second reception signal PRX2a.

[0261] When the sensor driver 200C receives the first reception signal PRX1a from the first electrode 210 and the second reception signal PRX2a from the second electrode 220, all ends of the third electrode 230 and the fourth electrode 240 may float. Therefore, through the coupling between the first electrode 210 and the third electrode 230 and through the coupling between the second electrode 220 and the fourth electrode 240, the compensation of the sensing signal may be improved or maximized.

[0262] In addition, the other ends of the third electrode 230 and the fourth electrode 240 may be grounded or floated. Therefore, through the coupling between the first electrode 210 and the third electrode 230 and the coupling between the second electrode 220 and the fourth electrode 240, the third induced current Ic and the fourth induced current Id may be sufficiently transmitted to the first electrode 210 and the second electrode 220, respectively.

[0263] Fig.19 is a plan view showing a display panel DP and a circuit board MFPC according to one or more embodiments of the present disclosure.

[0264] refer to Figure 7 and Fig.19, a portion of the display panel DP may be bent and modularized. For example, the bending area BA may be bent so that the second area AA2 is located below the first area AA1 (eg, in the third direction DR3). Therefore, the second area AA2 of the display panel DP and the circuit board MFPC may be located below the first area AA1.

[0265] Fig.19 An example is shown in which the first measurement area TA1, the second measurement area TA2, and the third measurement area TA3 overlap with the sensing area 200A. The first measurement area TA1 and the second measurement area TA2 may not overlap with the second area AA2 and the circuit board MFPC, and the third measurement area TA3 may overlap with the second area AA2 and the circuit board MFPC (e.g., in the thickness direction). An input may be provided corresponding to each of the first measurement area TA1, the second measurement area TA2, and the third measurement area TA3, and the signal-to-noise ratio may be measured accordingly.

[0266] A portion of the first loop trace 230rt1 located in the first area AA1 and a portion of the first loop trace 230rt1 located in the second area AA2 may overlap each other. In addition, a portion of the first loop trace 230rt1 located in the first area AA1 and a plurality of connection lines 230c included in the circuit board MFPC may overlap each other.

[0267] Unlike some embodiments of the present disclosure, if the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the second area AA2 are different from each other and are affected by each other, the first magnetic field and the second magnetic field may cancel each other. Figure 1A ) provides a strength of a magnetic field. In this case, the pen PN may not be sufficiently charged, and the magnetic field emitted from the pen PN may not be sufficient. The signal-to-noise ratio of the third measurement area TA3 may be less than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Therefore, the electronic device 1000 (see Figure 1A )’s sensing sensitivity of pen PN.

[0268] According to one or more embodiments of the present disclosure, a structure may be provided in which a first magnetic field generated in the first area AA1 and a second magnetic field generated in the second area AA2 or the circuit board MFPC do not cancel each other out. For example, the arrangement of the first annular trace 230rt1, the second annular trace 230rt2, or the plurality of connecting lines 230c may be adjusted so that the direction of the first magnetic field generated in the first area AA1 is the same as the direction of the second magnetic field generated in the second area AA2 or the circuit board MFPC. Alternatively, a shielding structure may be applied to the electronic device 1000 so that the second magnetic field generated in the second area AA2 or the circuit board MFPC does not affect the first magnetic field generated in the first area AA1. Therefore, the signal-to-noise ratio of the third measurement area TA3 may be increased to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Therefore, the electronic device 1000 (see Figure 1A )’s sensing sensitivity of pen PN.

[0269] Fig. 20 is a view of a display panel DP and a circuit board MFPC according to one or more embodiments of the present disclosure.

[0270] refer to Figure 7 , Fig.19 and Fig. 20 The first circular trace 230rt1 may include a first-first circular trace 230rt11, a first-second circular trace 230rt12, a first-third circular trace 230rt13, a first-fourth circular trace 230rt14, a first-fifth circular trace 230rt15, and a first-sixth circular trace 230rt16.

[0271] The second line portion 232t, the first-first circular trace 230rt11 to the first-sixth circular trace 230rt16, and the third line portion 233t may be sequentially arranged along the first direction DR1. For example, in the display panel DP, the second line portion 232t, the first-first circular trace 230rt11 to the first-sixth circular trace 230rt16, and the third line portion 233t may extend from the first area AA1 toward the second area AA2 via the bending area BA.

[0272] The circuit board MFPC may include a plurality of connection lines 230c electrically connected in a one-to-one correspondence to the second line portion 232t, the first-first circular trace 230rt11 to the first-sixth circular trace 230rt16, and the third line portion 233. The plurality of connection lines 230c may include a first connection line 230c1, a second connection line 230c2, a third connection line 230c3, a fourth connection line 230c4, a fifth connection line 230c5, a sixth connection line 230c6, a seventh connection line 230c7, and an eighth connection line 230c8.

[0273] According to one or more embodiments of the present disclosure, the arrangement order of the third electrode 230 may be different from the arrangement order of the second connection lines 230c2 to the seventh connection lines 230c7 which are electrically connected to the third electrode 230, respectively. In addition, the arrangement order of the second line portion 232t, the first-first ring trace 230rt11 to the first-sixth ring trace 230rt16, and the third line portion 233t may be different from the arrangement order of the first connection line 230c1 to the eighth connection line 230c8 which are electrically connected to each other, respectively. For example, the second line portion 232t, the first-first ring trace 230rt11 to the first-sixth ring trace 230rt16, and the third line portion 233t may be sequentially arranged along the first direction DR1, and at least some of the first connection lines 230c1 to the eighth connection lines 230c8 may be sequentially arranged along the direction opposite to the first direction DR1.

[0274] In one or more embodiments of the present disclosure, all of the first to eighth connection lines 230c1 to 230c8 may be sequentially arranged in a direction opposite to the first direction DR1. In this case, the first connection line 230c1 electrically connected to the second line portion 232t may be located at the rightmost side, and the eighth connection line 230c8 electrically connected to the third line portion 233t may be located at the leftmost side. That is, if the second line portion 232t, the first-first ring trace 230rt11 to the first-sixth ring trace 230rt16, and the third line portion 233t are arranged in a forward order, the first to eighth connection lines 230c1 to 230c8 may be arranged in a reverse order.

[0275] In one or more embodiments of the present disclosure, the second connection lines 230c2 to 230c7, which are electrically connected only to the first-first ring traces 230rt11 to the first-sixth ring traces 230rt16 among the first to eighth connection lines 230c1 to 230c8, may be arranged in a direction opposite to the first direction DR1. In this case, the first connection line 230c1, the seventh connection line 230c7, the sixth connection line 230c6, the fifth connection line 230c5, the fourth connection line 230c4, the third connection line 230c3, the second connection line 230c2, and the eighth connection line 230c8 may be sequentially arranged along the first direction DR1.

[0276] According to one or more embodiments of the present disclosure, the circuit board MFPC may further include a plurality of bridge wires BL. The bridge wires BL may include a first bridge wire BL1, a second bridge wire BL2, a third bridge wire BL3, a fourth bridge wire BL4, a fifth bridge wire BL5, a sixth bridge wire BL6, a seventh bridge wire BL7, and an eighth bridge wire BL8. The first bridge wire BL1, the second bridge wire BL2, the third bridge wire BL3, the fourth bridge wire BL4, the fifth bridge wire BL5, the sixth bridge wire BL6, the seventh bridge wire BL7, and the eighth bridge wire BL8 may be electrically connected to the first connection wire 230c1 to the eighth connection wire 230c8 in a one-to-one correspondence. In addition, the first bridge wire BL1, the second bridge wire BL2, the third bridge wire BL3, the fourth bridge wire BL4, the fifth bridge wire BL5, the sixth bridge wire BL6, the seventh bridge wire BL7, and the eighth bridge wire BL8 may be electrically connected to the second line portion 232t and the first-first ring trace 230rt11 to the first-sixth ring trace 230rt16 and the third line portion 233t in a one-to-one correspondence.

[0277] The first bridge wire BL1, the second bridge wire BL2, the third bridge wire BL3, the fourth bridge wire BL4, the fifth bridge wire BL5, the sixth bridge wire BL6, the seventh bridge wire BL7, and the eighth bridge wire BL8 may extend along the first direction DR1 and may be arranged to be spaced apart from each other in the second direction DR2. However, this is only an example, and if the arrangement order of the second line portion 232t, the first-first loop trace 230rt11 to the first-sixth loop trace 230rt16, and the third line portion 233t and the arrangement order of the first connecting wire 230c1 to the eighth connecting wire 230c8 electrically connected to the corresponding connection wires are adjusted differently, the first bridge wire BL1, the second bridge wire BL2, the third bridge wire BL3, the fourth bridge wire BL4, the fifth bridge wire BL5, the sixth bridge wire BL6, the seventh bridge wire BL7, and the eighth bridge wire BL8 may have various shapes and may be arranged in various ways.

[0278] According to one or more embodiments of the present disclosure, each of the second line portion 232t, the first-first circular trace 230rt11 to the first-sixth circular trace 230rt16, and the third line portion 233t and the first to eighth connecting wires 230c1 to 230c8 electrically connected thereto correspondingly may be spaced apart from each other in the first direction DR1. For example, one circular trace and one connecting wire electrically connected thereto may be spaced apart from each other in the first direction DR1.

[0279] Reference together Fig.19 , the bending area BA may be bent, and the second area AA2 and the circuit board MFPC may be located below the first area AA1. In this case, a bending edge BA-E may be defined in the bending area BA. According to one or more embodiments of the present disclosure, if the display panel DP is bent, the first bridge wire BL1, the second bridge wire BL2, the third bridge wire BL3, the fourth bridge wire BL4, the fifth bridge wire BL5, the sixth bridge wire BL6, the seventh bridge wire BL7 and the eighth bridge wire BL8 may be located within a limited distance (e.g., a predetermined distance) DT from the bending edge BA-E. For example, the limited distance (e.g., a predetermined distance) DT may be about 50 mm, but the present disclosure is not particularly limited thereto. In the area within the limited distance DT from the bending edge BA-E, the arrangement order of the second line portion 232t, the first-first annular trace 230rt11 to the first-sixth annular trace 230rt16 and the third line portion 233t may be changed.

[0280] Lines having the same arrangement order as the second line portion 232t, the first-first circular trace 230rt11 to the first-sixth circular trace 230rt16, and the third line portion 233t may overlap each other on a plane, and the directions of the overlapping magnetic fields may be opposite, and thus the magnetic fields may cancel each other out. Therefore, the positions of the first bridge wire BL1, the second bridge wire BL2, the third bridge wire BL3, the fourth bridge wire BL4, the fifth bridge wire BL5, the sixth bridge wire BL6, the seventh bridge wire BL7, and the eighth bridge wire BL8 may be closer to the bending edge BA-E, and in a state in which the display panel DP is bent, the area in the magnetic field may be further reduced.

[0281] According to one or more embodiments of the present disclosure, if the bending area BA of the display panel DP is bent and assembled, the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the circuit board MFPC in the charging drive mode may be the same. Therefore, the magnetic fields in the third measurement area TA3 and the area adjacent thereto may not be offset. For example, the intensity of the magnetic field received by the pen PN adjacent to the third measurement area TA3 may be equal to or greater than the intensity of the magnetic field received by the pen PN adjacent to the first measurement area TA1 or the second measurement area TA2. Therefore, the signal-to-noise ratio of the third measurement area TA3 can be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Therefore, the performance of the electronic device 1000 (see Figure 1A )’s sensing sensitivity of pen PN.

[0282] Fig.21 is a view of a display panel and a circuit board MFPC according to one or more embodiments of the present disclosure. Fig.21 In the description of Fig. 20 The same components are given the same reference numerals, and their detailed description will be omitted.

[0283] refer to Figure 7 , Fig.19 and Fig.21 , the arrangement order of the second line portion 232t, the first-first ring trace 230rt11 to the first-sixth ring trace 230rt16, and the third line portion 233t may be different from the arrangement order of the first connection line 230c1 to the eighth connection line 230c8 that are electrically connected to each other correspondingly. For example, the second line portion 232t, the first-first ring trace 230rt11 to the first-sixth ring trace 230rt16, and the third line portion 233t may be sequentially arranged along the first direction DR1, and at least some of the first connection line 230c1 to the eighth connection line 230c8 may be sequentially arranged along the direction opposite to the first direction DR1.

[0284] The arrangement order of the second line portion 232t, the first-first circular trace 230rt11 to the first-sixth circular trace 230rt16, and the third line portion 233t may be changed within the display panel DP. For example, the arrangement order may be changed in the peripheral area 200NA.

[0285] According to one or more embodiments of the present disclosure, the display panel DP may include a first bridge wire BL1a, a second bridge wire BL2a, a third bridge wire BL3a, a fourth bridge wire BL4a, a fifth bridge wire BL5a, a sixth bridge wire BL6a, a seventh bridge wire BL7a, and an eighth bridge wire BL8a. The first bridge wire BL1a to the eighth bridge wire BL8a may be arranged in the first area AA1. In addition, the first bridge wire BL1a to the eighth bridge wire BL8a may be located in the peripheral area 200NA.

[0286] The second line portion 232t, the first-first loop trace 230rt11 to the first-sixth loop trace 230rt16, and the third line portion 233t can be electrically connected to the first bridge wire BL1a, the second bridge wire BL2a, the third bridge wire BL3a, the fourth bridge wire BL4a, the fifth bridge wire BL5a, the sixth bridge wire BL6a, the seventh bridge wire BL7a, and the eighth bridge wire BL8a in one-to-one correspondence. The first connection wire 230c1 to the eighth connection wire 230c8 can be electrically connected to the first bridge wire BL1a, the second bridge wire BL2a, the third bridge wire BL3a, the fourth bridge wire BL4a, the fifth bridge wire BL5a, the sixth bridge wire BL6a, the seventh bridge wire BL7a, and the eighth bridge wire BL8a in one-to-one correspondence.

[0287] The arrangement order of the first connecting line 230c1 to the eighth connecting line 230c8 that receive the same signal as the second line portion 232t, the first-first ring trace 230rt11 to the first-sixth ring trace 230rt16 and the third line portion 233t can be changed by the first bridge line BL1a, the second bridge line BL2a, the third bridge line BL3a, the fourth bridge line BL4a, the fifth bridge line BL5a, the sixth bridge line BL6a, the seventh bridge line BL7a and the eighth bridge line BL8a.

[0288] Therefore, if the bending area BA of the display panel DP is bent and assembled, the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the second area AA2 and the circuit board MFPC in the charging driving mode may be the same. Therefore, the magnetic fields in the third measurement area TA3 and the area adjacent thereto may not be offset. Therefore, the signal-to-noise ratio of the third measurement area TA3 may be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Therefore, the electronic device 1000 (see Figure 1A )’s sensing sensitivity of pen PN.

[0289] Fig. 22 is a view of a display panel and a circuit board MFPC according to one or more embodiments of the present disclosure. Fig. 22In the description of Fig. 20 and Fig.21 , and the description thereof will be omitted.

[0290] refer to Figure 7 , Fig.19 and Fig. 22 , the display panel DP may include a first bridge wire BL1a, a second bridge wire BL2a, a third bridge wire BL3b, a fourth bridge wire BL4b, a fifth bridge wire BL5b, a sixth bridge wire BL6b, a seventh bridge wire BL7a, and an eighth bridge wire BL8a. The first bridge wire BL1a, the second bridge wire BL2a, the third bridge wire BL3b, the fourth bridge wire BL4b, the fifth bridge wire BL5b, the sixth bridge wire BL6b, the seventh bridge wire BL7a, and the eighth bridge wire BL8a may be arranged in the first area AA1.

[0291] In one or more embodiments of the present disclosure, at least some of the first bridge wire BL1a, the second bridge wire BL2a, the third bridge wire BL3b, the fourth bridge wire BL4b, the fifth bridge wire BL5b, the sixth bridge wire BL6b, the seventh bridge wire BL7a, and the eighth bridge wire BL8a may overlap with the sensing area 200A. For example, the third bridge wire BL3b, the fourth bridge wire BL4b, the fifth bridge wire BL5b, and the sixth bridge wire BL6b may be located in the sensing area 200A, and the first bridge wire BL1a, the second bridge wire BL2a, the seventh bridge wire BL7a, and the eighth bridge wire BL8a may be located in the peripheral area 200NA. However, this is only an example, and the arrangement relationship may be modified in various ways.

[0292] In one or more embodiments of the present disclosure, some of the third electrodes 230 may be directly connected to the third bridge wire BL3b, the fourth bridge wire BL4b, the fifth bridge wire BL5b, and the sixth bridge wire BL6b. That is, the first-second annular trace 230rt12, the first-third annular trace 230rt13, the first-fourth annular trace 230rt14, and the first-fifth annular trace 230rt15 may be connected to the third electrodes 230 corresponding to the third bridge wire BL3b, the fourth bridge wire BL4b, the fifth bridge wire BL5b, and the sixth bridge wire BL6b.

[0293] According to one or more embodiments of the present disclosure, if the bending area BA of the display panel DP is bent and assembled, the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the circuit board MFPC and the second area AA2 in the charging driving mode may be the same. Therefore, the signal-to-noise ratio of the third measurement area TA3 may be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Therefore, the electronic device 1000 (see Figure 1A )’s sensing sensitivity of pen PN.

[0294] Fig.23 is a view of a display panel and a circuit board MFPC according to one or more embodiments of the present disclosure. Fig.23 In the description of Fig.21 The same components are given the same reference numerals, and their detailed description will be omitted.

[0295] refer to Figure 7 , Fig.19 and Fig.23 , the display panel DP may include a first bridge wire BL1a, a second bridge wire BL2a, a third bridge wire BL3a, a fourth bridge wire BL4a, a fifth bridge wire BL5a, a sixth bridge wire BL6a, a seventh bridge wire BL7a, and an eighth bridge wire BL8a. The first bridge wire BL1a to the eighth bridge wire BL8a may be located in the peripheral area 200NA. For example, the first bridge wire BL1a to the eighth bridge wire BL8a may be located in at least one of the first area AA1, the bending area BA, and the second area AA2. Fig.23 An example is shown in which the first to eighth bridge lines BL1a to BL8a are uniformly located in the first area AA1, the bending area BA, and the second area AA2.

[0296] According to one or more embodiments of the present disclosure, when the bending area BA of the display panel DP is bent and assembled, the direction of the first magnetic field generated in the first area AA1 (particularly in the sensing area 200A in the charging driving mode) and the direction of the second magnetic field generated in the circuit board MFPC may be the same. Therefore, the signal-to-noise ratio of the third measurement area TA3 may be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Therefore, the electronic device 1000 (see Figure 1A )’s sensing sensitivity of pen PN.

[0297] Fig.24 is a view of a display panel and a circuit board MFPC according to one or more embodiments of the present disclosure. Fig.24 In the description of Fig. 20 and Fig.21 , and the description thereof will be omitted.

[0298] refer to Figure 7 , Fig.19 and Fig.24 , at least one of the display panel DP and the circuit board MFPC may include a first bridge wire BL1b, a second bridge wire BL2b, a third bridge wire BL3a, a fourth bridge wire BL4a, a fifth bridge wire BL5a, a sixth bridge wire BL6a, a seventh bridge wire BL7b, and an eighth bridge wire BL8b. For example, the first bridge wire BL1b, the second bridge wire BL2b, the seventh bridge wire BL7b, and the eighth bridge wire BL8b may be included in the circuit board MFPC, and the third bridge wire BL3a, the fourth bridge wire BL4a, the fifth bridge wire BL5a, and the sixth bridge wire BL6a may be included in the display panel DP. However, this is only an example, and the arrangement positions of the first bridge wire BL1b, the second bridge wire BL2b, the third bridge wire BL3a, the fourth bridge wire BL4a, the fifth bridge wire BL5a, the sixth bridge wire BL6a, the seventh bridge wire BL7b, and the eighth bridge wire BL8b may be modified in various ways.

[0299] In addition, if Fig.24 As shown in , the first-first circular trace 230rt11 to the first-sixth circular trace 230rt16 may be connected to the third electrode 230 , respectively.

[0300] Fig.25A is a view showing a result of simulating a magnetic field on a surface of a display panel according to a comparative example of the present disclosure. Fig.25B is a view showing a result of simulating a magnetic field on a surface of a display panel according to an embodiment of the present disclosure.

[0301] refer to Figure 7 , Fig.19 , Fig.25A and Fig.25B ,exist Fig.25A and Fig.25B In the simulation results of , the magnetic field measured in the third measurement area TA3 is represented by contour lines.

[0302] Fig.25A and Fig.25B The reference line RER shown in the figure indicates that if Figure 7 The height of the reference magnetic field intensity is measured when the display panel DP is not bent as shown in FIG. For example, the intensity of the reference magnetic field may be about 3×10 -7 T.

[0303] According to a comparative example of the present disclosure, the arrangement sequence of the first loop trace 230rt1 electrically connected to the third electrode 230 may be extended without being changed and electrically connected to the sensor driver 200C. Fig.25A , if the display panel DP is bent and assembled, the directions of the currents AA1em1 and AA1em2 in the first area AA1 and the directions of the currents AA2em1c and AA2em2c in the second area AA2 or the circuit board MFPC in the charging driving mode may be different from each other. Therefore, the directions of the first magnetic field generated in the first area AA1 and the directions of the second magnetic field generated in the second area AA2 and the circuit board MFPC may be different from each other. Therefore, the height SEM-c having the intensity of the reference magnetic field may be smaller than the reference line RER.

[0304] According to one or more embodiments of the present disclosure, as previously mentioned Figure 20 to Figure 24 As described above, the arrangement order of the first ring-shaped trace 230rt1 electrically connected to the third electrode 230 may be changed to be electrically connected to the sensor driver 200C. Fig.25B , if the display panel DP is bent and assembled, the directions of the currents AA1em1 and AA1em2 in the first area AA1 and the directions of the currents AA2em1 and AA2em2 in the second area AA2 or the circuit board MFPC in the charging driving mode may be the same. Therefore, the directions of the first magnetic field generated in the first area AA1 and the directions of the second magnetic field generated in the second area AA2 and the circuit board MFPC may be the same. Therefore, the height SEM having the intensity of the reference magnetic field may be greater than the reference line RER.

[0305] Fig.26 According to one or more embodiments of the present disclosure, Fig.19 A cross-sectional view of the electronic device 1000 taken along line II-II′.

[0306] refer to Figure 7 , Fig.19 and Fig.26 , if the bending area BA of the display panel DP is bent, the first area AA1 may overlap the second area AA2 and the circuit board MFPC. Figure 20 to Figure 24 As described, the arrangement order of the first ring-shaped trace 230rt1 electrically connected to the third electrode 230 may be changed to be electrically connected to the sensor driver 200C.

[0307] In the charging drive mode, the direction of the first magnetic field generated in the first area AA1 and the direction of the second magnetic field generated in the second area AA2 and the circuit board MFPC may be the same. Therefore, the magnetic fields in the third measurement area TA3 and the area adjacent thereto may not be offset. Therefore, the signal-to-noise ratio of the third measurement area TA3 may be improved to a level similar to or slightly higher than the signal-to-noise ratio of each of the first measurement area TA1 and the second measurement area TA2. Therefore, the electronic device 1000 (see Figure 1A )’s sensing sensitivity of pen PN.

[0308] According to one or more embodiments of the present disclosure, the electronic device 1000 may further include a first magnetic field shielding layer MSL1 located below the first area AA1 of the display panel DP and a lower plate (e.g., a metal lower plate) LST located below the first magnetic field shielding layer MSL1. The second area AA2 and the circuit board MFPC may be located below the lower plate LST.

[0309] The first magnetic field shielding layer MSL1 may include magnetic metal powder. The first magnetic field shielding layer MSL1 may be referred to as a ferrite sheet, a magnetic metal powder layer, a magnetic layer, a magnetic path layer, or a magnetic path layer. The first magnetic field shielding layer MSL1 may shield the magnetic field from the first area AA1 of the display panel DP to the second area AA2 of the display panel DP. For example, the first magnetic field shielding layer MSL1 may be used to guide the direction of the transmitted magnetic field in another direction. Therefore, the magnetic field reaching the first magnetic field shielding layer MSL1 may be shielded without leaking to the outside, for example, leaking to the lower portion of the first magnetic field shielding layer MSL1.

[0310] The lower plate LST may be a plate for reflecting a magnetic field toward the first magnetic field shielding layer MSL1. The lower plate LST may include a metal or a metal alloy. For example, the lower plate LST may include aluminum, copper, or a copper alloy.

[0311] Fig. 27 According to one or more embodiments of the present disclosure, Fig.19 A cross-sectional view of the electronic device 1000a taken along line II-II'. Fig. 27 In the description of Fig.26 The same components are given the same reference numerals, and their detailed description will be omitted.

[0312] refer to Figure 7 and Fig. 27The electronic device 1000a may further include a first magnetic field shielding layer MSL1 located below the first area AA1 of the display panel DP, a lower plate LST located below the first magnetic field shielding layer MSL1, and a second magnetic field shielding layer MSL2 located below the lower plate LST. The second area AA2 and the circuit board MFPC may be located below the second magnetic field shielding layer MSL2.

[0313] The second magnetic field shielding layer MSL2 may also include a material substantially the same as that of the first magnetic field shielding layer MSL1. Therefore, according to one or more embodiments of the present disclosure, two or more magnetic field shielding layers MSL1 and MSL2 may be located between the first area AA1 of the display panel DP and the second area AA2 of the display panel DP and between the first area AA1 of the display panel DP and the circuit board MFPC. Therefore, the possibility that the magnetic field generated in the first area AA1 and the magnetic field generated in the second area AA2 and the circuit board MFPC are affected by each other can be reduced.

[0314] According to one or more embodiments of the present disclosure, the area (e.g., surface area) of the first magnetic field shielding layer MSL1 may be greater than the area (e.g., surface area) of the second magnetic field shielding layer MSL2. For example, the first magnetic field shielding layer MSL1 may completely overlap with the first area AA1 of the display panel DP, and the second magnetic field shielding layer MSL2 may overlap with the second area AA2 of the display panel DP and the circuit board MFPC.

[0315] The first area AA1 may include a first partial area AAp1, a second partial area AAp2, and a third partial area AAp3. The first partial area AAp1 may be an area that does not overlap with the second area AA2 of the display panel DP and the circuit board MFPC.

[0316] The magnetic field generated in the first partial area AAp1 may not be offset by the magnetic field generated in the second area AA2 and the circuit board MFPC, or may be only slightly offset.

[0317] The second partial area AAp2 may be an area overlapping with the circuit board MFPC. The third partial area AAp3 may be an area overlapping with the second area AA2 of the display panel DP. That is, the magnetic field generated in the second partial area AAp2 and the third partial area AAp3 may be offset by the magnetic field generated in the second area AA2 and the circuit board MFPC. Therefore, in one or more embodiments, two or more magnetic field shielding layers MSL1 and MSL2 may be located between the second partial area AAp2 and the third partial area AAp3 and the circuit board MFPC to reduce or minimize the offset of the magnetic field. Therefore, the possibility of the magnetic field generated in the first area AA1 and the magnetic field generated in the second area AA2 and the circuit board MFPC being affected by each other can be reduced.

[0318] In the corresponding Fig. 27 In the case of one or more embodiments, it can be combined with the above reference Figure 20 to Figure 24 Each combination of the embodiments described. Fig. 27 The corresponding one or more embodiments may be combined with a structure in which the arrangement sequence of the first ring-shaped trace 230rt1 electrically connected to the third electrode 230 is extended without being changed and electrically connected to the sensor driver 200C.

[0319] Fig.28 According to one or more embodiments of the present disclosure, Fig.19 A cross-sectional view of the electronic device 1000b taken along line II-II'. Fig.28 In the description of Fig. 27 The same components are given the same reference numerals, and their detailed description will be omitted.

[0320] refer to Figure 7 and Fig.28 The electronic device 1000b may further include a first magnetic field shielding layer MSL1 located below the first area AA1 of the display panel DP, a lower plate LST located below the first magnetic field shielding layer MSL1, and a second magnetic field shielding layer MSL2a located below the lower plate LST. The second area AA2 and the circuit board MFPC may be located below the second magnetic field shielding layer MSL2a.

[0321] According to one or more embodiments of the present disclosure, the area of ​​the first magnetic field shielding layer MSL1 may be substantially the same as that of the second magnetic field shielding layer MSL2a. For example, each of the first magnetic field shielding layer MSL1 and the second magnetic field shielding layer MSL2a may completely overlap the first area AA1 of the display panel DP.

[0322] In the corresponding Fig.28 In the case of one or more embodiments, it can be combined with the above reference Figure 20 to Figure 24 Each combination of the embodiments described. Fig.28 The corresponding one or more embodiments may be combined with a structure in which the arrangement sequence of the first ring-shaped trace 230rt1 electrically connected to the third electrode 230 is extended without being changed and electrically connected to the sensor driver 200C.

[0323] Fig.29 is a cross-sectional view of a circuit board MFPC according to one or more embodiments of the present disclosure. For example, Fig.29 yes Fig.28 An enlarged plan view of the area CC' shown in FIG.

[0324] refer to Fig.28 and Fig.29 The circuit board MFPC may include a plurality of conductive layers ML1, ML2, and ML3, and the plurality of connection lines 230c may be included in the conductive layer ML3, which is the layer farthest from the first area AA1 of the display panel DP among the plurality of conductive layers ML1, ML2, and ML3. The plurality of conductive layers ML1 and ML2 may be referred to as conductive shielding layers.

[0325] Fig.29 An example is shown in which the circuit board MFPC includes three conductive layers ML1, ML2, and ML3, but the present disclosure is not particularly limited thereto. For example, the circuit board MFPC may include two conductive layers, or may include four or more conductive layers.

[0326] Fig. 30A is a cross-sectional view of a circuit board MFPCa according to one or more embodiments of the present disclosure. Fig. 30B is a plan view of a circuit board MFPCa according to one or more embodiments of the present disclosure. Fig. 30A yes Fig.28 An enlarged plan view of area CC'.

[0327] refer to Fig.28 , Fig. 30A and Fig. 30B The circuit board MFPCa may include a plurality of conductive layers ML1a, ML2, and ML3, and the plurality of connection lines 230c may be included in the conductive layer ML3 which is the farthest layer from the first area AA1 of the display panel DP among the plurality of conductive layers ML1a, ML2, and ML3.

[0328] In one or more embodiments of the present disclosure, a shielding layer ML1a may be provided between the connection line 230c and the first area AA1 of the display panel DP. That is, at least one of the plurality of conductive layers ML1a, ML2, and ML3 may be used as the shielding layer ML1a, which may be referred to as the shielding layer ML1a. When viewed on a plane, for example, when viewed in the third direction DR3, the shielding layer ML1a may overlap with all the connection lines 230c.

[0329] In one or more embodiments of the present disclosure, the shielding layer ML1a may be grounded or may be provided at a constant voltage (e.g., a predetermined constant voltage). In this case, the shielding layer ML1a may reduce the possibility that the magnetic field generated in the first area AA1 and the magnetic field generated in the second area AA2 and the circuit board MFPCa are affected by each other.

[0330] Corresponds to Fig. 30A and Fig. 30B One or more embodiments may be combined with the previously referenced Figure 20 to Figure 24Each combination of the embodiments described. Fig. 30A and Fig. 30B The corresponding one or more embodiments may be combined with a structure in which the arrangement sequence of the first ring-shaped trace 230rt1 electrically connected to the third electrode 230 is extended without change and electrically connected to the sensor driver 200C. Fig. 30A and Fig. 30B One or more embodiments may be combined with the previously referenced Figure 26 to Figure 28 Each combination of the embodiments described. In addition, corresponding to Fig. 30A and Fig. 30B One or more embodiments may be referred to as Figure 20 to Figure 24 Description of the embodiments and references Figure 26 to Figure 28 Each combination of the described embodiments.

[0331] Fig.31 is a cross-sectional view of a circuit board MFPCb according to one or more embodiments of the present disclosure. For example, Fig.31 yes Fig.28 An enlarged plan view of area CC'.

[0332] refer to Fig.28 and Fig.31 The circuit board MFPCb may include a plurality of layers ML1b, ML2b, ML3b, ML4b, ML5b and ML6b and an insulating layer IL between the plurality of layers ML1b, ML2b, ML3b, ML4b, ML5b and ML6b. The plurality of layers ML1b, ML2b, ML3b, ML4b, ML5b and ML6b may include a first shielding layer ML1b, a first line layer ML2b, a second shielding layer ML3b, a third shielding layer ML4b, a second line layer ML5b and a fourth shielding layer ML6b.

[0333] The first shielding layer ML1b may be the closest to the display panel DP (see Figure 7 Therefore, it can be understood that the first shielding layer ML1b, the first line layer ML2b, the second shielding layer ML3b, the third shielding layer ML4b, the second line layer ML5b and the fourth shielding layer ML6b are sequentially stacked in a direction away from the display panel DP.

[0334] Fig.32A is a plan view of a first shielding layer (eg, first conductive shielding layer) ML1b according to one or more embodiments of the present disclosure.

[0335] refer to Fig.31 and Fig.32A, the first shielding layer ML1b of the circuit board MFPCb and the outer line MFPC-OL are shown together. The first shielding layer ML1b may not cover the pad area PD-MA in which the pad PD-M of the circuit board MFPCb is located.

[0336] Fig.32B is a plan view of a first line layer ML2 b according to one or more embodiments of the present disclosure.

[0337] refer to Fig.31 and Fig.32B , the circuit board MFPCb may include a plurality of connection lines 230ca. Fig.32B Some of the connection lines 230ca included in the first line layer (eg, first conductive layer) ML2b are shown.

[0338] The connection lines 230ca may include a plurality of first connection lines 230ca1 and a plurality of second connection lines 230ca2. The first connection lines 230ca1 and the second connection lines 230ca2 may be spaced apart from each other in the first direction DR1.

[0339] The sensor driver 200C may be installed adjacent to any one of the first connection line 230ca1 and the second connection line 230ca2. In this case, any one of the first connection line 230ca1 and the second connection line 230ca2 may be connected to the circuit board MFPCb via an extended connection line 230ca2-CL (see FIG. 2 ) extending in the width direction (e.g., in the first direction DR1) of the circuit board MFPCb. Fig.32E ) is connected to the sensor driver 200C.

[0340] According to one or more embodiments of the present disclosure, the first line layer ML2b may correspond to a layer closer to the display panel DP than the second line layer ML5b to be described later (see Figure 7 Therefore, a portion extending along the width direction of the circuit board MFPCb (eg, along the first direction DR1) may not be included in the first line layer ML2b.

[0341] The first shielding layer ML1b is disposed between the connection line 230ca and the first electrode portion. The first electrode portion may include a first annular trace 230rt1 (see Figure 7 ) of the first part, the second line portion 232t (see Figure 7 ) and the third line portion 233t (see Figure 7 ) of at least one of the first portions, and the third electrode 230 (see Figure 7 ) are each arranged in the first area AA1 (see Figure 7 )middle.

[0342] Fig.32Cis a plan view of the second shielding layer ML3b according to one or more embodiments of the present disclosure. Fig.32D is a plan view of the third shielding layer ML4b according to one or more embodiments of the present disclosure.

[0343] refer to Fig.32A , Fig.32B , Fig.32C and Fig.32D , each of the second shielding layer (e.g., second conductive shielding layer) ML3b and the third shielding layer (e.g., third conductive shielding layer) ML4b or the first shielding layer ML1b may be grounded or provided with a constant voltage (e.g., a predetermined constant voltage). However, the present disclosure is not limited thereto, and the second shielding layer ML3b and the third shielding layer ML4b may also be floated.

[0344] Each of the second shielding layer ML3b and the third shielding layer ML4b may include a conductive material. Therefore, the second shielding layer ML3b and the third shielding layer ML4b may further include a line through which a signal (eg, a predetermined signal) is transmitted.

[0345] Fig.32E is a plan view of the second line layer ML5 b according to one or more embodiments of the present disclosure. Fig.32F is a plan view of the fourth shielding layer ML6b according to one or more embodiments of the present disclosure.

[0346] refer to Fig.32B , Fig.32E and Fig.32F The second line layer (eg, second conductive layer) ML5b may include an extended connection line 230ca2-CL. The extended connection line 230ca2-CL may be connected to the second connection line 230ca2 to extend along the width direction of the circuit board MFPCb.

[0347] The second shielding layer ML3b (see Fig.32C ) and the third shielding layer ML4b (see Fig.32D ) is arranged between the connecting line 230ca and the extended connecting line 230ca2-CL.

[0348] refer to Fig.32F , showing a mounting area 200C-A on which the sensor driver 200C is mounted. Therefore, an extended connection line 230ca2-CL may be provided to allow a second connection line 230ca2 relatively far from the sensor driver 200C to extend to the mounting area 200C-A overlapping the sensor driver 200C.

[0349] The length of the extended connection line 230ca2-CL may be longer than that of the second connection line 230ca2. Therefore, the extended connection line 230ca2-CL may be designed to be included in the first line layer ML2b and the second line layer ML5b and relatively far from the display panel DP (see Figure 7 ) in the second line layer ML5b.

[0350] The fourth shielding layer ML6b may cover the second line layer ML5b. The sensor driver 200C may be mounted on a mounting area 200C-A shown on the fourth shielding layer ML6b.

[0351] refer to Figure 7 , Fig.31 and FIG. 32A to FIG. 32F , the circuit board MFPcb may be designed to reduce or minimize the cancellation of the magnetic field generated in the first area AA1 of the display panel DP by the connection line 230ca. For example, the circuit board MFPcb may include at least two line layers including the connection line 230ca, and the portion having a relatively long length may be located on the layer farthest from the display panel DP. In addition, the circuit board MFPcb may be provided with a plurality of shielding layers, such as the second shielding layer ML3b and the third shielding layer ML4b, not only between the fourth shielding layer ML6b and the first shielding layer ML1b arranged at the outermost portion but also between the first line layer ML2b and the second line layer ML5b, and thus the possibility that the magnetic field generated in the first area AA1 and the magnetic field generated in the circuit board MFPc are affected by each other may be further reduced.

[0352] As described above, the sensor layer can be used to sense the input of the pen as well as the touch input. Therefore, since there is no need to add a separate component (e.g., a digitizer) for pen sensing to the electronic device, the increase in thickness and weight of the electronic device and the reduction in flexibility of the electronic device due to the addition of the digitizer may not occur. In addition, a structure can be provided in which the first magnetic field generated in the first area of ​​the display panel and the second magnetic field generated in the second area or the circuit board are not offset. In this case, the signal-to-noise ratio of the second area of ​​the display panel and an area of ​​the electronic device overlapping the circuit board can be improved to be similar to or slightly greater than the signal-to-noise ratio of the first area of ​​the display panel and another area of ​​the electronic device that does not overlap the circuit board. Therefore, the pen sensing sensitivity of the electronic device can be improved.

[0353] It will be apparent to those skilled in the art that various modifications and deviations may be made in the present disclosure. Therefore, the present disclosure is intended to cover modifications and deviations of the disclosed embodiments as long as they are within the scope of the attached claims and their equivalents. Therefore, the technical scope of the present disclosure should not be limited to what is described in the detailed description of the specification, but should be determined by the claims.

Claims

1. An electronic device, comprising: Display panel, including: First region; a bending area, wherein the display panel is bent at the bending area; a second area, overlapping with the first area; a first electrode arranged in the first region in a first direction; a second electrode arranged in the first region in a second direction intersecting the first direction and intersecting the first electrode; and a third electrode in the first region and overlapping the first electrode; a circuit board coupled to the display panel at the second region and comprising connection lines arranged in the first direction and electrically connected to the third electrodes, respectively; A metal lower plate, between the display panel and the circuit board; A first magnetic field shielding layer, between the third electrode of the display panel and the metal lower plate; and The second magnetic field shielding layer is between the connecting wire of the circuit board and the metal lower plate.

2. The electronic device according to claim 1, wherein: The connection line is electrically connected to the third electrode at the first region, the bending region, or the second region, respectively.

3. The electronic device according to claim 1, wherein: The display panel further includes a display layer and a sensor layer, and the sensor layer includes: first annular traces, electrically connected to first ends of the third electrodes, respectively, and arranged in the first direction; and A second annular trace is electrically connected to the second end of the third electrode.

4. The electronic device according to claim 3, wherein: The first loop trace is spaced apart from the connection lines electrically connected to the first loop traces, respectively, in the first direction.

5. The electronic device according to claim 3, wherein: The second annular trace comprises: a first line portion electrically connected to the third electrode; a second line portion extending from a first end of the first line portion in the second direction; and a third line portion extending from a second end of the first line portion in the second direction, Wherein, the second line portion, the first loop trace and the third line portion are sequentially arranged in the first direction.

6. The electronic device according to claim 3, wherein: At least one of the display panel and the circuit board further includes a bridge line electrically connecting the connection line and the third electrode, respectively.

7. The electronic device according to claim 6, wherein: The bridging line extends in the first direction.

8. The electronic device according to claim 6, wherein: The bridge line is in the first region.

9. The electronic device according to claim 6, wherein: The first area includes a sensing area for sensing an external input and a peripheral area adjacent to the sensing area, and Wherein, at least some of the bridging lines are in the peripheral region.

10. The electronic device according to claim 6, wherein: The bridging line is separated from the bending region.

11. The electronic device according to claim 6, wherein: Some of the bridge lines are in the first region, and wherein other of the bridge lines are in the circuit board.

12. An electronic device comprising: Display panel, including: First region; a bending area, wherein the display panel is bent at the bending area; a second area, overlapping with the first area; a first electrode portion arranged in the first region in a first direction; a second electrode portion arranged in the first direction in the bent region and electrically connected to the first electrode portion; and a third electrode portion arranged in the first direction in the second region and electrically connected to the second electrode portion; a circuit board coupled to the display panel at the second region and including a connection line arranged in the first direction and electrically connected to the third electrode portion; A metal lower plate between the first electrode portion and the connecting line; a first magnetic field shielding layer between the first electrode portion and the metal lower plate; and The second magnetic field shielding layer is between the connecting wire and the metal lower plate.

13. The electronic device according to claim 12, wherein: The connection lines have an arrangement order in the first direction that is different from an arrangement order in the first direction of the third electrode portions respectively connected to the connection lines.

14. The electronic device according to claim 13, wherein: The arrangement order of the third electrode parts is opposite to the arrangement order of the connection lines.

15. An electronic device comprising: Display panel, including: First region; a bending area, wherein the display panel is bent at the bending area; a second area, overlapping with the first area; a first electrode portion arranged in the first region in a first direction; a second electrode portion arranged in the first direction in the bent region and electrically connected to the first electrode portion; and a third electrode portion arranged in the first direction in the second region and electrically connected to the second electrode portion; a circuit board coupled to the display panel at the second region and comprising: a connection line electrically connected to the third electrode portion at the first layer; extending a connection line connected to the connection line at a second layer different from the first layer; a first conductive shielding layer between the first electrode portion and the connecting line; and a second conductive shielding layer, between the connecting wire and the extended connecting wire; a metal lower plate, between the display panel and the circuit board; and A magnetic field shielding layer is between the display panel and the metal lower plate.

16. The electronic device according to claim 15, wherein: The first conductive shielding layer or the second conductive shielding layer is grounded.

17. The electronic device according to claim 15, wherein: The first conductive shielding layer or the second conductive shielding layer is configured to receive a constant voltage.

18. The electronic device according to claim 15, wherein: The circuit board is located below the display panel in the first area and further includes a first conductive layer having the connecting line and a second conductive layer having the extending connecting line, and The first conductive layer is between the second conductive layer and the first region of the display panel.

19. The electronic device according to claim 18, wherein: The first conductive layer is below the first conductive shielding layer and partially overlaps the second area of ​​the display panel.

20. The electronic device according to claim 18, wherein: The second conductive layer is below the second conductive shielding layer and partially overlaps the second area of ​​the display panel.

21. An electronic device comprising: A substrate, comprising a first region, a bending region, and a second region overlapping the first region, wherein the substrate is bent at the bending region; a circuit layer, over the substrate, and including transistors; a light emitting element layer, above the circuit layer and including a light emitting element electrically connected to the transistor; a sensor layer, above the light emitting element layer, and including electrodes arranged in a first direction in the first region; a sensor driver configured to generate a magnetic field for charging a pen including an RLC resonant circuit using the electrodes; a circuit board coupled to the substrate at the second region and comprising connection lines electrically connected to the electrodes; A metal lower plate, between the electrodes and the connecting wires; A first magnetic field shielding layer, between the electrode and the metal lower plate; as well as The second magnetic field shielding layer is between the connecting wire and the metal lower plate.

22. The electronic device according to claim 21, wherein: The sensor driver is configured to selectively operate in a first mode or a second mode, in which the sensor layer is driven to sense a touch input and in which the sensor driver is driven to sense a pen input, the second mode including a charging drive mode.

23. The electronic device according to claim 22, wherein: The sensor layer is configured to sense the pen input by applying a first signal to at least one of the electrodes and by applying a second signal to at least another one of the electrodes.

24. The electronic device according to claim 21, wherein: The sensor layer further includes a first mesh line having a first width, a second mesh line above the first mesh line and having a second width equal to or greater than the first width, and an intermediate insulating layer between the first mesh line and the second mesh line.

25. The electronic device according to claim 21, wherein: The connection lines have an arrangement order in the first direction that is different from an arrangement order of the electrodes respectively connected to the connection lines in the first direction. 26 . The electronic device according to claim 21 , further comprising bridge wires in the first region of the substrate and / or in the circuit board, the bridge wires electrically connecting the electrodes to the connection wires, respectively.

27. The electronic device according to claim 26, wherein: The bridging line is within a finite distance from a bending edge defined in the bending region.

28. The electronic device according to claim 21, further comprising a display driver in the second region and configured to control the circuit layer, in, The circuit board overlaps the first area.

29. The electronic device according to claim 21, wherein: The second magnetic field shielding layer overlaps the circuit board and the second area of ​​the substrate.

30. The electronic device according to claim 21, wherein: The surface area of ​​the first magnetic field shielding layer is equal to or greater than the surface area of ​​the second magnetic field shielding layer.

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