Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display, a pixel circuit group comprises a first pixel circuit column and a second pixel circuit column, a data signal line is arranged between the first pixel circuit column and the second pixel circuit column, a first data write-in module is electrically connected with the data signal line through a first switch, and a second data write-in module is electrically connected with the data signal line through a second switch. The second data write-in module is electrically connected with the data signal line through the second switch; the first switch is connected to a first control signal line, the second switch is connected to a second control signal line, each first control signal line is connected to the flexible circuit board through a first switch control line, and each second control signal line is connected to the flexible circuit board through a second switch control line. Therefore, the number of the data signal lines can be reduced by half, the arrangement of the multipath distribution units is reduced, and a narrow frame can be realized.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] As the resolution of display products increases, the number of pixels increases, resulting in an increase in the number of data lines. In existing display products, a Demux (demultiplexer) circuit is usually used to connect the data line to the pad. However, the Demux circuit is not conducive to the realization of a narrow frame and will increase the power consumption of the display product. Therefore, how to simultaneously achieve a narrow frame of a display product and reduce the number of data lines has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device, which are used to simultaneously achieve a narrow frame of a display product and reduce data lines.

[0005] In a first aspect, the present disclosure provides a display panel, comprising: a plurality of pixel circuit groups arranged along a first direction, the pixel circuit group comprising a first pixel circuit column and a second pixel circuit column adjacent to each other along the first direction, the first pixel circuit column and the second pixel circuit column respectively comprising a plurality of pixel circuits arranged along a second direction, the first direction and the second direction intersecting;

[0006] In the pixel circuit group, a data signal line extending along the second direction is arranged between the first pixel circuit column and the second pixel circuit column, and the pixel circuits in the first pixel circuit column and the second pixel circuit column are electrically connected to the same data signal line;

[0007] The pixel circuit comprises a data writing module, wherein in the first pixel circuit column, the data writing module in each pixel circuit is electrically connected to the data signal line via a first switch; in the second pixel circuit column, the data writing module in each pixel circuit is electrically connected to the data signal line via a second switch, and the first switch and the second switch are turned on in a time-sharing manner;

[0008] The display panel includes a first control signal line and a second control signal line extending along the second direction. The first switches corresponding to different pixel circuits in the first pixel circuit column are connected to the same first control signal line, and the second switches corresponding to different pixel circuits in the second pixel circuit column are connected to the same second control signal line;

[0009] The display panel includes a display area and a non-display area located on at least one side of the display area. The non-display area includes a flexible circuit board;

[0010] The non-display area includes a first switch control line and a second switch control line extending along the first direction. Each first control signal line is connected to the flexible circuit board through a first switch control line, and each second control signal line is connected to the flexible circuit board through a second switch control line.

[0011] In a second aspect, the present disclosure provides a display device including the display panel as described in the first aspect.

[0012] The technical solutions provided by the embodiments of the present disclosure have the following advantages compared with the prior art:

[0013] By providing a switch between the data writing module of the pixel circuit group and the corresponding data signal line, time-division conduction of adjacent pixel circuit columns can be achieved, and the number of data signal lines in the display panel can be halved, thereby reducing costs; by connecting each control signal line in different pixel circuit groups to its corresponding switch control line and further connecting to the flexible circuit board, the layout of the multiplexing unit can be reduced, which is beneficial to achieving a narrow bezel design and reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0015] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0016] Figure 1 Shown is a connection schematic diagram of a display panel in the related art;

[0017] Figure 2 Shown is a connection schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 3 ForFigure 2 Schematic diagram of the connection of the middle pixel circuit;

[0019] Figure 4 The figure shows a wiring schematic diagram of a data line and a connection line segment provided by an embodiment of the present disclosure;

[0020] Figure 5 The figure shows a relative position relationship diagram of a data signal line, a control signal line, and a connection trace provided by an embodiment of the present disclosure;

[0021] Figure 6 The figure shows a relative position relationship schematic diagram of a first connection line segment and a second connection line segment provided by an embodiment of the present disclosure;

[0022] Figure 7 The figure shows a film layer schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0023] Figure 8 The figure shows a relative position relationship diagram of a second metal layer and a third metal layer provided by an embodiment of the present disclosure;

[0024] Figure 9 The figure shows a circuit layout provided by an embodiment of the present disclosure;

[0025] Figure 10 The figure shows a schematic diagram of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0026] In order to more clearly understand the above-mentioned objects, features, and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0027] In the following description, many specific details are set forth in order to fully understand the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0028] Figure 1 The figure shows a connection schematic diagram of a display panel in the related art. Please refer to Figure 1, the display panel 100’ includes a display area AA’ and a non-display area NA’. The non-display area NA’ is located on at least one side of the display area AA’. The display area AA’ includes a plurality of data lines D0’ extending along the second direction D2’ and arranged along the first direction D1’. The display area AA’ includes a first display area AA1’ and a second display area AA2’. The second display area AA2’ is located on at least one side of the first display area AA1’. The data lines D0’ in the second display area AA2’ extend to the first display area AA1’ through connection traces L0’ and are then connected to fan-out traces S0’ in the non-display area NA’. The connection trace L0’ includes a first connection segment L1’ and a second connection segment L2’. The non-display area NA’ includes a multiplexing unit F0’. The multiplexing unit F0’ includes switching elements T’. The bonding area B0’ is located on the side of the multiplexing unit F0’ away from the display area AA’. The bonding area B0’ includes a plurality of conductive pads P0’. The conductive pads P0’ are used for bonding with a control chip. The switching element T’ includes a control terminal, an input terminal, and an output terminal, Figure 1 Taking the example that only one multiplexing unit F0’ includes 2 switching elements T’, the input terminals of the 2 switching elements T’ in the same multiplexing unit F0’ are connected together for connecting to the same conductive pad P0’. The output terminals of the switching elements T’ are connected to the data lines D0’ in a one-to-one correspondence through the fan-out traces S0’. The control terminals of the 2 switching elements T’ in the same multiplexing unit F0’ are connected to 2 switching control lines K0’ in a one-to-one correspondence. That is, the conductive pad P0’ forms an electrical connection with the data line D0’ through the switching element T’ in the multiplexing unit F0’. The related art realizes the signal transmission of the data line D0’ by setting the multiplexing unit F0’ and the connection trace L0’. With the increase of the pixel density of the display product, the number of data lines D0’ increases. The setting of the multiplexing unit F0’ is not conducive to the realization of a narrow border and will cause an increase in the power consumption of the display product.

[0029] In view of the above problems, the present disclosure provides a display panel 100 for reducing the number of data lines, realizing a narrow border, and reducing the production cost. Figure 2 The following shows a connection schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 3 For Figure 2 the pixel circuit connection schematic diagram, please refer to Figure 2 and Figure 3 , the present disclosure provides a display panel 100, including: a plurality of pixel circuit groups B0 arranged along the first direction D1. The pixel circuit group B0 includes a first pixel circuit column B1 and a second pixel circuit column B2 adjacent to each other along the first direction D1. The first pixel circuit column B1 and the second pixel circuit column B2 respectively include a plurality of pixel circuits B01 arranged along the second direction D2. The first direction D1 and the second direction D2 intersect; Figure 2Only a partial pixel circuit group B0 included on the display panel 100 is schematically shown, and the number of pixel circuit groups B0 actually included on the display panel 100 is not limited; Figure 2 Taking the example that the first pixel circuit column B1 is located on one side of the second pixel circuit column B2 along the first direction D1 for illustration; Figure 2 Only the pixel circuit B01 in the display panel 100 is schematically shown in the structure of a rectangular frame, and the structure of the pixel circuit B01 actually included on the display panel 100 is not limited.

[0030] In the pixel circuit group B0, a data signal line D0 extending along the second direction D2 is provided between the first pixel circuit column B1 and the second pixel circuit column B2, and the pixel circuits B01 in the first pixel circuit column B1 and the second pixel circuit column B2 are electrically connected to the same data signal line D0; Figure 2 and Figure 3 Only a partial pixel circuit B01 included in the pixel circuit column on the display panel 100 is schematically shown, and the number of pixel circuits B01 actually included in the pixel circuit column is not limited. It should be noted that the electrical connection mentioned in the embodiments of the present invention may be a direct connection between two connection bodies, or a signal connection formed by other line segments between two connection bodies, or a signal connection formed by a switching element (such as a transistor) between two connection bodies, etc.

[0031] Please refer to Figure 3 , the pixel circuit B01 includes a data writing module X, the first pixel circuit column B1 includes a first pixel circuit B11, and the first data writing module X1 in each first pixel circuit B11 is electrically connected to the data signal line D0 through a first switch Y1; the second pixel circuit column B2 includes a second pixel circuit B12, and the second data writing module X2 in each second pixel circuit B12 is electrically connected to the data signal line D0 through a second switch Y2, and the first switch Y1 and the second switch Y2 are turned on in a time-sharing manner; that is, the first pixel circuit column B1 and the second pixel circuit column B2 in the same pixel circuit group B0 share a data signal line D0. By setting a switch Y between the data signal line D0 and the data writing module X in each pixel circuit B01, time-sharing conduction of the first pixel circuit column B1 and the second pixel circuit column B2 can be achieved. In this way, sharing of the data signal line D0 between adjacent pixel columns can be realized, the number of data signal lines D0 in the display panel 100 can be halved, thereby reducing costs; when the number of data signal lines D0 is halved, a multi-channel distribution unit does not need to be provided, or the number of switches in the multi-channel distribution unit is small, which is beneficial to realizing a narrow border compared with the related art.

[0032] Optionally, the pixel circuit B01 further includes a first reset transistor T5, a compensation transistor T4, a driving transistor T3, a writing transistor T2, a first light-emitting control transistor T1, a second light-emitting control transistor T6, a second reset transistor T7, a bias transistor T8, and a storage capacitor Cst; two electrodes of the storage capacitor Cst are respectively connected to a power supply signal line PVDD and a first node N1, two electrodes of the first reset transistor T5 are respectively connected to a first reset signal line Vref1 and the first node N1, and a gate of the first reset transistor T5 is connected to a first scan line S1N. Two electrodes of the compensation transistor T4 are respectively connected to a third node N3 and the first reset transistor T5, and a gate is connected to a second scan line S2N. Two electrodes of the writing transistor T2 are respectively connected to a data signal line D0 and a second node N2, where a switch Y is included between the writing transistor T2 and the data signal line D0, and a gate of the writing transistor T2 is connected to a third scan line SP. Two electrodes of the first light-emitting control transistor T1 are respectively connected to the power supply signal line PVDD and the second node N2, and a gate is connected to a light-emitting control line EMIT. Two electrodes of the second light-emitting control transistor T6 are respectively connected to the third node N3 and a fourth node N4, and a gate is connected to the light-emitting control line EMIT. Two electrodes of the second reset transistor T7 are respectively connected to a second reset signal line Vref2 and the fourth node N4, the fourth node N4 is connected to an anode of a light-emitting element, and a gate is connected to a fourth scan line SP*. Two electrodes of the bias transistor T8 are respectively connected to a bias signal line VDH and the second node N2, and a gate is connected to the fourth scan line SP*. It should be noted that in the driving circuit of this embodiment, only P-type transistors are taken as examples for each transistor for illustration, but the type of the transistor is not limited. In addition, Figure 3 The structure of the shown pixel driving circuit is only schematic, and the present disclosure is not limited thereto.

[0033] It should be noted that, Figure 3 only the correspondence between one first pixel circuit B11 in the first pixel circuit column B1, one second pixel circuit B12 in the second pixel circuit column B2 and the data signal line D0 is schematically shown, and the correspondence between other pixel circuits B01 in the first pixel circuit column B1 and the second pixel circuit column B2 and the data signal line D0 can all be referred to Figure 3 .

[0034] Please refer to Figure 2 and Figure 3 , the display panel 100 includes a first control signal line S1 and a second control signal line S2 extending along the second direction D2, first switches Y1 corresponding to different pixel circuits B01 in the first pixel circuit column B1 are connected to the same first control signal line S1, and second switches Y2 corresponding to different pixel circuits B01 in the second pixel circuit column B2 are connected to the same second control signal line S2; Figure 2Only a part of the control signal lines S0 included on the display panel 100 is schematically shown, and the number of the control signal lines S0 actually included on the display panel 100 is not limited. Figure 2 Explanation is made with the first control signal line S1 and the second control signal line S2 respectively located on both sides of the data signal line D0 along the first direction D1.

[0035] The display panel 100 includes a display area AA and a non-display area NA located on at least one side of the display area AA. The non-display area NA includes a flexible circuit board 01. The non-display area NA includes a first switch control line K1 and a second switch control line K2 extending along the first direction D1. Each first control signal line S1 is connected to the flexible circuit board 01 through a first switch control line K1, and each second control signal line S2 is connected to the flexible circuit board 01 through a second switch control line K2.

[0036] Specifically, a first switch Y1 corresponding to each pixel circuit B01 in the first pixel circuit column B1 is connected to the first control signal line S1, and the first switch Y1 can be configured to be turned on or off by a first switch control signal applied by the first control signal line S1. A second switch Y2 corresponding to each pixel circuit B01 in the second pixel circuit column B2 is connected to the second control signal line S2, and the second switch Y2 can be configured to be turned on or off by a second switch control signal applied by the second control signal line S2. The first control signal lines S1 in different pixel circuit groups B0 are connected to a first switch control line K1 located in the non-display area NA, and the second control signal lines S2 in different pixel circuit groups B0 are connected to a second switch control line K2 located in the non-display area NA. The first switch control line K1 and the second switch control line K2 extend along the first direction D1, and the first switch control line K1 and the second switch control line K2 are respectively connected to the flexible circuit board 01. Optionally, the flexible circuit board 01 includes a control chip, and the control chip can send a control signal to the corresponding control signal line S0 through a conductive pad, a switch control line K0 electrically connected to the conductive pad, and a control signal line S0 connected to the switch control line K0 to realize the time-division conduction of the first switch Y1 and the second switch Y2. The display panel 100 further includes a driving chip 02, and the driving chip 02 sends a data signal to the corresponding data signal line D0. Through the time-division conduction of the first switch Y1 and the second switch Y2, the time-division conduction of the first pixel circuit column B1 and the second pixel circuit column B2 is realized, and further the data signal transmission is realized. That is to say, in the embodiments of the present disclosure, it is not necessary to arrange a multi-way distribution unit in the non-display area NA to realize the data signal transmission between the flexible circuit board 01 and the data signal line D0, thereby providing a compressed space for the display panel 100 and the border of the display device, which is beneficial to realizing a further narrow border design of the display panel 100 and the display device and improving the user experience effect.

[0037] Thus, by providing a switch Y between the data writing module X of the pixel circuit group B0 and the corresponding data signal line D0, time-division conduction of adjacent pixel circuit columns can be achieved, and the number of data signal lines D0 in the display panel 100 can be halved, thereby reducing costs; by connecting the control signal lines S0 in different pixel circuit groups B0 to their corresponding switch control lines K0 and further connecting them to the flexible circuit board 01, the layout of the multiplexing unit can be reduced, which is conducive to achieving a narrow border design and reducing power consumption.

[0038] It should be noted that Figure 2 only the connections of the first switch control line K1 and the second switch control line K2 to the flexible circuit board 01 are schematically shown. The points where the first switch control line K1 and the second switch control line K2 lead out and are connected to the flexible circuit board 01 may be located below the first display area AA1. The present disclosure does not limit this.

[0039] Please continue to refer to Figure 2 and Figure 3 , the present disclosure provides a display panel 100. Between the first pixel circuit column B1 and the second pixel circuit column B2, along the first direction D1, the first control signal line S1 and the second control signal line S2 are respectively located on both sides of the data signal line D0.

[0040] Specifically, the pixel circuit group B0 includes a first pixel circuit column B1 and a second pixel circuit column B2. The first pixel circuit column B1 includes a plurality of first pixel circuits B11 arranged along the second direction D2, and the second pixel circuit column B2 includes a plurality of second pixel circuits B12 arranged along the second direction D2. The pixel circuit B01 includes a data writing module X. The first data writing modules X1 of the first pixel circuits B11 in the first pixel circuit column B1 are respectively connected to the data signal line D0 through first switches Y1, and the second data writing modules X2 of the second pixel circuits B12 in the second pixel circuit column B2 are respectively connected to the data signal line D0 through second switches Y2. Each of the first switches Y1 is connected to the same first control signal line S1, and each of the second switches Y2 is connected to the same second control signal line S2. That is, in a pixel circuit group B0, there are included a first control signal line S1, a second control signal line S2, and a data signal line D0. The first control signal line S1, the second control signal line S2, and the data signal line D0 are located between the first pixel circuit column B1 and the second pixel circuit column B2. Along the first direction D1, the data signal line D0 is located between the first control signal line S1 and the second control signal line S2, which can make the distance from the data signal line D0 to the first control signal line S1 the same as the distance from the data signal line D0 to the second control signal line S2, minimizing the influence of signal coupling and being beneficial to normal display. Thus, between the first pixel circuit column B1 and the second pixel circuit column B2, by setting the data signal line D0 between the first control signal line S1 and the second control signal line S2, it is convenient to connect the first control signal line S1 and the second control signal line S2 to the data signal line D0, and the distance from the data signal line D0 to the first control signal line S1 and the second control signal line S2 can be made the same, reducing the influence of signal coupling caused by unequal distances and being beneficial to the normal display of the display panel 100.

[0041] Figure 4 The following is a wiring schematic diagram of a data line and a connection line segment provided by an embodiment of the present disclosure. Please refer to Figure 2 and Figure 4 , the present disclosure provides a display panel 100. The display area AA includes a connection line segment L0, and the non-display area NA includes a fan-out trace S0. The non-display area NA includes a fan-out area A1 located on one side of the display area AA along the second direction D2. The fan-out area A1 includes a plurality of fan-out traces S0. The display area AA includes a first display area AA1 and a second display area AA2. The second display area AA2 is located on at least one side of the first display area AA1 along the first direction D1. Optionally, in this embodiment, the first display area AA1 is located in the middle area of the display panel 100, and the second display area AA2 is located on one side or both sides of the display panel 100 along the first direction D1. Figure 2 and Figure 4Taking the example that the second display area AA2 is provided on both sides of the first display area AA1 for illustration.

[0042] The data signal line D0 includes a first data signal line D1 and a second data signal line D2. The first data signal line D1 is located in the first display area AA1, and the second data signal line D2 is located in the second display area AA2. The first data signal line D1 is electrically connected to the fan-out trace S0, and the second data signal line D2 is electrically connected to the fan-out trace S0 through the connection trace L0. The connection trace L0 is located in the display area AA and includes a first connection segment L1 extending along the first direction D1 and a second connection segment L2 extending along the second direction D2. The second data signal line D2 is electrically connected to the second connection segment L2 located in the first display area AA1 through the first connection segment L1. In the first display area AA1, the second connection segment L2 is electrically connected to the fan-out trace S0.

[0043] Specifically, the first connection segment L1 extends along the first direction D1 and is connected to the second data signal line D2 in the second display area AA2. The second connection segment L2 extends along the second direction D2 and is connected to the fan-out trace S0 in the non-display area NA. The first data signal line D1 in the first display area AA1 is directly connected to the fan-out trace S0 in the non-display area NA. That is, the second data signal line D2 located in the second display area AA2 is connected to the fan-out trace S0 through the connection trace L0 to obtain signals, and the first signal line located in the first display area AA1 can be directly connected to the fan-out trace S0 to obtain signals. In this way, by setting the connection segment L0, there is no need to route wires at the lower left border and / or lower right border of the display panel 100. Instead, the second data signal line D2 is electrically connected to the fan-out trace S0 by the second connection segment L2 in the first display area AA1, providing compressed space for the lower left border and / or lower right border of the display panel 100, which is beneficial to realizing the narrow border design of the product.

[0044] It should be noted that the first connection segment L1 extending along the first direction D1 means that the overall extension trend of the first connection segment L1 is the first direction D1, and it does not limit that the first connection segment L1 must be a straight line. Similarly, the second connection segment L2 extending along the second direction D2 means that the overall extension trend of the second connection segment L2 is the second direction D2, and it does not limit that the second connection segment L2 must be a straight line.

[0045] Please refer to Figure 4, the present disclosure provides a display panel 100. The display panel 100 further includes a plurality of first dummy line segments L01 extending along a first direction D1 and a plurality of second dummy line segments L02 extending along a second direction D2. The first dummy line segments L01 are disposed on the same layer as the first connection line segments L1 and are insulated from the first connection line segments L1 and the second connection line segments L2. The second dummy line segments L02 are disposed on the same layer as the second connection line segments L2 and are insulated from the second connection line segments L2 and the first connection line segments L1.

[0046] Specifically, when the first dummy line segments L01 and the first connection line segments L1 are disposed in the same film layer, these line segments can be formed in the same process, which is beneficial to simplifying the wiring process. Additionally, if the first dummy line segments L01 are not disposed in the film layer where the first connection line segments L1 are located, and only the first connection line segments L1 are disposed in the film layer where the first connection line segments L1 are located, the metal density of this film layer is uneven. It may cause the off-screen mura phenomenon due to the difference in the metal reflection effect in different regions. At the same time, the uneven metal density of this film layer may lead to poor uniformity of exposure and etching in the manufacturing process, resulting in uneven line widths of the first connection line segments L1, and further leading to an increase in the capacitance load difference in different regions, affecting the display uniformity. In this embodiment, the first dummy line segments L01 are disposed in the film layer where the first connection line segments L1 are located, and the extending direction of the first dummy line segments L01 is the same as that of the first connection line segments L1, and the first dummy line segments L01 are insulated from the first connection line segments L1 and the second connection line segments L2, which is beneficial to improving the uniformity of the metal density of the film layer where the first connection line segments L1 are located, thereby being beneficial to improving the off-screen mura phenomenon that may be caused by uneven metal density and being beneficial to enhancing the display uniformity of the display panel 100. Similarly, when the second connection line segments L2 and the second dummy line segments L02 are disposed in the same film layer, these line segments can be formed in the same process, which is beneficial to simplifying the wiring process. In this embodiment, the second dummy line segments L02 are disposed in the film layer where the second connection line segments L2 are located, and the extending direction of the second dummy line segments L02 is the same as that of the second connection line segments L2, and the second dummy line segments L02 are insulated from the first connection line segments L1 and the second connection line segments L2, which is beneficial to improving the uniformity of the metal density of the film layer where the second connection line segments L2 are located and is beneficial to improving the off-screen mura phenomenon that may be caused by uneven metal density. In this way, by disposing the first dummy line segments L01 on the same layer as the first connection line segments L1 and insulating them, and disposing the second dummy line segments L02 on the same layer as the second connection line segments L2 and insulating them, the uniformity of exposure and etching of film layer etching can be improved, the metal density of the film layer can be effectively improved, and the display uniformity can be enhanced.

[0047] Please continue to refer to Figure 4, the present disclosure provides a display panel 100. In at least a part of the pixel circuit group B0, along the first direction D1, the data signal line D0 and the second connection line segment L2 are located between the first control signal line S1 and the second control signal line S2; in at least a part of the pixel circuit group B0, along the first direction D1, the data signal line D0 and the second dummy line segment L02 are located between the first control signal line S1 and the second control signal line S2.

[0048] Specifically, in an optional embodiment provided by the present disclosure, the second connection line segment L2 is located in the first display area AA1, at least a part of the second dummy line segment L02 is located in the first display area AA1, and at least a part of the second dummy line segment L02 is located in the second display area AA2. The second dummy line segment L02 and the second connection line segment L2 have the same extension direction, are arranged in the same layer and are insulated. In the second display area AA2, along the first direction D1, between the first control signal line S1 and the second control signal line S2, there are included the data signal line D0 and the second dummy line segment L02; in the first display area AA1, along the first direction D1, between at least a part of the first control signal line S1 and the second control signal line S2, there are included the data signal line D0 and the second connection line segment L2, and between at least a part of the first control signal line S1 and the second control signal line S2, there are included the data signal line D0 and the second dummy line segment L02; that is to say, the second dummy line segment L02 can be arranged between the first control signal line S1 and the second control signal line S2 where the second connection line segment L2 is not provided in the second display area AA2, the second dummy line segment L02 can be arranged between the first control signal line S1 and the second control signal line S2 where the second connection line segment L2 is not provided in the first display area AA1, and the second connection line segment L2 can be arranged between at least a part of the first control signal line S1 and the second control signal line S2 in the first display area AA1 to form a trace extending along the second direction D2 and uniformly arranged in the metal layer, which is beneficial to improving the uniformity of the arrangement of the traces in the metal layer, beneficial to improving the uniformity of the metal density of the film layer where the second connection line segment L2 is located, can improve the uniformity of the exposure and etching of the film layer etching, effectively improve the metal density of the film layer, and is beneficial to improving the display uniformity. Thus, by arranging the second dummy line segment L02 between the first control signal line S1 and the second control signal line S2 where the second connection line segment L2 is not provided, the uniformity of the arrangement of the traces in the metal layer can be improved, the metal density of the film layer can be effectively improved, and the display uniformity of the display panel 100 is beneficial to be improved.

[0049] Figure 5 The figure shows a relative position relationship diagram of a data signal line, a control signal line, and a connection trace provided by an embodiment of the present disclosure. Please refer to Figures 4 to 5 , the present disclosure provides a display panel 100. In at least a part of the pixel circuit group B0, the data signal line D0, the first control signal line S1, the second connection line segment L2, the second control signal line S2, and the second dummy line segment L02 are arranged in the same layer.

[0050] Specifically, in an optional embodiment provided by the present disclosure, the data signal line D0, the first control signal line S1, the second control signal line S2, and the second connection segment L2 are arranged on the same layer. That is, the second dummy segment L02 is also located in the third metal layer M3. When the data signal line D0, the first control signal line S1, the second control signal line S2, the second connection segment L2, and the second dummy segment L02 are arranged on the same layer, there is no need to introduce a new film layer for the first control signal line S1 and the second control signal line S2, and there is no need to introduce a new film layer for the second connection segment L2 and the second dummy segment L02. When manufacturing the data signal line D0, the first control signal line S1, the second control signal line S2, the second connection segment L2, and the second dummy segment L02 can be manufactured by using a single mask plate in one production process. This is beneficial to simplifying the overall film layer structure of the display panel 100, saving the number of mask plates in the manufacturing process, and at the same time beneficial to improving the production efficiency of the display panel 100. Thus, when the data signal line D0, the first control signal line S1, the second control signal line S2, the second connection segment L2, and the second dummy segment L02 are arranged on the same layer, the above-mentioned wiring can be manufactured by using only one mask plate in one production process, which can simplify the film layer structure and improve the production efficiency.

[0051] Figure 6 The following shows a schematic diagram of the relative position relationship between a first connection segment and a second connection segment provided by an embodiment of the present disclosure. Please refer to Figures 4 to 6 The present disclosure provides a display panel 100. The first connection segments L1 in each connection trace L0 are arranged on the same layer, the second connection segments L2 in each connection trace L0 are arranged on the same layer, and the first connection segment L1 and the second connection segment L2 are arranged on different layers.

[0052] Specifically, in an alternative embodiment provided by the present disclosure, the first connection line segment L1 is entirely located in the second metal layer M2, and the second connection line segment L2 is entirely located in the third metal layer M3. By arranging the first connection line segment L1 and the second connection line segment L2 in different layers, the wiring density in the third metal layer M3 can be reduced to avoid overcrowding. Moreover, there is no need to consider the phenomenon of short circuit between the first connection line segment L1 and different second connection line segments L2. Only by electrically connecting the first connection line segment L1 to the corresponding second connection line segment L2 through vias can the wiring difficulty of the first connection line segment L1 and the second connection line segment L2 be simplified. In addition, by arranging the first connection line segment L1 in the second metal layer M2 and the second connection line segment L2 in the third metal layer M3, the number of insulating layers between the first connection line segment L1 and the second connection line segment L2 can be reduced, facilitating the via connection between the first connection line segment L1 and the second connection line segment L2. In this way, by arranging the first connection line segment L1 and the second connection line segment L2 in different layers, the probability of short circuit between the first connection line segment L1 and different second connection line segments L2 can be reduced, which is beneficial to simplifying the wiring difficulty.

[0053] Please refer to Figure 4 and Figure 6 , the present disclosure provides a display panel 100, in which at least one first dummy line segment L01 is floating; and / or, at least one second dummy line segment L02 is floating.

[0054] Specifically, to simplify the manufacturing process, when the first connection line segment L1 and the first dummy line segment L01 are simultaneously arranged in the film layer where the first connection line segment L1 is located, at least one first dummy line segment L01 introduced in this film layer can be made floating without being connected to other signal lines, thereby simplifying the manufacturing processes such as via punching in the display panel 100. Alternatively, when the second connection line segment L2 and the second dummy line segment L02 are simultaneously arranged in the film layer where the second connection line segment L2 is located, at least one second dummy line segment L02 introduced in this film layer can be made floating without being connected to other signal lines, which is also beneficial to simplifying the manufacturing processes such as via punching in the display panel 100. Optionally, each first dummy line segment L01 in the film layer where the first connection line segment L1 is located is floating, and each second dummy line segment L02 in the film layer where the second connection line segment L2 is located is floating. In this way, while improving the uniformity of the metal density in the film layer, the number of vias can be reduced, further simplifying the manufacturing process.

[0055] Figure 7 The following shows a schematic diagram of the film layer of a display panel provided by an embodiment of the present disclosure. Figure 8 The following shows a relative position relationship diagram of the second metal layer and the third metal layer provided by an embodiment of the present disclosure. Figure 9 The following shows a circuit layout provided by an embodiment of the present disclosure. Please refer to Figure 5 , Figure 7 and Figure 9, the present disclosure provides a display panel 100. The display panel 100 includes a substrate 00 and a first metal layer M1, a capacitive metal layer MC, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 disposed on the substrate 00. Along the thickness direction of the display panel 100, the capacitive metal layer MC is located on the side of the first metal layer M1 away from the substrate 00. The first metal layer M1 can be, for example, a gate metal layer, and the gate of the transistor T in the display panel 100 can be disposed on the first metal layer M1. The second metal layer M2 is located on the side of the capacitive metal layer MC away from the substrate 00. The capacitive metal layer MC is used to form a capacitive structure with the first metal layer M1 or the second metal layer M2. The third metal layer M3 is located on the side of the second metal layer M2 away from the substrate 00, and the fourth metal layer M4 is located on the side of the third metal layer M3 away from the substrate 00. The display panel 100 further includes a metal layer M0 and a semiconductor layer poly. Among them, the metal layer M0 is located on the side of the first metal layer M1 facing the substrate, and the metal layer M0 is used for light shielding and improving the antistatic ability of the display panel 100; the semiconductor layer poly is located on the side of the first metal layer M1 facing the substrate 00. In some other embodiments, the semiconductor layer poly can also be located on the side of the first metal layer M1 away from the substrate 00, which is not limited in the present disclosure. The semiconductor layer poly includes a source region and a drain region, and the source region and the drain region are formed by doping N-type impurity ions or P-type impurity ions. The source electrode s and the drain electrode d of the transistor T in the display panel 100 can be located on the second metal layer M2, and the source electrode s and the drain electrode d of the transistor T are electrically connected to the semiconductor layer poly through contact holes respectively. Signal traces or dummy traces can be arranged on the second metal layer M2, the third metal layer M3, and the fourth metal layer M4. In an optional embodiment provided by the present disclosure, the data signal line D0, the second connection segment L2, and the second dummy segment L02 are located on the third metal layer M3.

[0056] Specifically, the data signal line D0, the second connection segment L2, and the second dummy segment L02 are located on the same layer, such as on the third metal layer M3, which is beneficial to simplifying the connection between the second data signal line D02 and the second connection segment L2 and reducing the number of vias. By arranging the data signal line D0, the second connection segment L2, and the second dummy segment L02 with the same extension direction on the third metal layer M3, it is not necessary to additionally provide a film layer for the second connection segment L2 and the second dummy segment L02. The above traces can be fabricated simultaneously only through one mask, which simplifies the process and improves the metal density uniformity of the third metal layer M3. Please refer to Figure 8 , the power supply signal line PVDD can also be arranged on the third metal layer M3. It should be noted that the power supply signal line PVDD needs to be insulated from the data signal line D0.

[0057] Please refer to Figures 5 to 9, the present disclosure provides a display panel 100, where the first connection line segment L1 and the first dummy line segment L01 are located in the second metal layer M2.

[0058] Specifically, in an optional embodiment provided by the present disclosure, the connection line segment L0 includes a first connection line segment L1 and a second connection line segment L2. The second connection line segment L2 and the second dummy line segment L02 are located in the third metal layer M3, and the first connection line segment L1 and the first dummy line segment L01 are located in the second metal layer M2. The source electrode s, the drain electrode d, the second connection line segment L2, and the second dummy line segment L02 can be fabricated by only one mask plate, which simplifies the process and improves the metal density uniformity of the second metal layer M2 to improve display uniformity. The first connection line segment L1 and the second connection line segment L2 are arranged in different layers and are connected by vias, which can reduce the routing arrangement density of the third metal layer M3. In this way, by arranging the first connection line segment L1 and the first dummy line segment L01 in the second metal layer M2, the wiring density of the third metal layer M3 can be reduced, and the short-circuit probability between the first dummy line segment L01 and the second connection line segment L2 or the second dummy line segment L02 can be reduced, which is beneficial to improving the display performance.

[0059] Please refer to Figure 2 , Figure 3 and Figure 9 , the present disclosure provides a display panel 100, where the first pixel circuit column B1 and the second pixel circuit column B2 connected to the same data signal line D0 are arranged in a mirror image.

[0060] Specifically, in the same pixel circuit group B0, the first pixel circuit B11 in the first pixel circuit column B1 and the second pixel circuit B12 in the second pixel circuit column B2 can have substantially the same structure. Further, the structures of the first pixel circuit B11 in the first pixel circuit column B1 and the second pixel circuit B12 in the second pixel circuit column B2 can be symmetrical to each other. For example, the first pixel circuit B11 in the first pixel circuit column B1 includes transistors T1 to T8, a storage capacitor Cst, and a light-emitting element. The transistors T1 to T8, the storage capacitor Cst, and the light-emitting element in the first pixel circuit column B1 can be arranged symmetrically with the transistors T1 to T8, the storage capacitor Cst, and the light-emitting element in the second pixel circuit column B2. In this way, by arranging the first pixel circuit column B1 and the second pixel circuit column B2 connected to the same data signal line D0 in a mirror image, it is convenient for the newly introduced switch Y to be connected to the data signal line D0 and the data writing module X respectively, reducing the wiring.

[0061] Please refer to Figure 3 and Figure 9, the present disclosure provides a display panel 100. The data writing module X includes a writing transistor T5, and no other transistors are provided between the writing transistor T5 and the first switch Y1, and / or no other transistors are provided between the writing transistor T5 and the second switch Y2.

[0062] Specifically, in an optional embodiment provided by the present disclosure, the writing transistor T5 in the first pixel circuit column B1 is directly connected to the first switch Y1; in another optional embodiment provided by the present disclosure, the writing transistor T5 in the second pixel circuit column B2 is directly connected to the second switch Y2; in still another optional embodiment provided by the present disclosure, the writing transistor T5 in the first pixel circuit column B1 is directly connected to the first switch Y1, and the writing transistor T5 in the second pixel circuit column B2 is directly connected to the second switch Y2. That is to say, no other transistors are provided between the writing transistor T5 in the first pixel circuit B11 and the first switch Y1. The data signal can be directly transmitted to the first pixel circuit B11 through the conduction of the first switch Y1 without passing through other switching elements; no other transistors are provided between the writing transistor T5 in the second pixel circuit B12 and the second switch Y2. The data signal can be directly transmitted to the second pixel circuit B12 through the conduction of the second switch Y2 without passing through other switching elements, which is beneficial to improving the signal transmission efficiency and pixel density.

[0063] Figure 10 The following shows a schematic diagram of a display device provided by an embodiment of the present disclosure. Please refer to Figure 10 , the present disclosure provides a display device 200, including the display panel 100 described above. The display device 200 provided by the embodiment of the present disclosure can be any electronic device with a display function, such as a touch display screen, a mobile phone, a tablet computer, a notebook computer, an e-reader or a television. The display device 200 provided by the embodiment of the present disclosure has the beneficial effects of the display panel 100 provided by the embodiment of the present disclosure. For specific descriptions of the display panel 100, reference can be made to the above embodiments, and details are not described herein again.

[0064] It can be understood that Figure 10 Only a right-angled rectangular structure is taken as an example to illustrate one shape of the display device 200. In some other embodiments of the present disclosure, the display device 200 can also be embodied as a circular shape, an oval shape or any other feasible shape, and the present disclosure does not specifically limit this.

[0065] In summary, for a display panel and a display device provided by the present disclosure, by arranging switches between the data writing modules of pixel circuit groups and corresponding data signal lines, time-division conduction of adjacent pixel circuit columns can be achieved, and the number of data signal lines in the display panel can be halved, thereby reducing costs. By connecting each control signal line in different pixel circuit groups to its corresponding switch control line and further connecting to a flexible circuit board, the layout of multiplexing units can be reduced, which is beneficial to achieving a narrow border design and reducing power consumption. By arranging the data signal lines between the first control signal line and the second control signal line, the distances between the data signal lines and the first control signal line and the second control signal line can be made consistent, reducing the influence of signal coupling caused by unequal distances. By arranging connection segments, there is no need to route wires at the lower left border and / or lower right border of the display panel, providing compressed space for the lower left border and / or lower right border of the display panel, which is beneficial to achieving a narrow border design for the product. By arranging the first dummy segment and the first connection segment on the same layer and insulating them, and arranging the second dummy segment and the second connection segment on the same layer and insulating them, the exposure and etching uniformity of film layer etching can be improved, effectively improving the metal density of the film layer and enhancing display uniformity. By arranging the first dummy segment and the second dummy segment, the layout uniformity of the traces in the metal layer can be improved, effectively improving the metal density of the film layer. By arranging the data signal lines, the first control signal line, the second control signal line, the second connection segment, and the second dummy segment on the same layer, the above-mentioned trace production can be completed using only one mask in one production process, which can simplify the film layer structure and improve production efficiency. By arranging the first connection segment and the second connection segment on different layers, the probability of short circuit between the first connection segment and different second connection segments can be reduced, which is beneficial to simplifying the wiring difficulty. By arranging the first connection segment L1 and the first dummy segment on the second metal layer, the wiring density of the third metal layer can be reduced, and the probability of short circuit between the first dummy segment and the second connection segment or the second dummy segment can be reduced, which is beneficial to improving display performance.

[0066] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: A plurality of pixel circuit groups arranged along a first direction, the pixel circuit group comprising a first pixel circuit column and a second pixel circuit column adjacent to each other along the first direction, the first pixel circuit column and the second pixel circuit column respectively comprising a plurality of pixel circuits arranged along a second direction, the first direction and the second direction intersecting; In the pixel circuit group, a data signal line extending along the second direction is arranged between the first pixel circuit column and the second pixel circuit column, and the pixel circuits in the first pixel circuit column and the second pixel circuit column are electrically connected to the same data signal line; The pixel circuit comprises a data writing module, wherein in the first pixel circuit column, the data writing module in each pixel circuit is electrically connected to the data signal line via a first switch; in the second pixel circuit column, the data writing module in each pixel circuit is electrically connected to the data signal line via a second switch, and the first switch and the second switch are turned on in a time-sharing manner; The display panel comprises a first control signal line and a second control signal line extending along the second direction, the first switches corresponding to different pixel circuits in the first pixel circuit column are connected to the same first control signal line, and the second switches corresponding to different pixel circuits in the second pixel circuit column are connected to the same second control signal line; The display panel includes a display area and a non-display area located at least on one side of the display area, and the non-display area includes a flexible circuit board; The non-display area includes first switch control lines and second switch control lines extending along the first direction, each of the first control signal lines is connected to the flexible circuit board through a first switch control line, and each of the second control signal lines is connected to the flexible circuit board through a second switch control line.

2. The display panel according to claim 1, wherein: Between the first pixel circuit column and the second pixel circuit column, along the first direction, the first control signal line and the second control signal line are respectively located at two sides of the data signal line.

3. The display panel according to claim 1, wherein: The display area includes connecting line segments, and the non-display area includes fan-out routing lines; The non-display area includes a fan-out area located at one side of the display area along the second direction, and the fan-out area includes a plurality of fan-out wirings; The display area includes a first display area and a second display area, the second display area is located at least on one side of the first display area along the first direction; the data signal line includes a first data signal line and a second data signal line, the first data signal line is located in the first display area, the second data signal line is located in the second display area, the first data signal line is electrically connected to the fan-out line, and the second data signal line is electrically connected to the fan-out line through the connecting line; The connecting line is located in the display area and includes a first connecting line segment extending along the first direction and a second connecting line segment extending along the second direction, and the second data signal line is electrically connected to the second connecting line segment located in the first display area through the first connecting line segment; In the first display area, the second connecting line segment is electrically connected to the fan-out wiring.

4. The display panel according to claim 3, wherein: The display panel also includes a plurality of first virtual line segments extending along the first direction and a plurality of second virtual line segments extending along the second direction, the first virtual line segments being arranged on the same layer as the first connecting line segments and being insulated from the first connecting line segments and the second connecting line segments, and the second virtual line segments being arranged on the same layer as the second connecting line segments and being insulated from the second connecting line segments and the first connecting line segments.

5. The display panel according to claim 4, wherein: In at least part of the pixel circuit groups, along the first direction, the data signal line and the second connection line segment are located between the first control signal line and the second control signal line; In at least part of the pixel circuit groups, along the first direction, the data signal line and the second dummy line segment are located between the first control signal line and the second control signal line.

6. The display panel according to claim 4, wherein: In at least part of the pixel circuit groups, the data signal line, the first control signal line, the second connection line segment, the second control signal line, and the second dummy line segment are arranged in the same layer.

7. The display panel according to claim 4, wherein: The first connection line segments in each of the connection lines are arranged on the same layer, the second connection line segments in each of the connection lines are arranged on the same layer, and the first connection line segments and the second connection line segments are arranged on different layers.

8. The display panel according to claim 4, wherein: At least one of the first imaginary line segments is floating; And / or, at least one of the second virtual line segments is floating.

9. The display panel according to claim 4, wherein: The display panel comprises a substrate and a first metal layer, a capacitor metal layer, a second metal layer, a third metal layer and a fourth metal layer arranged on the substrate, wherein along the thickness direction of the display panel, the capacitor metal layer is located on a side of the first metal layer away from the substrate, and the second metal layer is located on a side of the capacitor metal layer away from the substrate; The third metal layer is located on a side of the second metal layer facing away from the substrate, and the fourth metal layer is located on a side of the third metal layer facing away from the substrate; The data signal line, the second connecting line segment, and the second dummy line segment are located in the third metal layer.

10. The display panel according to claim 9, wherein: The first connecting line segment and the first dummy line segment are located in the second metal layer.

11. The display panel according to claim 1, wherein: The first pixel circuit column and the second pixel circuit column connected to the same data signal line are arranged in a mirror image.

12. The display panel according to claim 1, wherein: The data writing module includes a data writing transistor, and no other transistor is arranged between the data writing transistor and the first switch, and / or no other transistor is arranged between the data writing transistor and the second switch.

13. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-12.

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