Electrical connection testing

Abstract

A method for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element, the method comprising: applying a reference potential to a first of the two electrodes of each device; directing the charged particle beam onto a second of the two electrodes of each device; varying a signal applied to a control element of each device; and for each signal applied, monitoring signal charged particles from the second electrode of each device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to European patent application 22201818.6 filed on October 17, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments provided herein disclose a method for testing an array of devices, a charged particle optical apparatus for testing an array of devices, a substrate including a two-dimensional array of logic transistors in a test area, and a non-transitory computer readable medium. Background Art

[0004] During the manufacturing process of integrated circuits (ICs), unfinished or completed circuit components are inspected to ensure that they are manufactured according to design and are defect-free. Inspection systems that utilize optical microscopes or charged particle (e.g., electron) beam microscopes, such as scanning electron microscopes (SEMs), can be employed. As the physical size of IC components continues to shrink and their structures continue to become more complex, the accuracy and throughput of defect detection and inspection become more important. The overall image quality depends on a combination of high secondary electron and backscattered electron signal detection efficiency. Backscattered electrons have higher emission energy to escape from deeper layers of the sample, and therefore, their detection can be desirable for imaging of complex structures of 3D NAND devices, such as buried layers, nodes, high aspect ratio trenches, or holes. For applications such as overlay metrology, high-quality imaging and efficient collection of surface information from secondary electrons and buried layer information from backscattered electrons can be desired, highlighting the need to use multiple electron detectors in the SEM. Although multiple electron detectors in various structural arrangements can be used to maximize the collection and detection efficiency of secondary electrons and backscattered electrons, respectively, the combined detection efficiency is still low, and therefore, the image quality obtained may not be sufficient for high-precision and high-throughput defect inspection and metrology of two-dimensional and three-dimensional structures. Summary of the invention

[0005] An embodiment of the present disclosure provides a method for testing an array of devices, each device having an electrical connection between two electrodes that can be controlled by a signal applied to a control element, the method comprising: applying a reference potential to a first electrode of the two electrodes of each device; directing a charged particle beam to a second electrode of the two electrodes of each device; varying the signal applied to the control element of each device; and monitoring the signal charged particles from the second electrode of each device for each signal applied.

[0006] An embodiment of the present disclosure provides a charged particle optical device for testing an array of devices, each device having an electrical connection between two electrodes that can be controlled by a signal applied to a control element, the charged particle optical device comprising: a reference voltage source configured to supply a reference potential to a first electrode of the two electrodes of each device; a charged particle optical device configured to guide a charged particle beam to a second electrode of the two electrodes of each device; a signal source configured to vary the signal applied to the control element of each device; and a detector for monitoring signal charged particles from the second electrode of each device for each signal applied.

[0007] Embodiments of the present disclosure provide a substrate comprising an arrangement of devices in a test area, each device having an electrical connection between a source electrode and a drain electrode capable of being controlled by an electric potential applied to a gate electrode, wherein the source electrode or the drain electrode is connected to a common reference contact, and any one of the source electrode and the drain electrode that is not connected to the common reference contact is electrically coupled to a corresponding electrode contact exposed at a surface of the substrate.

[0008] An embodiment of the present disclosure provides a non-transitory computer-readable medium storing instructions for a processor of a controller to execute for testing an array of devices, each device having an electrical connection between two electrodes that can be controlled by a signal applied to a control element, the method comprising: controlling a reference potential to be applied to a first electrode of the two electrodes of each device; controlling a charged particle beam to be directed to a second electrode of the two electrodes of each device; controlling a change in a signal applied to a control element of each device; and for each signal applied, controlling monitoring of signal charged particles from a second electrode of each device.

[0009] Other advantages of embodiments of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings which illustrate by way of illustration and example certain embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects of the present disclosure will become more apparent through the description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system consistent with embodiments of the present disclosure.

[0012] Figure 2A , Figure 2B and Figure 2Cis a schematic diagram illustrating an exemplary electron beam tool consistent with embodiments of the present disclosure, which tool can be used as Figure 1 A portion of an exemplary electron beam inspection system.

[0013] Figure 3 is a schematic diagram of a logic transistor array used to test electrical connections.

[0014] Figure 4 is a graph showing the relationship between the gate voltage of a logic transistor and the signal electrons detected from the drain electrode.

[0015] Figure 5 is a schematic diagram of a DRAM structure array used to test electrical connections.

[0016] Figure 6 is a schematic diagram of an array of devices under test (DUT) for testing electrical connections with varying structures across the array.

[0017] Figure 7 is a schematic diagram of an arrangement of logic transistors for testing electrical connections.

[0018] Figure 8 It is shown Figure 7 Schematic diagram of how the logic transistors are electrically connected to the surface of the substrate.

[0019] Fig. 9 is a schematic diagram of an alternative arrangement of devices such as logic transistors.

[0020] Fig.10 is a schematic diagram of different types of DUT arrays.

[0021] Fig.11 is a schematic diagram of an alternative arrangement of logic transistors for testing electrical connections.

[0022] Fig.12 is a schematic diagram showing a general implementation of device measurements using a charged particle beam. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein the same numbers in different drawings represent the same or similar elements, unless otherwise specified. The embodiments set forth in the following description of the exemplary embodiments do not represent all embodiments. Rather, they are merely examples of apparatus and methods consistent with aspects related to the disclosed embodiments recited in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the present disclosure is not limited thereto. Other types of charged particle beams may be similarly applied.

[0024] Electronic devices are made up of circuits formed on a silicon wafer called a substrate. Many circuits can be formed together on the same silicon wafer and are called an integrated circuit or IC. The size of these circuits has been reduced significantly so that more circuits can be fitted on a substrate. For example, an IC chip in a smartphone can be as small as a thumbnail but can include over 2 billion transistors, each of which is less than 1 / 1000 the size of a human hair.

[0025] The characterization of transistors during manufacturing can be accomplished by electrical testing performed by physical probes and metal pads. These test structures require a large area. In practice, only a small number of transistors of a given type can be tested per substrate. Embodiments of the present disclosure allow characterization of transistors based on, for example, scanning a large number of transistors with a SEM and detecting secondary electron and backscattered electron signals. The detected signal indicates the degree of conduction of each transistor. This allows testing of a greater number of transistors (or other devices with switchable currents).

[0026] For the sake of clarity, the relative size of the components in the figure can be enlarged. In the following description of the accompanying drawings, the same or similar reference numerals refer to the same or similar components or entities, and only the differences about the various embodiments are described. As used herein, unless otherwise explicitly stated, the term "or (or)" covers all possible combinations unless it is not feasible. For example, if it is specified that a component can include A or B, then, unless otherwise specifically stated or not feasible, the component can include A, or B, or A and B. As a second example, if it is specified that a component can include A, B or C, then, unless otherwise specifically stated or not feasible, the component can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0027] Reference Figure 1 , Figure 1 An exemplary EBI system 10 consistent with an embodiment of the present disclosure is illustrated, which may include a detector. The EBI system 10 may be used for imaging. Figure 1 As shown, the EBI system 10 includes a main chamber 11, a load / lock chamber 20, an electron beam tool 100, and an instrument front end module (EFEM) 30. The electron beam tool 100 is located in the main chamber 11. The EFEM 30 includes a first load port 30a and a second load port 30b. The EFEM 30 may include (multiple) additional load ports. The first load port 30a and the second load port 30b receive a front opening wafer transport box (FOUP), which includes a wafer to be inspected (e.g., a semiconductor wafer or a wafer made of (multiple) other materials) or a sample (wafers and samples may be collectively referred to as "samples" in this article).

[0028] One or more robotic arms (not shown) in the EFEM 30 can transport the wafer to the load / lock chamber 20. The load / lock chamber 20 is connected to a load / lock vacuum pump system (not shown) that removes gas molecules in the load / lock chamber 20 to reach a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transport the wafer from the load / lock chamber 20 to the main chamber 11. The main chamber 11 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules in the main chamber 11 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is inspected by the electron beam tool 100. The electron beam tool 100 can be a single beam system or a multi-beam system. The controller 109 is electrically connected to the electron beam tool 100 and can also be electrically connected to other components. The controller 109 can be a computer configured to implement various controls of the EBI system 10. Although the controller 109 is Figure 1 1 is shown as being outside the structure including the main chamber 11, the load / lock chamber 20 and the EFEM 30, but it should be understood that the controller 109 can be part of the structure.

[0029] Figure 2A A charged particle beam apparatus is illustrated, wherein the inspection system may include a multi-beam inspection tool that uses multiple primary electron beam waves to simultaneously scan multiple locations on the sample.

[0030] like Figure 2A As shown, the electron beam tool 100A (also referred to herein as the electron beam apparatus 100A or electron optical device) may include an electron source 202, a gun aperture 204, a focusing lens 206, a primary electron beam 210 emitted from the electron source 202, a source conversion unit 212, a plurality of beams 214, 216 and 218 of the primary electron beam 210, a primary projection optical system 220, a wafer stage ( Figure 2A ), a plurality of secondary electron beams 236, 238, and 240, a secondary optical system 242, and an electron detection device 244. The electron source 202 may generate primary particles, such as electrons of the primary electron beam 210. A controller, an image processing system, etc. may be coupled to the electron detection device 244. The primary projection optical system 220 may include a beam splitter 222, a deflection scanning unit 226, and an objective lens 228. The electron detection device 244 may include detection sub-areas 246, 248, and 250.

[0031] The electron source 202, the gun aperture 204, the focusing lens 206, the source conversion unit 212, the beam splitter 222, the deflection scanning unit 226 and the objective lens 228 can be aligned with the primary optical axis 260 of the electron beam device 100A. The secondary optical system 242 and the electron detection device 244 can be aligned with the secondary optical axis 252 of the electron beam device 100A.

[0032] The electron source 202 may include a cathode, an extractor, or an anode, where primary electrons may be emitted from the cathode and extracted or accelerated to form a primary electron beam 210 having a cross (virtual or real) 208. The primary electron beam 210 may be visualized as being emitted from the cross 208. The gun aperture 204 may block peripheral electrons of the primary electron beam 210 to reduce the size of the probe spots 270, 272, and 274.

[0033] The source conversion unit 212 may include an imaging element array (not shown). Figure 2A ) and a beam limiting aperture array (not shown in Figure 2A ). Examples of source conversion unit 212 can be found in U.S. Patent No. 9,691,586; U.S. Publication No. 2017 / 0025243; and International Application No. PCT / EP2017 / 084429, all of which are incorporated herein by reference in their entirety. The imaging element array may include a microdeflector or microlens array. The image forming element array may form multiple parallel images (virtual or real) of intersection 208 with multiple beam waves 214, 216, and 218 of the primary electron beam 210. The beam limiting aperture array may limit the multiple beam waves 214, 216, and 218.

[0034] The converging lens 206 can focus the primary electron beam 210. The current of the beams 214, 216 and 218 downstream of the source conversion unit 212 can be changed by adjusting the focusing power of the converging lens 206 or by changing the radial size of the corresponding beam limiting apertures in the beam limiting aperture array. The converging lens 206 can be a movable converging lens, which can be configured so that the position of its first principal plane is movable. The movable converging lens can be configured to be magnetic, which can cause the off-axis beams 216 and 218 to fall on the beam limiting aperture at a rotation angle. The rotation angle changes with the focusing power of the movable converging lens and the position of the first principal plane. In some embodiments, the movable converging lens can be a movable anti-rotation converging lens, which involves an anti-rotation lens having a movable first principal plane. The movable converging lens is also described in U.S. Publication No. 2017 / 0025241, the entire contents of which are incorporated herein by reference.

[0035] The objective lens 228 may focus the beams 214 , 216 , and 218 onto a wafer 230 (ie, a sample) for inspection, and may form a plurality of probe points 270 , 272 , and 274 on the surface of the wafer 230 .

[0036] The beam splitter 222 can be a Venn filter type beam splitter that generates an electrostatic dipole field and a magnetic dipole field. In some embodiments, if these two fields are applied, the force exerted by the electrostatic dipole field on the electrons of the beam waves 214, 216 and 218 can be equal in magnitude and opposite in direction to the force exerted by the magnetic dipole field on the electrons. The beam waves 214, 216 and 218 can therefore pass directly through the beam splitter 222 at a zero deflection angle. However, the total dispersion of the beam waves 214, 216 and 218 generated by the beam splitter 222 can also be non-zero. The beam splitter 222 can separate the secondary electron beams 236, 238 and 240 from the beam waves 214, 216 and 218, and guide the secondary electron beams 236, 238 and 240 to the secondary optical system 242.

[0037] The deflection scanning unit 226 can deflect the beams 214, 216, and 218 to scan the probe points 270, 272, and 274 over the surface area of ​​the wafer 230. In response to the incidence of the beams 214, 216, and 218 at the probe points 270, 272, and 274, secondary electron beams 236, 238, and 240 can be emitted from the wafer 230. The secondary electron beams 236, 238, and 240 can include electrons whose energy distribution includes secondary electrons and backscattered electrons. The secondary optical system 242 can focus the secondary electron beams 236, 238, and 240 onto the detection sub-regions 246, 248, and 250 of the electron detection device 244. The detection sub-regions 246, 248, and 250 can be configured to detect the corresponding secondary electron beams 236, 238, and 240, and generate corresponding signals for reconstructing an image of the surface area of ​​the wafer 230.

[0038] Although Figure 2A An example of a multi-beam tool using multiple beams, namely an electron beam tool 100, is shown, but the embodiments of the present disclosure are not limited thereto. For example, the electron beam tool 100 may also be a single beam tool that uses only one primary electron beam to scan one location on the wafer at a time.

[0039] like Figure 2BAs shown, the electron beam tool 100B (also referred to herein as the electron beam apparatus 100B) can be a single-beam inspection tool for the EBI system 10. The electron beam apparatus 100B includes electron optics configured to project electrons toward a sample location (i.e., the location where the wafer is located), and a wafer holder 136 supported by a motorized stage 134 to hold the wafer 150 (i.e., the sample) to be inspected. The electron beam tool 100B includes an electron emitter, which may include a cathode 103, an anode 121, and a gun aperture 122. The electron beam tool 100B further includes a beam limiting aperture 125, a condenser lens 126, a column aperture 135, an objective assembly 132, and a detector 144. In some embodiments, the objective assembly 132 can be a modified SORIL lens, which includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an excitation coil 132d. During imaging, the electron beam 161 emitted from the tip of the cathode 103 can be accelerated by the voltage of the anode 121, pass through the gun aperture 122, the beam limiting aperture 125, the condenser lens 126, and be focused into a probe point 170 by the modified SORIL lens, and impinge on the surface of the wafer 150. The probe point 170 can be scanned across the surface of the wafer 150 by a deflector (such as the deflector 132c or other deflectors in the SORIL lens). The detector 144 can collect secondary or scattered primary particles emitted from the wafer surface, such as secondary electrons or scattered primary electrons, to determine the intensity of the beam, so that an image of the region of interest on the wafer 150 can be reconstructed.

[0040] An image processing system 199 may also be provided, which includes an image acquisition device 120, a storage device 130, and a controller 109. The image acquisition device 120 may include one or more processors. For example, the image acquisition device 120 may include a computer, a server, a mainframe, a terminal, a personal computer, any kind of mobile computing device, or the like, or a combination thereof. The image acquisition device 120 may be connected to the detector 144 of the electron beam tool 100B through a medium such as an electrical conductor, an optical cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, radio, or a combination thereof. The image acquisition device 120 may receive a signal from the detector 144 and may construct an image. The image acquisition device 120 may thus acquire an image of the wafer 150. The image acquisition device 120 may also perform various post-processing functions, such as generating a contour, superimposing an indicator on the acquired image, and the like. The image acquisition device 120 may be configured to perform adjustments to the brightness and contrast of the acquired image, and the like. The storage device 130 may be a storage medium, such as a hard disk, a random access memory (RAM), a cloud storage device, other types of computer-readable memory, and the like. The storage element 130 may be coupled to the image acquirer 120 and may be used to save the scanned raw image data as raw images and post-processed images. The image acquirer 120 and the storage element 130 may be connected to the controller 109. In some embodiments, the image acquirer 120, the storage element 130 and the controller 109 may be integrated together as an electronic control unit.

[0041] In some embodiments, the image acquirer 120 may acquire one or more images of the sample based on the imaging signal received from the detector 144. The imaging signal may correspond to a scanning operation for performing charged particle imaging. The acquired image may be a single image including a plurality of imaging regions, which may include various features of the wafer 150. The single image may be stored in the storage element 130. Imaging may be performed on an imaging frame basis.

[0042] The condenser and illumination optics of an electron beam tool may include or be supplemented by an electromagnetic quadrupole electron lens. Figure 2B As shown, the electron beam tool 100B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used to control the electron beam. For example, the first quadrupole lens 148 may be controlled to adjust the beam current, and the second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0043] Figure 2B A charged particle beam arrangement is shown in which the inspection system may use a single primary beam that may be configured to generate secondary electrons by interacting with the wafer 150. The detector 144 may be positioned along the optical axis 105, such as Figure 2B The primary electron beam can be configured to travel along the optical axis 105. Thus, the detector 144 can include a hole at its center so that the primary electron beam can pass through to the wafer 150. However, some embodiments may use a detector that is placed off-axis relative to the optical axis along which the primary electron beam travels. For example, as in Figure 2A In the embodiment shown, a beam splitter 222 may be provided to direct the secondary electron beam to an off-axis placed detector. The beam splitter 222 may be configured to steer the secondary electron beam to an angle α.

[0044] Now refer to Figure 2C Another example of a charged particle beam device is discussed. An electron beam tool 100C (also referred to herein as an electron beam device 100C or an electron optical device) may be an example of an electron beam tool 100 and may be similar to Figure 2A An electron beam tool 100A is shown.

[0045] like Figure 2C As shown, beam splitter 222 can be a Venn filter type beam splitter that generates an electrostatic dipole field and a magnetic dipole field. In some embodiments, if both fields are applied, the force exerted on the electrons of beams 214, 216, and 218 by the electrostatic dipole field can be equal in magnitude and opposite in direction to the force exerted on the electrons by the magnetic dipole field. Beams 214, 216, and 218 can therefore pass directly through beam splitter 222 at a zero deflection angle. However, the total dispersion of beams 214, 216, and 218 generated by beam splitter 222 can also be non-zero. For the dispersion plane 224 of beam splitter 222, Figure 2C A beam 214 having a nominal energy V0 and an energy spread ΔV is shown dispersed into a beam portion 262 corresponding to energy V0, a ​​beam portion 264 corresponding to energy V0+ΔV / 2, and a beam portion 266 corresponding to energy V0-ΔV / 2. The resultant force exerted by the beam splitter 222 on the electrons of the secondary electron beams 236, 238, and 240 may be non-zero. The beam splitter 222 may separate the secondary electron beams 236, 238, and 240 from the beams 214, 216, and 218 and direct the secondary electron beams 236, 238, and 240 to the secondary optical system 242.

[0046] Semiconductor electron detectors (sometimes referred to as "PIN detectors") can be used in the apparatus 100 in the EBI system 10. The EBI system 10 can be a high-speed wafer imaging SEM including an image processor. The electron beam generated by the EBI system 10 can irradiate the surface of the sample or can penetrate the sample. The EBI system 10 can be used to image the structure on the surface or below the surface of the sample, such as for analyzing layer alignment. In some embodiments, the EBI system 10 can detect and report process defects related to the manufacture of semiconductor wafers by, for example, comparing the SEM image with the device layout pattern or the SEM image of the same pattern at other locations on the wafer being inspected. The PIN detector can include a silicon PIN diode that can operate under a negative bias. The PIN detector can be configured so that the incoming electrons generate relatively large and different detection signals. In some embodiments, the PIN detector can be configured so that the incoming electrons can generate multiple electron-hole pairs, while the photons can only generate one electron-hole pair. Compared with the photodiode for photon detection, the PIN detector for electron counting can have many differences, as described below.

[0047] In an embodiment, a detector (e.g. Figure 2A or Figure 2C The electronic detection device 244 or Figure 2B The detector 144 shown includes a plurality of detector elements (e.g., detection sub-regions 246, 248, and 250). The detector elements may be connected to one or more circuit layers. The circuit layer of the detector may include circuit devices having amplification and / or digitization functions, for example, it may include an amplifier circuit. The circuit layer may include one or more transimpedance amplifiers (TIAs) and one or more ADCs. The detector elements and associated feedback resistors may be connected to the TIAs and ADCs. One or more digital signal lines may be connected from the ADC to transmit digital signals (e.g., connected to Figure 2B 120 as shown).

[0048] In some embodiments, the detector can communicate with the controller controlling the charged particle beam system. The controller can instruct the components of the charged particle beam system to perform various functions, such as controlling the charged particle source to generate the charged particle beam, and controlling the deflector to scan the charged particle beam. The controller can also perform various other functions, such as adjusting the sampling rate of the detector, resetting the sensing element, or performing image processing. In one embodiment, the controller is configured to control the setting of the ADC. The controller can include a storage component, which is a storage medium, such as a hard disk, a random access memory (RAM), other types of computer readable memory, etc. The storage component can be used to save the scanned raw image data as a raw image and a post-processing image. A non-transient computer readable medium can be provided, which stores instructions for the processor of the controller 109 to perform charged particle beam detection, sampling period determination, image processing, or other functions and methods that meet the present disclosure. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage medium, CD-ROMs, any other optical data storage medium, any physical medium having a pattern of holes, ROMs, PROMs and EPROMs, FLASH-EPROMs or any other flash memory, NVRAM, cache memory, registers, any other memory chip or cartridge memory and networked versions thereof.

[0049] The block diagram in the figure can illustrate the architecture, functionality and operation of the possible implementation of the system, method and computer hardware / software product according to various exemplary embodiments of the present disclosure. In this regard, each block in the schematic diagram can represent a specific arithmetic or logic operation process that can be implemented using hardware such as an electronic circuit. The block can also represent a module, a code segment or a code portion, which includes one or more executable instructions for implementing a specified logical function. It should be understood that in some alternative embodiments, the function indicated in the block may not occur in the order shown in the figure. For example, two blocks shown in succession can be performed or implemented substantially simultaneously, or two blocks can sometimes be performed in reverse order, depending on the functionality involved. Some blocks can also be omitted. It should also be understood that each block of the block diagram and the combination of blocks can be implemented by a dedicated hardware-based system that performs a specified function or action, or by a combination of dedicated hardware and computer instructions.

[0050] A method for testing electrical connections is disclosed. In an embodiment, the method is used to characterize a device (e.g., a transistor) on a substrate. Characterization of the device may include determining one or more properties of the device. For example, when the device is a transistor, the transistor is characterized by one or more of its threshold voltage (on / off gate voltage), its leakage current at zero gate voltage, and its subthreshold IV slope (which determines the steepness of the on / off transition).

[0051] Embodiments of the method are described below primarily in the context of testing logic transistors (i.e., transistors used in logic circuits). Such logic transistors may be used for binary purposes, or may be used for analog applications. However, the method may be applied to testing other devices, particularly devices having an electrical connection between two electrodes that may be controlled by a signal applied to a control element (e.g., a gate electrode of a transistor). For example, the device may be a DRAM structure or a photodiode.

[0052] Figure 3 The device array 50 is schematically shown. Figure 3 In the example shown, the device is a transistor 51. Figure 3 As shown, in an embodiment, array 50 is a two-dimensional array. In an embodiment, transistors 51 are arranged in a regular pattern to form array 50. In an embodiment, transistors 51 are arranged in the array 50 in columns and rows of a grid. It is not necessary for transistors 51 to be arranged in a regular pattern. Transistors 51 can be arranged irregularly. A regular pattern can more easily provide a higher density of transistors 51 in array 50.

[0053] In an embodiment, array 50 is a test structure used when characterizing transistor 51. The test structure may not be used for a functionalized portion of a substrate (e.g., a functionalized portion of an IC). In an embodiment, the test structure is located in a scribe line of the substrate. When a chip is cut from the substrate, the test structure may be cut away.

[0054] In an embodiment, the transistors are formed in a particularly dense pattern. For example, in an embodiment, the transistors 51 are arranged at a pitch of at most 500nm, optionally at most 200nm, optionally at most 100nm, and optionally at most 50nm. In an embodiment, the pitch applies to both the rows and columns of the grid of the array 50.

[0055] In an embodiment, all transistors 51 within the array 50 are of the same type. This means that all transistors 51 are manufactured to have the same expected characteristics. For example, the transistors 51 can be designed to have the same threshold voltage as each other. Of course, there may be some variation in the actual properties (characteristics) of the transistors 51. It is desirable to test the array 50 of transistors 51 in order to determine the characteristics of the actual transistors 51. For example, it may be determined what the average value (e.g., mean) of the voltage thresholds of the transistors 51 across the array 50 and / or the distribution (e.g., standard deviation) of the threshold voltages is.

[0056] like Figure 3As shown, in an embodiment, each device includes two electrodes, which can be electrically connected. In the example of transistor 51, the two electrodes can be a source electrode 52 and a drain electrode 53. When the transistor is turned on, a considerable or significant current can flow between the source electrode 52 and the drain electrode 53. When the transistor 51 is turned off, a sufficiently low current (or no current) can flow between the source electrode 52 and the drain electrode 53.

[0057] In an embodiment, the method comprises applying a reference potential to a first electrode of the two electrodes 52, 53 of each device. Figure 3 In the arrangement shown, the reference potential is applied to the source electrode 52 of each transistor 51. In an alternative embodiment, the reference potential may be applied to the drain electrode 53 of each transistor 51.

[0058] like Figure 3 As shown, in an embodiment, the first electrode (e.g., source electrode 52) of transistor 51 is connected to a common reference potential so that a reference potential is applied. For example, all source electrodes 52 may be electrically connected to a common reference contact 57. Common reference contact 57 may be a terminal such as a pad. The voltage of common reference contact 57 may be controlled to control the reference potential applied to source electrode 52 of transistor 51. By connecting transistor 51 to a common reference potential, a reference potential may be more easily applied to each transistor 51. By providing a single common reference contact 57, the space occupied by the entire test structure may be reduced.

[0059] In an embodiment, the reference potential is ground. For example, ground may be a reference ground potential of an electron optical device such as the electron beam tool 100. Alternatively, a different reference potential may be used.

[0060] In an embodiment, the method includes directing (e.g., projecting) a charged particle beam (e.g., an electron beam 55) onto a second electrode of two electrodes of each device (e.g., a transistor 51). The second electrode is an electrode to which no reference potential is applied. In the case of transistor 51, the second electrode is one of the source electrode 52 and the drain electrode 53. Figure 3 In the example shown, the second electrode is the drain electrode 53. Alternatively, the reference potential may be applied to the drain electrode 53 and the charged particle beam may be directed onto the source electrode 52.

[0061] In an embodiment, the electron beam is projected by an electron optical device of an electron optical apparatus, such as electron beam tool 100. In an embodiment, the electron beam is projected onto all drain electrodes 52 simultaneously. Alternatively, the electron beam may be scanned across array 50 so as to project the electron beam onto drain electrodes 53 sequentially.

[0062] In an embodiment, the controller 109 is configured to control the landing energy of the electron beam. The landing energy of the electron beam is the energy of the electrons at the sample position. In an embodiment, the controller 109 is configured to control the landing energy of the electron beam according to the type of transistors 51 within the array 50.

[0063] For example, when the transistor 51 is a PMOS transistor, the landing energy can be controlled to be at least 1 keV, optionally at least 2 keV, optionally at least 5 keV, optionally at least 10 keV. Such landing energy can cause negative charging of the PMOS transistor, so that the pn junction under the irradiated drain electrode 53 is reverse biased. Reverse bias means that the electrons from the electron beam do not flow from the exposed drain electrode 53 to the silicon directly below. Instead, if the channel is opened, the charge can only flow through the channel, or if the channel is closed, the charge accumulates at the drain electrode 53.

[0064] When the transistor 51 is an NMOS transistor, the controller 109 may control the landing energy to be at most 1 keV, optionally at most 500 eV and / or at least 100 eV, optionally at least 200 eV, optionally at least 500 eV. Such landing energy may cause positive charging of the NMOS transistor, so that the pn junction under the irradiated drain electrode 53 is reverse biased.

[0065] In an embodiment, the method includes: changing a signal applied to a control element of each device (e.g., transistor 51). In the example of transistor 51 as a device, the control element may be a gate electrode 54 of transistor 51. The signal may be an electric potential. When a voltage higher than a threshold voltage is applied to gate electrode 54, a considerable or significant current may flow between source electrode 52 and drain electrode 53. When a voltage lower than the threshold voltage is applied to gate electrode 54, no current may flow between source electrode 52 and drain electrode 53.

[0066] like Figure 3 As shown, in the embodiment shown, control elements of a plurality of devices are connected to a common control electrode 59 so as to apply a varying electrical potential. Figure 3 The gate electrodes 54 of all transistors 51 are shown electrically connected to a common control electrode 59. By providing a common control electrode 59, a known potential can be applied to the gate electrodes 54 across the transistors 51 of the array 50. It is easier to apply and vary the potential to the gate electrodes 54. By providing a common control electrode 59 for multiple transistors 51, the total amount of space occupied by the test structure can be reduced. In particular, there may be no need to provide separate pads to apply a gate voltage to each transistor individually.

[0067] In an embodiment, the signal applied to the control element of each device (e.g., transistor 51) is gradually increased or decreased. For example, when the signal is an electric potential, the electric potential applied to the control element can be gradually increased. In an embodiment, the signal is changed by scanning the signal within a range. In an embodiment, the lower limit of the range is lower than the threshold signal of the device, so that each device is turned off, and the high effective resistance of the transistor will produce a dark voltage contrast signal. A transistor with a threshold voltage lower than the applied gate voltage will give a voltage contrast signal with a first intensity, and a transistor with a threshold voltage higher than the applied gate voltage will give a voltage contrast signal with a second intensity, and the intensity of the second voltage contrast signal is weaker than the first voltage contrast signal. It should be noted that when the applied gate voltage is lower than the threshold voltage, the transistor current decreases exponentially, so when the applied gate voltage is lower than the threshold voltage, the voltage contrast signal depending on the current through the transistor is also significantly reduced. In an embodiment, the upper limit of the range is higher than the signal threshold of the device, so that the device is turned on and the current flows between the two electrodes. As the signal gradually increases, the device at the lowest threshold signal is turned on. This can be detected as described in more detail below. As the signal increases, more and more devices are turned on. At the upper end of the range, all devices are turned on. Of course, there may be one or more defective devices that never turn on.

[0068] In an embodiment, the method includes: for each signal applied, monitoring the signal charged particles (e.g., signal electrons) from the second electrode of each device. For example, when a signal (e.g., a specific potential) is applied to the control element (e.g., gate electrode 54) of each device (e.g., transistor 51), the detector 144 of the electron beam tool 100 detects signal electrons from each transistor 51, such as backscattered electrons and secondary electrons. The detected signal electron data can be recorded for a given signal applied to the control element of the device. Then, the signal applied to the control element of the device can be changed (e.g., incrementally increased), and the signal electrons generated by the electron beam projected onto the drain electrode 53 can be monitored for the newly applied signal. This monitoring step can be performed sequentially for each changed signal. As a result, for each device in the array 50, signal electrons are detected for a given potential applied to the gate electrode 54.

[0069] Figure 4 is a graph showing the relationship between the potential applied to the gate electrode 54 and the current detected as the signal electrons from the transistor 51. Figure 4 In FIG. 5 , the X-axis represents the potential applied to the gate electrode 54 of a given transistor 51. The Y-axis represents the current of the signal electrons detected from the transistor 51. This may also be referred to as a voltage versus signal. Figure 4A plurality of curves 41 of signal electrons versus gate voltage are shown. Each curve 41 may correspond to a respective transistor 51 of the array 50.

[0070] like Figure 4 As shown, the curves 41 may generally have similar forms to each other. However, there is a spread of the curves. It is desirable to measure the extent of the spread of the curves. This may be an indication of manufacturing tolerances of parameters of a given type of transistor 51.

[0071] In an embodiment, the electron beam 55 is projected onto vias or contact metals associated with the transistors 51. In an embodiment, the electron beam 55 induces a current that passes through the exposed vias or contact metals and into the drain electrode 53 of each transistor 51. The current of the signal electrons from each via or contact metal depends on the threshold voltage of the associated transistor 51 and the potential applied to the gate electrode 54. The threshold voltage of the transistors 51 may vary across the array 50 even if nominally all transistors 51 are of the same type (e.g., have the same expected threshold voltage). Figure 4 As shown, the output may be a series of curves 51 showing the voltage versus signal for each transistor 51 plotted against the gate voltage. The curves may be sufficient to measure the distribution of threshold voltages. Additional information may also be obtained from the data. Figure 4 A threshold range 42 of values ​​is shown within which the threshold voltages of different transistors 51 of array 50 may vary.

[0072] The current of the signal electrons detected from the through hole or contact metal of the transistor 51 depends on the degree of conduction of the transistor 51, that is, the degree to which current can flow between the source electrode 52 and the drain electrode 53. When a sufficiently low current (or no current) flows between the source electrode 52 and the drain electrode 53, then charge can accumulate at the drain electrode 53.

[0073] For certain types of transistors 51, positive charge can accumulate. The accumulated positive charge can reduce the likelihood of secondary electrons reaching the detector. This reduces the number of secondary electrons reaching the detector 144. For example, this can cause dark spots to be generated in any SEM image. In contrast, when current can flow freely between the source electrode 52 and the drain electrode 53, secondary electrons can more freely reach the detector 144 of the electron beam tool 100. For example, this can cause a higher voltage contrast signal and brighter spots to be generated in any SEM image.

[0074] Embodiments of the present disclosure are expected to reduce the area required for the test structure for testing a given number of devices. In particular, known test structures require large areas because metal pads can occupy an area of ​​several microns. Each transistor to be tested requires such an area. For example, embodiments of the present invention are expected to allow for testing orders of magnitude more transistors 51 on a given area.

[0075] Embodiments of the present disclosure are expected to increase the number of statistical data that can be measured for a given type of device. Using known techniques, only tens to hundreds of transistors of a given type can be measured using electrical testing of the entire substrate. This provides a limited number of statistical data. It is expected that embodiments of the present disclosure greatly increase the number of transistors of a given type that can be measured, thereby improving the statistical data (e.g., characteristics) that can be measured. Such statistical data can help manufacturers determine the possible range of structural design features of equipment so that the equipment has desired characteristics / attributes. For example, if it is known that a transistor needs to have a given average threshold voltage and a given standard deviation of the threshold voltage, it can be determined what size of electrode is needed to meet these requirements.

[0076] Embodiments of the present disclosure are expected to provide improved fault analysis. For known test structures, the measured information does not allow simple fault analysis. One reason is that the measured information may not be specific local information for each transistor. This is because for a given substrate, only a small amount of transistors can actually be tested. Embodiments of the present disclosure are expected to allow testing of a greater number of transistors (or other devices) on the entire substrate. This allows the measured information to be more localized for each transistor, thereby making fault analysis easier.

[0077] In an embodiment, the signal applied to the control element of each device is applied by a test probe. For example, a nanoprobe can be used to apply and vary a voltage applied to a common control electrode 59. The voltage applied to the common control electrode 59 is applied to the gate electrodes 54 of all transistors 51 of the array 50. In an embodiment, the test probe is used in parallel with the voltage contrast measurement. In an embodiment, the electron beam tool 100 is configured to support the nanoprobe in parallel with the voltage contrast measurement.

[0078] While scanning the electron beam 55 across the array 50 and detecting the signal electrons from the transistor 51, a signal can be applied to the control element of the device. However, it is not necessary to apply a potential to the gate electrode 54 while scanning. In an alternative embodiment, a potential for the gate electrode 54 can be initially applied. The application of the potential can then be suppressed (e.g., stopped) during the scan. During the scan, the potential that has been applied to the gate electrode 54 can be stable. Assuming that the potential is stable during the scan, it is not necessary to actively apply a voltage to the gate electrode 54 during the scan.

[0079] It is not necessary to apply the signal to the control element of the device through the test probe. Alternative ways of applying a signal such as a gate voltage are described below.

[0080] In an embodiment, a signal applied to a control element of each device is applied by directing (e.g., projecting) another charged particle beam to a common control contact connected to a plurality of switches. For example, a second electron beam can be used to supply a gate voltage. In an embodiment, the electron beam tool 100 is configured to project a plurality of electron beams. One of the plurality of electron beams can be used to supply a gate voltage (e.g., by projecting the electron beam onto a common control contact 59). One or more other electron beams 55 can be projected onto a through hole of a drain electrode 53 of a transistor 51 connected to the array. This can allow a gate voltage to be applied while performing a scan of the array 50.

[0081] In an embodiment, common control contact 59 is at least 500 nm, optionally at least 1 μm, optionally at least 2 μm, optionally at least 5 μm, and optionally at least 10 μm away from transistor 51. A greater distance between common control contact 59 and transistor 51 can make it easier to distinguish signal electrons from the electron beam on common control contact 59 from signal electrons from electron beam 55 projected onto transistor 51.

[0082] In an alternative embodiment, before the charged particle beam is projected onto the second electrode of each device, the signal applied to the control element of each device is applied by projecting the charged particle beam onto a common control contact 59 connected to a plurality of control elements. The common control contact 59 has a capacitance so that the signal applied to the control element of each device is maintained while monitoring the signal charged particles from the second electrode of each device. The electron beam tool 100 may not need to project multiple electron beams. In an embodiment, the electron beam tool 100 is configured to project a single beam. The common control contact 59 may have a capacitance large enough to be charged by the electron beam and stably maintain a desired voltage during the voltage contrast scan of the transistor 51.

[0083] In alternative embodiments, light can be used to supply an effective gate voltage to the transistors 51. For example, in an embodiment, the electron beam tool 100 can include a light source configured to project photons onto the array 50. For example, the photons can strike all of the transistors 51 and generate electron / hole pairs in the transistor channels. The light can induce a conductive path between the source electrode 52 and the drain electrode 53 of each transistor 51. In an embodiment, the light source is configured to apply light while the device is scanned by the electron beam 55.

[0084] Fig.12 is a schematic diagram showing a general implementation of transistor measurement using an electron beam 55. Fig.12 As shown, transistor 51 is connected to control contact 59 and reference contact 57. Drain electrode 53 (or in an alternative embodiment, source electrode 52) is exposed and scanned with electron beam 55. Fig.12 The arrangement shown can be repeated, arranged and connected in various ways, for example Figure 3 shown. Figure 3 A two-dimensional array is shown in which transistors 51 are in array 50 and share a common control contact 59 and a common reference contact 57. Another possibility is to position transistors 51 more irregularly around the electronic structure, for example as reference Figure 7 In a further alternative, the plurality of transistors are electrically coupled to different control contacts, rather than a common control contact.

[0085] As mentioned above, Figure 3 As shown, in an embodiment, the device is a transistor 51. However, these devices need not be transistors. In an alternative embodiment, the device is a DRAM structure 61.

[0086] Figure 5 61 is a schematic diagram of an array 50 of DRAM structures. Figure 5 As shown, in an embodiment, DRAM structures 61 are arranged in a two-dimensional grid. DRAM structures 61 can be arranged in a regular pattern. DRAM structures 61 can be arranged in multiple columns and rows of a grid. Array 50 of DRAM structures 61 can be dual-purpose. Array 50 can be used for testing equipment and can also be used as a functionalized part of a circuit (e.g., as a memory).

[0087] In an embodiment, each DRAM structure 61 includes a source electrode 52 , a drain electrode 53 , and a gate electrode 54 . Figure 5 Some of the features of the arrangement shown may be combined with Figure 3 For example, a common control contact 59 can be connected to all gate electrodes 54 of a DRAM structure 61. A common reference contact 57 can be electrically connected to source electrodes 52 of all DRAM structures 61.

[0088] The difference between the array 50 of DRAM structures 61 and the array 50 of logic transistors 51 is that the drain electrodes 53 in the array 50 of DRAM structures 61 are connected to capacitors 62. In contrast, logic transistors do not have such capacitors. Each DRAM structure 61 includes a corresponding capacitor 62 connected to its drain electrode 53. The capacitor 62 can be electrically located between the drain electrode 53 and a terminal 63, which is connected to a via exposed at the surface of the substrate. In such an arrangement, readout is accomplished with an electron beam 55, which induces a current into the capacitor 62 of each DRAM structure 61 through the exposed via.

[0089] When the electron beam 55 is incident on the DRAM structure 61, if the potential applied to the gate electrode 54 causes the transistor to be turned off, the capacitor 62 will charge. In contrast, if the gate voltage causes the transistor to be turned on, the capacitor 62 will not charge. Plotting the voltage of the capacitor 62 versus the signal versus the gate voltage gives a set of graphs similar to Figure 4 When the gate voltage is lower than the threshold voltage of the DRAM structure 61, the capacitor 62 is charged and the voltage comparison signal is low. At a larger gate voltage, the charge will not accumulate in the capacitor 62, which results in a larger voltage comparison signal.

[0090] In an alternative embodiment, the device may be another type of device having an electrical connection between two electrodes that can be controlled by a signal applied to a control element. For example, in an embodiment, the device is a photodiode. The signal applied to the control element may be a photon signal, such as light.

[0091] In an embodiment, the photon signal is varied by varying the light intensity applied to the light-sensitive control element of the photodiode. For example, the light intensity can be swept from a low intensity to a high intensity. Each photodiode can have a threshold intensity at which current begins to flow between the two electrodes of the photodiode.

[0092] Additionally or alternatively, the wavelength of the photon signal may be swept across a range of wavelengths. There may be a threshold wavelength at which the photodiode controls the element to turn on or controls the element to turn off. By scanning a range of wavelengths, the on / off wavelength of each photodiode may be measured. Of course, the photon signal (e.g., a light beam) may include a range of wavelengths. In an embodiment, the wavelength of the photon signal is the dominant wavelength of the photon signal, e.g., the wavelength of maximum intensity.

[0093] In an embodiment, the method includes determining at least one of a threshold signal (e.g., a threshold voltage), a leakage current, and a subthreshold slope for each device. These values ​​can be determined from the monitored signal particles. For example, these values ​​can be determined from Figure 4 is determined by the curve 41 shown.

[0094] The threshold voltage may be determined as the gate voltage at which the voltage comparison signal increases above a threshold level. It is not necessary to determine the threshold voltage of each transistor 51 individually. In alternative embodiments, it may be sufficient to determine the average (e.g., mean) threshold voltage of the array 50 of transistors 51 as a whole. Alternatively, the threshold voltage may not need to be measured at all.

[0095] When the transistor 51 is turned off (eg, when the potential applied to the gate electrode 54 is equal to the reference potential applied to the source electrode 52), the leakage current is the current between the source electrode 52 and the drain electrode 53. The leakage current may also be referred to as dark current.

[0096] In an embodiment, the signal electrons detected by the detector 144 may include backscattered electrons and secondary electrons. The current of the backscattered electrons detected by the detector 144 may be expected to remain substantially constant, regardless of the potential applied to the gate electrode 54. In contrast, the current of the secondary electrons may be expected to vary depending on the gate voltage. The constant current of the backscattered electrons may be known. By measuring the detector current, the current of the secondary electrons may be determined.

[0097] Subthreshold slope and below threshold voltage Figure 4 The shape of the curve 41 shown is relevant. The subthreshold slope is the slope of the curve 41 before the transistor 51 controls the element to turn on.

[0098] Calibration of the measured values ​​may be required in order to determine some properties of the transistor 51. For example, it may be desirable to correlate the signal measured by the electron beam tool 100 with the actual current through the substrate. Calibration may be performed using SEM images of a device having one or more known properties.

[0099] As described below, in addition to calibrating the system, additionally or alternatively, the system may be mathematically modeled. This may allow one or more properties of transistor 51 to be measured.

[0100] The electron beam tool 100 can represent the voltage contrast signal as a grayscale value (GLV). The current I detected by the detector 144 d It is related to GLV by:

[0101]

[0102] where a i is the amplifier gain factor, B is the brightness, and C is the contrast.

[0103] The detector current consists of the secondary electron (SE) current and the backscattered electron (BSE) current:

[0104] Id =I d-SE +I d-BSE =δI p +ηε C I p

[0105] where δ(η) is the SE(BSE) electron yield, and ε C is the collection efficiency of detector 144 for BSE. p is the primary beam electron current. The BSE yield is not affected by the charging that occurs when irradiating the via, so we can assume we know its value. This is not the case for the SE yield. By measuring the detector current and assuming the BSE current component is known, the SE current component can be found.

[0106] The charging that occurs at the via follows the charge conservation law:

[0107] I P +I device =δI p +ηI p

[0108] The two components on the right hand side and the primary beam current can be known or determined. The device current can be calculated. As the electron beam is scanned over the exposed vias of the transistor, charges are created and then neutralized to a certain degree depending on how well the vias are connected to a free charge source. Assuming that all contact charge neutralization will flow out of the transistor channel, the device current is equivalent to the drain-source current of the transistor.

[0109] Adding a model for the secondary electron yield emission of the metal contacts allows the measured SE current to be converted to the drain-source voltage of the transistor. In the case of positive charge, this model can be found in the literature and is as follows:

[0110]

[0111] where δ 0 is the SE yield of the through hole when there is no charging, is its work function, and V s is the voltage developed between the via surface and the drain (ignoring the current flowing through the substrate under the contact). Assume δ 0 It is known that the measured SE current gives the drain-source voltage.

[0112] In an embodiment, the method comprises: varying the current of the charged particle beam applied to the second electrode of each device while maintaining the signal applied to the control element of each device. In an embodiment, the method comprises: monitoring the signal charged particles from the second electrode of each device for the varying current. For example, the primary beam current (i.e., the current of the electron beam 55) can be varied. This makes it possible to plot the source-drain current versus the source-drain voltage at a given gate voltage. In an embodiment, the method comprises: determining, for each device, the relationship between the potential difference between the two electrodes and the current between the two electrodes.

[0113] In an embodiment, the secondary electron yield model may be calibrated. In order to know the secondary electron yield of a via exposed at the surface of the substrate, it may be desirable to measure the current of the secondary electrons without charging. To avoid charging, it may be desirable to ensure that sufficient charge can flow between, for example, the drain electrode 53 and the source electrode 52 of the transistor 51. The charge can then flow to the contact for neutralization, thereby avoiding charging at the exposed via.

[0114] In an embodiment, the method includes: applying a saturation signal to the control element of each device. For example, the potential applied to the gate electrode 54 can be set larger (higher than the expected threshold voltage of the transistor 51). This can cause a maximum current of secondary electrons from the through-holes exposed at the surface of the substrate. Additionally or alternatively, the method can include: projecting light onto each device so that the two electrodes in substantially all devices are electrically connected. For example, a light beam can be irradiated on the array 50 to control the charge accumulated due to effects such as photoconductivity, photoelectric or thermal effects. This may cause saturation of the signal electrons from the exposed through-holes. This can allow the second electron yield of the metal of the exposed through-hole to be known.

[0115] In an embodiment, the method comprises: monitoring the signal charged particles from the second electrode of each device while inhibiting (eg stopping) the charged particle beam from being projected onto the second electrode of each device. The secondary electron current may be measured without charging.

[0116] In an embodiment, a charged particle optical device is used to test an array 50 of devices. The device includes a reference voltage source. The reference voltage source is configured to supply a reference potential to a first electrode of each electrode of each device. For example, the reference voltage source may be electrically connected to a common reference contact 57. The reference voltage source may simply be a reference ground potential of the device (e.g., electron beam tool 100).

[0117] In an embodiment, the apparatus comprises a charged particle optical device configured to project a charged particle beam onto a second electrode of the two electrodes of each device. Figure 2A , Figure 2B or Figure 2C The illustrated electron beam tool 100 may be used to project an electron beam onto the drain electrode 53 of the transistor 51 .

[0118] In an embodiment, the device includes a signal source. The signal source is configured to vary the signal applied to the control element of each device. For example, the signal source may include a voltage source electrically connected to the common control contact 59. The signal source may include a test probe configured to be electrically connected to the common control contact 59 so as to apply a varying signal (e.g., potential).

[0119] Alternatively, the signal source may comprise a controllable light source for emitting light of controlled intensity and / or wavelength.

[0120] In an embodiment, the apparatus includes a detector 144 for monitoring the signal charged particles from the second electrode of each device for each signal applied. For example, the detector may be as described above in Figure 2A , Figure 2B or Figure 2C described in the context of.

[0121] Figure 6 70 is a schematic diagram. Figure 6 As shown, in an embodiment, the marker 70 includes a plurality of DUTs. The DUTs may be arranged in a two-dimensional grid. The grid may include columns and rows. Figure 6 In the figure, not all DUTs are shown. Figure 6 As shown, the tag 70 may include multiple columns and rows of DUTs arranged in a regular pattern. Each DUT may include an array of devices 50. For example, there may be approximately 1000 devices in each array 50 of the tag 70. The tag 70 may be provided in a substrate.

[0122] like Figure 6 As shown, in an embodiment, a common control contact 59 is electrically connected to a control element of each device of array 50. For example, a common control contact 59 may be connected to gate electrodes 54 of all transistors 51 of all arrays 50 of tag 70. Tag 70 may include arrays 50 of transistors 51.

[0123] In an embodiment, at least one structural feature of the device varies in a predetermined manner across arrays or indicia 70. For example, within each array 50 of indicia 70, all transistors 51 may be designed to be of the same type. However, between arrays 50, there may be one or more expected structural differences. For example, in an embodiment, the at least one structural feature that varies in a predetermined manner includes at least one of an overlap shift between layers of the device and a size of a component of the device.

[0124] In an embodiment, the marking 70 includes a column variation 71. For example, the column variation 71 may be a program overlay shift between two layers of a device. In an embodiment, the marking 70 includes a row variation 72. For example, the row variation may be an increased size of a gate electrode 54 of a device.

[0125] For example, by scanning the gate voltage as described above, it is possible to measure how the threshold voltage and / or other parameters of the device depend on programmable variations of the device. This can help designers identify possible values ​​of different sizes and acceptable overlap values ​​that will result in acceptable results.

[0126] For example, in an embodiment, in each DUT (e.g., each array 50), the number of transistors 51 that are turned on and off can be counted for each applied gate voltage. For each DUT, a yield number can be determined, which can be the ratio of transistors that are turned on to the total number of transistors. The relationship between the yield number and overlap or size (e.g., critical dimension) can be studied. Additionally or alternatively, the relationship between one or more parameters (such as threshold voltage) and geometric variations in the design of the device can be studied.

[0127] Figure 7 Schematically showing, for example Figure 3 An alternative arrangement of the devices to the arrangement shown. In an embodiment, the devices are arranged in an array 50. Figure 7 In the example shown, the device is a transistor 51. Figure 7 As shown, transistors 51 may be arranged in lines. However, transistors 51 may be arranged differently and need not be arranged in any regular pattern. Transistors 51 may be arranged irregularly.

[0128] Transistor 51 may be located in a specific context. A specific context refers to the environment of transistor 51. For example, the context of transistor 51 may relate to the location of transistor 51 on a substrate (e.g., how far away from the edge of the substrate), and / or what type of structure is adjacent to transistor 51. Different types of structures may have different corresponding manufacturing processes associated with them. Depending on the manufacturing process of the structure near transistor 51, the manufacturing process may affect the properties of transistor 51. It is contemplated that embodiments of the present invention are capable of evaluating how the context of transistor 51 (or other types of devices) affects its properties.

[0129] like Figure 7 As shown, in an embodiment, the substrate including the transistor 51 includes an electrode contact 76. In an embodiment, the electrode to which the electron beam is directed is connected to the corresponding electrode contact 76. The electrode contact 76 is exposed at the surface of the substrate. The electrode contact 76 can be a pad, such as a metal pad. Figure 7In the arrangement shown, the drain electrode 53 is connected to a respective electrode contact 76. Alternatively, the source electrode 52 may be connected to a respective electrode contact 76 and the drain electrode 53 may be connected to a reference potential.

[0130] like Figure 7 As shown, the electrode contact 76 can be away from the drain electrode 53. Figure 7 As shown, in an embodiment, the electrode contact 76 is arranged in the contact region. The contact region can be far away from the drain electrode 53, the source electrode 52 and / or the gate electrode 54. By making the electrode contact 76 far away from the transistor 51, the transistor 51 is less likely to be adversely affected by the electron beam used to charge the electrode contact 76. The drain electrode 53 can be indirectly charged by the electron beam. The electron beam can be directly incident on the electrode contact 76. The electrode contact 76 is electrically connected to their corresponding drain electrode 53. The electron beam is indirectly guided to the drain electrode 53 via the electrode contact 76.

[0131] By physically positioning electrode contact 76 away from transistor 51, the likelihood of undesired capacitive effects on the transistor due to the application of the electron beam is reduced. For example, the likelihood of undesired charging of gate electrode 54 by the electron beam can be reduced. Embodiments of the present invention contemplate improved accuracy in evaluating transistor 51. During evaluation of transistor 51, any undesired disturbances to transistor 51 caused by the electron beam may undesirably affect the accuracy of the evaluation.

[0132] like Figure 7 As shown, the contact area may include compact electrode contacts 76. For example, the electrode contacts 76 may be arranged in an array (such as a two-dimensional array). The electrode contacts 76 may be arranged in multiple rows and / or multiple columns. The electrode contacts 76 may be arranged in a regular arrangement. Embodiments of the present invention contemplate reducing the total area that the electron beam needs to scan in order to evaluate the transistor 51. By arranging the electrode contacts 76 compactly, the required scanning range may be reduced. This may reduce the time required for evaluation.

[0133] like Figure 7 As shown, the substrate may include one or more electronic structures 73. The electronic structure 73 may be located near the transistor 51, for example adjacent to the transistor 51. The electronic structure 73 may form part of the background of the transistor 51 to be tested. The electronic structure 73 may be an electronic product or part of an electronic product. The electronic structure may include a transistor and / or a memory device (such as a DRAM and / or SRAM). The electronic structure 73 may include a processor for executing a process.

[0134] By placing transistor 51 near electronic structure 73, transistor 51 can better represent the properties of the device of electronic structure 73. By positioning transistor 51 near a particular electronic structure 73, it is possible to evaluate the effect (which may be referred to as the proximity effect) that electronic structure 73 may have on the properties of transistor 51. Embodiments of the present invention contemplate improving the accuracy of evaluation devices for electronic structures, which may be electronic products or a portion (or portions) of electronic products.

[0135] like Figure 7 As shown, in an embodiment, the gate electrode 54 is connected to a common control contact 59. However, it is not necessary to provide a common control contact 59. In an alternative embodiment, the gate electrode 54 can be connected to a corresponding individual control contact. In another alternative, the gate electrodes 54 can be grouped together, and each group includes a plurality of gate electrodes 54. All gate electrodes 54 of a group can be connected to a common group control contact. Multiple group control contacts can be provided for corresponding multiple groups of data electrodes 54.

[0136] like Figure 7 As shown, in the embodiment shown, the common control contact 59 is adjacent to the contact area where the electrode contacts 76 are provided. Figure 7 As shown, in an embodiment, the substrate includes a scanning area 75. The scanning area 75 may correspond to an area of ​​the surface of the substrate that is to be scanned by the electron beam. Figure 7 As shown, the contact area of ​​the electrode contact 76 can be within the scanning area 75. During the scanning of the electron beam across the substrate, the electrode contact 76 is scanned. Figure 7 As shown, scanning area 75 can be much smaller than the overall size of the substrate. Embodiments of the present invention contemplate reducing the scanning area required to access transistor 51. For example, Figure 7 As shown, the electrode contacts 76 may be arranged in a relatively small contact area.

[0137] like Figure 7 As shown, in an embodiment, at least a portion of the common control contact 59 is located within the scanning region 75. The common control contact 59 can be scanned by the electron beam during scanning of the electron beam across the surface of the substrate. In an embodiment, the electron beam is directed onto the common control contact 59 in the same scan line used to scan the electrode contact 76. Figure 7 As shown, in an embodiment, at least a portion of the common reference contact 57 is within the scanning area 75. In an embodiment, the electron beam is directed to the common reference contact 57. For example, in an embodiment, the electron beam can be scanned using a frame scanning mode. Frame scanning includes scanning the electron beam along a plurality of substantially parallel lines. For example, the electron beam can be horizontally scanned along a first line from the upper left corner of the scanning area 75 to Figure 7The upper right corner of the scanning area shown. Subsequent scanning lines can be parallel to and slightly below the scanning line. By scanning these lines in sequence, the electron beam can scan the entire scanning area 75.

[0138] like Figure 7 As shown, in an embodiment, in addition to a plurality (e.g., a row) of electrode contacts 76, each row of the frame scan also includes a scanned portion of a common control contact 59 and / or a portion of a common reference contact 57. Figure 7 As shown, in an embodiment, scan region 75 includes electrode contacts 76, at least a portion of common control contact 59, and at least a portion of common reference contact 57. The ignored electrons in each region may be shown within a single image.

[0139] In an embodiment, within each line of scanning, before scanning the row of electrode contacts, the electron beam is directed onto common control contact 59. In an embodiment, the electron beam is directed onto common reference contact 57 after it has been directed onto multiple (e.g., row) electrode contacts 76.

[0140] like Figure 7 As shown, in an embodiment, the substrate includes a plurality of electrical traces 77 to 79. The electrical traces electrically connect the electrode contacts 76 to the corresponding drain electrodes 53. If there is enough space, the electrical traces 77 to 79 can be arranged adjacent to each other. The electrical traces can be provided at substantially the same level within the substrate.

[0141] Alternatively, the electrical traces 77 to 79 may be provided at different levels within the substrate. The electrical traces 77 to 79 may be arranged to extend through the substrate at different levels within the substrate. Figure 8 As shown in Figure 8 As shown, there may be multiple (eg, three) levels within their substrate to which electrical traces 77 to 79 extend. Each electrical trace 77 to 79 electrically connects the drain electrode 53 to a corresponding electrode contact.

[0142] like Figure 8 As shown, in an embodiment, the first electrical trace 77 is provided at the lowest level among the electrical traces 77 to 79. The second electrical trace 78 is provided at an intermediate level within the substrate. The third electrical trace 79 is provided at the highest level within the substrate. By providing the electrical traces 77 to 79 at different levels, the electrical traces 77 to 79 can occupy less space on the substrate.

[0143] like Figure 7 As shown, in an embodiment, the substrate includes a reset switch 74. For example, the reset switch 74 may include a transistor. In an embodiment, the charging of the gate electrode of the transistor of the reset switch 74 is controlled so as to control whether the gate electrode 54 of the transistor 51 is connected to the reference potential. Figure 7 In the arrangement shown, the reset switch 74 is configured to control whether the common reference contact 59 is in electrical contact with the common control contact 59. When the electrical connection is provided, the gate electrode 54 is discharged. This allows the evaluation of the transistor 51 to be performed again (e.g., repeated testing) without the subsequent test being undesirably affected by the previous test.

[0144] In an embodiment, the reset switch 74 is closed by directing an electron beam onto the reset switch 74, for example, onto a gate electrode or a pad connected to the gate electrode. The reset switch 74 can then be reopened by allowing charge to leak (e.g., through gate leakage). Alternatively, the properties of the electron beam can be changed and the electron beam can be directed onto the reset switch 74 again so as to negatively charge the gate electrode of the reset switch 74. For example, the landing energy of the electrons of the electron beam can be adjusted so as to oppositely charge the gate electrode of the reset switch 74.

[0145] Alternatively, the reset switch 74 may be closed by illuminating the reset switch 74 with light (e.g., utilizing light-induced conductivity). This may temporarily close the reset switch 74 while the light is incident on the reset switch 74. The light may be turned off in order to reopen the reset switch 74. By using light, the reset switch 74 may be expected to reopen more quickly than if the reset switch 74 were controlled using an electron beam.

[0146] Fig. 9 is a schematic diagram of an alternative arrangement of a device such as transistor 51. Fig. 9 As shown, in an embodiment, transistors 51 are arranged in a plurality of arrays 50. However, it is not necessary that transistors 51 be arranged in arrays 50. Transistors 51 may be reorganized as needed and need not be organized in a row.

[0147] For example, Fig. 9 As shown, in an embodiment, transistor 51 is arranged around one or more electronic structures 73. Fig. 9 In the example shown, one group of transistors 51 is arranged around one electronic structure 73, and another group of transistors 51 is arranged around another electronic structure 73. Transistors 51 may be located adjacent to electronic structure 73. Transistors 51 may have properties that more accurately represent properties of a transistor or other device that forms part of electronic structure 73.

[0148] like Fig. 9 As shown, in an embodiment, the scanning region 75 is remote from the transistor 51. An electrode contact 76 may be provided within the scanning region 75.

[0149] The transistor 51 may be located at various locations in the substrate. For example, different transistors 51 may be located in different contexts, such as near different types of electronic structures 73 or different types of devices with different manufacturing processes. Fig. 9 As shown, electrical traces 77 may be provided for electrically connecting electrode contacts 76 to transistor 51. In an embodiment, the electron beam is scanned over only one field of view (i.e., scanning area 75) while accessing the effects of different backgrounds on the electrical quantity of transistor 51. Fig. 9 In the embodiment, only the electrical traces 77 between the electrode contacts and the transistors 51 are schematically shown. In the embodiment, each transistor 51 is electrically connected to the corresponding electrode contact 76 by the electrical traces 77.

[0150] Fig.10 70 is a schematic diagram showing an array 50 including devices such as transistors. Figure 6 The arrangements shown have the same features. For example, the common control contact 59 and the common reference contact 57 may be as described elsewhere.

[0151] like Fig.10 As shown, in an embodiment, the marking 70 includes a column variation 71. For example, the column variation 71 may be a programmable overlay shift between two layers of the device. Alternatively, the column variation may be, for example, increasing the size of the gate electrode 54 of the device.

[0152] like Fig.10 As shown, in an embodiment, the mark 70 includes an arrangement of arrays 50. In an embodiment, the arrays 50 are different types of devices. For example, some arrays 50A are transistor arrays with relatively high threshold voltages. In addition, multiple arrays 50B can be transistor arrays with relatively low threshold voltages.

[0153] like Fig.10 As shown, in an embodiment, the marker 70 includes a mixture of different types of devices, such as a mixture of high threshold voltage transistors and low threshold voltage transistors. Fig.10 As shown, in an embodiment, the marking 70 comprises an array of arrays 50 .

[0154] By mixing arrays 50 of different types of transistors, markers 70 can be used to incorporate geometric variations and proximity effects. Fig.1071, but there may be row variations in addition to the column variations 71 shown. Different types of transistors may be formed using different manufacturing processes. The manufacturing process used to make high threshold voltage transistors may have an undesirable effect on the properties of low threshold voltage transistors. Similarly, the manufacturing process used to make low threshold voltage transistors may have an undesirable effect on the properties of high threshold voltage transistors. By placing different types of transistors close to each other, the effects of the manufacturing processes of nearby devices may be measured.

[0155] By providing column variations and / or row variations, an optimal process window can be found. For example, it can be determined which transistor 51 attributes (metrics) overlap within specifications, i.e., are acceptable, and which overlap metrics are outside specifications. This helps define an overlap window, i.e., a window in which the manufacturing process has acceptable results.

[0156] like Fig.10 As shown, in an embodiment, a common reference contact 57 may be provided for multiple or all arrays 50. Fig.10 As shown, in an embodiment, a common control contact 59 may be provided for a plurality of arrays 50 , or optionally all arrays 50 in a tag 70 .

[0157] Fig.11 is a schematic diagram showing an alternative arrangement of transistors 51 to be tested. Fig.11 As shown, in an embodiment, transistors 51 are arranged in an array 50. However, transistors 51 may be arranged more irregularly.

[0158] For the sake of brevity, this is not described below. Fig.11 The features shown in and other figures may be as described elsewhere. For example, common reference contact 57, common control contact 59, transistor 51, and electrode contact 76 may be as described elsewhere. Fig.11 As shown, in an embodiment, the substrate includes a probe contact 82. The probe contact 82 may be referred to as a probe measurement site. The probe contact 82 is exposed at the surface of the substrate. In an embodiment, the probe contact 82 includes a pad, such as a metal pad.

[0159] like Fig.11 As shown, in an embodiment, the probe contact 82 is electrically connected to one of the electrode contacts 76. For example, in an embodiment, the probe contact 82 and the connected electrode contact 76 can be formed integrally with each other. For example, a single metal pad can be provided to serve as both the probe contact 82 and the connected electrode contact 76. Alternatively, the probe contact 82 and the connected electrode contact 76 can be provided as separate contacts, which are electrically connected, for example, by electrical traces.

[0160] like Fig.11As shown, in an embodiment, the probe contact 82 is larger than the electrode contact 76. The probe contact 82 may be large enough to allow a physical probe to make electrical contact with the probe contact 82. The electrode contact 76 may not need to be large enough to be touched by the physical probe.

[0161] In an embodiment, the probe contacts 82 are used to electrically connect the connected electrode contacts 76 to the probe. By providing the probe contacts 82 as larger pads, the physical tip of the probe can be used to connect to the probe contacts 82.

[0162] In an embodiment, the calibration method includes connecting a probe to a plurality of probe contacts 82, a common reference contact 57, and a common control contact 59. The probe may be used to measure current and / or voltage.

[0163] like Fig.11 As shown, in an embodiment, scanning region 75 includes electrode contacts 76. Scanning region 75 may include a portion of common control contact 59.

[0164] like Fig.11 As shown, in an embodiment, the scanning area 75 is scanned by the electron beam by scanning a plurality of substantially parallel lines 80. The lines 80 may be scanned sequentially so that the entire scanning area 75 is scanned.

[0165] In an embodiment, the common control contact 59 is scanned before scanning the electrode contacts 76. The common control contact 59 may be charged before the electron beam scans the electrode contacts 76. In an embodiment, the scanning area 75 is scanned using a frame scanning mode.

[0166] Fig.11 An alternative scanning mode is shown. In particular, in an embodiment, the electrode contacts 76 are scanned in a line scanning mode. In the line scanning mode, the scanning area 75 does not need to be scanned. In contrast, a single scanning line 81 can be scanned. The scanning line can be straight, i.e. linear. In Fig.11 In the arrangement shown, one scan line 81 is shown for scanning half of the electrode contacts 76. In an embodiment, a second scan line will be scanned to scan the other half of the electrode contacts 76. In an embodiment, the common control contact 59 is discharged between scanning of different scan lines 81.

[0167] like Fig.11 As shown, in an embodiment, the scan line 81 covers a portion of the common control electrode 59 and a plurality of electrode contacts 76. In an embodiment, the common control contact 59 is scanned within the scan line 81 before the electrode contacts 76 are scanned.

[0168] In the arrangements described with reference to the drawings, devices such as transistors 51 are generally provided with respective electrode contacts 76. However, this is not required. For example, in alternative embodiments, multiple or all drain electrodes 53 of transistors 51 are connected to a common electrode contact (not shown), for example by electrically connecting the electrode contacts 76 shown in the figure or by providing a large electrode contact 76 connected to multiple drain electrodes 53 of transistors 51. In an embodiment, a separate control contact is provided for the respective transistors 51, which contact is connected to the respective gate electrode 54, for example. By providing separate control contacts, transistors 51 can be individually addressable, even though they can share a common electrode contact for the drain electrodes 53.

[0169] In an embodiment, a non-transitory computer readable medium stores instructions for a processor of a controller (eg, controller 109 ) to perform the above-described method.

[0170] Exemplary embodiments of the present disclosure are listed in the following numbered clauses:

[0171] 1. A method for testing an array of devices, each device having an electrical connection between two electrodes, the two electrodes being controllable by a signal applied to a control element, the method comprising:

[0172] applying a reference potential to a first electrode of two electrodes of each device;

[0173] directing a charged particle beam onto a second electrode of two electrodes of each device;

[0174] varying the signal applied to the control element of each device; and

[0175] For each signal applied, the signal charged particles from the second electrode of each device are monitored.

[0176] 2. A method according to clause 1, wherein the signal is an electric potential.

[0177] 3. A method according to clause 2, wherein control elements of a plurality of devices are connected to a common control contact so as to apply a varying electrical potential.

[0178] 4. A method according to any preceding clause, wherein the signal applied to the control element of each device is applied by a test probe.

[0179] 5. A method according to any of clauses 1 to 3, wherein the signal applied to the control element of each device is applied by directing a further charged particle beam to a common control contact connected to a plurality of control elements.

[0180] 6. A method according to any one of clauses 1-3, wherein before directing the charged particle beam to the second electrode of each device, the signal applied to the control element of each device is applied by directing the charged particle beam to a common control contact connected to a plurality of control elements, whereby the common control contact has a capacitance so that the signal applied to the control element of each device is maintained while monitoring the signal charged particles from the second electrode of each device.

[0181] 7. The method according to clause 6, further comprising: directing the charged particle beam to a common reference contact connected to the plurality of first electrodes.

[0182] 8. The method of clause 7, wherein after directing the charged particle beam onto the second electrodes of the plurality of devices, the charged particle beam is directed onto the common reference contact.

[0183] 9. The method according to clause 1, wherein the signal is a photon signal, and the step of varying the photon signal comprises varying at least one of an intensity and a wavelength of the photon signal.

[0184] 10 A method according to any preceding clause, wherein the first electrodes of the plurality of devices are connected to a common reference potential so as to apply the reference potential.

[0185] 11. A method according to any preceding clause, the method comprising determining, for each device, at least one of a threshold signal, a leakage current and a subthreshold slope based on signal particles monitored for a varying signal.

[0186] 12. A method according to any preceding clause, further comprising:

[0187] varying the current of the charged particle beam applied to the second electrode of each device while maintaining the signal applied to the control element of each device; and

[0188] The signal charged particles from the second electrode of each device are monitored for varying current.

[0189] 13. The method according to clause 12, further comprising: determining, for each device, a relationship between a potential difference between two electrodes and a current between the two electrodes based on the signal particles monitored for the varying signal.

[0190] 14. A method according to any preceding clause, further comprising:

[0191] applying a saturation signal to a control element of each device and / or directing light onto each device such that both electrodes in substantially all devices are electrically connected; and

[0192] Signal charged particles from the second electrode of each device are monitored while guiding of the charged particle beam onto the second electrode of each device is suppressed.

[0193] 15. A method according to any preceding clause, wherein the second electrode is electrically coupled to a respective electrode contact arranged in a contact area remote from the first electrode and the control element.

[0194] 16. The method according to clause 15, wherein the charged particle beam is directed onto the second electrode by scanning the charged particle beam across the contact region such that the charged particle beam is indirectly directed onto the second electrode via directing the charged particle beam onto the electrode contact directly.

[0195] 17. The method according to clause 16, wherein scanning comprises scanning the charged particle beam along a plurality of substantially parallel lines.

[0196] 18. The method of clause 17, further comprising: scanning the charged particle beam along a plurality of substantially parallel lines across a common control contact connected to a plurality of control elements.

[0197] 19. The method of clause 17, wherein scanning each line comprises scanning the charged particle beam across a common control contact electrically coupled to a plurality of control elements and across a plurality of electrode contacts.

[0198] 20. The method of clause 16, wherein scanning comprises scanning the charged particle beam along at least one straight line, across common control contacts connected to the plurality of control elements and across electrode contacts.

[0199] 21. A method according to any of clauses 18-20, wherein the common control contact is scanned before scanning the electrode contacts.

[0200] 22. A charged particle optical device for testing an array of devices, each device having an electrical connection between two electrodes which can be controlled by a signal applied to a control element, the device comprising:

[0201] a reference voltage source configured to supply a reference potential to a first electrode of the two electrodes of each device;

[0202] a charged particle optical device configured to direct a charged particle beam onto a second of the two electrodes of each device;

[0203] a signal source configured to vary a signal applied to a control element of each device; and a detector for monitoring signal charged particles from the second electrode of each device for each signal applied.

[0204] 23. A charged particle optical device according to clause 22, further comprising a substrate located at the sample location, the substrate comprising an array of devices, each device having an electrical connection between two electrodes which can be controlled by a signal applied to a control element.

[0205] 24. A charged particle optical device according to clause 23, wherein the device is a logic transistor or a DRAM structure.

[0206] 25. A charged particle optical device according to clause 23 or 24, wherein at least one structural feature of the apparatus varies in a predetermined manner across the array.

[0207] 26. A charged particle optical device according to any of clauses 23-25, wherein the at least one characteristic comprises at least one of an overlap shift between layers of the device and a size of a component of the device.

[0208] 27. A substrate comprising an arrangement of devices in a test area, each device having an electrical connection between a source electrode and a drain electrode, the source electrode and the drain electrode being controllable by a potential applied to a gate electrode, wherein the source electrode or the drain electrode is connected to a common reference contact, and whichever of the source electrode and the drain electrode is not connected to the common reference contact is electrically connected to a corresponding electrode contact exposed at a surface of the substrate.

[0209] 28. A substrate according to clause 27, wherein the arrangement comprises a two-dimensional array.

[0210] 29. A substrate according to clause 27 or 28, wherein the device comprises a logic transistor or a memory structure.

[0211] 30. A substrate according to any of clauses 27-29, wherein the gate electrodes are electrically coupled to a common control contact.

[0212] 31. A substrate according to any of clauses 27-30, wherein the electrode contacts comprise individual through-holes.

[0213] 32. A substrate according to any of clauses 27 to 31, wherein the electrode contact is arranged in a contact region remote from the gate electrode, and any one of the source electrode and the drain electrode is connected to a common reference contact.

[0214] 33. The substrate according to clause 32, wherein the contact region is adjacent to a common control contact to which the gate electrode is electrically coupled.

[0215] 34. The substrate of any of clauses 27-33, wherein the electrode contacts are arranged in a two-dimensional array.

[0216] 35. A substrate according to any of clauses 27-34, wherein the electrode contact is arranged adjacent to the electronic structure.

[0217] 36. A substrate according to any of clauses 27-35, wherein the electrode contacts are arranged around the electronic structure.

[0218] 37. A substrate according to any of clauses 27 to 36, wherein an electrical trace extends between the electrode contact and any one of the source electrode and the drain electrode that is not connected to the common reference contact.

[0219] 38. A substrate according to clause 37, wherein the electrical traces extend across the substrate at a plurality of layers within the substrate.

[0220] 39. The substrate of any of clauses 27-38, comprising an arrangement of another device having a different target property than the arrangement of devices.

[0221] 40. The substrate of claim 39, wherein the arrangements are adjacent to each other.

[0222] 41. The substrate of any of clauses 27-40, comprising a probe contact connected to one of the electrode contacts, the probe contact being used to electrically connect the electrode contact to the probe.

[0223] 42. The substrate of any of clauses 27-41, further comprising a reset switch configured to selectively couple the gate electrode to the common reference contact.

[0224] 43. A substrate according to any of clauses 27-42, wherein the devices are arranged at a pitch of at most about 200 nm, optionally at most about 100 nm and optionally at most about 50 nm.

[0225] 44. The substrate of any of clauses 27-43, wherein the arrangement is located in a scribe lane of the substrate.

[0226] 45. A non-transitory computer readable medium storing instructions for a processor of a controller to execute a method for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element, the method comprising:

[0227] controlling application of a reference potential to a first electrode of two electrodes of each device;

[0228] controlling to direct the charged particle beam onto a second electrode of the two electrodes of each device;

[0229] controlling the change of the signal applied to the control element of each device; and

[0230] For each signal applied, monitoring of the signal charged particles from the second electrode of each device is controlled.

[0231] A non-transitory computer readable medium may be provided that stores a controller (eg, Figure 1 Instructions of a processor of a controller 109 in the apparatus to perform image inspection, image acquisition, activation of a charged particle source, adjustment of electrical excitation of an stigmator, adjustment of landing energy of electrons, adjustment of objective lens excitation, adjustment of secondary electron detector position and orientation, stage motion control, beam splitter excitation, application of scanning deflection voltage to a beam deflector, receiving and processing data associated with signal information from an electron detector, configuring electrostatic elements, detecting signal electronics, adjustment of control electrode potentials, adjustment of voltages applied to an electron source, an extractor electrode and a sample, etc. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage medium, compact disk read-only memory (CD-ROM), any other optical data storage medium, any physical medium having a pattern of holes, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), FLASH-EPROM or any other flash memory device, non-volatile random access memory (NVRAM), cache devices, registers, any other memory chip or cartridge memory, and network versions.

[0232] It should be understood that the embodiments of the present disclosure are not limited to the exact structures described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in conjunction with various embodiments, and other embodiments of the present invention will be apparent to those skilled in the art in view of the description and practice of the invention disclosed herein. The description and embodiments are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the appended claims.

[0233] The above description is intended to be illustrative rather than limiting. Therefore, it will be apparent to those skilled in the art that modifications as described above may be made without departing from the scope of the claims set forth below.

Claims

1. A method for testing an array of devices, each device having an electrical connection between two electrodes that can be controlled by a signal applied to a control element, the method comprises: applying a reference potential to a first one of the two electrodes of each device; directing a charged particle beam onto a second one of the two electrodes of each device; varying the signal applied to the control element of each device; and for each signal applied, monitoring the signal charged particles from the second electrode of each device.

2. The method according to claim 1, wherein the signal is a potential.

3. The method according to claim 2, wherein the control elements of a plurality of the devices are connected to a common control contact for applying the varying potential.

4. The method according to claim 1, wherein the signal applied to the control element of each device is applied by a test probe.

5. The method according to claim 1, wherein the signal applied to the control element of each device is applied by directing an additional charged particle beam onto a common control contact connected to a plurality of the control elements.

6. The method according to claim 1, wherein before directing the charged particle beam onto the second electrode of each device, the signal applied to the control element of each device is applied by directing a charged particle beam onto a common control contact connected to a plurality of the control elements, whereby the common control contact has a capacitance such that the signal applied to the control element of each device is maintained while monitoring the signal charged particles from the second electrode of each device.

7. The method according to claim 1, wherein the signal is a photon signal, and the step of varying the photon signal comprises varying at least one of the intensity and wavelength of the photon signal.

8. The method according to claim 1, wherein the first electrodes of a plurality of the devices are connected to a common reference potential for applying the reference potential.

9. The method according to claim 1, the method comprises: determining, for each device, at least one of a threshold signal, a leakage current, and a subthreshold slope based on the signal particles monitored for the varying signal.

10. The method according to claim 1, the method comprises: varying the current of the charged particle beam applied to the second electrode of each device while maintaining the signal applied to the control element of each device; and for the varying current, monitoring the signal charged particles from the second electrode of each device.

11. The method according to claim 10, the method comprises: determining, for each device, the relationship between the potential difference between the two electrodes and the current between the two electrodes based on the signal particles monitored for the varying signal.

12. The method according to claim 1, the method comprises: applying a saturation signal to the control element of each device and / or directing light onto each device such that the two electrodes in substantially all of the devices are electrically connected; and Monitoring the signal charged particles from the second electrode of each device while suppressing the guiding of the charged particle beam onto the second electrode of each device.

13. A charged particle optical device for testing an array of devices, each device having an electrical connection between two electrodes, the two electrodes being controllable by a signal applied to a control element, the electron optical device comprises: a reference voltage source configured to supply a reference electric potential to a first electrode of the two electrodes of each device; a charged particle optical device configured to direct a charged particle beam onto a second electrode of the two electrodes of each device; a signal source configured to vary the signal applied to the control element of each device; and a detector for monitoring, for each applied signal, the signal charged particles from the second electrode of each device.

14. The charged particle optical device according to claim 13, wherein the charged particle optical device further comprises a substrate located at the sample position, the substrate comprising an array of devices, each device having an electrical connection between two electrodes, the two electrodes being controllable by a signal applied to a control element.

15. The charged particle optical device according to claim 14, wherein the device is a logic transistor or a DRAM structure.

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