Low-redundancy cascode bias circuit for cascode current mirror

Abstract

The cascode bias circuit biases the grid electrode of the cascode transistor in the cascode current mirror. The cascode bias circuit includes a first transistor configured to conduct a first current, and includes a second transistor configured to conduct a second current. The first transistor and the second transistor are coupled to a third transistor configured to conduct a sum of the first current and the second current. A gate of the first transistor is coupled to a gate of the cascode transistor to bias the cascode transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of U.S. Patent Application No. 17 / 982,420, filed on November 7, 2022, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes. Technical field

[0003] This application relates to a bias circuit for a current mirror, and more particularly, to a low - headroom cascode bias circuit for a cascode current mirror. Background art

[0004] As Figure 1 shown, a current mirror 100 can be constructed using a diode - connected transistor M1 having a gate connected to a matching current - source transistor M2. A current source 105 drives a reference current I through the channel of the diode - connected transistor M1. Assuming the reference current induces a sufficient (greater than sub - threshold) current density in the diode - connected transistor M1, the diode - connected transistor M1 conducts the reference current in the saturation state. The gate - source voltage of the diode - connected transistor M1 is thus a function of the reference current. Since the current - source transistor M2 has the same gate - source voltage, the current - source transistor M2 will ideally operate in the saturation state to conduct a copy of the reference current.

[0005] The problem with this ideal behavior is that the drain - source voltage across the diode - connected transistor M1 is its gate - source voltage, while the drain - source voltage across the current - source transistor M2 will depend on the voltage characteristics of the output voltage circuit 110. Thus, the drain - source voltages of transistors M1 and M2 can be unequal. The unequal drain - source voltages of transistors M1 and M2 result in unequal effective channel lengths for transistors M1 and M2. The resulting channel - length modulation reduces the accuracy of the current mirroring. Summary of the invention

[0006] According to one aspect of the present disclosure, there is provided a cascode bias circuit, comprising: a first current source configured to supply a first current; a second current source configured to supply a second current; a first transistor having a drain coupled to the first current source; a second transistor having a source coupled to the source of the first transistor and a drain coupled to the second current source; and a third transistor having a drain coupled to the source of the first transistor and coupled to the source of the second transistor.

[0007] According to another aspect of the present disclosure, a method of biasing a cascode current mirror is provided. The method includes: driving a first current into a first transistor to generate a gate-source voltage across the first transistor; driving a second current into a second transistor to generate a threshold voltage difference between the gate and the drain of the second transistor; combining the second current at the drain of the second transistor and the first current at the drain of the first transistor to form a combined current; driving the combined current into a third transistor to make the gate voltage of the first transistor equal to the sum of the gate-source voltage of the first transistor and the drain-source voltage of the third transistor; and using the gate voltage of the first transistor to bias the gate of a first cascode transistor in the cascode current mirror.

[0008] According to another aspect of the present disclosure, a cascode current mirror is provided. The cascode current mirror includes: a first cascode transistor; a current source transistor in series with the first cascode transistor; and a cascode biasing circuit including: a first transistor configured to conduct a first current to generate a first gate-source voltage, the first transistor having a gate coupled to the gate of the first cascode transistor; a second transistor configured to conduct a second current to generate a second gate-source voltage substantially equal to the transistor threshold voltage; and a third transistor coupled to the drain of the first transistor and the drain of the second transistor, the third transistor having a gate coupled to the gate of the second transistor.

[0009] According to yet another aspect of the present disclosure, a cascode current mirror is provided. The cascode current mirror includes: a first current source configured to provide a first current; a first cascode transistor configured to conduct the first current; a cascode biasing circuit including: a second current source configured to supply a second current; a first transistor configured to conduct the second current and having a gate coupled to the gate of the first cascode transistor; a second current source configured to supply a third current; a second transistor configured to conduct the second current; and a third transistor coupled to the drain of the first transistor and the drain of the second transistor, the third transistor having a gate coupled to the gate of the second transistor, wherein both the second current and the third current are less than the first current.

[0010] These and other advantageous features can be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a circuit diagram of a current mirror.

[0012] Figure 2A circuit diagram of an NMOS cascode current mirror including a cascode biasing circuit according to an aspect of the present disclosure, wherein the cascode biasing circuit biases only the gates of a pair of cascode transistors.

[0013] Figure 3 A circuit diagram of a cascode biasing circuit.

[0014] Figure 4 According to an aspect of the present disclosure Figure 2 A circuit diagram of the cascode biasing circuit in the cascode current mirror according to an aspect of the present disclosure.

[0015] Figure 5 A circuit diagram of an NMOS cascode current mirror including a cascode biasing circuit according to an aspect of the present disclosure, wherein the cascode biasing circuit biases only the gates of the cascode transistors and the gate of the current source transistor.

[0016] Figure 6A A circuit diagram of a PMOS cascode current mirror including a cascode biasing circuit according to an aspect of the present disclosure, wherein the cascode biasing circuit biases only the gates of a pair of cascode transistors.

[0017] Figure 6B A circuit diagram of a PMOS cascode current mirror including a cascode biasing circuit according to an aspect of the present disclosure, wherein the cascode biasing circuit biases only the gates of the cascode transistors and the gate of the current source transistor.

[0018] Figure 7 Shows some example electronic devices including a cascode biasing circuit according to an aspect of the present disclosure.

[0019] Figure 8 A flowchart of an example method for biasing a cascode current mirror according to an aspect of the present disclosure.

[0020] The implementation and advantages of the present disclosure can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more of the drawings. Detailed Description

[0021] As discussed with respect to current mirror 100, if the diode-connected transistor M1 and the current source transistor M2 have unequal drain-source voltages, the resulting channel length modulation adversely affects the current mirror accuracy. Therefore, it is advantageous for the diode-connected transistor M1 and the current source transistor M2 to have equal drain-source voltages. To provide these equal drain-to-source voltages, the current mirror 100 is modified herein as Figure 2is shown by the cascode current mirror 200. The cascode transistor M3 at the drain of the current source transistor M2 effectively isolates the current source transistor M2 from any varying voltage from the output circuit 110. To allow the current source transistor M2 to operate at the edge of the saturation region, the diode connection of the diode-connected transistor M1 is modified such that the cascode transistor M4 is coupled between the gate and the drain of the diode-connected transistor M1. Although there is a cascode transistor M4 between the gate and the drain of the diode-connected transistor M1, it can be shown that the diode-connected transistor M1 is indeed effectively diode-connected. The cascode transistor M4 introduces a voltage drop between the gate voltage and the drain voltage of the diode-connected transistor M1. Both cascode transistors M3 and M4 are matched. As defined herein, one transistor is considered to be matched to another transistor when the relative dimensions and biasing of one transistor and the other transistor result in the two transistors having the same current density when operating in the saturation state. Then, as further explained herein, the current mirror transistor M2 will conduct a copy of the reference current without any inaccuracies caused by the channel length modulation effect. Although the problem of channel length modulation is thus effectively solved, a suitable cascode biasing circuit is needed to bias the cascode transistors. However, it is difficult to design a cascode biasing circuit with a low voltage margin and without body effect or other problems. These design problems are solved such that the cascode biasing circuit introduced herein has a favorable low margin (the maximum voltage in the cascode biasing circuit) and is substantially free of any body effect.

[0022] The disclosed cascode biasing circuit can be constructed using n-type metal-oxide-semiconductor (NMOS) transistors or p-type metal-oxide-semiconductor (PMOS) transistors. The current mirror 200 is an NMOS current mirror and thus includes an NMOS cascode biasing circuit 205. Similarly, a PMOS cascode biasing circuit is used to bias a PMOS cascode current mirror. The NMOS cascode biasing circuit 205 will be discussed first, and then the PMOS implementation will be discussed. Before analyzing the NMOS cascode biasing circuit 205 in detail, the cascode current mirror 200 will be discussed in more detail as follows. The gate of the diode-connected transistor M1 and the drain of the cascode transistor M4 are both coupled to a current source 105 that provides a reference current (I). The cascode transistor M4 is also denoted herein as the first cascode transistor. The cascode transistor M3 is coupled between the drain of the current source transistor M2 and the output circuit 110. The cascode transistor M3 is also denoted herein as the second cascode transistor. The sources of the diode-connected transistor M1 and the current source transistor M2 are both coupled to ground.

[0023] The gate of the diode-connected transistor M1 is coupled to the gate of the current source transistor M2. The gate-source voltage Vgs1 of the diode-connected transistor M1 is thus also the gate-source voltage of the current source transistor M2. The cascode bias circuit 205 biases the gates of the cascode transistors M3 and M4 using the cascode bias voltage Vbias. Since the matched cascode transistors M3 and M4 have the same gate voltage Vbias and conduct the same reference current, the gate-source voltage Vgs4 of the cascode transistor M4 is equal to the gate-source voltage Vgs3 of the cascode transistor M3. The drain-source voltage Vds1 of the diode-connected transistor M1 and the drain-source voltage of the current source transistor M2 are thus equal. Since both the transistors M1 and M2 are in saturation if the gate voltage Vbias is greater than the sum of Vgs4 and Vds1, the following discussion refers to the drain-source voltage Vds1 of the diode-connected transistor M1 as Vdsat1. Thus, it can be understood that the gate-source voltage Vgs1 of the diode-connected transistor M1 is equal to the gate-source voltage of the current source transistor M2, and the two transistors have the same drain-source voltage. In this manner, the current source transistor M2 accurately mirrors the reference current, which is then conducted by the output circuit 110 as desired.

[0024] To provide the lowest possible drain voltage of the cascode transistor M3 while still keeping the cascode transistor M3 in saturation, the diode-connected transistor M1 should be at the edge of saturation, i.e., its drain-source voltage Vdsat1 should be substantially equal to Vgs1 - Vth1, where Vth1 is the threshold voltage of the diode-connected transistor M1. Assume that the sizes of the cascode transistors M3 and M4 are designed such that their overdrive voltages (the difference between their gate-source voltages and their threshold voltages) are much lower than their threshold voltages. Due to the diode connection of the diode-connected transistor M1, the drain voltage of the cascode transistor M4 is Vgs1. The minimum drain-source voltage Vds4 of the cascode transistor M4 (where the cascode transistor M4 is still in saturation) is the difference between its gate-source voltage Vgs4 and its threshold voltage Vth4. Since the source voltage of the cascode transistor M4 is Vdsat1, the gate voltage of Vgs4 is equal to the sum of its gate-source voltage Vgs4 and Vdsat1. Thus, the cascode bias voltage Vbias is equal to the sum of Vgs4 and Vdsat1.

[0025] Thus, it is desirable for the cascode bias circuit to generate a cascode bias voltage equal to the sum of Vgs4 and Vdsat1, but the generation of such a cascode bias voltage is difficult. For example, consider Figure 3The cascode bias circuit 300. The NMOS transistor M5 is diode-connected and has a source coupled to ground. The drain of the transistor M5 is coupled to the source of the transistor M6. The drain of the transistor M6 is coupled to the source of the diode-connected NMOS transistor M7. The gate of the transistor M7 is coupled to the gate of the transistor M6 and the drain of the transistor M7. The current source 305 drives a reference current I through the channels of the transistors M5, M6, and M7. The transistor M5 matches the cascode transistor M4 of the cascode current mirror 200. The gate-source voltage of the transistor M5 is thus equal to Vgs4. The transistor M6 matches the diode-connected transistor M1 of the cascode current mirror 200. The drain-source voltage of the transistor M6 is thus equal to Vdsat1. A cascode bias voltage Vbias is generated at the drain of the transistor M6. Thus, the cascode bias voltage Vbias ideally equals Vgs4 + Vdsat1. Regarding this cascode bias voltage generation, the size of the transistor M7 is designed such that it operates at the edge of the subthreshold region. The gate-source voltage of the transistor M7 is thus equal to its threshold voltage. (Again assuming that the transistor M5 matches the cascode transistor M4 of the cascode current mirror 200, and the transistor M6 matches the diode-connected transistor M1 of the cascode current mirror 200) The gate voltage of the transistor M7 is the sum of Vgs4 and Vgs1. Assuming that the threshold voltage of the transistor M7 matches the threshold voltage Vth1 of the diode-connected transistor M1 of the cascode current mirror 200, the threshold voltage drop of Vth1 from the gate voltage of the transistor M7 indeed provides the desired value of the cascode bias voltage Vgs4 + Vdsat1.

[0026] Although the cascode bias circuit 300 ideally generates the desired value of the cascode bias voltage Vbias, there are several issues that affect the accuracy of the bias voltage generation. For example, the source voltage of transistor M7 is substantially equal to the sum of Vgs4 + Vdsat1. In contrast, the source voltage of the diode-connected transistor M1 is grounded. Therefore, there is a significant body effect difference between the threshold voltages of transistors M1 and M7, which is not conducive to the desired matching of the threshold voltages. In addition, if the threshold voltage of transistor M7 is too large, transistor M6 is forced into the triode region instead of operating in the saturation state. Further, the source voltage of transistor M5 is grounded, while the source voltage of the cascode transistor M4 is Vdsat1, resulting in a body effect difference between these two transistors, which leads to a threshold voltage difference. Similarly, the threshold voltages of the diode-connected transistor M1 and transistor M6 will be different due to the body effect difference. In addition, the headroom of the cascode bias circuit 300 is limited because the drain voltage of transistor M7 is substantially equal to the sum of Vgs4 and Vgs1. Considering this limited headroom, if the supply voltage of current source 305 is relatively low, current source 305 may not have sufficient voltage headroom to operate properly or as designed.

[0027] The cascode bias circuit 205 of the current mirror 200 advantageously avoids these problems. Figure 4 The cascode bias circuit 205 is shown in more detail in. The source of NMOS transistor M8 is coupled to ground and the drain is coupled to NMOS transistor M9. The gate of transistor M8 is coupled to the gate of transistor M9. The drain of transistor M9 is coupled to its gate and is also coupled to the output terminal of current source 405, which outputs half of the reference current (I / 2). The source of the NMOS diode-connected transistor M10 is coupled to the drain of transistor M8. Current source 410 drives half of the reference current (I / 2) into the gate and drain of transistor M10. Transistor M10 may also be represented as the first transistor herein. Similarly, transistor M9 may be represented as the second transistor, while transistor M8 may be represented as the third transistor.

[0028] Transistor M8 conducts the reference current I because it has to conduct the combined current formed by the combination of I / 2 from current source 405 and I / 2 from current source 410. Transistor M8 matches the diode-connected transistor M1 in the cascode current mirror 200. The gate-source voltage of transistor M8 will thus be substantially equal to Vgs1. The size of transistor M9 is designed to be at the edge of the subthreshold region when it conducts I / 2. The gate-source voltage of transistor M9 is thus equal to the threshold voltage of transistor M9. Assuming that this threshold voltage is substantially equal to the threshold voltage Vth1 of the diode-connected transistor M1, the source voltage of transistor M9 is thus substantially equal to Vgs1 - Vth1 (equal to Vdsat1). Transistor M10 can be half the size of cascode transistor M4. Since this half-sized transistor conducts half of the reference current, the current density in transistor M10 matches the current density in cascode transistor M4. Thus, the gate-source voltage of transistor M10 is equal to Vgs4. The cascode bias voltage Vbias is induced at the drain of transistor M10 and will thus be equal to the desired value of Vgs4 + Vdsat1.

[0029] The cascode bias circuit 205 has many advantages compared to the cascode bias circuit 300. For example, the source voltage of transistor M8 matches the source voltage of the diode-connected transistor M1 in the cascode current mirror 200. Thus, there is no body effect problem that would affect the matching between transistor M8 and the diode-connected transistor M1. In contrast, the source voltages of transistor M6 and the diode-connected transistor M1 in the cascode bias circuit 300 are different. Similarly, the source voltage of transistor M10 in the cascode bias circuit 205 is the same as the source voltage of the cascode transistor M4 in the cascode current mirror 200. In contrast, the source voltage of transistor M5 in the cascode bias circuit 300 is not equal to the source voltage of the cascode transistor M4. Although the source voltage of transistor M9 in the cascode bias circuit 205 is not equal to the source voltage of the diode-connected transistor M1, these two source voltages are relatively similar compared to the larger source voltage difference between transistor M7 and the diode-connected transistor M1 in the cascode bias circuit 300. Transistor M9 in the cascode bias circuit 205 thus better matches the threshold voltage of the diode-connected transistor M1. Finally, the highest voltage in the cascode bias circuit 300 is Vgs4 + Vgs1, while in the cascode bias circuit 205 it is only Vgs1 + Vdsat1. Thus, the cascode bias circuit 205 advantageously has substantially no body effect error and has improved margin and reduced process, voltage, and temperature variations.

[0030] It should be understood that the cascode bias circuit 205 can be modified as long as the desired matching current density in saturation is achieved between the transistors. For example, assume that current sources 405 and 410 each supply a reference current I instead of I / 2. In this case, the size of transistor M8 will be designed to be twice that of diode-connected transistor M1 so that the two transistors have the same current density when operating in saturation. Similarly, transistor M10 will then have the same size as cascode transistor M4. The size of transistor M9 will also have to be adjusted so that it is at the edge of the threshold region when conducting the reference current I. More generally, the sizes of transistors M8, M9, and M10 and the currents from current sources 405 and 410 can vary as long as the desired current density is achieved.

[0031] Note that transistor M8 is effectively diode-connected and can thus be used as an analogue of diode-connected transistor M1. Thus, diode-connected transistor M1 and cascode transistor M4 are not included in the resulting cascode current mirror 500 as Figure 5 shown. Current source transistor M2, cascode transistor M3, and output circuit 110 are arranged as discussed for cascode current mirror 200. Cascode bias circuit 505 has current sources 405 and 410 coupled to transistors M8, M9, and M10 as discussed for cascode bias circuit 205. However, the gate of transistor M8 in cascode bias circuit 505 is coupled to the gate of current source transistor M2. Additionally, when cascode transistor M4 is eliminated, the drain of transistor M10 in cascode bias circuit 505 is coupled only to the gate of transistor M3. Since cascode transistor M3 matches cascode transistor M4 in cascode current mirror 200, assuming the same transistor sizes as discussed for cascode current mirror 200, the current density in transistor M10 in cascode current mirror 500 matches the current density in cascode transistor M3. The sizes of transistors M8 and M2 are designed so that they have matching current densities. Since their gates are coupled, the gate-source voltage Vgs1 of current source transistor M2 is also the gate-source voltage of transistor M8. Transistors M8 and M2 both have the same gate-source voltage Vdsat1 so that current source transistor M2 accurately mirrors the reference current I. The PMOS implementation of the cascode bias circuit will now be discussed.

[0032] Only NMOS implementation, and the PMOS implementation can include PMOS equivalents of the diode-connected transistor M1 and the cascode transistor M4 in the PMOS cascode current mirror. In such an implementation, the PMOS cascode bias circuit will only bias the cascode transistor. However, as similarly pointed out regarding the cascode current mirror 500, the PMOS cascode bias circuit itself includes an analog of the diode-connected transistor in the cascode current mirror. In such an implementation, the PMOS cascode bias circuit not only biases the cascode transistor but also biases the current source transistor. First, the PMOS cascode bias circuit that only biases the cascode transistor in the PMOS cascode current mirror will be discussed, and then the PMOS cascode bias circuit that biases both the cascode transistor and the current source transistor in the PMOS cascode current mirror will be discussed.

[0033] Figure 6A An example PMOS cascode bias circuit 605 is shown, which only biases a pair of cascode transistors P4 and P3 in the PMOS cascode current mirror 600. The diode-connected PMOS transistor P1 is the PMOS analog of the diode-connected transistor M1 of the NMOS cascode current mirror 200. The gate of the diode-connected transistor P1 is coupled to the gate of the PMOS current mirror transistor P2, which is the analog of the NMOS current mirror transistor M2. The sources of the transistors P1 and P2 are coupled to the power supply node for the power supply voltage Vdd through respective degeneration resistors each having a resistance R. Note that in the NMOS cascode bias circuit implementation, similar degeneration resistors can be used at the sources of the transistors M1 and M2. The PMOS cascode transistor P3 is coupled between the drain of the current mirror transistor P2 and the output circuit 315, and the output circuit 315 will receive a mirrored version of the reference current I. Similarly, the PMOS cascode transistor P4 is coupled between the drain of the diode-connected transistor P1 and the current source 610 that supplies the reference current. The gate of the (effectively) diode-connected transistor P1 is coupled to the drain of the cascode transistor P4. The cascode transistor P4 is an example of the first cascode transistor, and the cascode transistor P3 is an example of the second cascode transistor.

[0034] The cascode bias circuit 605 serves as the PMOS analog of the NMOS cascode bias circuit 205. The PMOS transistor P1' matches the diode-connected transistor P1. The source of the transistor P1' is coupled to the power node for the power supply voltage Vdd through a degeneration resistor of the resistor R. It should be understood that a similar degeneration resistor can be inserted at the source of the transistor M8 in the NMOS cascode bias circuit 205. The transistor P1' conducts a combined current that is equal to the reference current I, which is generated by the current source 615 supplying I / 2 and by the current source 620 supplying I / 2. The resistor R at the source of the transistor P1' introduces an ohmic voltage loss equal to the product of I and its resistance R, such that the source voltage of the transistor P4' is equal to Vdd - IR. The drain of the transistor P1' is coupled to the source of the PMOS transistor P5. The drain of the transistor P5 is coupled to the current source 615. The gate of the transistor P1' is coupled to the drain of the transistor P5, such that the transistor P1' is effectively diode-connected. The gate of the transistor P1' is also coupled to the gate of the transistor P5. The drain of the transistor P1' is also coupled to the source of the PMOS diode-connected transistor P4'. The drain of the transistor P4' is coupled to the current source 620. Since both the transistors P5 and P4' conduct I / 2, it can be readily seen that the transistor P1' conducts a combined current equal to the reference current I. The size of the transistor P5 is designed to be similar to the size discussed for the transistor M9, such that the gate-source voltage of the transistor P5 is equal to its threshold voltage. Assuming that this threshold voltage is equal to the threshold voltage Vth1 of the transistor P1, the drain voltage of the transistor P5 is equal to Vdd - IR + Vgs1 - Vth1, which is equal to the desired value of Vdd - IR + Vdsat1.

[0035] The gate of transistor P4’ is coupled to the gates of cascode transistors P3 and P4 to bias the gates of cascode transistors P3 and P4 with the cascode bias voltage Vbias. As discussed for transistor M10, transistor P4’ can be half the size of transistor P4 such that it has the same current density as transistor P4. More generally, the sizes and currents of transistors P4 and P4’ can vary from these values as long as they operate in saturation and have the same current density. Thus, the gate-source voltage of transistor P4’ will match the gate-source voltage Vgs4 of cascode transistor P4. In this way, the gate-source voltage of transistor P4’ will replicate Vgs4. A similar match of current density is established for transistors P1 and P1’. The drain-source voltage Vdsat1 of transistor P1 thus matches the drain-source voltage of transistor P1’. Since each of the degeneration resistors introduces a voltage drop of IR, the source voltages of transistors P1 and P1’ are both equal to Vdd - IR. The gate voltage of transistor P1’ is equal to Vdd - IR + Vgs1 (note that for a PMOS implementation, Vgs1 is negative). The drain of transistor P1’ is equal to Vdd - IR + Vgs1 + Vdsat1 (note that the drain-source voltage Vdsat1 of transistor P1 is negative). Since transistor P4’ matches the current density of transistor P4 in saturation, the gate-source voltage Vgs4 of transistor P4 is also the gate-source voltage of transistor P4’. The gate voltage of transistor P4’ is thus equal to Vdd - IR + Vgs4 + Vdsat1, which serves as the cascode bias voltage Vbias generated by cascode bias circuit 605.

[0036] Using the cascode bias voltage Vbias at the gate of cascode transistor P4, its source voltage will be equal to Vdd - IR + Vdsat1. Similarly, the source voltage of cascode transistor P3 will be equal to Vdd - IR + Vdsat1. The drain-source voltages of diode-connected transistor P1 and current-source transistor P2 will thus both be equal to Vdsat1 such that current-source transistor P2 accurately mirrors the reference current I into output circuit 315 through cascode transistor P3. The source voltage of transistor P4’ will also be equal to Vdd - IR + Vdsat1, and thus there is no body effect that affects the matching of transistors P4 and P4’. Similarly, the voltage difference between the source voltage of transistor P5 and the source voltage of transistor P1 is only Vdsat1. Thus, the body effect is relatively small and will not cause the threshold voltage Vth1 generated by transistor P5 to be incorrect. Additionally, there is more voltage margin in cascode bias circuit 605 compared to the PMOS implementation of cascode bias circuit 300. Now a PMOS cascode bias circuit implementation will be discussed where the PMOS cascode current mirror does not include the equivalent of diode-connected transistor P1 and its corresponding cascode transistor P4.

[0037] Figure 6B An exemplary cascode bias circuit 655 is shown for biasing the current source transistor P2 and the cascode transistor P3 in the PMOS cascode current mirror 650. The transistors P1', P4', P5, and the current sources 615 and 620 are arranged as discussed for the cascode bias circuit 605. The gate voltage of the transistor P4' thus serves as a cascode bias voltage to bias the gate of the cascode transistor P3. The transistor P4' and the cascode transistor P3 are matched. Similarly, the transistor P1' and the current source transistor P2 are matched. The gate voltage of the transistor P1' is equal to Vdd - IR + Vgs1, as discussed for the cascode bias circuit 605. However, the gate of the transistor P1' in the cascode bias circuit 655 is now coupled to the gate of the current source transistor P2. The gate voltage of the transistor P4' is thus denoted as a first cascode bias voltage Vbias1, and the gate voltage of the transistor P1' is denoted as a second cascode bias voltage Vbias2. Since the gates of the transistors P1 and P1' are both coupled and their source voltages are equal, the gate-source voltage Vgs1 of the transistor P1' is equal to the gate-source voltage of the transistor P2. The size of the transistor P5 is designed such that its gate-source voltage is substantially equal to the threshold voltage Vth1 of the transistor P1'. The drain voltages of the transistor P1' and the current source transistor P2 are thus both equal to Vdd - IR + Vgs1 - Vth1. In the case where the transistor P1' is effectively diode-connected, the transistor P1' and P2 have the same gate-source voltage, and in the case where the transistor P1' and P2 have the same drain-source voltage, the current source transistor P2 will accurately mirror the reference current I. Additionally, similar to what was discussed regarding the cascode bias circuit 605, the cascode bias circuit 655 has the advantage over the method of the cascode bias circuit 300.

[0038] The cascode bias circuits as disclosed herein can be incorporated in any suitable mobile device or electronic system. For example, as Figure 7 shown, the base station 700, the laptop computer 705, and the tablet PC 710 can all include a cascode bias circuit according to the present disclosure. Other exemplary electronic systems such as cellular phones, music players, video players, communication devices, and personal computers can also be configured with a cascode bias circuit constructed according to the present disclosure.

[0039] Now reference will be made to Figure 8The method of the cascode current mirror will be discussed with reference to the flowchart. The method includes operation 800 which drives a first current into a first transistor to generate a gate-source voltage across the first transistor. Driving transistor M10 by current source 410 and driving transistor P4' by current source 620 are examples of operation 800. The method further includes operation 805 which drives a second current into a second transistor to generate a threshold voltage difference between the gate and the drain of the second transistor. Driving transistor M9 by current source 405 or driving transistor P5 is an example of operation 805. The method also includes operation 810: combining the second current at the drain of the second transistor and the first current at the drain of the first transistor to form a combined current. Combining the currents from current sources 405 and 410 or from current sources 615 and 620 is an example of operation 810. Additionally, the method includes operation 815: driving the combined current into a third transistor to make the gate voltage of the first transistor equal to the sum of the gate-source voltage of the first transistor and the drain-source voltage of the third transistor. Driving the combined current through transistor P1' or through transistor M8 is an example of operation 815. Finally, the method includes operation 820: using the gate voltage of the first transistor to bias the gate of the first cascode transistor in the cascode current mirror. Biasing any one of the cascode transistors M3, M4, P3, or P4 is an example of operation 820.

[0040] The present disclosure will now be outlined in the following series of articles:

[0041] Article 1. A cascode biasing circuit, comprising:

[0042] A first current source configured to supply a first current;

[0043] A second current source configured to supply a second current;

[0044] A first transistor having a drain coupled to the first current source;

[0045] A second transistor having a source coupled to the source of the first transistor and a drain coupled to the second current source; and

[0046] A third transistor having a drain coupled to the source of the first transistor and coupled to the source of the second transistor.

[0047] Article 2. The cascode biasing circuit according to Article 1, wherein each of the first transistor and the second transistor is diode-connected.

[0048] Clause 3. The cascode bias circuit as described in any one of Clauses 1-2, wherein the gate of the first transistor is coupled to the gate of the first cascode transistor in the cascode current mirror.

[0049] Clause 4. The cascode bias circuit according to Clause 3, wherein the first current is equal to the second current, and wherein the cascode current mirror further includes a first diode-connected transistor, the first diode-connected transistor is arranged in series with the first cascode transistor and in series with a third current source, the third current source is configured to supply a third current, and the third current is twice the first current.

[0050] Clause 5. The cascode bias circuit as described in any one of Clauses 3-4, wherein the gate of the second transistor is coupled to the gate of the third transistor.

[0051] Clause 6. The cascode bias circuit as described in any one of Clauses 3 to 5, wherein the second transistor is configured to have a gate-source voltage equal to the transistor threshold voltage.

[0052] Clause 7. The cascode bias circuit according to Clause 4, wherein the cascode current mirror further includes:

[0053] a current source transistor having a gate coupled to the gate of the first diode-connected transistor; and

[0054] a second cascode transistor arranged in series with the current source transistor and having a gate coupled to the gate of the first transistor.

[0055] Clause 8. The cascode bias circuit according to any one of Clauses 1-9, wherein the first transistor, the second transistor, and the third transistor each include an n-type metal oxide semiconductor transistor.

[0056] Clause 9. The cascode bias circuit according to any one of Clauses 1-9, wherein the first transistor, the second transistor, and the third transistor each include a p-type metal oxide semiconductor transistor.

[0057] Clause 10. The cascode bias circuit according to Clause 7, further including:

[0058] a first resistor coupled to the source of the third transistor.

[0059] Clause 11. The cascode bias circuit according to Clause 10, wherein the cascode current mirror further includes a second resistor coupled to the source of the first diode-connected transistor and includes a third resistor coupled to the source of the current source transistor.

[0060] Clause 12. The cascode bias circuit according to Clause 7, wherein the first current source, the size of the first transistor, the third current source, and the size of the first cascode transistor are all configured such that the current density of the first transistor matches the current density of the first cascode transistor.

[0061] Clause 13. The cascode bias circuit according to Clause 4, wherein the drain-source voltage of the second transistor matches the drain-source voltage of the first diode-connected transistor of the cascode current mirror.

[0062] Clause 14. The cascode bias circuit according to any one of Clauses 1 to 14, wherein the cascode bias circuit is included in a cellular phone.

[0063] Clause 15. The cascode bias circuit according to Clause 7, further including an output circuit coupled to the drain of the second cascode transistor of the cascode current mirror.

[0064] Clause 16. A method for biasing a cascode current mirror, including:

[0065] Driving a first current into a first transistor to generate a gate-source voltage across the first transistor;

[0066] Driving a second current into a second transistor to generate a threshold voltage difference between the gate and the drain of the second transistor;

[0067] Combining the first current and the second current at the drain of the second transistor and the drain of the first transistor to form a combined current;

[0068] Driving the combined current into a third transistor to make the gate voltage of the first transistor equal to the sum of the gate-source voltage of the first transistor and the drain-source voltage of the third transistor; and

[0069] Using the gate voltage of the first transistor to bias the gate of the first cascode transistor in the cascode current mirror.

[0070] Clause 17. The method according to Clause 16, further including:

[0071] Use the gate voltage of the third transistor to bias the gate of the current source transistor in the cascode current mirror so that the third transistor conducts a mirrored version of the combined current.

[0072] Clause 18. The method according to clause 16 further includes:

[0073] Use the gate voltage of the first transistor to bias the gate of the second cascode transistor in the cascode current mirror.

[0074] Clause 19. A cascode current mirror includes:

[0075] A first cascode transistor;

[0076] A current source transistor in series with the first cascode transistor; and

[0077] A cascode biasing circuit including:

[0078] A first transistor configured to conduct a first current to generate a first gate-source voltage, the first transistor having a gate coupled to the gate of the first cascode transistor;

[0079] A second transistor configured to conduct a second current to generate a second gate-source voltage substantially equal to the transistor threshold voltage; and

[0080] A third transistor coupled to the drain of the first transistor and the drain of the second transistor, the third transistor having a gate coupled to the gate of the second transistor.

[0081] Clause 20. The cascode current mirror according to clause 19 further includes:

[0082] A second cascode transistor having a gate coupled to the gate of the first transistor.

[0083] Clause 21. The cascode current mirror according to any one of clauses 19-20, wherein the cascode biasing circuit further includes:

[0084] A first current source configured to supply the first current; and

[0085] A second current source configured to supply the second current.

[0086] Clause 22. The cascode current mirror according to any one of clauses 19-21, wherein the first transistor and the second transistor are each diode-connected.

[0087] Clause 23. The cascode current mirror according to Clause 21 further includes:

[0088] A fourth transistor, the fourth transistor being connected in series with the first cascode transistor and having a gate coupled to the drain of the first cascode transistor; and

[0089] A third current source, the third current source being configured to drive a third current into the drain of the first cascode transistor.

[0090] Clause 24. A cascode current mirror includes:

[0091] A first current source, the first current source being configured to supply a first current;

[0092] A first cascode transistor, the first cascode transistor being configured to conduct the first current;

[0093] A cascode bias circuit, including:

[0094] A second current source, the second current source being configured to supply a second current;

[0095] A first transistor, the first transistor being configured to conduct the second current and having a gate coupled to the gate of the first cascode transistor;

[0096] A second current source, the second current source being configured to supply a third current;

[0097] A second transistor, the second transistor being configured to conduct the second current; and

[0098] A third transistor, the third transistor being coupled to the drain of the first transistor and the drain of the second transistor, the third transistor having a gate coupled to the gate of the second transistor, wherein both the second current and the third current are less than the first current.

[0099] Clause 25. In the cascode current mirror according to Clause 24, wherein the second current and the third current are each half of the first current.

[0100] Clause 26. In the cascode current mirror according to Clause 24, wherein the second current and the third current are each one quarter of the first current.

[0101] It should be understood that many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments shown and described herein, as they are merely by way of some examples, but should be commensurate in scope with the scope of the appended claims and their functional equivalents.

Claims

1. A cascode bias circuit, comprising: a first current source configured to supply a first current; a second current source configured to supply a second current; a first transistor having a drain coupled to the first current source; a second transistor having a source coupled to the source of the first transistor and a drain coupled to the second current source; and a third transistor having a drain coupled to the source of the first transistor and to the source of the second transistor.

2. The cascode bias circuit according to claim 1, wherein the first transistor and the second transistor are each diode-connected.

3. The cascode bias circuit according to claim 1, wherein the gate of the first transistor is coupled to the gate of a first cascode transistor in a cascode current mirror.

4. The cascode bias circuit according to claim 3, wherein the first current is equal to the second current, and wherein the cascode current mirror further includes a first diode-connected transistor arranged in series with the first cascode transistor and in series with a third current source configured to supply a third current that is twice the first current.

5. The cascode bias circuit according to claim 3, wherein the gate of the second transistor is coupled to the gate of the third transistor.

6. The cascode bias circuit according to claim 3, wherein the second transistor is configured to have a gate-source voltage equal to the transistor threshold voltage.

7. The cascode bias circuit according to claim 4, wherein the cascode current mirror further includes: a current source transistor having a gate coupled to the gate of the first diode-connected transistor; and a second cascode transistor arranged in series with the current source transistor and having a gate coupled to the gate of the first transistor.

8. The cascode bias circuit according to claim 1, wherein the first transistor, the second transistor, and the third transistor each include an n-type metal-oxide semiconductor transistor.

9. The cascode bias circuit according to claim 1, wherein the first transistor, the second transistor, and the third transistor each include a p-type metal-oxide semiconductor transistor.

10. The cascode bias circuit according to claim 7, further comprising: a first resistor coupled to the source of the third transistor.

11. The cascode bias circuit according to claim 10, wherein the cascode current mirror further includes a second resistor coupled to the source of the first diode-connected transistor and includes a third resistor coupled to the source of the current source transistor.

12. The cascode bias circuit according to claim 7, wherein The sizes of the first current source, the first transistor, the third current source, and the first cascode transistor are all configured such that the current density of the first transistor matches the current density of the first cascode transistor.

13. The cascode biasing circuit according to claim 4, wherein, the drain-source voltage of the second transistor matches the drain-source voltage of the diode-connected transistor of the cascode current mirror.

14. The cascode biasing circuit according to claim 1, wherein, the cascode biasing circuit is included in a base station.

15. The cascode biasing circuit according to claim 7, further comprising an output circuit coupled to the drain of the second cascode transistor of the cascode current mirror.

16. A method for biasing a cascode current mirror, comprising: driving a first current into a first transistor to generate a gate-source voltage across the first transistor; driving a second current into a second transistor to generate a threshold voltage difference between the gate and the drain of the second transistor; combining the second current at the drain of the second transistor and the first current at the drain of the first transistor to form a combined current; driving the combined current into a third transistor such that the gate voltage of the first transistor is equal to the sum of the gate-source voltage of the first transistor and the drain-source voltage of the third transistor; and biasing the gate of a first cascode transistor in the cascode current mirror using the gate voltage of the first transistor.

17. The method according to claim 16, further comprising: biasing the gate of a current source transistor in the cascode current mirror using the gate voltage of the third transistor such that the third transistor conducts a mirrored version of the combined current.

18. The method according to claim 16, further comprising: biasing the gate of a second cascode transistor in the cascode current mirror using the gate voltage of the first transistor.

19. A cascode current mirror, comprising: a first cascode transistor; a current source transistor in series with the first cascode transistor; and a cascode biasing circuit, comprising: a first transistor configured to conduct a first current to generate a first gate-source voltage, the first transistor having a gate coupled to the gate of the first cascode transistor; a second transistor configured to conduct a second current to generate a second gate-source voltage substantially equal to the transistor threshold voltage; and a third transistor coupled to the drain of the first transistor and the drain of the second transistor, the third transistor having a gate coupled to the gate of the second transistor.

20. The cascode current mirror according to claim 19, further comprising: a second cascode transistor having a gate coupled to the gate of the first transistor.

21. The cascode current mirror according to claim 19, wherein, the cascode biasing circuit further comprises: A first current source configured to supply the first current; and A second current source configured to supply the second current.

22. The cascode current mirror according to claim 19,[[]]END]] wherein,[[]]END]] The first transistor and the second transistor are each diode-connected.

23. The cascode current mirror according to claim 21, further comprising:[[]]END]] A fourth transistor in series with the first cascode transistor and having a gate coupled to the drain of the first cascode transistor; and A third current source configured to drive a third current into the drain of the first cascode transistor.

24. A cascode current mirror,[[]]END]] comprising:[[]]END]] A first current source configured to supply a first current; A first cascode transistor configured to conduct the first current; A cascode biasing circuit comprising:[[]]END]] A second current source configured to supply a second current; A first transistor configured to conduct the second current and having a gate coupled to the gate of the first cascode transistor; A second current source configured to supply a third current; A second transistor configured to conduct the second current; and A third transistor coupled to the drain of the first transistor and the drain of the second transistor, the third transistor having a gate coupled to the gate of the second transistor, wherein both the second current and the third current are less than the first current.

25. The cascode current mirror according to claim 24,[[]]END]] wherein,[[]]END]] The second current and the third current are each half of the first current.

26. The cascode current mirror according to claim 24,[[]]END]] wherein,[[]]END]] The second current and the third current are each one quarter of the first current.

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