Improved channel uniformity for horizontal wrap-around gate devices

Abstract

A method of forming a multilayer semiconductor device on a substrate includes forming a plurality of alternating superlattices of first layers of a first material and second layers of a second material; removing the second layer of the superlattice; etching the first layer of material to form a trimmed first layer therefrom, wherein the amounts of material removed from different ones of the first layers are different amounts; forming a capping layer over the first layer; the distance between the cover layers formed on different ones of the first layers, the thickness of different ones of the cover layers formed on different ones of the trimmed first layers, and the thickness of the different ones of the cover layers formed on the trimmed first layers are measured. And at least one of a different thickness in a combined thickness of a different one of the trimmed first layers and a capping layer formed thereover; and calculating a new thickness of the etched first layer based on the measured difference.

Description

Field of the Invention

[0001] The examples described herein generally relate to the field of semiconductor processing and, more specifically, to integrated semiconductor processing solutions. Background of the Invention

[0002] Reliably generating nano and smaller features is one of the key technology challenges for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. As the limits of circuit technology are pushed, the scaled dimensions of VLSI and ULSI technologies have placed additional requirements on processing capabilities. As the size of integrated circuit components decreases (e.g., to nano dimensions), great care is generally taken in the selection of materials and processes used to fabricate the components in order to obtain a satisfactory level of electrical performance.

[0003] One known device structure is the horizontal surround gate structure, also known as hGGA, where multiple semiconductor channels are under a gate electrode and stacked above one another to extend between a source and a drain of an individual semiconductor device. The semiconductor channel portions are configured by epitaxially forming multiple alternating layers of semiconductor material and sacrificial material to form a superlattice structure and patterning that superlattice structure into multiple superlattice fins or mesa having a width slightly greater than the length of the finished channel. The sacrificial material is removed to leave individual lengths of semiconductor material that will form the individual channels, and these individual lengths or wires of semiconductor material are then trimmed to the desired channel length, which also results in the removal of a portion of each wire on other surfaces. A capping layer (e.g., an additional semiconductor layer) is then formed on each wire, each wire is subsequently coated with a dielectric having a high dielectric constant value, and a work function tuning material is then formed above it. The high dielectric constant value dielectric and the work function tuning material are thus deposited on the surface of each wire facing the underlying substrate, as well as on the surfaces of the wires on the opposite sides of the wires. In the known structure, the first semiconductor layer in the superlattice structure is silicon, e.g., single crystal silicon, which can be a doped single crystal silicon material epitaxially grown on a underlying single crystal substrate or single crystal layer. In this known structure, the sacrificial material is, for example, silicon germanium, which can be epitaxially grown or formed on the underlying silicon crystal structure by a vapor deposition technique. Using silicon and silicon germanium allows the silicon layer of the known structure to be formed as a single crystal layer. The capping layer can be, for example, a silicon germanium layer.

[0004] To provide device-to-device repeatable functional performance, thickness variations of the silicon layer, the silicon germanium layer, and thus the high dielectric constant value dielectric and work function tuning layer material layers formed between adjacent layers of silicon surrounded by silicon germanium should be minimized. However, it has been found that the thicknesses of these layers can vary significantly in the stack of silicon, silicon germanium, high dielectric constant value dielectric, and work function tuning layers. This results in poor performance and repeatability of these structures. Summary of the Invention

[0005] Embodiments of the present disclosure include a method for semiconductor processing. In one aspect thereof, a method of forming a semiconductor device includes:

[0006] forming a first superlattice on a first substrate, the first superlattice including alternating sub-layers of a first material containing a semiconductor and a second material, wherein the thickness of the first material sub-layers is a first thickness and the thickness of the second material sub-layers is a second thickness, wherein at least a first sub-layer of the first material and a second sub-layer of the first material are formed in the first superlattice, and the second sub-layer of the first material is interposed between the first sub-layer of the first material and the substrate;

[0007] removing the sub-layers of the second material from the first superlattice;

[0008] etching the first and second sub-layers of the first material of the first superlattice to remove a portion of the first material therefrom, and forming a first trimmed sub-layer of the first material and a second trimmed sub-layer of the first material, wherein the amount of the first material removed from the first sub-layer of the first material is greater than the amount of the material removed from the second sub-layer of the first material; and

[0009] depositing a covering layer over the first trimmed sub-layer of the first material of the first superlattice, over the second trimmed sub-layer of the first material of the first superlattice, and over the exposed surface of the substrate;

[0010] measuring the distance between the covering layer on the first sub-layer and the covering layer on the second sub-layer, and the distance between the covering layer on the second sub-layer and the covering layer on the substrate, and determining a first difference between those distances;

[0011] forming a second superlattice on a second substrate, the second superlattice including alternating sub-layers of a first material containing a semiconductor and a second material, wherein the thickness of the first material sub-layers is a first thickness and the thickness of the second material sub-layers is a second thickness, wherein at least a first sub-layer of the first material and a second sub-layer of the first material are formed in the second superlattice, and the second sub-layer of the first material is interposed between the first sub-layer of the first material and the second substrate;

[0012] removing the sub-layers of the second material from the second superlattice and the second substrate;

[0013] etching the first and second sub-layers of the first material of the second superlattice to remove a portion of the first material therefrom and forming a first trimmed sub-layer of the first material and a second trimmed sub-layer of the first material, wherein the processing conditions for removing the portions of the first sub-layer of the first material and the second sub-layer of the first material are different from those for removing the portions of the first sub-layer of the first material and the second sub-layer of the first material of the first superlattice; and

[0014] Deposit a capping layer over a first trimmed sublayer of a first material of a second superlattice and over a second trimmed sublayer of the first material of the second superlattice and on an exposed surface of a substrate;

[0015] wherein a difference between a distance between the capping layer on the first sublayer of the first material and the capping layer on the second sublayer of the first material of the second superlattice and a distance between the capping layer on the second sublayer of the first material of the second superlattice and the capping layer on a second substrate is less than a first difference.

[0016] In another aspect thereof, a method of forming a semiconductor device on a substrate includes:

[0017] Form a superlattice on the substrate, the superlattice including alternating sublayers of a first material including a semiconductor and a second material, wherein at least a first sublayer of the first material layer and a second sublayer of the first material have different thicknesses, and the second sublayer of the first material is interposed between the first sublayer of the first material and the substrate;

[0018] Remove the second material sublayers from the superlattice;

[0019] Etch the first sublayer of the first material and the second sublayer of the first material such that a different amount of the first material is removed from the first sublayer of the first material compared to an amount of material removed from the second sublayer of the first material; and

[0020] Deposit a capping layer over the etched first sublayer of the first material and over the etched second sublayer of the first material, wherein a thickness of the capping layer deposited on the first sublayer of the first material is different from a thickness of the capping layer deposited on the second sublayer of the first material.

[0021] In another aspect, a method of forming a multi-layer semiconductor device includes:

[0022] Provide a first substrate;

[0023] Form a superlattice on the first substrate, the superlattice including a plurality of alternating first layers composed of a first material and second layers formed of a second material;

[0024] Selectively remove the second layers of the superlattice;

[0025] Expose the first layers of the superlattice to an etchant using first processing conditions and remove a portion of the first material therefrom to form trimmed first layers, wherein different amounts of material are removed from different first layers in the first layer;

[0026] Form a capping layer over the first layers in the superlattice stack;

[0027] Measure at least one of the distances between the capping layers formed on different first layers in the first layer, the thicknesses of different capping layers among the capping layers formed on different trimmed first layers in the trimmed first layer, and the different thicknesses of the combined thicknesses of different first layers in the trimmed first layer and the capping layers formed thereabove; and

[0028] Calculate the new thickness of the trimmed first layer based on the difference between at least one of the distances between the capping layers formed on different first layers in the first layer, the thicknesses of different capping layers among the capping layers formed on different trimmed first layers in the trimmed first layer, and the different thicknesses of the combined thicknesses of different first layers in the trimmed first layer and the capping layers formed thereabove. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] For a more particular description of the manner in which the above-recited features of the present disclosure can be understood, reference may be made to the examples, some of which are illustrated in the accompanying drawings. It will be noted, however, that the drawings illustrate only some examples and are not to be considered limiting of the scope of the present disclosure, as the present disclosure may admit other equally effective examples.

[0030] Figure 1 is a partial cross-sectional view of a horizontal surround gate structure.

[0031] FIGS. 2A to 2D are schematic cross-sectional views showing the effects of certain actions during the processing of a horizontal surround gate structure.

[0032] FIGS. 3A to 3D are schematic cross-sectional views showing the effects of a first alternative series of actions during the processing of a horizontal surround gate structure.

[0033] FIGS. 4A to 4D are schematic cross-sectional views showing the effects of a first alternative series of actions during the processing of a horizontal surround gate structure.

[0034] Figure 5 is a schematic top view of an example of an exemplary multi-chamber processing system in accordance with some examples of the present disclosure.

[0035] Figure 6 is a cross-sectional view of a processing chamber that can be used to perform a cleaning process in accordance with some examples of the present disclosure.

[0036] Figure 7 is a cross-sectional view of a processing chamber that can be used to perform a selective etching process and a trimming process in accordance with some examples of the present disclosure.

[0037] Figure 8 is a cross-sectional view of a heat treatment chamber that can be used to perform epitaxial growth in accordance with some examples of the present disclosure.

[0038] For ease of understanding, like reference numerals have been used, where possible, to identify like elements common to the figures. Detailed Description

[0039] Generally, the examples described herein relate to semiconductor device structures, methods of forming semiconductor structures, and semiconductor processing systems for forming individual semiconductor layers in a superlattice, isolating individual semiconductor structures in the superlattice from one another using gaps therebetween, and forming a capping layer over a trim layer. In one aspect, the difference in spacing between isolated semiconductor structures is reduced. In one aspect, the individual semiconductor layers (as intermediate structures in the fabrication of a device) separated from one another by gaps are single-crystalline silicon layers. Additionally, the capping layer may be provided as a silicon-germanium layer epitaxially grown or formed over the individual single-crystalline silicon layers. For example, such a reduction in the variation of the spacing or gap between individual trim semiconductor layers may be provided by initially forming different layers in the stack to have different thicknesses such that the material removal rate and the variation in the material removed from different layers in the stack during trimming result in a more uniform trim thickness of the semiconductor layers. In another aspect, process parameter variations in the trimming process are used to result in a more uniform trim thickness of the semiconductor layers. The structures formed by such processing may be implemented in, for example, a horizontal gate-all-around field-effect transistor (hGAA μmFET). The methods and semiconductor processing systems may provide an integrated solution to trim the layer to be trimmed and then epitaxially grow a capping layer over the trimmed layer.

[0040] Initially referring Figure 1 , a partial cross-sectional view of a horizontal gate-all-around structure or HGAA formed on a substrate 2 is shown. Only one side of the HGAA is shown, and those skilled in the art will recognize that the device includes structures including a source or drain on a side opposite the shown source or drain 60.

[0041] Here, a plurality of “wires” formed of semiconductor (e.g., epitaxially grown or deposited single-crystalline silicon) extend laterally or horizontally from the source or drain 60 to the other of the source or drain (not shown) on the right side of the figure. Each of the wires is formed as a trimmed wire preform 52’ to 56’ as will be described herein. Each wire (here the trimmed wire preforms 52’ to 56’) is covered by a surrounding capping layer 24. The capping layer preferably grows epitaxially over and around the trimmed wire preforms 52’ to 56’ and also grows above the upper surface of the substrate 2. For example, the capping layer is silicon-germanium. Additional gate functional layers are grown or deposited over the capping layer 24, and a gate 62 is formed thereabove. Additional intermediate layers (such as barrier layers, high-k dielectric layers, and work function tuning layers), or other layers may be integrated into Figure 1 the stack of layers shown. Thus, Figure 1The structure is provided as an example of an HGAA structure and does not limit such a structure.

[0042] FIGS. 2A-2D are Figure 1 cross-sectional views of a portion of the HGGA structure, showing the results of process operations for forming the trimmed wire preforms 52', 54', 56', and the overcoat 24 for the HGAA structure. Referring to FIGS. 2A-2D, the results of performing an operation sequence of separating individual semiconductor layers of the wire stack from the superlattice, trimming the individual semiconductor layers isolated from the superlattice, and forming an overcoat (e.g., a secondary semiconductor layer) over the trimmed semiconductor layers are shown in sequence. Here, the superlattice is formed by sequentially growing a plurality of alternating layers of sacrificial material (such as silicon germanium layers 6) and semiconductor layers (such as silicon layers 8) over a substrate 2. A first sacrificial layer is epitaxially grown on the substrate 2, a first semiconductor layer is epitaxially grown on the first sacrificial layer, and subsequent sacrificial and semiconductor layers are epitaxially grown thereover in an alternating manner.

[0043] In FIG. 2A, the superlattice that divides fins or mesa 10 over the substrate includes semiconductor layers that are doped single-crystalline silicon and sacrificial layers that are silicon germanium. The thickness of each of the semiconductor layers is within deposition tolerances and is formed to be the same for each of the semiconductor layers. In FIG. 2A, the thickness of each sacrificial layer is within deposition tolerances and is formed to have the same thickness for each of the sacrificial layers. The thicknesses of the semiconductor and sacrificial layers can be the same or different.

[0044] Initially, the left-hand side of FIGS. 2-4 (here FIGS. 2A, 3A, and 4A) depicts a cross-sectional view of a single superlattice fin or mesa 10 of a plurality of fins or mesa defined by a superlattice stack by a reactive ion etching process. It will be understood that one or more such fins or mesa 10 (extending inwardly and outwardly from Figures 5 to 7 the plane of) can be aligned with their sidewalls facing each other over the width of trench 11, which is etched inwardly from the superlattice in the Y direction and has a trench width in the X direction of FIGS. 2A-4A. For ease of illustration, only one fin or mesa 10 is shown in FIGS. 2A-4A. Trench 11 defines or divides fins or mesa 10 having alternating silicon germanium layers 6 and silicon layers 8 from a superlattice (not shown) of silicon layers 8 and silicon germanium layers 6. This same etching step can be used to etch trench 11 inwardly from the underlying single-crystalline silicon substrate 2 to define isolated linear segments or mesa of the semiconductor substrate 2 (extending inwardly and outwardly from the plane of FIGS. 2A-4A) beneath each of the fins or mesa 10. Here, in Figure 5In the y-direction in the superlattice and thus in the fin or mesa 10, the initial thicknesses t1a, t1b, and t1c of the silicon layers are equal to each other within their deposition tolerance or deposition ability. In other words, in the original superlattice, the thicknesses t1a, t1b, and t1c of the silicon layer 8 are related such that t1a = t1b = t1c. Similarly, in the Y-direction of FIG. 2a and thus in the fin or mesa 10, the thicknesses s1a, s1b, and s1c of the sacrificial silicon germanium layer are equal to each other within their deposition tolerance or deposition ability. In other words, in the original superlattice, the thicknesses s1a, s1b, and s1c of the sacrificial silicon germanium layer 6, and thus the spacing between the individual silicon layer 8 and the lowermost silicon layer 8 and the substrate, are related such that s1a = s1b = s1c.

[0045] After the fin or mesa 10 is defined by a superlattice of alternating silicon germanium and silicon layers 6, 8, a portion of the isolated sacrificial silicon germanium layer 6 is removed from the stack or fin 10 using a selective removal process, the result being shown in FIG. 2b. The silicon germanium layer 6 is selectively removed by a selective etching process (e.g., a selective isotropic etching process) using an etching gas composed of, for example, NF 3 which dissociates in a remote plasma source into F radicals and F 2 and then flows over the substrate 2 to penetrate the trenches and contact and selectively remove the silicon germanium of the silicon germanium layer 6. This leaves separate, now segmented portions of the silicon layer 8 in each fin or mesa 10, here three wire preforms 52, 54, and 56 composed of silicon, the wire preforms being spaced apart and isolated from each other in the Y-direction of FIG. 2b by the thickness of each removed silicon germanium sacrificial layer 6 (here s1a and s1b), which thicknesses are equal or substantially equal. In other words, the spacing between the individual wire preforms 52, 54, and 56 is equal to the original thickness of the removed silicon germanium layer. The third wire preform 56 of the isolated mesa closest to the substrate 2 is similarly spaced from the upper surface facing the substrate 2 by the thickness s1c of the removed sacrificial silicon germanium layer 6. Thus, the spacing in the Y-direction between the facing surface of the semiconductor substrate 2 and the third wire preform 56, between the second and third wire preforms 54, 56, and between the first and second wire preforms 52, 54 is a substantially equal distance or span, substantially equal to the thicknesses s1a, s1b, and s1c of the silicon germanium layer 6 that previously extended therebetween, and s1a = s1b = s1c.

[0046] After the separate first to third wiring preforms 52, 54, and 56 are isolated from the silicon layer 8 of the superlattice, they are trimmed, in other words, their size is reduced. The trimming is performed using an etching process, such as a remote plasma etching process, where the reactive etching gas is at least partially ionized in a plasma located remotely from the substrate, and the radicals of the etching reaction gas are directed or flow towards the substrate to etch the silicon on the first to third wiring preforms 52 to 56, resulting in first to third trimmed wiring preforms 52', 54', and 56' that are smaller in thickness in the Y direction and smaller in width in the X direction in Figure 2c compared to the first to third wiring preforms 52 - 56 shown in Figure 2b. Here, the original size of each of the first to third wiring preforms 52 - 56 is shown in Figure 2c by a dashed outline around its corresponding trimmed state.

[0047] Trimming the first to third wiring preforms 52 - 56 can be performed using Figure 7 the processing chamber 120 shown in. The trimming process includes flowing a first etching gas from a gas source 316 at a flow rate 318, where the first etching gas can include one or more of nitrogen trifluoride (NF 3 ), a mixture of nitrogen trifluoride (NF 3 ) and helium (He), or the like, and flowing a second etching gas from a gas source 338 at a flow rate 340, where the second etching gas can include one or more of nitrogen trifluoride (NF 3 ). The mixture of nitrogen trifluoride (NF 3 ) and helium (He) can be in a ratio in the range from 1:350 (NF3:He) to 1:120 (NF3:He), and the mixture can flow from the gas source 316 at a flow rate in the range from 5000 sccm to 7000 sccm, such as at a flow rate of nitrogen trifluoride (NF3) in the range from 10 sccm to 25 sccm, and at a flow rate of helium (He) in the range from about 3000 sccm to 3500 sccm. The pressure in the chamber 120 can be maintained in the range from 0.25 Torr to about 2 Torr. At a frequency from about 10 MHz to about 50 MHz (e.g., 13.56 MHz), the power applied by the RF power supply 320 can be in the range from about 10 W to about 50 W. This can be performed in an etching chamber available from Applied Materials, Inc. of Santa Clara, California, where the gas is excited to plasma in the lid assembly 304 and then the excited NF3 and H2 gases are flowed onto the substrate.

[0048] Here, this trimming process results in the thickness t1a' of the first trimmed lead preform 52' being slightly less than the thickness t1b' of the second trimmed lead preform 54', which is slightly less than the thickness t1c' of the trimmed lead preform 56'. In other words, the trimmed lead preform thicknesses t1a', t1b', and t1c' have the relationship t1c' > t1b' > t1a'. It is believed that this thickness difference (where the lead preforms 52, 54, and 56 have the same initial thickness t1a = t1b = t1c) is due to the depletion of the etchant chemical in the depth or Y direction of the trenches 11 between adjacent fins or pads 10 during the trimming process. In other words, the relative availability of the etchant at the first lead preform 52, which is furthest from the underlying substrate 2, is greater compared to the etchant available at the second lead preform 54, as a portion of it is consumed in the etch-based trimming of the first lead preform 52. Similarly, it is believed that the relative availability of the etchant and thus the deepest trench in the trench 11 is smaller at the third lead preform 56, which is closest to the substrate 2, compared to the second lead preform 54, as a portion of it is consumed in the etch-based trimming of the first and second lead preforms 52, 54.

[0049] After the trimmed post-wiring preforms 52', 54' and 56' are prepared, the structure of the final wiring 58 is completed by depositing an additional second semiconductor layer thereon (here, the capping layer 24 of silicon germanium as previously described herein). The resulting structure of the final wiring 58 thus includes three separate wirings 58, here the first to third final wirings 58a, 58b and 58c composed of the corresponding silicon trimmed post-wiring preforms 52' to 56' and the deposited capping layer 24 of silicon germanium. The first to third final wirings 58a, 58b and 58c are spaced apart from each other and are spaced from the underlying semiconductor substrate 2 by the spacing distances s1a' to s1c'. Here, the thickness d1 of the capping layer 24 deposited on the first trimmed post-wiring preform 52' in the Y direction of FIG. 2d is thicker than the thickness d2 of the capping layer 24 grown on the second trimmed post-wiring preform 54' in the Y direction of FIG. 2d. Similarly, the thickness d3 of the capping layer 24 on the third trimmed post-wiring preform 56' in the Y direction of FIG. 2d is thinner compared to the capping layer 24 grown on the first and second trimmed post-wiring preforms 52, 54. In other words, the relationship of the thicknesses d1, d2 and d3 of the capping layer 24 is d1>d2>d3. Due to this and the different thicknesses of the trimmed post-wiring preforms 52', 54' and 56', the thicknesses T1 to T3 of the final wirings 58a, 58b and 58c are different in the Y direction of FIG. 2d, and the spacings s1a' to s1c’ in the Y direction between the first to third final wirings 58a to 58c and between the third final wiring 58c and the facing surface of the capping layer 24 on the substrate 2 are different. Here, the spacing s1a' between the facing surfaces of the first and second final wirings 58a, b is less than the spacing s1b' between the facing surfaces of the second and third final wirings 58b, c. The spacing s1c' between the facing surface of the third final wiring 58c and the facing surface of the capping layer on the substrate 2 is greater than the spacing s1b'. In other words, s1c'>s1b'>s1a'. Therefore, the thicknesses of the high-k dielectric layer and the work function tuning layer subsequently formed to fill the spaces between the adjacent first and third final wirings 58a-58c and between the third final wiring 58c and the facing surface of the capping layer 24 on the substrate 2 will vary relative to each other, and the electrical performance of each of the first to third wirings 58a to 58c operating as channels will be different. In addition, the space between two adjacent wirings among the first to third final wirings 58a to 58c may become too small to accommodate the thickness of the high-k dielectric layer, the work function tuning layer or both, which is required to achieve the desired performance of one or more of the first to third final wirings 58a to 58c as functional channels.

[0050] The present disclosure provides mechanisms and processes for overcoming these variations in layer thickness and spacing to produce a more repeatable and uniform spacing between the final interconnects, and a more uniform thickness of the final interconnects. Here, this is provided at least in part by tuning the thicknesses of the individual first through third trimmed interconnect preforms 52' to 56', and ensuring that a minimum desired spacing is maintained between the first through third final interconnects 58a to 58c after the formation of the overcoat layer. Specifically, the thickness of the silicon layer 6 in the superlattice, or the trimming process of the first through third trimmed interconnect preforms 52' to 56', or both, are adjusted or modified to produce a resulting stack of the first through third final interconnects 58a to 58c that are spaced apart from one another in the Y-direction (with a more uniform space or distance therebetween in the Y-direction), and a more uniform thickness of the final interconnects 58a to 58c.

[0051] Referring to FIGS. 3a through 3d, there are schematically shown the results of a sequence of processing actions for reducing the thickness variations between the first through third final interconnects 58a to 58c and thus reducing the variations in the spacings s1a' and s1b' between the first through third final interconnects 58a - c and the spacing s1c' between the third final interconnect 58c closest to the substrate 2 and the facing surface of the overcoat layer 24 on the substrate 2. In the process for forming the first through third final interconnects 58a - 58c of FIGS. 2a through 2d, variations in the thicknesses of the overcoat layer 24 and the trimmed interconnect preforms result in a thickness difference in the first through third final interconnects 58a to 58c in the Y-direction. Here, to compensate for this variation between adjacent completed interconnects 58a to 58c and between the third completed interconnect 58c and the surface of the overcoat layer 24 on the substrate 2, the relative thicknesses of the individual silicon-germanium layer 6 and silicon layer 8 in the superlattice stack are changed compared to those in FIG. 2a. Here, in the trimmed interconnect preform where the overcoat layer is inherently deposited to a thinner thickness compared to the other trimmed interconnect preforms, the thickness of the silicon layer 8 in the superlattice is increased relative to the other silicon layers 8 in the superlattice and is greater than its thickness in FIG. 2a. In the trimmed interconnect preform where the overcoat layer 24 is deposited to a greater thickness compared to the other trimmed interconnect preforms, the silicon layer 8 is formed to be thinner relative to the other silicon layers 8 in the superlattice and thinner compared to its thickness in FIG. 2a.

[0052] To meet the same design constraints desired for the partial HGAA structure in FIGS. 2a - 2d, the total thickness of the superlattice composed of the stack of the silicon germanium layer 6 and the silicon layer 8 should remain the same as in FIG. 2a within design and deposition tolerances. Similarly, the centerlines (not shown) of the first to third final interconnects 58a - 58c in the X - direction should preferably be located at the same distance from the upper surface of the substrate in the Y - direction, as the final interconnects are generally in FIG. 2a. Due to these constraints, if the thickness of one of the three sets of layers of the silicon layer and the silicon germanium layers 8, 6 is changed, the thickness of the other of the silicon layer and the silicon germanium layers 8, 6 must also be changed, but in the opposite manner. The desired end result is to provide a plurality of final interconnects 58 that are spaced apart from each other and from the surface of the overlying layer 24 on the substrate 2 by the same or nearly the same distance, and the final interconnect thickness is more uniform compared to those in FIG. 2d.

[0053] Here, as described herein, the thickness of the silicon layer 8 is selected such that the thickness of the final wiring 58a - 58c is relatively equal, and the thickness of the silicon germanium layer 6 is selected to result in relatively equal spacing between the final wirings 58a - 58c and between the final wiring 58c and the facing surface of the overcoat 24 on the substrate 2. Thus, different silicon layers 8 can have different thicknesses in the superlattice, and different silicon germanium layers 6 can have different thicknesses, as shown in FIG. 3a. Subsequently, the silicon germanium layer 6 is selectively removed in the same manner as described herein with respect to FIGS. 2a - 2d, resulting in the outcome shown in FIG. 3b. Here, the spacing between the individual wiring preforms 52 - 56 has the thickness of the removed silicon germanium layer 6. It is noted here that these spacings are not equal to each other. In addition, contrary to those shown in FIG. 2c (which are equal to each other), the thicknesses of the wiring preforms 52 - 56 are different from each other. Subsequently, the wiring preforms 52 - 56 are isotropically etched in the same manner as described herein with respect to FIGS. 2a - 2d, and the trimmed wiring preforms 52' to 56' have different thicknesses from each other, with the result shown in FIG. 3c. Subsequently, the overcoat 24 is formed using the same epitaxial deposition process as used to form the overcoat 24 of different thicknesses shown in FIG. 2d, and each of the exposed surfaces of the trimmed wiring preforms 52' - 56' and the substrate 2 is now covered with the overcoat 24. Using the same processing conditions as used to form the overcoat 24 of FIG. 2d, the non-uniformity of the thickness of the overcoat 24 formed on the different trimmed wiring preforms 52', 56' in FIG. 3d is the same or nearly the same as in FIG. 2d. Because the thicknesses of the trimmed wiring preforms 52' - 56' have been modified compared to those in FIGS. 2c and 2d, the resulting final wiring thicknesses 58a - 58c are the same or substantially the same, and the spacing between the final wirings 58a - 58c and between the final wiring 58c and the facing surface of the overcoat 24 on the substrate 2 is the same or substantially the same. Depending on the application requirements of the HGAA, within the design tolerances, the wiring thickness, the spacing, or the difference between the two is substantially the same.

[0054] To achieve the resulting structures shown in FIGS. 3a - 3d, a first - order assumption is made that the chemical depletion effects that result in the thickness differences of the trimmed wiring preforms 52' - 56' as shown in FIG. 2c and the deposition thickness differences of the overcoat 24 on the trimmed wiring preforms 52' - 56' as shown in FIG. 2d will not change significantly, even though the initial thickness of the silicon layers 8 in the superlattice is changed compared to those shown in FIG. 2a. Additionally, based on the design specifications of the HGAA device, the minimum spacing between the final wirings 58 - 58c is known. Thus, the thickness of the silicon layers 8 can be modified to result in final wirings 58a - 58c having the same or substantially the same thickness after processing to trim the silicon and form the overcoat 24 thereon. Similarly, the thickness of the silicon - germanium layers is modified due to the change in the silicon layer thickness, and a uniform or substantially uniform spacing is created between adjacent final wirings 58a - 58c and between the final wiring 58c and the facing surface of the overcoat 24 on the substrate 2. By measuring the thicknesses of the different wirings in the final wirings 58a - 58d in FIG. 2d and the overcoat 24 on each of those final wirings 58a - 58c, the change in the thickness of the silicon layer 8 that will result in a uniform or more uniform thickness of the final wirings 58a - 58c is determined. This assumption is that a change in the thickness of any one of the silicon layers 8 in the Y - direction in the superlattice results in an equal change in the thickness in the Y - direction on the trimmed wiring preforms 52' - 56', and using the same trimming and overcoat deposition processing conditions will result in trimming and overcoat characteristics similar to those shown in FIGS. 2c and 2d. Subsequently, based on the assumed thicknesses of the trimmed wiring preforms 52' - 56' and the overcoat 24 thereon and the overcoat on the etched or trimmed surface of the substrate 2, the relative position of each of the silicon layers 8 with respect to the upper surface of the substrate 2 can be determined to produce the final wirings 58a - 58c and an equal spacing between the final wiring 58c and the facing surface of the overcoat 24 on the substrate 2. In this determination, it is assumed that the thickness of the overcoat 24 formed on the trimmed wiring preforms 52 - 56' and on the upper surface of the substrate 2 will not change significantly compared to the results in FIG. 2d. Thus, the desired final thickness of each of the final wirings 58a - 58c can be selected, and similarly, the spacing between the wiring preforms 52 - 56 can be selected. Subsequently, the thickness of the trimmed wiring preforms required in each of the final wirings 58a - 58c is determined arithmetically based on the assumed thickness of the overcoat 24 thereon. Subsequently, the difference between this desired thickness and the actual thickness of the trimmed wiring preforms 52' - 56' is determined. If the thickness of the trimmed wiring preforms 52' - 56' is less than the new desired thickness, the difference between this actual thickness and the desired thickness in FIG. 2d is added to the thickness of the silicon layer 8 in the superlattice from which the discussed trimmed wiring preforms are formed.Similarly, if the desired thickness is less than the thickness of the trimmed wire preforms 52'-56' of FIG. 2d, the thickness of the silicon layer 8 in the superlattice is reduced. Subsequently, the thickness of the silicon-germanium layer 6 in the superlattice required to result in a uniform spacing between the final wires 58a-58c and between the final wire 58c and the overlying layer on the substrate 2 is determined.

[0055] To determine the thicknesses of the different silicon-germanium layers 6 in the superlattice, the center position in the Y direction of each of the modified trimmed wire preforms 52' to 56' in the equally spaced final wires 58a-58c as shown in FIG. 3d can be used as the center in the Y direction of the silicon layer 8 of the corresponding superlattice. Subsequently, based on the new thickness of the silicon layer 8 of the modified thickness of FIG. 3c and the center of each of them in the Y direction, the thicknesses required to correctly position the silicon-germanium layer 6 relative to the substrate can be calculated, and these thicknesses of the silicon-germanium layer 6 are used to form the superlattice. Further, when determining the positions of the trimmed wire preforms 52'-56' to result in an equal spacing of the final wires 58a to 58c, it is assumed that the amount of silicon removed from the wire preforms 52-56 is substantially the same as the amount of silicon removed in the examples of FIGS. 2a to 2d, and the thickness of the overlying layer 24 on the different trimmed wire preforms 52'-56' will be the same as in the examples of FIGS. 2a to 2d. Here, within the design tolerances, the thicknesses of the superlattices of the fins or mesa 10 of FIGS. 2a and 3 are the same.

[0056] In one aspect, to determine the desired thickness of the silicon layer 8 of the modified thickness of FIG. 3a, the average value of the thicknesses T1 to T3 of the first to third final wires 58a to 58c of FIG. 2a can be calculated. The thickness of the silicon layer 8 in the superlattice can then be modified using this information. Thus, the silicon layer 8 corresponding to a thickness thicker than the average thickness of the final wires 58a-58c of FIG. 2d becomes smaller, and the silicon layer 8 corresponding to a thickness thinner than the average thickness of the final wires 58a-58c of FIG. 2d becomes thinner. Alternatively, the average value of the thicknesses or other criteria can be used to adjust the magnitude of the thickness of the silicon layer 8 in the superlattice of equal thicknesses of FIG. 2d. In the case of using the average value of the thicknesses T1 to T3, the silicon layer 8 corresponding to the final wire thicker than the average value of the thicknesses T1 to T3 in FIG. 2b is modified such that those corresponding final wires 58 having a thickness greater than the average value will be modified to be thinner than those corresponding final wires 58 having a thickness less than the average value. Using this method, the minimum design thickness of the trimmed wire preforms 52'-56' must be considered.

[0057] Integrate two different variations in thickness into a mean or average using the mean or average of the thicknesses of the first through third final leads 58a to 58c: the variations in the thicknesses t2a' to t2c' of the first through third trimmed lead preforms 52, 54, and 56 and the variations in the thicknesses d1 to d3 of the second silicon germanium layer 24. An additional example for varying the dimensions of the silicon layers 8 in the superlattice is to determine only the average or mean of the thicknesses d1 to d3 of only the second silicon germanium layer 24 of FIG. 2d. The difference between these average (or mean) thicknesses is used to modify the thickness of the silicon layer 8 of the superlattice corresponding to a particular lead in the first through third final leads 58.

[0058] The differences in the spacings s1a', s1b', and s1c' of the resulting structure of FIG. 2d can also be used to determine the amount of change in the thickness of the superlattice or the silicon layer 8 in the superlattice. The difference in the spacings reflects the inverse of the change in the thickness of the first through third final leads 58a to 58c and can thus be used in the same manner as the difference in the thicknesses of the first through third final leads 58a to 58c to determine the change in the silicon layer thicknesses from those in FIG. 2a to those in FIG. 3a.

[0059] Since the uppermost silicon layer 8 in the fin or mesa 10 of FIG. 2a results in the first final lead 58a having the greatest thickness, the magnitude of the thickness t2a of the uppermost silicon layer in FIG. 3a is reduced compared to the silicon layer 8 in FIG. 2a using one of the variation examples discussed herein. The thickness t2b of the middle silicon layer 8 in the fin or mesa 10 of FIG. 3a (which results in the second final lead 58b having the middle thickness among the three first through third final leads 58a to 58c of FIG. 2d) can be varied based on one of the examples discussed herein. Here, the thickness t1b is approximately the same as the thickness of the corresponding silicon layer 8 in FIG. 2a. The lowermost silicon layer of the fin or mesa 10 in FIG. 3a (which results in the third final lead 58c having the smallest thickness among the first through third final leads 58a to 58c) is increased compared to the corresponding silicon layer 8 in FIG. 2a, for example using the examples described herein. Thus, when comparing the thicknesses of the silicon layers 8 in FIGS. 2a and 3a, t1a > t2a, t1b = t2b, and t1c < t2c, and t2c > t2b > t2a. Here, preferably the same variation example is used to set the thicknesses of all the silicon layers 8 in the superlattice, where a greater or lesser number of silicon layers 8 are provided. Using the known change in the thickness of the silicon layers 8 in the stack, the corresponding change in the thickness of the silicon germanium layer 6 is determined. The difference in the thickness of the silicon germanium layer can be determined by taking one-half of the change in the thickness of the silicon germanium layer and the change of each of its adjacent silicon layers.

[0060] In addition, to achieve greater uniformity in the final contact 58 pitch and final contact 58 thickness, the relative sizes of the silicon layers in the superlattice can be simply increased or decreased based on the resulting dimensions of the structure of FIG. 2d. By using the same device structure, but varying the thicknesses of the initial silicon layer 8 and the silicon germanium layer 6, removing the silicon germanium layer, trimming the silicon layer 8, and subsequently forming a silicon germanium overlay on the trimmed silicon layer 8, the resulting uniformity or non-uniformity can be determined, such as by measuring using TEM or SEM to image the cross-sectional structure as shown in FIGS. 2d or 3d. Subsequently, if the uniformity is acceptable, the silicon layer 8 and the silicon germanium layer 6 of the new thicknesses are used to form the HGAA device. If the non-uniformity in the final contact 58 pitch, the final contact 58 thickness, or both, is insufficient, a new size can be selected for the silicon layer 8 and the silicon germanium layer 6 can be selected, and the superlattice can be processed again as shown in FIGS. 3a to 3d, and the thickness and pitch of the final contact 58 are evaluated again. If necessary, using multiple iterations of the relative thicknesses of the silicon and silicon germanium layers, the final thickness of the silicon layer 8 can be determined and, thus, the final thickness of the silicon germanium layer 6 can be determined.

[0061] As described with respect to FIG. 2a, the thickness of the epitaxially grown silicon-germanium overlay 24 is inherently thinner (and thus deeper in the trench 11) above the trimmed wire preform 56c' closest to the substrate 2 than that formed on the first trimmed wire preform 52' furthest from the substrate 2. Thus, the third silicon layer 8 closest to the substrate 2 here is thicker than the trimmed first silicon layer 8 furthest from the substrate 2 after etching to trim that silicon layer 8. Using the measured thicknesses of the first through third trimmed wire preforms 52' to 56' of FIG. 2d and the second silicon-germanium layer 24, and determining the difference between the measured thickness of the final wire 58 in the Y direction and the desired thickness, the thickness change (if any) of each of the resulting silicon layers 8 is determined. For example, if the spacing between any of the first through third final wires 58a to 58c or the third final wire 58c and the substrate 2 is too small, the thickness of the first silicon-germanium layer therebetween can be increased, and the thickness of one or both of the adjacent silicon layers 8 can be decreased. Further, in order to form final wires 58 of equal thickness above the substrate 2, the thickness of the silicon layer can be increased where the thickness of the final wire formed therefrom is smaller compared to the final wires 58 formed from the other silicon layers 8. Here, for example, assuming that the thickness of the silicon-germanium layer will change substantially the same in the depth direction of the trench between adjacent fins 10 (as they change in FIG. 2d) when deposited on silicon layers of different thicknesses, the increase in the thickness of the lower (closer to the substrate 2) silicon layer 8 can be calculated. Thus, an estimate of the desired thickness of each of the silicon layers 8 of the superlattice and the corresponding silicon-germanium layers therebetween (and between the silicon layer closest to the substrate 2 and the facing surface of the substrate 2) is calculated. A superlattice is formed having silicon-germanium layers 6 and silicon layers 8 of these different thicknesses in the depth direction of the superlattice (the silicon layer 8 furthest from the substrate 2 being thinner while the silicon layer closer to the substrate 2 is thicker). In order to maintain the desired position of the surface of the superlattice furthest from the substrate 2 relative to the facing surface of the substrate, the thickness of the silicon-germanium layer will also change in the depth direction of the trench 11 (i.e., the superlattice), with the thicker silicon-germanium layers 6 being further from the substrate 2 and the thinner silicon-germanium layers being closer to the substrate 2. As a result of this construction, after selectively removing the silicon-germanium layer 6, trimming the resulting first through third wire preforms 52-56, and depositing the second silicon-germanium layer as the overlay 24 onto the first through third trimmed wire preforms 52'-56', the spacings s2a', s2b' between adjacent completed wires 58a and 58b and the spacing between the third completed wire 58c and the facing surface of the substrate 2 are more uniform as shown in FIG. 3d compared to FIG. 2d.

[0062] If the final uniformity of the spacings s2a', s2b' between adjacent completed wirings 58a and 58b and the spacing s2c' between the third completed wiring 58c and the facing surface of the overcoat 24 on the substrate 2 is not sufficiently uniform, perform the process of measuring the resulting dimensions of the new or freshly formed group of the first to third final wirings 58a, 58b, and 58c of the new or freshly formed structure, and determining the new thickness of the silicon layer in the superlattice stack to provide a more uniform thickness of the completed wirings 58a to 58c, as well as the spacings s2a', s2b', and s2c'. Thus, for a given horizontal surround gate structure, the thicknesses of the silicon layer 8 and the first silicon germanium layer 6 (which will result in uniform spacings of the spacings s2a', s2b', and s2c' and a more uniform thickness of the completed wirings 58a to 58c) can be determined iteratively and implemented in the intermediate preform of the HGAA device.

[0063] Referring now to FIGS. 4a through 4d, another approach for reducing the variation in the spacing between adjacent finished wiring 58a - 58c and between the finished wiring 58c and the substrate 2 in a horizontal wrap-around gate structure is schematically shown. Here, the individual silicon germanium layer 6 and silicon layer 8 are grown or formed to the same thickness as in FIG. 2a, i.e., t2a = t2b = t2c, but the nature of the trimming process is changed to modify the thickness variation of the first through third trimmed wiring preforms 52' - 56' in the depth direction of the trench 11. For example, compared to the pressure in the processing chamber where the remote plasma etching process is being performed that resulted in the first through third trimmed wiring preforms 52 through 56 of FIG. 2c, with the relative concentration of the gases used in the trimming process not changed, the amount of the first trimmed wiring preform 52' that is farthest from the substrate 2 and is etched away is greater than the amount removed from the second trimmed wiring preform 54', and the amount itself is greater than the amount of material removed or etched from the third trimmed wiring preform 56' that is closest to the substrate 2. Here, the processing time for forming the trim can be extended compared to the processing time used to form the trimmed wiring preforms 52' - 56' of FIG. 2c. Thus, with a cover layer 24 of the same thickness as in FIG. 2d deposited thereon, the spacings s1 - s3 between the first through third final wiring 58a through 58c and between the lowermost third final wiring 58c and the facing surface of the cover layer 24 on the substrate 2 are more uniform, even though the silicon layer 8 and thus the first through third wiring preforms 52 - 56 all have the same thickness and are spaced from each other within deposition and design tolerances. Here, by adjusting the deposition parameters as described, the thickness t2a' of the first trimmed wiring preform 52' is less than the thickness t2b' of the second trimmed wiring preform 54'. Similarly, the thickness t2b' of the second trimmed wiring preform 54' is less than the thickness t2c' of the third trimmed wiring preform 56'. In other words, by changing the processing parameters used to trim the silicon layer 8 and using the same silicon layer and silicon germanium layer 6 thickness as used in the superlattice of FIG. 2a, different thicknesses of the silicon layer 8 can be achieved after trimming compared to those in FIG. 2c. Here, by adjusting those parameters, the thicknesses of the trimmed wiring preforms follow the paradigm of t2c' > t2b' > t2a'. By depositing a cover layer 24, such as silicon germanium, on the exposed surfaces of the first through third trimmed wiring preforms 52' through 56' and the substrate 2, since the cover layer 24 deposited on the first through third trimmed wiring preforms 52' through 56' has different thicknesses relative to each other on the different preforms among the first through third trimmed wiring preforms 52' through 56' as discussed herein with respect to FIG. 2d, the thicknesses of the spacings s1a', s1b', and s1c' between the final wiring 58a - 58d will be more uniform compared to the spacings where a cover layer 24 of the same relative thickness is formed using the process described with respect to FIG. 2d.

[0064] The desired relative thicknesses of the first through third trimmed wiring preforms 52' to 56' of FIG. 4c can be determined using the same exemplary variations discussed with respect to the process described for FIGS. 3a through 3c. The difference here is that the difference in desired thicknesses is applied to form the first through third trimmed wiring preforms 52' to 56', rather than to form the original silicon layer 8. Here, preferably, the non-uniform thicknesses T1, T2, and T3 of the first through third final wirings 58a, 58b, and 58c (such as those of FIG. 2d) are used to determine the desired thicknesses of the first through third trimmed wiring preforms 52', 54', and 56'. Because the same superlattice stack of FIG. 2a is employed, the positions of the individual first through third wiring preforms 52', 54', and 56' are preset by the thickness of the first silicon germanium layer 6. Here, the etching used to trim the first through third wiring preforms 52 - 56 is isotropic, or predominantly isotropic, such that silicon of substantially equal thickness will be uniformly removed from the exposed outer surfaces of the individual first through third wiring preforms 52 - 56, although different thicknesses will be inherently etched away on the different wiring preforms at different distances from the upper surface of the substrate 2 for the wiring preforms 52, 54, 56.

[0065] The relative thicknesses of the first through third post-wiring preforms 52' to 56' and the relative thickness of the overcoat layer 24 thereon can be simply increased or decreased to experimentally and iteratively achieve an acceptable result in terms of the thickness difference in the Y direction of the final wirings 58 to 58c. However, a first approximation for determining these thicknesses can be obtained arithmetically. Here, the thicknesses t1a', t1b', and t1c' of each of the first through third trimmed post-wiring preforms 52' to 56' of FIG. 2d are measured as the total thicknesses T1, T2, and T3 of each of the finished wirings 58a to 58c of FIG. 2d. The average value of the thicknesses T1, T2, and T3 is determined arithmetically as Tave = (T1 + T2 + T3) / 3. In the case where subtracting Tave from a given finished wiring thickness is positive, that positive value is subtracted from the desired trimmed post-wiring thickness of that finished wiring to provide the target trimmed post-wiring thickness. In the case where subtracting Tave from a given finished wiring thickness is negative, that negative value is added to the desired trimmed post-wiring thickness of that finished wiring to provide the target trimmed post-wiring thickness. The purpose here is to provide a target thickness for the thickness of the trimmed post-wiring preforms 52'-56' based on the thickness difference of the final wirings 58a-58c in which the trimmed post-wiring preforms 52'-56' are located. Subsequently, using the same etch chemistry and remote plasma method for trimming the wiring preforms 52-56 of FIG. 2d, and by varying process parameters of the trimming process, such as the process pressure, the target or desired thickness of the trimmed post-wiring preforms 52' to 56' can be achieved. By simple iteration of running the process at different process parameters and trimming etch concentrations, a thickness that is sufficiently close to the desired thickness of the trimmed post-wiring preforms 52' to 56' and the relative thicknesses between those trimmed post-wiring preforms 52' to 56' can be achieved.

[0066] For example, as shown in FIG. 2d, the first final wiring 58a is thicker than both the second final wiring 58b and the third final wiring 58c, and is thicker than the average final wiring 58. Accordingly, the difference between the final wiring thickness T1 and Tave of FIG. 2d is subtracted from the thickness tla' of the first trimmed post-wiring preform 52' to yield the target thickness T for that first trimmed post-wiring preform 52'. tar Similarly, as shown in FIG. 2d, the third final wiring 58c is thicker than the first final wiring 58a and the second final wiring 58b, and is thus thinner than the average finished wiring 58. Accordingly, the difference between the thickness T3 and Tave of the third final wiring 58c of FIG. 2d is added to the thickness t1c' of the trimmed post-wiring preform 56' to yield the target thickness T for the post-wiring preform 56'. tarSimilarly, if there is a difference between T2 and Tave, the difference between those values is used to adjust the thickness of the trimmed wire preform 54'. Thus, by varying the etch nature of the trimming process to produce a T for each wire preform tar , after forming the overcoat 24 thereabove, the resulting final wires 58a to 58c will have equal or nearly equal thickness values in the Y direction. Thus, the spacing between and among the completed wires 58a to 58c and between the completed wire 58c and the facing surface of the overcoat 24 formed on the substrate will have the same or nearly the same span or gap value.

[0067] If the resulting spacings s2a', s2b' and s2c' and the final wire thicknesses T1 - T3 are not uniform enough, the etch process used to trim the wire preforms 52 - 56 can be modified again to iteratively achieve the desired uniformity.

[0068] Figure 5 is a schematic top view of an example of a multi - chamber processing system 100 that can be used to form individual semiconductor layers and overcoats in accordance with some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load - lock chambers 104, 106, transfer chambers 108, 116 with respective transfer robots 110, 118, holding chambers 112, 114, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 can be processed in the various chambers and transferred between the various chambers without exposing the substrates to the surrounding environment (e.g., the ambient atmosphere, such as may exist in a factory) external to the processing system 100. For example, substrates can be processed in and transferred between the various chambers under a low pressure (e.g., less than or equal to about 300 Torr) or in a vacuum environment without disrupting the low - pressure or vacuum environment between the various processes performed on the substrates in the processing system 100. Thus, the processing system 100 can provide an integrated solution for some processing of substrates.

[0069] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include or an integrated processing system or other suitable processing systems commercially available from Applied Materials, Inc., Santa Clara, California. It will be expected that other processing systems (including those from other manufacturers) can be adapted to benefit from the aspects described herein

[0070] In the example shown in FIG. 5, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate the transfer of substrates. The docking station 140 is configured to receive one or more front-opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 typically includes blades 148 disposed at one end of the respective factory interface robot 142, the blades being configured to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0071] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 112, 114 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 116 has respective ports 166, 168 coupled to the holding chambers 112, 114 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. The ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 can be, for example, slit valve openings having slit valves that are used to transfer substrates therethrough by transfer robots 110, 118 and to provide a seal between the respective chambers to prevent the transfer of gas between the respective chambers. Generally, any port is opened for transferring a substrate therethrough; otherwise, the port is closed.

[0072] The load lock chambers 104, 106, the transfer chambers 108, 116, the holding chambers 112, 114, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not shown specifically). The gas and pressure control system can include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps, etc.), gas sources, various valves, and piping fluidly coupled to the respective chambers. In operation, the factory interface robot 142 transfers a substrate from the FOUP 144 through port 150 or 152 to the load lock chamber 104 or 106. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 116 and the holding chambers 112, 114 with an internal low pressure or vacuum environment (which can include an inert gas). Thus, evacuating the load lock chamber 104 or 106 facilitates the transfer of substrates between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0073] Using the substrate in the already evacuated load lock chamber 104 or 106, transfer robot 110 transfers the substrate through port 154 or 156 from the load lock chamber 104 or 106 to the transfer chamber 108. Transfer robot 110 can then transfer the substrate through the corresponding ports 162, 164 to either of the processing chambers 120, 122 and / or transfer between either of the processing chambers for processing, and transfer through the corresponding ports 158, 160 to the holding chambers 112, 114 and / or transfer between the holding chambers for holding to await further transfer. Similarly, transfer robot 118 can access the substrate in the holding chamber 112 or 114 through port 166 or 168, and can transfer the substrate through the corresponding ports 170, 172, 174, 176 to either of the processing chambers 124, 126, 128, 130 and / or transfer between either of the processing chambers for processing, and transfer through the corresponding ports 166, 168 to the holding chambers 112, 114 and / or transfer between the holding chambers for holding to await further transfer. Transferring and holding the substrate within and among the various chambers can be in a low pressure or vacuum environment provided by a gas and pressure control system.

[0074] Processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing substrates. In some examples, processing chamber 122 can be capable of performing a cleaning process; processing chamber 120 can be capable of performing an etching process; and processing chambers 124, 126, 128, 130 can be capable of performing corresponding epitaxial growth processes. Processing chamber 122 can be a SiCoNi TM pre-cleaning chamber. Processing chamber 120 can be a Selectra TM etching chamber available from Applied Materials of Santa Clara, Calif.

[0075] System controller 190 is coupled to processing system 100 for controlling processing system 100 or its components. For example, system controller 190 can control the operation of processing system 100 using direct control of the chambers 104, 106, 108, 112, 114, 116, 120, 122, 124, 126, 128, 130 of processing system 100 or by controlling the controllers associated with the chambers 104, 106, 108, 112, 114, 116, 120, 122, 124, 126, 128, 130. In operation, system controller 190 implements data collection and feedback from the respective chambers to coordinate the performance of processing system 100.

[0076] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuitry 196. The CPU 192 can be any form of general-purpose processor that can be used in an industrial setting. The memory 194 or non-transitory computer-readable medium is accessible by the CPU 192 and can be one or more memories, such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of digital storage device (local or remote). The support circuitry 196 is coupled to the CPU 192 and can include cache memory, clock circuitry, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented by executing computer instruction code (e.g., as software routines) stored in the memory 194 (or in the memory of a particular processing chamber) under the control of the CPU 192 by the CPU 192. When the computer instruction code is executed by the CPU 192, the CPU 192 controls the chamber to perform processes according to the various methods.

[0077] Other processing systems can be in other configurations. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 116 and holding chambers 112, 114. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device in a processing system.

[0078] Figure 6 is a cross-sectional view of a processing chamber 122 that can be used to perform a cleaning process. The processing chamber 122 can be an Applied Materials pre-cleaning chamber obtained from Santa Clara, Calif. The processing chamber 122 includes a chamber body 212, a lid assembly 214, and a support assembly 216. The lid assembly 214 is disposed at the upper end of the chamber body 212, and the support assembly 216 is at least partially disposed within the chamber body 212. The chamber body 212, the lid assembly 214, and the support assembly 216 together define an area in which a substrate can be processed.

[0079] The lid assembly 214 includes at least two stacked components configured to form a plasma region therebetween. A first electrode 220 is vertically disposed above a second electrode 222 for defining a plasma volume therebetween. The first electrode 220 is connected to a radio frequency (RF) power supply 224, and the second electrode 222 is connected to ground, forming a capacitance between the first electrode 220 and the second electrode 222.

[0080] The lid assembly 214 also includes one or more gas inlets 226 for providing a cleaning gas to the substrate surface through the baffle plate 228 and the gas distribution plate 230 (such as a showerhead). The cleaning gas can be an etchant, an ionized gas, or an active radical, such as ionized fluorine, chlorine, or ammonia. In other examples, different cleaning processes can be used to clean the substrate surface. For example, a remote plasma containing He and NF3 can be introduced into the processing chamber 122 through the gas distribution plate 230, while NH3 can be directly injected into the processing chamber 122 via a separate gas inlet 225 provided at the side of the chamber body 212.

[0081] The support assembly 216 can include a substrate support 232 to support the substrate 210 thereon during processing. The substrate support 232 has a flat substrate support surface for supporting the substrate to be processed thereon. The substrate support 232 can be coupled to an actuator 234 through a shaft member 236 that extends through a centrally located opening formed in the bottom of the chamber body 212. The actuator 234 can be flexibly sealed to the chamber body 212 through a bellows (not shown) that prevents vacuum leakage around the shaft member 236. The actuator 234 allows the substrate support 232 to move vertically within the chamber body 212 between a processing position and a lower transfer position. The transfer position is slightly lower than the opening of the slit valve opening formed in the sidewall of the chamber body 212. In operation, the substrate support 232 can be lifted to a position closely adjacent to the lid assembly 214 to control the temperature of the processed substrate 210. Thus, the substrate 210 can be heated by radiation or convection emitted from the gas distribution plate 230.

[0082] The bias RF power supply 280 can be coupled to the substrate support 232 via a matching network 284. The bias RF power supply 280 provides a bias to the substrate 210 to direct the ionized cleaning gas toward the substrate 210.

[0083] A vacuum system (which can be part of the gas and pressure control system of the processing system 100) can be used to remove gas from the processing chamber 122. The vacuum system includes a vacuum pump 218 coupled to a vacuum port 221 provided in the chamber body 212. The processing chamber 122 also includes a controller (not shown) that can be the system controller 190 or a controller controlled by the system controller 190 for controlling the processes within the processing chamber 122.

[0084] Figure 7 is a cross-sectional view of the processing chamber 120 that can be used to perform selective etching processes and trimming processes. The processing chamber 120 can be from Applied Materials of Santa Clara, Calif Etching chamber. The processing chamber 120 includes a chamber body 302, a cover assembly 304, and a support assembly 306. The cover assembly 304 is disposed at the upper end of the chamber body 302, and the support assembly 306 is at least partially disposed within the chamber body 302. The chamber body 302, the cover assembly 304, and the support assembly 306 together define a region in which substrates can be processed. As will be apparent from the following description, the processing chamber 120 can implement one or more capacitively coupled plasmas (CCPs).

[0085] The cover assembly 304 includes an RF electrode 308. A gas inlet tube 310 extends through the RF electrode 308 and is further coupled to a gas manifold 312. A flow centering insert 314 can be disposed within the gas inlet tube 310. A gas source 316 is fluidly coupled to the gas inlet tube 310 via the gas manifold 312. The gas source 316 can provide a gas flow rate 318 through the gas inlet tube 310 and further through the flow centering insert 314. An RF power supply 320 and an RF matching network 322 are coupled to the RF electrode 308 and thus also to the gas inlet tube 310.

[0086] A baffle plate 324 is coupled to the RF electrode 308 and can be maintained at the same potential as the RF electrode 308. The baffle plate 324 has holes therethrough that allow gas to flow through the baffle plate 324. A gas distribution plate 326 is likewise coupled to the RF electrode 308 and can be maintained at the same potential as the RF electrode 308. The gas distribution plate 326 is further from the RF electrode 308 than the baffle plate 324. The gas distribution plate 326 also has holes therethrough that allow gas to flow through the gas distribution plate 326. The baffle plate 324 and the gas distribution plate 326 can be used to redirect the gas flow rate such that the gas flow rate is more uniform on the respective sides of the baffle plate 324 and the gas distribution plate 326 opposite the gas source (e.g., the gas inlet tube 310) in the chamber 120.

[0087] The insulator 330 separates and electrically insulates the gas distribution plate 326 from the gas distribution element 334. The gas distribution element 334 is grounded. The gas distribution element 334 is grounded and has a hole therethrough. The surfaces of the gas distribution plate 326, the gas distribution element 334, and the insulator 330 define a first plasma region 332 (e.g., a remote plasma region). Plasma can be generated in the first plasma region 332 when a flow 318 of gas is provided through the gas inlet tube 310, which passes through the baffle plate 324 and the gas distribution plate 326, and RF energy is provided through the RF power supply 320 through the RF electrode 308 and the gas distribution plate 326. Plasma products (e.g., radicals, ions, and electrons) can pass through the gas distribution element 334 when plasma is generated in the first plasma region 332. Generally, the position of the grounded gas distribution element 334 between the gas distribution plate 326 and the processing region 352 minimizes or prevents ionized gas in the plasma formed above the gas distribution element 334 during processing from reaching the surface of the substrate. Attributed to the bombardment of the substrate surface by ions generated by the plasma, the reduced exposure to ion-containing process gas prevents or minimizes the amount of damage caused to the substrate.

[0088] The gas distribution element 334 further has a channel 336 fluidly coupled to a gas source 338, and the gas source can be used to introduce one or more additional gases on the side of the gas distribution element 334 remote from the first plasma region 332. The gas source 338 can provide a flow 340 of gas through the channel 336. A heating element 342 can be disposed in the gas distribution element 334 or other components and can facilitate the thermal distribution and maintenance of the plasma in the first plasma region 332.

[0089] The support assembly 306 includes a substrate support 348 supported by the chamber body 302. The support assembly 306 is configured to support the substrate 350. A second plasma region (e.g., a direct plasma region) is defined in the processing region 352 between the gas distribution element 334 and the substrate 350. The gas from the flow 318 and the plasma products from the first plasma region 332 can be transferred through the gas distribution element 334 into the processing region 352. The substrate support 348 is further connected to an RF power supply 354 to provide a bias during processing. When a flow 340 of gas is provided through the channel 336 of the gas distribution element 334 and RF energy is provided to the substrate support 348 through the RF power supply 354, plasma can be generated in the second plasma region in the processing region 352.

[0090] The support assembly 306 can include an electrostatic chuck (ESC). The substrate support 348 can be coupled to the actuator 356 via a shaft 358 that extends through a centrally located opening formed in the bottom of the chamber body 302. The actuator 356 can be flexibly sealed to the chamber body 302 via a bellows (not shown) that prevents vacuum leakage around the shaft 358. The actuator 356 allows the substrate support 348 to move vertically within the chamber body 302 between a processing position and a lower transfer position. The transfer position is slightly below a slit valve opening (not shown) formed in the sidewall of the chamber body 302. In operation, the substrate support 348 can be lifted to a position closely adjacent to the lid assembly 304. Although not specifically shown, the substrate support 348 can include heating and cooling elements to maintain the substrate 350 at a target temperature during processing.

[0091] A vacuum system, which can be part of the gas and pressure control system of the processing system 100, can be used to remove gas from the processing chamber 120. The vacuum system includes a vacuum pump 362 coupled to a vacuum port 364 disposed in the chamber body 302.

[0092] The processing chamber 120 also includes a controller (not shown), which can be the system controller 190 or a controller controlled by the system controller 190, for controlling the processes within the processing chamber 120.

[0093] Figure 8 is a cross-sectional view of a heat treatment chamber 400 that can be used to perform epitaxial growth. The processing chamber 400 includes a chamber body 402, a support system 404, and a controller 406. The chamber body 402 includes an upper portion 412 and a lower portion 414. The upper portion 412 includes a region within the chamber body 402 between the upper dome 416 and the substrate 401. The lower portion 414 includes a region within the chamber body 402 between the lower dome 430 and the bottom of the substrate 401. The deposition process generally occurs on the upper surface of the substrate 401 within the upper portion 412.

[0094] The support system 404 includes components for performing and monitoring a predetermined process, such as the growth of an epitaxial film in the processing chamber 400. The controller 406 is coupled to the support system 404 and is adapted to control the processing chamber 400 and the support system 404. The controller 406 can be the system controller 190 or a controller controlled by the system controller 190, for controlling the processes within the processing chamber 400.

[0095] The processing chamber 400 includes a plurality of heat sources, such as lamps 435, which are adapted to provide thermal energy to components positioned within the processing chamber 400. For example, the lamps 435 may be adapted to provide thermal energy to the substrate 401, the susceptor 426, and / or the preheat ring 423. The lower dome 430 may be formed of an optically transparent material, such as quartz, to facilitate the transmission of thermal radiation therethrough. It will be appreciated that the lamps 435 may be positioned to provide thermal energy through the upper dome 416 as well as the lower dome 430.

[0096] The chamber body 402 includes a plurality of gas chambers formed therein. The gas chambers are in fluid communication with one or more gas sources 476, such as carrier gases, and one or more precursor sources 478, such as deposition gases and dopant gases. For example, the first gas chamber 420 may be adapted to provide deposition gas 450 passing therethrough into the upper portion 412 of the chamber body 402, while the second gas chamber 424 may be adapted to discharge the deposition gas 450 from the upper portion 412. In this manner, the deposition gas 450 may flow parallel to the upper surface of the substrate 401.

[0097] In the case of using a liquid precursor, the heat treatment chamber 400 may include a liquid evaporator 480 in fluid communication with a liquid precursor source 482. The liquid evaporator 480 is used to evaporate the liquid precursor to be delivered to the heat treatment chamber 400. Although not shown, it will be appreciated that the liquid precursor source 482 may include, for example, one or more ampoules of precursor liquid and solvent liquid, shut-off valves, and liquid flow meters (LFMs).

[0098] The substrate support assembly 432 is positioned in the lower portion 414 of the chamber body 402. The substrate support assembly 432 is shown supporting the substrate 401 in a processing position. The substrate support assembly 432 includes a susceptor support shaft 427 formed of an optically transparent material and a susceptor 426 supported by the susceptor support shaft 427. The shaft 460 of the susceptor support shaft 427 is positioned within a shroud 431 to which a lift pin contact 442 is coupled. The susceptor support shaft 427 is rotatable to facilitate rotation of the substrate 401 during processing. Rotation of the susceptor support shaft 427 is facilitated by an actuator 429 coupled to the susceptor support shaft 427. The position of the shroud 431 is generally fixed and thus does not rotate during processing. Support pins 437 couple the susceptor support shaft 427 to the susceptor 426.

[0099] The lift pins 433 are disposed through openings (not labeled) formed in the susceptor support shaft 427. The lift pins 433 are vertically actuatable and adapted to contact the bottom side of the substrate 401 to lift the substrate 401 from the processing position (as shown) to a substrate removal position.

[0100] The preheating ring 423 is removably disposed on a lower liner 440 coupled to the chamber body 402. The preheating ring 423 is disposed around the internal volume of the chamber body 402 and circumscribes the substrate 401 while the substrate 401 is in the processing position. As the process gas enters the chamber body 402 through a first gas chamber 420 adjacent to the preheating ring 423, the preheating ring 423 facilitates preheating of the process gas.

[0101] The central window portion 415 of the upper dome 416 and the bottom 417 of the lower dome 430 may be formed of an optically transparent material such as quartz. The peripheral flange 419 of the upper dome 416, which engages the central window portion 415 around the circumference of the central window portion 415, and the peripheral flange 421 of the lower dome 430, which engages the bottom around the circumference of the bottom, may both be formed of opaque quartz to protect the O-ring 422 near the peripheral flange from being directly exposed to thermal radiation. The peripheral flange 419 may be formed of an optically transparent material such as quartz.

[0102] As previously discussed, the hGAA structure uses multiple semiconductor layers stacked on top of each other and extending between the source and drain regions of the substrate. To form the structure, superlattices, individual semiconductor layers (e.g., semiconductor fin layers) are sequentially deposited or formed using an epitaxial deposition process, where sacrificial layers are alternately deposited or formed between each of the semiconductor layers. In one aspect, the semiconductor layer is single-crystalline silicon, e.g., doped single-crystalline silicon, and the sacrificial layer is a silicon-germanium layer. This process results in a stack of silicon and silicon-germanium layers, which are then divided into individual fins or mesa of the superlattice that will extend between the source and drain regions of the device.

[0103] Although the foregoing relates to various examples of the present disclosure, other and further examples may be devised without departing from its basic scope, which is determined by the following claims.

Claims

1. A method of forming a semiconductor device, comprising: forming a first superlattice on a first substrate, the first superlattice including alternating sub-layers of a first material containing a semiconductor and sub-layers of a second material, wherein the thickness of the first material sub-layers is a first thickness and the thickness of the second material sub-layers is a second thickness, wherein at least a first sub-layer of the first material and a second sub-layer of the first material are formed in the first superlattice, and the second sub-layer of the first material is interposed between the first sub-layer of the first material and the substrate; removing the sub-layers of the second material from the first superlattice; etching the first and second sub-layers of the first material of the first superlattice to remove a portion of the first material therefrom and form a first trimmed sub-layer of the first material and a second trimmed sub-layer of the first material, wherein the amount of the first material removed from the first sub-layer of the first material is greater than the amount of the material removed from the second sub-layer of the first material; and depositing a covering layer above the first trimmed sub-layer of the first material of the first superlattice, above the second trimmed sub-layer of the first material of the first superlattice, and on the exposed surface of the substrate; measuring the distance between the covering layer on the first sub-layer and the covering layer on the second sub-layer, and the distance between the covering layer on the second sub-layer and the covering layer on the substrate, and determining a first difference between those distances; forming a second superlattice on a second substrate, the second superlattice including alternating sub-layers of the first material containing a semiconductor and sub-layers of the second material, wherein the thickness of the first material sub-layers is a first thickness and the thickness of the second material sub-layers is a second thickness, wherein at least a first sub-layer of the first material and a second sub-layer of the first material are formed in the second superlattice, and the second sub-layer of the first material is interposed between the first sub-layer of the first material and the second substrate; removing the sub-layers of the second material from the second superlattice and the second substrate; etching the first and second sub-layers of the first material of the second superlattice to remove a portion of the first material therefrom and form a first trimmed sub-layer of the first material and a second trimmed sub-layer of the first material, wherein the processing conditions for removing the portions of the first sub-layer of the first material and the second sub-layer of the first material are different from those for removing the portions of the first sub-layer of the first material and the second sub-layer of the first material of the first superlattice; and depositing a covering layer above the first trimmed sub-layer of the first material of the second superlattice and above the second trimmed sub-layer of the first material of the second superlattice and on the exposed surface of the substrate; The difference between the distance between the cover layer on the first sub-layer of the first material and the cover layer on the second sub-layer of the first material of the second superlattice and the distance between the cover layer on the second sub-layer of the first material of the second superlattice and the cover layer on the second substrate is less than the first difference.

2. The method according to claim 1, wherein the processing pressure during etching of the first sub-layer of the first material and the second sub-layer of the first material on the second superlattice is lower than the processing pressure during etching of the first sub-layer of the first material and the second sub-layer of the first material on the first superlattice.

3. The method according to claim 2, wherein the relative concentration of the gas during etching of the first sub-layer of the first material and the second sub-layer of the first material on the second superlattice is the same as the relative concentration of the gas used for etching the first sub-layer of the first material and the second sub-layer of the first material on the first superlattice.

4. The method according to claim 2, wherein the processing time during etching of the first sub-layer of the first material and the second sub-layer of the first material on the second superlattice is longer than the processing time for etching the first sub-layer of the first material and the second sub-layer of the first material on the first superlattice.

5. The method according to claim 2, wherein the sum of the thickness of the cover layer formed on the first trimmed sub-layer of the first material of the second superlattice and the thickness of the first trimmed sub-layer of the first material of the second superlattice is equal to the sum of the thickness of the cover layer formed on the second trimmed sub-layer of the first material of the second superlattice and the thickness of the second trimmed sub-layer of the first material of the second superlattice.

6. The method according to claim 5, wherein the thickness of the cover layer formed on the first trimmed sub-layer of the first material of the second superlattice is greater than the thickness of the cover layer formed on the second trimmed sub-layer of the first material of the second superlattice.

7. A method of forming a semiconductor device on a substrate, comprising: forming a superlattice on the substrate, the superlattice comprising alternating sub-layers of a first material containing a semiconductor and a second material, wherein at least the first sub-layer of the first material layer and the second sub-layer of the first material have different thicknesses, and the second sub-layer of the first material is interposed between the first sub-layer of the first material and the substrate; removing the second material sub-layers from the superlattice; etching the first sub-layer of the first material and the second sub-layer of the first material such that a different amount of the first material is removed from the first sub-layer of the first material compared to the amount of material removed from the second sub-layer of the first material; and Deposit a cover layer over the etched first sub-layer of the first material and over the etched second sub-layer of the first material, wherein the thickness of the cover layer deposited on the first sub-layer of the first material is different from the thickness of the cover layer deposited on the second sub-layer of the first material.

8. The method according to claim 7, wherein the first sub-layer of the first material is positioned further away from the substrate as compared to the second sub-layer of the first material, and the thickness of the first sub-layer of the first material before etching is greater than the thickness of the second sub-layer of the first material before etching.

9. The method according to claim 8, wherein the thickness of the cover layer on the etched first sub-layer of the first material is thicker as compared to the thickness of the cover layer on the etched second sub-layer of the first material.

10. The method according to claim 9, wherein the etched first sub-layer of the first material has a first side facing away from the second sub-layer of the first material and a second side facing the second sub-layer of the first material; the etched second sub-layer of the first material has a first side facing the first sub-layer of the first material and a second side facing the substrate; the cover layer is formed at least on the first and second sides of the etched first sub-layer of the first material and at least on the first and second sides of the etched second sub-layer of the first material; and the sum of the thickness of the etched first sub-layer of the first material and the thickness of the cover layer formed on its first and second sides is equal to the sum of the thickness of the etched second sub-layer of the first material and the thickness of the cover layer formed on its first and second sides.

11. The method according to claim 9, wherein the etched first sub-layer of the first material has a first side facing away from the second sub-layer of the first material and a second side facing the second sub-layer of the first material; the etched second sub-layer of the first material has a first side facing the first sub-layer of the first material and a second side facing the substrate; the cover layer is formed on the first and second sides of the etched first sub-layer of the first material and on the first and second sides of the etched second sub-layer of the first material; and the distance between the outer surface of the cover layer on the etched first sub-layer of the first material facing the etched second sub-layer of the first material and the surface of the cover layer on the etched second sub-layer of the first material facing the etched first sub-layer of the first material is equal to the spacing between the surface of the cover layer on the etched second sub-layer of the first material facing the substrate and the surface of the cover layer on the substrate furthest from the substrate.

12. The method according to claim 10, wherein the first etched sub-layer of the first material and the second etched sub-layer of the first material are silicon layers that form channels in the HGGA device.

13. The method according to claim 11, wherein the capping layer comprises silicon germanium, and the first etched sub-layer of the first material and the capping layer thereabove, and the second etched sub-layer of the first material and the capping layer thereabove form channels in the HGGA device.

14. A method of forming a multi-layer semiconductor device, comprising: providing a first substrate; forming a superlattice on the first substrate, the superlattice comprising a plurality of alternating first layers composed of a first material and second layers formed of a second material; selectively removing the second layers of the superlattice; exposing the first layers of the superlattice to an etchant under first processing conditions and removing a portion of the first material therefrom to form trimmed first layers, wherein the amount of material removed from different first layers in the first layer is a different amount; forming a capping layer above the first layers in the superlattice stack; measuring at least one of the distances between the capping layers formed on different first layers in the first layer, the thicknesses of the different capping layers in the capping layers formed on different trimmed first layers in the trimmed first layer, and the different thicknesses of the combined thicknesses of the different first layers in the trimmed first layer and the capping layers formed thereabove; and calculating a new thickness of the trimmed first layer based on the difference between at least one of the distances between the capping layers formed on different first layers in the first layer, the thicknesses of the different capping layers in the capping layers formed on different trimmed first layers in the trimmed first layer, and the different thicknesses of the combined thicknesses of the different first layers in the trimmed first layer and the capping layers formed thereabove.

15. The method according to claim 14, further comprising providing a second substrate; forming a superlattice on the second substrate, the superlattice comprising a plurality of alternating first layers composed of a first material and second layers formed of a second material, wherein at least two of the first layers of the superlattice have different thicknesses, the different thicknesses being selected at least in part based on the difference between at least one of the distances between the capping layers formed on different first layers in the first layer on the first substrate, the thicknesses of the different capping layers in the capping layers formed on different trimmed first layers in the trimmed first layer on the first substrate, and the different thicknesses of the combined thicknesses of the different first layers in the trimmed first layer on the first substrate and the capping layers formed thereabove; selectively removing at least the first portion of the second layers of the superlattice; Expose the first layer of the at least first portion of the superlattice stack to an etchant and remove a portion of the first material therefrom to form a trimmed first layer therefrom.

16. The method according to claim 14, further comprising providing a second substrate; Form a superlattice on the second substrate, the superlattice including a plurality of alternating first layers composed of a first material and second layers formed of a second material, wherein the first layers have a common first thickness and the second layers have a common second thickness; Selectively remove the second layer of at least the first portion of the superlattice; Expose the first layer of the at least first portion of the superlattice stack to an etchant and remove a portion of the first material therefrom using a second processing condition different from the first processing condition to form a trimmed first layer therefrom, wherein the amounts of material removed from different first layers in the first layer are different amounts, and the different amounts are selected based on at least one of the distance between the overlayers formed on the different first layers in the first layer on the first substrate, the thickness of the different overlayers in the overlayers formed on the different trimmed first layers in the trimmed first layer on the first substrate, and the different thicknesses in the combined thickness of the different trimmed first layers and the overlayers formed thereabove in the trimmed first layer on the first substrate.

17. The method according to claim 15, wherein the spaces between adjacent layers of the covering material on different trimmed first layers of the second substrate are equal to each other.

18. The method according to claim 16, wherein the spaces between adjacent layers of the covering material on different trimmed first layers of the second substrate are equal to each other.

19. The method according to claim 16, wherein the thickness of the overlayer on the layer of the first material closest to the substrate is less than the thickness of the overlayer on the layer of the first material farthest from the substrate.

20. The method according to claim 15, wherein the first layer and the second layer are epitaxial layers.

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