Method, system, and computer program product for data communication

Abstract

A method and apparatus for transmitting a data signal, comprising receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting a clock signal by a first counter; transmitting a first select signal to a first select signal input of the transmitter multiplexer in response to the first counter counting a threshold number of clock cycles by the first counter; and alternately transmitting the digital data signal and the inverted digital data signal as a transmitter output signal to a receiver in response to the first select signal and by a first digital data signal output of the transmitter multiplexer, the receiver and the digital data signal output operably coupled to a data link.

Description

Background Technology

[0001] This invention relates to data transmission technology, and more particularly, to data transmission technology over one or more data links.

[0002] A data link is an interconnection between agents, where, in a given data transaction, one agent is the "transmitter" and the other is the "receiver." Among other examples, sample data links can be positioned between a processor and a disk drive, between processors on separate boards in a computer system, and / or between processors on the same board or package. For the two agents to communicate, they agree on the timing of sending and receiving data. This agreement is often referred to as the clocking scheme in the link design.

[0003] For example, in a "common clock" scheme, all interconnected components share a single clock when sending and receiving data. In a "source-synchronous" clock scheme, the clock signal is transmitted along with the data signal. An "embedded" clock scheme embeds the clock signal into the data transmission, but it is not without drawbacks, including the need for clock data recovery circuitry and bandwidth limitations. Within a given clock scheme, the transmission protocol defines when the transmitter sends data and when the receiver samples the transmitted data.

[0004] Transport protocols may include techniques for idling agents that may have no data to transmit or are in an idle state, but such idling introduces various delays, data overhead, and complexities. Summary of the Invention

[0005] According to a first embodiment of the present invention, a method includes: receiving a digital data signal via a first input of a multiplexer operatively coupled to a data link; transmitting the digital data signal to a receiver operatively coupled to the data link via a digital data signal output of the multiplexer; receiving a first selection signal indicating an idle mode for the transmitter via a selection signal input of the multiplexer; receiving a patterned data signal via a second input of the multiplexer; and transmitting the patterned data signal to the receiver via a digital data signal output in response to the first selection signal.

[0006] In a first aspect of the first embodiment, the method further includes intermittently transmitting a patterned data signal to a second input, thereby reducing the switching rate of the patterned data signal received through the second input of the multiplexer.

[0007] In a second aspect, in conjunction with the first embodiment and / or other aspects, the method further includes receiving a second selection signal indicating a data signal transmission mode for a transmitter via a selection signal input of a multiplexer, and the step of transmitting a digital data signal includes transmitting a digital data signal to a receiver in response to the second selection signal.

[0008] In a third aspect, in conjunction with the first embodiment and / or its aspects, the method further includes selecting an idle mode for the transmitter based on the digital data signal. In a fourth aspect, the selection step includes selecting an idle mode for the transmitter based on a switching activity value of the digital data signal. In a fifth aspect, the selection step includes detecting at least one of an idle flow control unit / digital (flit) of the digital data signal and an idle physical digital (phit) of the digital data signal, and selecting an idle mode for the transmitter based on at least one of the idle flit and the idle phit.

[0009] In a sixth aspect, in conjunction with the first embodiment and / or other aspects, the first processor includes a transmitter, and the second processor includes a receiver.

[0010] According to a second embodiment of the present invention, a method includes: receiving a digital data signal through a first data input of a transmitter multiplexer; inverting the digital data signal through a first inverter to provide an inverted digital data signal; receiving the inverted digital data signal through the first inverted data input of the transmitter multiplexer; counting a clock signal through a first counter; transmitting a first selection signal to a first selection signal input of the transmitter multiplexer through the first counter and in response to counting a threshold number of clock cycles; and, in response to the first selection signal and through a first digital data signal output of the transmitter multiplexer, alternately transmitting the digital data signal and the inverted digital data signal as a transmitter output signal to a receiver, wherein the receiver and the digital data signal output are operatively coupled to a data link.

[0011] In a first aspect of the second embodiment, the receiver includes a second counter and a receiver multiplexer arranged for receiving a transmitter output signal. The method further includes receiving the transmitter output signal through a second data input of the receiver multiplexer; inverting the transmitter output signal through a second inverter to provide an inverted transmitter output signal; receiving an inverted digital data signal through the second inverted data input of the receiver multiplexer; counting a clock signal through the second counter; sending a second selection signal to a second selection signal input of the receiver multiplexer through the second counter and in response to counting a threshold number of clock cycles through the second counter; and alternately providing the transmitter output signal and the inverted transmitter output signal in response to the selection signal and through the second digital data signal output of the receiver multiplexer.

[0012] In a second aspect of the second embodiment, the counting step via the first counter includes counting each occurrence of a clock cycle for counting a threshold number using the first counter, and providing a first selection signal in response to each occurrence of a clock cycle for counting a threshold number; and the counting step via the second counter includes counting each occurrence of a clock cycle for counting a threshold number using the second counter, and providing a second selection signal in response to each occurrence of a clock cycle for counting a threshold number.

[0013] In a third aspect of the second embodiment, in conjunction with the second embodiment and / or its aspects, the method further includes synchronizing a first counter and a second counter. In a fourth aspect, in conjunction with the second embodiment and / or its aspects, the first processor includes a transmitter multiplexer, and the second processor includes a receiver multiplexer.

[0014] As described herein, the first and second embodiments and aspects thereof may be combined in other embodiments.

[0015] According to a third embodiment of the present invention, a system includes a data link; a receiver operatively coupled to the data link; a memory containing data for generating patterned data signals; and a transmitter operatively coupled to the data link and the memory, the transmitter being arranged to transmit digital data signals and including a multiplexer comprising a first input arranged to receive digital data signals, a second input arranged to receive patterned data signals, a selection signal input arranged to receive a mode selection signal, and a digital data signal output arranged to transmit a multiplexer output signal to the data link, the multiplexer being adapted to selectively output digital data signals and patterned data signals as multiplexer output signals in response to a receive mode selection signal, the mode selection signal indicating an idle mode of the transmitter and a data signal transmission mode of the transmitter.

[0016] In a first aspect of the third embodiment, a system further includes a switch arranged between a memory and a patterned data signal input for intermittently transmitting patterned data signals to the patterned data signal input.

[0017] In a second aspect of the third embodiment, in conjunction with the third embodiment and / or its aspects, the processor includes at least one of a memory and a transmitter. In a third aspect of the third embodiment, in conjunction with the third embodiment and / or its aspects, the memory includes a processor register that stores data for generating patterned data signals.

[0018] In a fourth aspect of the third embodiment, the system further includes a serializer operatively coupled to a processor register and a second input, the serializer being adapted to serialize data to generate a patterned data signal. In a fifth aspect of the third embodiment, in conjunction with the third embodiment and / or its aspects, the multiplexer includes a 2-to-1 multiplexer.

[0019] In a sixth aspect of the third embodiment, in conjunction with the third embodiment and / or its aspects, the system further includes a mode selection controller adapted to provide a mode selection signal based on a digital data signal. In a seventh aspect of the third embodiment, the mode selection controller is adapted to provide a mode selection signal in response to a digital data signal including a flow control message indicating an idle mode. In an eighth aspect of the third embodiment, the mode selection controller is adapted to provide a mode selection signal in response to a digital data signal including a flow control message indicating a data signal transmission mode.

[0020] In a ninth aspect of the third embodiment, in conjunction with the third embodiment and / or its aspects, the transmitter is arranged to transmit a clockless data signal as a digital data signal. In a tenth aspect of the third embodiment, in conjunction with the third embodiment and / or its aspects, the memory includes a programmable memory arranged to receive data for generating a patterned data signal.

[0021] According to a fourth embodiment of the present invention, a system includes a first inverter arranged for receiving a digital data signal, a clock, a first counter operably coupled to the clock, and a transmitter multiplexer. The transmitter multiplexer includes: a first input arranged for receiving the digital data signal; a first inverted data input operably coupled to the first inverter and arranged for receiving the inverted digital data signal; a first selection signal input operably coupled to the first counter and arranged for receiving the first selection signal; and a first output arranged for transmitting a transmitter multiplexer output signal. The first counter is adapted to provide the first selection signal in response to a clock cycle counting a threshold number, such that the transmitter multiplexer alternately transmits the digital data signal and the inverted digital data signal as the transmitter multiplexer output signal.

[0022] In a first aspect of the fourth embodiment, the system further includes a second inverter arranged to receive a transmitter multiplexer output signal, a second counter, a receiver multiplexer, and a data link operatively coupled to the transmitter multiplexer and the receiver multiplexer. The receiver multiplexer includes a second input arranged to receive the transmitter multiplexer output signal, a second inverted data input operatively coupled to the second inverter and arranged to receive an inverted transmitter multiplexer output signal, a second selection signal input operatively coupled to the second counter and arranged to receive a second selection signal, and a second output arranged to provide a receiver multiplexer output signal. The second counter is adapted to provide the second selection signal in response to a clock cycle counting a threshold number, such that the receiver multiplexer alternately provides the transmitter multiplexer output signal and the inverted transmitter multiplexer output signal as the receiver multiplexer output signal.

[0023] In a second aspect of the fourth embodiment, in conjunction with the fourth embodiment and / or its aspects, the system further includes a processor operatively coupled to a computer-readable storage medium having computer-readable program code embodied therein, which can be executed by the processor to synchronize the first counter and the second counter.

[0024] In a third aspect of the fourth embodiment, in conjunction with the fourth embodiment and / or its aspects, the first processor includes a transmitter multiplexer, and the second processor includes a receiver multiplexer.

[0025] In a fourth aspect of the fourth embodiment, in conjunction with the fourth embodiment and / or its aspects, the first counter is a programmable counter adapted to change the number of clock cycles in which the programmable counter responds to counting to provide a first selection signal. In a fifth aspect of the fourth embodiment, in conjunction with the fourth embodiment and / or its aspects, the first counter is a first programmable counter adapted to change the number of clock cycles in which the first programmable counter responds to counting to provide a first selection signal, and the second counter is a second programmable counter adapted to change the number of clock cycles in which the second programmable counter responds to counting to provide a second selection signal.

[0026] As described herein, the third and fourth embodiments and aspects thereof may be combined in other embodiments. Attached Figure Description

[0027] Figure 1 An example of a communication system is described.

[0028] Figure 2 An example of a transmitter agent is described.

[0029] Figure 3 An example of a transmitter agent is described.

[0030] Figure 4 An example of a communication system is described.

[0031] Figure 5 An example method for data communication is described.

[0032] Figure 6 An example method for data communication is described.

[0033] Figure 7 An example method for data communication is described.

[0034] Figure 8 An example of a transmitter agent is described.

[0035] Figure 9 An example computing environment is described. Detailed Implementation

[0036] Various aspects of this disclosure are described by narrative text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). Regarding any flowchart, depending on the technology involved, operations may be performed in a different order than that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, concurrently, or in a manner that at least partially overlaps in time.

[0037] Computer Program Product Embodiment (“CPP Embodiment” or “CPP”) is a term used in this disclosure to describe any collection of one or more storage media (also referred to as “media”) collectively included in a collection of one or more storage devices, which collectively include machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. A “storage device” is any tangible device capable of holding and storing instructions used by a computer processor. Without limitation, a computer-readable storage medium can be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punch cards or pits / platforms formed in the main surface of the disk), or any suitable combination of the foregoing. Computer-readable storage media, as used in this disclosure, should not be construed as storing transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses transmitted through fiber optic cables, electrical signals communicated via lines, and / or other transmission media. As those skilled in the art will understand, data is typically moved at certain incidental points in time during the normal operation of the storage device, such as during access, defragmentation, or garbage collection; however, this does not cause the storage device to be construed as transient, since the data is not transient when it is stored.

[0038] Idle agents (e.g., processors) operate with a very small power budget. This causes a large change in current on the I / O power supply when transitioning from an idle state to an active state. Due to package inductance, this change in current translates into large voltage noise. This voltage noise will cause performance degradation of noisy I / Os or other I / Os operatively coupled to the same power supply. In one aspect, some embodiments can effectively provide a data link noise ceiling by ensuring minimal switching activity on the data link.

[0039] The power consumption of a digital circuit can be characterized by the switching activity of a digital signal (e.g., a digital data signal or a clock signal). Switching activity can be characterized as an activity factor (e.g., a switching activity value) of the digital signal, which has the probability of a power consumption transition per clock cycle. A clock signal has an activity factor expressed as a percentage of 100%, contrasting with a digital data signal whose activity factor is between 5% and 15%, meaning that the digital data signal will include power consumption transitions during 5% to 15% of clock cycles.

[0040] Now for reference Figure 1 In one embodiment, the communication system 100 includes a circuit board 101 having agents 102a and 102b and an optional agent 102c. Agent 102a includes a transmitter 106a and a receiver 122a. Agent 102b includes a transmitter 106b and a receiver 122b, and the optional agent 102c includes a transmitter 106c and a receiver 122c. The transmitters 106a and 106b and the receivers 122a and 122b can communicate via corresponding data links 120a and 120b. In one aspect, the data links 120a and 120b can be clockless data links (e.g., data links that do not carry data with an embedded clock signal).

[0041] Transmitter 106a and receiver 122a may be included in a processor occupying a computer motherboard, wherein data link 26 is a bus interconnecting the processors. Alternatively, transmitter 106a and receiver 122a may be arranged in separate chips located on respective circuit boards. Transmitter 106a and receiver 122a may be close to or further apart from each other, such as having signal traces of 100 inches or longer. In one aspect, transmitter 106a and receiver 122a may reside on a multi-chip package. In one aspect, data links 120a and 120b include one or more physical interconnections (e.g., point-to-point physical interconnections) to define physical links at the physical layer of system 100.

[0042] In one embodiment, multiplexer 108 includes a digital data input 110, a data pattern input 112, a mode selection input 114, and a digital data output 118. Digital data output 118 may be operatively coupled to Tx circuitry 116. In one aspect, input 110 may receive digital data signals for transmission via data link 120a. In another aspect, mode selection input 114 may receive a signal indicating that transmitter 106a is in idle mode.

[0043] The idle mode can be initiated using any of several criteria. Example embodiments include triggering conditions for initiating the idle mode, such as detecting an idle flick, an output signal below a switching activity threshold, and an empty transaction queue for the transport agent, or if the queue reaches a non-zero minimum threshold. Additionally or alternatively, the triggering conditions may reflect software-triggered events, events triggered by higher protocol layers, and / or power management events.

[0044] Upon receiving the idle mode selection signal at input 114, multiplexer 108 transmits the data pattern received via data pattern input 112. In one aspect, the data pattern is based on predetermined data to ensure minimum handover activity on data link 120a. Thus, the data pattern does not include the actual data to be processed, but rather includes data to ensure the maximum noise level or noise ceiling of the agent that ensures operative coupling between data link 120a and the agent. In another aspect, the transmitted data pattern is not processed by the receiving agent.

[0045] When input 114 receives a selection signal indicating the data signal transmission mode of transmitter 106a, multiplexer 108 transmits the digital data signal received through digital data input 110 to at least agent 102b. In some embodiments, multiplexer 108 is a 2-to-1 multiplexer.

[0046] Figure 2 An agent 202 is shown in an embodiment, including a processor 204, an optional switch controller 224, and a mode selection controller 228. In one embodiment, the processor 204 includes the switch controller 224 and the mode selection controller 228.

[0047] In one embodiment, processor 204 includes a multiplexer 108 having the aforementioned digital data input 110, data pattern input 112, mode selection input 114, and digital data output 118. In one embodiment, processor 204 may further include a clock 216 and internal memory 218. Internal memory 218 may include data for generating patterned data signals. In some embodiments, internal memory 218 includes programmable memory, thereby allowing modification and / or supplementation of the patterned signal data.

[0048] For example, processor 204 can be included in a wide range of different computing systems and subsystems, each with a different noise ceiling threshold to prevent the transmitted data from being corrupted by voltage noise. Different styled signal data can be provided to memory 218 for different computing systems / subsystems, allowing for adaptation to different noise ceiling thresholds. In some embodiments, the different styled signal data characterizes styled data signals with different activity factors. In a programmable memory embodiment of internal memory 218, a programmable communication protocol is implemented by programmably defining the styled signal data.

[0049] In one embodiment, the internal memory 218 can be relatively small (e.g., Figure 3 (As illustrated in the embodiment), and accommodates a small range of data values ​​with a relatively high activity factor for idle mode. For example, the styled data signal may have an activity factor of not less than 6%. In one embodiment, switch 220 switches the styled data signal to the application of input 112, thereby reducing the activity factor. In one aspect, switch 220 reduces the activity factor by approximately half, such that a signal with a 6% activity factor has an activity factor of approximately 3.25%.

[0050] In one embodiment, the switch controller 224 is adapted to control the application and / or switching rate of the switch 220. The variable switching rate can also provide input 112 with styled data input signals having different activity factors. For example, in some embodiments, the switch controller 224 can increase or decrease the switching speed of the switch 220 to intermittently provide styled data signals. In one embodiment, at least one of the switch 220 and the switch controller 224 is programmable, thereby allowing at least one instruction for defining the switching rate, as well as other possible instructions.

[0051] In one embodiment, the mode selection controller 228 can detect either a FLIT or a PHIT 230. "FLIT" stands for "Flow Control Unit / Digital," while "PHIT" stands for "Physical Digital." The smallest unit of information transmitted to / from the link layer is called a "FLIT." The smallest unit of data transmitted from one agent to another at the physical layer is called a "PHIT."

[0052] Not transmitting any data across the data link during idle mode may result in arbitrary voltage (e.g., noise) on the data link. Instead, in one embodiment, flit / phit 230 may include either an idle flit or an idle phit. In some embodiments, mode selection controller 228 may detect an idle flit and / or an idle phit indicating an idle mode for transmitter 206 and / or processor 204, and in response, provide an idle mode selection signal, thereby enabling multiplexer 108 to transmit styled data signals.

[0053] In one embodiment, the mode selection controller 228 may monitor the transaction queue 210 and / or the data therein. In one embodiment, the controller 228 provides an idle mode selection signal in response to an empty and / or nearly empty transaction queue 210.

[0054] Figure 3 An agent 302 is illustrated in an embodiment including a processor 304 with a transmitter 206, a clock 216, a receiver 306, a serializer 308, and internal memory 218. In one embodiment, the internal memory 218 includes a processor register 318 for holding (or storing) data 320 used to generate patterned data signals. In one embodiment, the processor register 318 may include 16 bits of data. Figure 3 As shown in hexadecimal format, in one aspect, storing data 320 in processor register 318 is a particularly efficient implementation in terms of memory utilization, computational resources and message passing efficiency, for providing styled data signals during idle mode.

[0055] Optional serializer 308 can receive data 320 in parallel via one or more inputs 310 and serialize the data 320 into a patterned data signal for input 112. That is, serializer 308 can include a parallel input serial output (PISO) block structure. In one aspect, serializer 308 can be a component of a SerDes (i.e., serializer / deserializer). Alternatively, data 320 can be output serially directly from memory 218 to input 112.

[0056] In this embodiment, even when the transmitter 206 is in idle mode, the processor 304 can still receive and process data received from the data output 340. That is, in some embodiments, the transmitter 206 and the receiver 306 can be independently idled.

[0057] Figure 4An example of a communication system 400 is depicted, which in an embodiment includes processors 404a and 404b, a data link 420, and a clock link 444. In one embodiment, the data link 420 and / or the clock link 444 includes one or more physical interconnections (e.g., point-to-point physical interconnections) to define physical links at the physical layer of the system 400.

[0058] exist Figure 4 In this embodiment, system 400 describes a "source-synchronous" clock scheme embodiment, but other embodiments may include a "common clock" scheme embodiment. For example, clock 416a may reside outside of processor 404a, wherein clock 416a provides clock signals to processors 404a and 404b.

[0059] In one embodiment, processor 404a includes a transmitter 406 and a clock 416a. In another embodiment, transmitter 406 includes an inverter 403a, a multiplexer 408a, a counter 414a, and a Tx circuit 416. Multiplexer 408a (e.g., a transmitter multiplexer) includes a digital data input 110, an inverted data input 410, a selection signal input 412a, and a data output 418.

[0060] In one embodiment, processor 404b includes receiver 422 and optional clock 416b. In one embodiment, clock 416b receives a clock signal to generate a further clock signal. In another embodiment, processor 404b does not include clock 416b and utilizes an external clock signal.

[0061] In one embodiment, receiver 422 includes an inverter 403b, a multiplexer 408b, a counter 414b, and an Rx circuit 424. Multiplexer 408b (e.g., a receiver multiplexer) includes a digital data input 426, an inverted data input 428, a selection signal input 412b, and a data output 440. In some embodiments, multiplexers 408a and 408b are 2-to-1 multiplexers.

[0062] In one embodiment, counters 414a and 414b are synchronized and, after at least a threshold number of clock cycles of clock 416a, transmit selection signals to the respective multiplexers 408a and 408b. In one aspect, multiplexers 408a and 408b are switched synchronously from output data or inverted data. For example, in one embodiment, data provided to data input 110 of transmitter 406 is provided via data link 420, received via data input 426, and provided via data output 440. In another embodiment, counters 414a and 414b synchronously provide (e.g., transmit) selection signals to the respective selection signal inputs 412a and 412b, such that multiplexers 408a and 408b are switched synchronously to output inverted data signals provided on the respective inverted data inputs 410 and 428.

[0063] In the inverting mode embodiment, the original data signal is inverted twice (e.g., first by inverter 403a, then by 403b), thereby providing an accurate data signal through output 440. Advantageously, because the data signal or the inverted data signal is provided independently of the data content, a minimal activity factor can be established (and therefore a noise ceiling can be established). For example, the actual data may include a long string of 0s or 1s, which may be biased by circuitry or otherwise introduce noise. However, in some embodiments, at least a portion of the long string of 0s or 1s may be inverted, thereby increasing the activity factor of the data signal.

[0064] Another advantage is that switching between the data signal and the inverted data signal can maintain circuit health. For example, by guaranteeing a minimum amount of switching for each threshold number of clock cycles, circuit components are more likely to remain within design tolerances with minimal power consumption, especially in embodiments with extended periods of minimal to no data transmission (e.g., processors with extended periods of empty transaction queues).

[0065] In one embodiment, counters 414a and 414b are programmable. For example, in one embodiment, counters 414a and 414b may be adapted to change a threshold number of clock cycles for triggering the selection signal via instructions. An example threshold may be 32,000 clock cycles, and in a programmable embodiment, this threshold may be updated to different clock cycle values. In a programmable embodiment of counters 414a and 414b, a programmable communication protocol is implemented by programmably defining the number of clock cycles that trigger, for example, counters 414a and 414b to synchronously transmit their respective selection signals.

[0066] System 400 can be included in a wide range of different computing systems and subsystems, each with a different noise ceiling threshold for transmitted data that is not corrupted by voltage noise. Different trigger clock cycle values ​​can be provided to clocks 416a and 416b for different computing systems / subsystems, allowing for adaptation to different noise ceiling thresholds.

[0067] Figure 5 An example method 500 for data communication is depicted, and the steps shown are included in an embodiment. In some embodiments, method 500 may correspond to... Figure 1 Agent 102a, Figure 2 Agent 202 and / or Figure 3 Agent 302.

[0068] Step 502 includes receiving a data link signal through a first input of a multiplexer operatively coupled to a data link transmitter. Step 504 includes transmitting a digital data signal to a receiver operatively coupled to a data link through a digital data signal output of the multiplexer.

[0069] Step 506 includes receiving a first selection signal indicating an idle mode for the transmitter via a selection signal input of a multiplexer. In some embodiments, the idle mode may be selected based on digital data signals such as switching activity values ​​of digital data signals and / or detection of at least one of idle flit and idle phit.

[0070] Optional step 508 includes intermittently transmitting a patterned data signal to the second signal input. (See reference...) Figure 2 As explained, the switch may intermittently couple or otherwise transmit styled data signals. In some embodiments, step 508 modifies the switching activity of the styled data signals, including reducing the activity factor of the styled data signals.

[0071] Step 510 includes receiving a styled data signal through a second input of the multiplexer. Step 512 includes transmitting the styled data signal to the receiver via a digital data signal output in response to a first selection signal. Optionally, step 514 includes receiving a second selection signal indicating a data signal transmission mode for the transmitter via a selection signal input of the multiplexer. In an embodiment, method 500 may then return to step 504, which is associated with the data signal transmission mode.

[0072] Figure 6An example method 600 for data communication is depicted, and the steps shown are included in the embodiments. In some embodiments, method 600 may correspond to communication system 400. Optional step 602 includes synchronizing at least a receiver counter and a transmitter counter. For example, the memory may include computer program instructions executable by a processor for synchronizing two or more counters. In some embodiments, the counters may have already been synchronized, such that the embodiment method can be performed at step 604.

[0073] Step 604 includes receiving a digital data signal through a first input of the transmitter multiplexer. Step 606 includes receiving an inverted digital data signal through a second input of the transmitter multiplexer. Step 608 includes transmitting a first selection signal to a selection signal input of the transmitter multiplexer via a transmitter counter and in response to counting a threshold number of clock cycles by the transmitter counter. In some embodiments, the counting includes counting each occurrence of a clock cycle for the threshold number of clock cycles, and providing the selection signal of step 608 in response to each occurrence of a clock cycle for the threshold number of clock cycles.

[0074] Step 610 includes alternately transmitting digital data signals and inverted digital data signals to the receiver in response to a first selection signal and through the digital data signal output of the transmitter multiplexer. As described above, some embodiments of the communication system (e.g., system 400) can switch between transmitting data and transmitting inverted data independently of idle mode or data signal transmission mode.

[0075] Figure 7 An example method 700 for data communication is depicted, and the steps shown are included in embodiments. In some embodiments, method 700 may correspond to communication system 400. Method 700 may include step 610. Step 702 includes alternately receiving digital data signals and inverted digital data signals from a transmitter through a first input of a receiver multiplexer. Step 704 includes receiving the inverted digital data signal or an inverted version of the digital data signal received in step 702 through a second input of the receiver multiplexer.

[0076] Step 706 includes transmitting a second selection signal to the selection signal input of the receiver multiplexer by counting clock cycles for a threshold number of times using a receiver counter. In some embodiments, step 706 may occur synchronously with step 608 of method 600, such that the transmitter and receiver alternately process the data input signal or the inverted data input signal. In some embodiments, the counting includes counting each occurrence of a clock cycle for a threshold number of times, and providing the selection signal of step 706 in response to each occurrence of a clock cycle for a threshold number of times.

[0077] Step 708 includes providing a digital data signal in response to a second selection signal and through the digital data signal output of a multiplexer. In one aspect, given that the receive and transmit counters are synchronized, the digital data signal of step 604 is faithfully reproduced as the digital data signal of step 708.

[0078] Now for reference Figure 8 In one embodiment, agent 802 includes processor 804 and transmitter 806. In another embodiment, transmitter 806 includes components operatively coupled to... Figure 4 408a multiplexer Figure 1 Multiplexer 108. In such an embodiment, as described above, digital data output 118 provides (actual) data signals or patterned data signals to the digital data input 810 and inverted data input 410 of multiplexer 408a as received digital data signals, based on an idle mode or data signal transmission mode. As described above, multiplexer 408a alternately provides received digital data signals or inverted digital data signals to digital data output 418 based on a counter 414a counting a threshold number of clock cycles. Thus, in some embodiments, proxy 802 combines Figure 1 and 4 Its features and advantages.

[0079] The computing environment 900 includes examples of environments for executing at least some of the computer code involved in performing the methods of the present invention, such as programmable communication protocol code block 1000. In addition to block 1000, the computing environment 900 includes, for example, a computer 901, a wide area network (WAN) 902, an end-user equipment (EUD) 903, a remote server 904, a public cloud 905, and a private cloud 906. In this embodiment, the computer 901 includes a processor group 910 (including processing circuitry 920 and a cache 921), a communication structure 911, volatile memory 912, persistent storage device 913 (including the operating system 922 and block 1000 as described above), a peripheral device group 914 (including a user interface (UI) device group 923, a storage device 924, and an Internet of Things (IoT) sensor group 925), and a network module 915. The remote server 904 includes a remote database 930. The public cloud 905 includes a gateway 940, a cloud orchestration module 941, a host physical unit 942, a virtual machine unit 943, and a container unit 944.

[0080] Computer 901 can take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or to be developed in the future capable of running programs, accessing networks, or querying databases such as remote database 930. As is well known in the field of computer technology, and depending on that technology, the execution of computer-implemented methods can be distributed among multiple computers and / or multiple locations. On the other hand, in this presentation of computing environment 900, the detailed discussion focuses on a single computer, specifically computer 901, to keep the presentation as simple as possible. Computer 901 can reside in the cloud, even... Figure 9 The document does not show that it is in the cloud; on the other hand, computer 901 does not need to be in the cloud unless to the extent that can be definitively indicated.

[0081] Processor group 910 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 920 may be distributed across multiple packages, such as multiple cooperating integrated circuit chips. Processing circuitry 920 may implement multiple processor threads and / or multiple processor cores. Cache 921 is memory located within the processor chip package(s) and is typically used for data or code that should be readily accessible by the threads or cores running on processor group 910. Cache memory is typically organized into multiple levels based on its relative proximity to the processing circuitry. Alternatively, some or all of the cache in the processor group may be located “off-chip.” In some computing environments, processor group 910 may be designed to work with qubits and perform quantum computing.

[0082] Computer-readable program instructions are typically loaded onto computer 901 to cause processor group 910 of computer 901 to perform a series of operational steps to implement a computer-implemented method, such that the instructions thus executed instantiate the method specified in the flowchart and / or the description of the computer-implemented method included in this document (collectively, the “method of the invention”). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 921 and other storage media discussed below. The program instructions and associated data are accessed by processor group 910 to control and direct the execution of the method of the invention. In computing environment 900, at least some of the instructions for performing the method of the invention may be stored in block 1000 of persistent storage 913.

[0083] The communication structure 911 is a signal transmission path that allows various components of the computer 901 to communicate with each other. Typically, this structure consists of switches and conductive paths, such as switches and conductive paths that form buses, bridges, physical input / output ports, etc. Other types of signal communication paths can be used, such as fiber optic communication paths and / or wireless communication paths.

[0084] Volatile memory 912 is any type of volatile memory now known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 912 is characterized by random access, but this is not necessary unless explicitly stated otherwise. In computer 901, volatile memory 912 is located in a single package and is internal to computer 901; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computer 901.

[0085] The persistent storage device 913 is any form of non-volatile storage for a computer, now known or to be developed in the future. The non-volatility of this storage device means that the stored data is retained regardless of whether power is supplied to the computer 901 and / or directly to the persistent storage device 913. The persistent storage device 913 may be a read-only memory (ROM), but typically at least a portion of the persistent storage device allows data to be written, deleted, and rewritten. Some common forms of persistent storage devices include hard disks and solid-state storage devices. The operating system 922 may take several forms, such as various known proprietary operating systems or operating systems employing an open-source portable operating system interface type with a kernel. The code included in block 1000 generally includes at least some of the computer code involved in performing the methods of the present invention.

[0086] Peripheral device group 914 includes a collection of peripheral devices for computer 901. Data communication connections between peripheral devices and other components of computer 901 can be implemented in various ways, such as Bluetooth connections, near field communication (NFC) connections, connections made by cables (such as Universal Serial Bus (USB) type cables), plug-in connections (e.g., Secure Digital (SD) cards), connections made through local area communication networks, and even connections made through wide area networks such as the Internet. In various embodiments, UI device group 923 may include components such as a display screen, speakers, microphones, wearable devices (e.g., goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage device 924 is external storage, such as an external hard drive, or pluggable storage, such as an SD card. Storage device 924 can be persistent and / or volatile. In some embodiments, storage device 924 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 901 requires substantial storage (e.g., where computer 901 locally stores and manages a large database), this storage can be provided by peripheral storage devices designed for storing very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor group 925 consists of sensors that can be used in IoT applications. For example, one sensor could be a thermometer, while another could be a motion detector.

[0087] Network module 915 is a collection of computer software, hardware, and firmware that allows computer 901 to communicate with other computers via WAN 902. Network module 915 may include hardware such as a modem or Wi-Fi transceiver, software for packetizing and / or depacketizing data transmitted over the communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control functions and network forwarding functions of network module 915 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN), the control functions and forwarding functions of network module 915 are executed on physically separate devices, such that the control functions manage several different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can typically be downloaded to computer 901 from an external computer or external storage device via a network adapter card or a network interface included in network module 915.

[0088] A WAN 902 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances using any technology now known or to be developed in the future for transmitting computer data. In some embodiments, a WAN 902 may be replaced by and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a local area such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0089] End User Equipment (EUD) 903 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 901) and can take any of the forms discussed above in conjunction with computer 901. EUD 903 typically receives useful and helpful data from the operation of computer 901. For example, assuming computer 901 is designed to provide recommendations to the end user, these recommendations are typically transmitted from network module 915 of computer 901 to EUD 903 via WAN 902. In this way, EUD 903 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 903 can be a client device, such as a thin client, a thick client, a mainframe computer, a desktop computer, etc.

[0090] Remote server 904 is any computer system that provides at least some data and / or functionality to computer 901. Remote server 904 can be controlled and used by the same entity operating computer 901. Remote server 904 represents a machine that collects and stores useful and beneficial data used by other computers, such as computer 901. For example, if computer 901 is designed and programmed to provide recommendations based on historical data, that historical data can be provided to computer 901 from a remote database 930 of remote server 904.

[0091] Public cloud 905 is any computer system that can be used by multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities (especially data storage (cloud storage) and computing power) without direct active management by the user. Cloud computing typically leverages resource sharing to achieve scalability consistency and economy. Direct and active management of the computing resources of public cloud 905 is performed by the computer hardware and / or software of cloud orchestration module 941. The computing resources provided by public cloud 905 are typically implemented by virtual computing environments running on various computers constituting host physical machine group 942, which is the entire set of physical computers in and / or available to public cloud 905. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine group 943 and / or containers from container group 944. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after instantiation of VCEs. The cloud coordination module 941 manages the delivery and storage of images, deploys new instantiations of VCE, and manages the instantiation of VCE deployment activities. Gateway 940 is a collection of computer software, hardware, and firmware that allows the public cloud 905 to communicate via WAN 902.

[0092] Now, we will provide some further explanation of Virtualized Computing Environments (VCEs). A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from this image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows multiple isolated user-space instances, called containers, to exist. From the perspective of the programs running within them, these isolated user-space instances typically appear as actual computers. Computer programs running on a regular operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices allocated to the container; this is a characteristic known as containerization.

[0093] Private cloud 906 is similar to public cloud 905, except that computing resources are only available for use by a single enterprise. While private cloud 906 is depicted as communicating with WAN 902, in other embodiments, private cloud can be completely disconnected from the internet and accessed only via a local / private network. Hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types) typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability across the multiple component clouds. In this embodiment, public cloud 905 and private cloud 906 are both part of a larger hybrid cloud.

[0094] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0095] In the foregoing, reference has been made to the embodiments presented in this disclosure. However, the scope of this disclosure is not limited to the specifically described embodiments. Rather, any combination of features and elements is contemplated for implementing and practicing the intended embodiments, regardless of whether different embodiments are involved. Furthermore, while the embodiments disclosed herein may achieve advantages over other possible solutions or prior art, whether a given embodiment achieves a particular advantage does not limit the scope of this disclosure. Therefore, the aspects, features, embodiments, and advantages discussed herein are merely illustrative and should not be considered as elements or limitations of the appended claims unless expressly stated in claim(s). Similarly, references to “the invention” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered as elements or limitations of the appended claims unless expressly stated in claim(s).

[0096] Various aspects of the present invention may take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may be collectively referred to herein as a “circuit,” a “module,” or a “system.”

[0097] While the foregoing relates to embodiments of the present invention, other and further embodiments of the present invention may be designed without departing from the basic scope of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A method for data communication, comprising: Receive digital data signals through the first data input of the transmitter multiplexer; The digital data signal is inverted by the first inverter, thereby providing an inverted digital data signal; The inverted digital data signal is received through the first inverted data input of the transmitter multiplexer; The clock signal is counted using the first counter; The first selection signal is transmitted to the first selection signal input of the transmitter multiplexer by counting clock cycles of a threshold number in response to the first counter. as well as In response to the first selection signal and through the first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal are alternately transmitted to the receiver as transmitter multiplexer output signals, and the receiver and the first digital data signal output are operatively coupled to a data link.

2. The method of claim 1, wherein the receiver comprises a second counter and a receiver multiplexer, the receiver multiplexer being configured to receive the transmitter multiplexer output signal, the method further comprising: The transmitter multiplexer output signal is received through the second data input of the receiver multiplexer; The transmitter multiplexer output signal is inverted by the second inverter, thereby providing an inverted transmitter multiplexer output signal; The inverted transmitter multiplexer output signal is received through the second inverted data input of the receiver multiplexer; The clock signal is counted using a second counter; The second selection signal is transmitted to the second selection signal input of the receiver multiplexer by counting the number of clock cycles of the threshold number through the second counter and in response to the second counter. as well as In response to the second selection signal and through the second digital data signal output of the receiver multiplexer, the transmitter multiplexer output signal and the inverted transmitter multiplexer output signal are alternately provided.

3. The method of claim 1, wherein the counting step via the first counter comprises counting each occurrence of a clock cycle of the count of the threshold number via the first counter, and providing the first selection signal in response to each occurrence of a clock cycle of the count of the threshold number.

4. The method of claim 2, wherein the counting step via the first counter comprises counting each occurrence of a clock cycle of the count of the threshold number via the first counter, and providing the first selection signal in response to each occurrence of a clock cycle of the count of the threshold number, and the counting step via the second counter comprises counting each occurrence of a clock cycle of the count of the threshold number via the second counter, and providing the second selection signal in response to each occurrence of a clock cycle of the count of the threshold number.

5. The method according to claim 2, further comprising synchronizing the first counter and the second counter.

6. The method of claim 1, wherein the first processor includes the transmitter multiplexer.

7. The method of claim 2, wherein the first processor includes the transmitter multiplexer, and the second processor includes the receiver multiplexer.

8. The method according to claim 1, further comprising: The third digital data signal is received through the third data signal input of the third multiplexer; The third digital data signal is transmitted to the transmitter multiplexer through the third digital data signal output of the third multiplexer; The mode selection signal is received by the mode selection input of the third multiplexer, and the mode selection signal indicates idle mode or data signal transmission mode. The data pattern input of the third multiplexer receives a styled data signal; as well as In response to the mode selection signal, the third digital data signal or the patterned data signal is selectively output to the transmitter multiplexer via the third digital data signal output of the third multiplexer, as the digital data signal received via the first data input of the transmitter multiplexer.

9. A system for data communication, comprising: A first inverter arranged for receiving digital data signals, a clock, a first counter operably coupled to the clock, and a transmitter multiplexer, the transmitter multiplexer comprising: A first data input, configured to receive digital data signals. A first inverted data input, operatively coupled to the first inverter and arranged to receive an inverted digital data signal, A first selection signal input, operatively coupled to the first counter and arranged to receive a first selection signal, and A first digital data signal output is provided, which is configured to transmit the transmitter multiplexer output signal. The first counter is adapted to provide the first selection signal in response to a clock cycle counting a threshold number, so that the transmitter multiplexer alternately transmits the digital data signal and the inverted digital data signal as the transmitter multiplexer output signal.

10. The system of claim 9, further comprising a second inverter, a second counter, a receiver multiplexer, and a data link operatively coupled to the transmitter multiplexer and the receiver multiplexer, the receiver multiplexer comprising: The second data input is configured to receive the transmitter multiplexer output signal. A second inverted data input, operatively coupled to the second inverter and arranged to receive the inverted transmitter multiplexer output signal, A second selection signal input, operatively coupled to the second counter and arranged to receive a second selection signal, and A second digital data signal output, configured to provide the receiver multiplexer output signal. The second counter is adapted to provide the second selection signal in response to a clock cycle of counting the threshold number, such that the receiver multiplexer alternately provides the transmitter multiplexer output signal and the inverted transmitter multiplexer output signal as the receiver multiplexer output signal.

11. The system of claim 10, further comprising a processor operatively coupled to a computer-readable storage medium having computer-readable program code embodied therein, the computer-readable program code being executable by the processor to synchronize the first counter and the second counter.

12. The system of claim 9, wherein the first processor includes the transmitter multiplexer.

13. The system of claim 10, wherein the first processor includes the transmitter multiplexer, and the second processor includes the receiver multiplexer.

14. The system of claim 12, wherein the first processor further comprises the first inverter, the clock, and the first counter.

15. The system of claim 13, wherein the first processor further includes the first inverter, the clock, and the first counter, and the second processor further includes the second inverter and the second counter.

16. The system of claim 9, wherein the first counter is a programmable counter adapted to change a threshold number of clock cycles in response to the programmable counter counting to provide the first selection signal.

17. The system of claim 10, wherein the first counter is a first programmable counter adapted to change a threshold number of clock cycles in which the first programmable counter responds to a count providing the first selection signal, and the second counter is a second programmable counter adapted to change a threshold number of clock cycles in which the second programmable counter responds to a count providing the second selection signal.

18. The system according to claim 9, further comprising: A memory that holds data for generating patterned data signals; as well as A third multiplexer, comprising: A third data signal input, configured to receive a third digital data signal. A styled data signal input, wherein the styled data signal input is configured to receive styled data signals. A mode selection signal input, wherein the mode selection signal input is configured to receive a mode selection signal, and A third digital data signal output is configured to transmit a third multiplexer output signal to the first data input and the input of the first inverter of the transmitter multiplexer. The third multiplexer is adapted to selectively output the third digital data signal or the styled data signal as the output signal of the third multiplexer in response to receiving the mode selection signal, wherein the mode selection signal indicates an idle mode or a data signal transmission mode.

19. The system of claim 18, wherein the processor includes the transmitter multiplexer, the third multiplexer, and the memory.

20. The system of claim 19, wherein the memory includes a processor register that stores data for generating the styled data signal.

21. A computer program product comprising program code adapted to perform the method steps of any one of claims 1 to 8 when the program is run on a computer.

Images