Methods of forming oxide-nitride-oxide stacks for non-volatile memory and integration with CMOS process flows

Abstract

A method of manufacturing a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride-oxide (ONO) stack over a substrate in an in situ atomic layer deposition (ALD) tool or chamber. A radical oxidation or oxide deposition process step is performed to form a tunnel dielectric layer overlying the substrate. A silicon nitride deposition process step is also performed to form a multi-layer charge trapping (CT) layer, wherein at least some process parameters of the silicon nitride deposition process step are adjusted in forming a first CT sub-layer and a second CT sub-layer of the multi-layer CT layer. Subsequently, a radical oxidation or oxide deposition process step is performed in the ALD tool to form a barrier dielectric layer overlying the multi-layer CT layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is an international application of U.S. non-provisional application No. 17 / 954,141 filed on September 27, 2022, and the contents of the above-mentioned U.S. non-provisional application are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to non-volatile memory (NVM) cells or devices, and more particularly to silicon (semiconductor)-oxide-nitride-oxide-silicon (semiconductor) (SONOS) based NVM cells or devices and methods of manufacturing the same. Background Art

[0004] NVM is widely used to store data in computer systems, typically including memory arrays with a large number of NVM cells arranged in rows and columns or other configurations. Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the evolving semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased within the limited space of a semiconductor chip. However, the quest for greater capacity is not without its problems. The necessity to optimize the performance of each device while scaling becomes increasingly important.

[0005] In some embodiments, the NVM cell may include at least a nonvolatile element, such as a charge trapping field effect transistor (FET), a floating gate transistor, which is programmed or erased by applying a voltage of appropriate polarity, magnitude, and duration between a control / storage gate and a substrate or drain / source region. For example, in an n-channel charge trapping FET, a positive gate-substrate voltage causes electrons to tunnel from the channel and be trapped in a charge trapping dielectric layer via Fermi-Nordheim (FN) tunneling, thereby increasing the transistor threshold voltage (V T ) or reduce its drain current (I D ). A negative gate-channel voltage causes holes to tunnel from the channel and be trapped in the charge trapping dielectric layer, thereby reducing the V T Or improve its I D In some embodiments, a SONOS-based memory array is used and operated as a digital data storage device, wherein two different V based on SONOS cells are stored. T or I D The level or value of the binary bits (0 and 1) of data.

[0006] There is a need to use NVM technology such as SONOS for analog memory and processing because it has multiple different VT and I D (more than two) levels. SONOS memory cells offer the low latency, low power, and low noise operation expected for analog processing, including edge inference computing, such as neuromorphic computing in artificial intelligence (AI) applications. However, multi-polar SONOS memory cells may cause more difficulties when scaling, such as charge retention in the ONO stack, V T degradation and / or migration.

[0007] It is therefore an object of the present invention to propose an improved manufacturing process for forming an ONO stack in a SONOS memory cell; and to integrate such a process into a baseline complementary metal oxide semiconductor (CMOS) process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be more fully understood from the following detailed description and the accompanying drawings and claims provided below, in which:

[0009] Figure 1 is a block diagram showing a cross-sectional side view of a SONOS-based non-volatile memory transistor or device;

[0010] Figure 2A is a representative flow chart illustrating an embodiment of a method of fabricating an oxide-nitride-oxide (ONO) stack in a SONOS-based nonvolatile memory transistor according to an embodiment of the present disclosure;

[0011] Figure 2B is a representative diagram illustrating an example of an atomic layer deposition (ALD) chamber or tool;

[0012] FIG. 3A to FIG. 3D It is shown that according to Figure 2A a representative view of a cross-sectional view of a tunnel dielectric portion of a SONOS-based non-volatile memory transistor during fabrication of the method;

[0013] FIG. 4A to FIG. 4E It is shown that according to Figure 2A a representative view of a cross-sectional view of a charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during fabrication of the method;

[0014] FIG. 5A to FIG. 5D It is shown that according to Figure 2A a representative view of a cross-sectional view of a top or blocking dielectric portion of a SONOS based non-volatile memory transistor during fabrication of the method of;

[0015] Figure 5E is a representative diagram showing a cross-sectional view of a memory stack of a floating gate memory transistor including an ONO blocking dielectric stack according to an embodiment of the present disclosure;

[0016] Figure 6 is a block diagram illustrating a cross-sectional side view of a portion of a SONOS-based non-volatile memory cell or device according to an embodiment of the present disclosure;

[0017] Figure 7 is a representative flow chart illustrating an embodiment of a manufacturing method for integrating a SONOS-based memory transistor into a MOS transistor process flow according to an embodiment of the present disclosure; and

[0018] FIG. 8A to FIG. 8E It shows that according to Figure 7 A representative diagram of a cross-sectional view of a portion of a SONOS-based memory device of the method. DETAILED DESCRIPTION

[0019] The following description sets forth many specific details, such as examples of specific systems, components, methods, etc., in order to provide a good understanding of several embodiments of the present subject matter. However, it will be apparent to those skilled in the art that at least some embodiments may be put into practice without these specific details. In other cases, known components or methods are not described in detail or presented in a simple block diagram format to avoid unnecessarily obscuring the technology described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may be different from these exemplary details and are still considered to be within the spirit and scope of the present subject matter.

[0020] Embodiments of memory cells with or without metal oxide semiconductor (MOS) transistors or field effect transistors (FETs) including SONOS-based transistors and methods of manufacturing the same are described herein with reference to the accompanying drawings. However, specific embodiments may be practiced without one or more of these specific details or in combination with other known methods, materials, and devices in the relevant art. In the following description, many specific details, such as specific materials, dimensions, concentrations, and process parameters, are set forth to provide a thorough understanding of the subject matter. In other cases, well-known semiconductor design and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the subject matter. The “embodiment”, “one embodiment”, “example embodiment”, “some embodiments”, and “various embodiments” mentioned in the specification mean that the specific features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the subject matter. In addition, the phrases “embodiment”, “one embodiment”, “example embodiment”, “some embodiments”, and “various embodiments” appearing in different places in the specification do not necessarily refer to the same embodiment.

[0021] The specification includes references to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show diagrams according to exemplary embodiments. These embodiments, which may also be referred to as "examples" herein, are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0022] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one layer relative to other layers. Thus, for example, a layer deposited or disposed above or below another layer may be directly in contact with the other layer, or may have one or more intervening layers. Additionally, a layer deposited or disposed between layers may be directly in contact with the layers, or may have one or more intervening layers. Furthermore, the relative position of one layer relative to other layers is provided assuming that the operations of depositing, modifying, and removing films relative to a starting substrate are performed without regard to the absolute orientation of the substrate.

[0023] Unless otherwise specifically noted, as will be apparent from the following discussion, it should be understood that terms such as "processing," "computing," "calculating," "determining," and the like are used throughout the specification to refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate data represented as physical (e.g., electronic) quantities within the computing system's registers and / or memories, and / or transform that data into other data similarly represented as physical quantities within the computing system's memories, registers, or other such information storage, transmission, or display devices.

[0024] Summary of the subject matter

[0025] According to one embodiment of a method for manufacturing a semiconductor device, the method may include the following steps: dividing a substrate into a first region and a second region, and forming a customizable oxide-nitride-oxide (ONO) stack in the first region; performing at least one of a first radical oxidation process step and a first oxide deposition process step in an atomic layer deposition (ALD) tool to form a tunnel dielectric layer covering the substrate; performing multiple silicon nitride deposition process steps in the ALD tool to form a multi-layer charge trapping (CT) layer; determining process parameters of a first silicon nitride deposition process step in multiple silicon nitride deposition process steps to form a first CT sublayer; modifying at least one of the process parameters; performing a second silicon nitride deposition process step to form a second CT sublayer covering the first CT sublayer; and performing at least one of a second radical oxidation process step and a second oxide deposition process step in the ALD tool to form a blocking dielectric layer covering the multi-layer CT layer in the first region.

[0026] In one embodiment, the formed silicon nitride may include silicon oxynitride containing oxygen.

[0027] In one embodiment, the customizable ONO stack formation process steps are performed in-situ in the same ALD tool.

[0028] In one embodiment, the film composition of silicon, oxygen and nitrogen of silicon nitride in the first CT sub-layer and the second CT sub-layer is different. In one embodiment, the first CT sub-layer is oxygen-rich silicon nitride, resulting in it being substantially free of charge traps, while the second CT sub-layer is oxygen-poor silicon nitride, resulting in it being substantially charge trap-rich.

[0029] According to an embodiment of the method for manufacturing a semiconductor device, the method may further include a step of performing a plurality of third silicon nitride deposition process steps to form a plurality of third CT sublayers disposed between the first CT sublayer and the second CT sublayer, in which the process parameters of the plurality of third silicon nitride deposition process steps are adjusted so that the oxygen enrichment levels of the plurality of third CT sublayers are between the oxygen enrichment levels of the first CT sublayer and the second CT sublayer. In an embodiment, the method further includes performing at least one of a third radical oxidation process step and a third oxide deposition process step in the same ALD tool to form a thin oxide film covering the first CT sublayer and below the second CT sublayer, wherein the thin oxide film is formed to reduce electron charges accumulated at the boundary of the second CT layer from tunneling into the first CT layer.

[0030] In one embodiment, the process parameters of the first free radical oxidation process step and the second free radical oxidation process step may include: 2 / H 2The process parameters include the type of reactant gas; the flow rate of the reactant gas entering the ALD tool; the reaction time for each reactant gas; the order in which the reactant gases enter the ALD tool; and the number of repetitions and the order of repetitions, wherein the process parameters are configured to: control at least one of the thickness, density, and quality of the oxide formed in the tunnel dielectric layer.

[0031] In one embodiment, the process parameters of the first oxide deposition process step and the second oxide deposition process step may include: the type of silicon source precursor gas including HCD; 2 / H 2 The type of reactive gas; the flow rate of the reactive gas and the silicon source precursor gas; the reaction time for each of the reactive gas and the silicon source precursor gas; and the order in which the reactive gas and the silicon source precursor gas enter the ALD tool, wherein the process parameters are configured to: control at least one of the thickness, density, and quality of the oxide formed in the blocking dielectric layer.

[0032] In one embodiment, the process parameters of the first silicon nitride deposition process step and the second silicon nitride deposition process step may include: the type of silicon source precursor gas including HCD; 3 / N 2 The type of O gas reaction gas; the flow rate of the reaction gas and the silicon source precursor gas; and the reaction time for each of the reaction gas and the silicon source precursor gas; the order in which the reaction gas and the silicon source precursor gas enter the ALD tool; and the number of repetitions and the repetition order.

[0033] In one embodiment, at least one silicon nitride deposition process step in the plurality of silicon nitride deposition process steps may be plasma enhanced.

[0034] In one embodiment, the first radical oxidation process step and the first oxide deposition process step may be repeated alone, alternately, or in combination to form a tunnel dielectric layer, and the second radical oxidation process step and the second oxide deposition process step may be repeated alone, alternately, or in combination to form a blocking dielectric layer, wherein process parameters of the first radical oxidation process step and the second radical oxidation process step and the first oxide deposition process step and the second oxide deposition process step are adjusted during the repeated process steps to customize the tunnel dielectric layer and the blocking dielectric layer.

[0035] According to one embodiment of the method for manufacturing a semiconductor device, the method further includes: a step of forming a high voltage (HV) gate oxide layer, an input / output (I / O) gate oxide layer, and a low voltage (LV) gate oxide layer in a second region of the substrate, wherein a blocking dielectric layer of the customizable ONO layer in the first region and at least one of the HV gate oxide layer, the I / O gate oxide layer, and the LV gate oxide layer are simultaneously formed by at least one of a second radical oxidation process step and a second oxide deposition process step.

[0036] In one embodiment, the multi-layer CT layer may include at least three CT sub-layers, and wherein process parameters of multiple silicon nitride deposition process steps are modified so that a top CT sub-layer adjacent to the blocking dielectric layer in the multi-layer CT layer is the most oxygen-poor, and a bottom CT sub-layer adjacent to the tunnel dielectric layer is the most oxygen-rich.

[0037] According to one embodiment of a method for manufacturing a memory device, the method may include the following steps: forming a tunnel oxide layer in a memory region and a logic region of a substrate; forming a customizable charge trapping (CT) layer and a cap layer covering the tunnel oxide layer, wherein the customizable CT layer includes a plurality of CT sublayers, and wherein each of the CT sublayers is formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber; patterning the tunnel oxide layer, the customizable CT layer, and the cap layer to form a memory stack in the memory region while removing these layers in the logic region; and performing at least one radical oxidation process step in the ALD chamber to simultaneously: convert at least the silicon nitride in the cap layer to form a blocking oxide layer covering the customizable CT layer, and convert silicon in the substrate to form a first gate oxide layer in the logic region.

[0038] In one embodiment, the method may further include the step of performing at least one oxide deposition process step in an ALD chamber to simultaneously increase the thickness of the first gate oxide layer and the blocking oxide layer in the logic region.

[0039] In one embodiment, the process parameters of one or more silicon nitride deposition process steps may include: the type of silicon source precursor gas including HCD, the type of silicon source precursor gas including NH 3 / N 2 The type of O gas reaction gas, the flow rate of the reaction gas and the silicon source precursor gas, the reaction time for each of the reaction gas and the silicon source precursor gas, and the order in which the reaction gas and the silicon source precursor gas enter the ALD chamber.

[0040] In one embodiment, process parameters of one or more silicon nitride deposition process steps may be adjusted to produce CT sublayers having different thicknesses, densities, and at least one of film compositions of Si, O, and N of the silicon nitride in the CT sublayers.

[0041] According to one embodiment of a method for manufacturing a SONOS-based memory device, the method may include the step of forming a memory cell including a SONOS transistor and a pass transistor in a memory region of a substrate, the step including: forming a tunnel oxide layer in the memory region and a logic region of the substrate; forming a customizable charge trapping (CT) layer and a capping layer covering the tunnel oxide layer, wherein the customizable CT layer includes a plurality of CT sub-layers, and wherein each of the CT sub-layers is formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber; patterning the tunnel oxide layer, the customizable CT layer, and the capping layer to form a memory stack in the memory region while removing these layers in the logic region; and forming a blocking oxide layer covering the customizable CT layer and a first gate oxide of the pass transistor in the memory region; the method also includes the step of forming a HV gate oxide layer of a high voltage (HV) transistor, an I / O gate oxide layer of an input / output (I / O) transistor, and a LV gate oxide layer of a low voltage (LV) transistor in the logic region. In one embodiment, at least one of the HV gate oxide, the I / O gate oxide, and the LV gate oxide is formed at least in part by performing at least one radical oxidation process step in an ALD chamber to simultaneously perform the following operations: in a storage region, at least silicon nitride in a cap layer is converted to form a blocking oxide layer and silicon is converted to form a first gate oxide, and in a logic region, silicon in a substrate is converted to at least partially form at least one of the HV gate oxide layer, the I / O gate oxide layer, and the LV gate oxide.

[0042] In one embodiment, the method may further include the step of performing at least one oxide deposition process step in the ALD chamber to simultaneously increase the thickness of the blocking oxide layer and the first gate oxide layer in the storage region.

[0043] In one embodiment, the pass transistor and the HV transistor may be of the same type, and wherein the first gate oxide and the HV gate oxide are formed simultaneously and have approximately the same thickness.

[0044] In one embodiment, process parameters of one or more silicon nitride deposition process steps may be adjusted to produce CT sub-layers having different film compositions of Si, O, and N of the silicon nitride, and wherein, in a customizable CT layer, the top CT sub-layer is the most oxygen-poor and the bottom CT sub-layer is the most oxygen-rich.

[0045] In one embodiment, the oxide deposition process step, the radical oxidation process step, and the silicon nitride deposition process step are performed in-situ in an ALD chamber, and the process temperature is controlled to be less than 650°C.

[0046] In one embodiment, the method may further include the step of forming a high-K metal gate (HKMG) covering the blocking oxide of the SONOS transistor and the first gate oxide layer of the pass transistor.

[0047] Description of Embodiments

[0048] Figure 1 is a block diagram showing a cross-sectional side view of a SONOS-based NVM device. Figure 1 In one embodiment shown, NVM transistor 100 is configured to store a binary value (“0” or “1”) or a multi-level analog value (e.g., 0 to 2) corresponding to the amount and polarity of trapped charge it holds. n -1) SONOS type charge trapping NVM transistor. Figure 1 , the NVM cell 90 includes a storage gate (MG) stack 150 formed above a substrate 102. The NVM transistor 100 also includes source / drain regions 104 formed in the substrate 102 or, alternatively, in a shallow positive well (SPW - not shown) in the substrate 102, on either side of the MG stack 150. The SPW may be at least partially encapsulated in a deep negative well (DNW - not shown). In one embodiment, the source / drain regions 104 are connected by a channel region 116 below the MG stack 150. The NVM transistor 100 includes a tunnel dielectric layer 106, a charge trapping layer 108, and a blocking dielectric layer 110, thereby forming an ONO stack 120. In one embodiment, the charge trapping layer 108 may be multi-layered and captures charge injected from the substrate 102 by FN tunneling or other mechanisms. The V T and I D The value may vary due at least in part to the amount and polarity of trapped charge. In one embodiment, a high-K dielectric layer may form at least a portion of the blocking dielectric layer 110. A polysilicon (poly) or metal gate layer 112 is provided to cover the ONO stack 120 and may be used as a control gate (CG) or a memory gate (MG). The NVM transistor 100 may also include a spacer 114 for providing electrical insulation to adjacent devices or other devices.

[0049] In various embodiments, the ONO stack 120 may be formed by a series of (thermal and / or free radical and / or other) oxidation, (physical, chemical, etc.) deposition, etching and / or cleaning process steps. These process steps may be performed in a single process chamber / tool ​​or multiple process chambers / tools. In some embodiments, the current ONO process limits the compositional variation that can be achieved in the thin layer of the SONOS stack, which is very important in advanced technology nodes such as 22nm or below. The current ONO formation process / tool ​​may also suffer from marginality with respect to the uniformity of film stoichiometry and thickness (e.g., wafer-to-wafer (WTW) thickness and wafer-in-wafer (WIW) thickness). This may adversely affect productivity and the quality of the ONO stack by limiting the batch size to about 50 wafers and reducing the production capacity of the manufacturing plant for related products. In advanced technology nodes, the thermal budget of some ONO processes such as in-situ steam generation (ISSG) oxidation, dry or wet oxidation in a furnace, chemical vapor deposition of oxides and nitrides, etc. may be too high. The high thermal budgets of these processes may be sufficient to significantly change the baseline CMOS device parameters, which in turn may require changes to the model of the baseline FET.

[0050] Figure 2A FIG. 1 is a diagram showing a method of manufacturing a SONOS-based nonvolatile memory transistor (eg, Figure 1 A representative flow chart of an embodiment of a method for forming an oxide-nitride-oxide (ONO) stack in an NVM transistor 100 in FIG. Figure 2A and Figure 3A The process may begin with a series of pre-steps (step 202) including forming a plurality of isolation structures or shallow trench isolations (STI) 301 in a wafer or substrate 302. In some embodiments, the pre-steps may also include forming trenches such as Figure 1 Channel 116, Figure 1 The source / drain 104 in the substrate 303, and / or the deep well and / or well. Various processes including pad oxide formation, wet / dry etching or cleaning, tunnel mask application, and dopant implantation can be performed according to the practice of ordinary technicians in the field. It will be understood that the above-mentioned pre-step or other pre-steps may not be performed or may be partially performed before forming the tunnel dielectric layer. Subsequently, a pre-cleaning process is performed on the substrate surface 303 to remove the pad oxide (if present) and / or other residual oxides, which can be a wet or dry process. In one embodiment, it can be a wet process using HF followed by standard cleaning (SC1) and (SC2), and is highly selective to the material of the substrate 302.

[0051] Refer to Figure 2 and Figure 3B , ONO layer such as Figure 1 The ONO stack 120, best shown in FIG. 1 , begins with forming a tunnel dielectric in step 204. The tunnel dielectric can be any material and have any thickness suitable for enabling charge carriers to tunnel into an overlying charge trapping layer under an applied gate bias while maintaining an appropriate leakage barrier when the transistor is not biased. In certain embodiments, the tunnel dielectric can be silicon dioxide, silicon nitride such as oxynitride, or a combination thereof, and can be deposited and / or grown by a thermal oxidation process in a furnace using ISSG or free radical oxidation. As previously described, the above process can be used to form very thin (e.g., less than 1000 Å) films with uniform film stoichiometry and WTW / WIW thickness under a thermal budget of less than 650°C. ) is a challenge. In one embodiment, which may be referred to as a preferred embodiment, the multi-layer silicon oxide tunnel dielectric layer 306 can be formed in a single in-situ atomic layer deposition (ALD) chamber that is capable of free radical oxidation, thermal ALD, or plasma enhanced ALD (PEALD) using batch or single tools. In one embodiment, both the free radical oxidation and ALD deposition processes can be performed in the same ALD chamber. The sequential, self-limiting surface reaction nature of ALD deposition and free radical oxidation facilitates film thickness and uniformity control with atomic-level precision at relatively low thermal budgets (e.g., less than 650°C). Reference Figure 2B , an example of an ALD chamber or tool 90 is shown. The ALD chamber 90 may be a batch processing tool in which multiple wafers (substrates) may be processed simultaneously. A precursor gas such as HCD may be introduced as a silicon source. Other reactive gases such as ammonia or nitrous oxide may be enhanced by a plasma source such as an inductively coupled plasma (ICP) before entering the chamber through a buffer nozzle with an electrode. Other reactive gases such as H 2 / O 2 It can be introduced by a cross-flow ejector. It will be appreciated that Figure 2B The ALD chamber 90 best shown in the figure is merely an example of an ALD tool capable of performing free radical oxidation, thermal ALD, and PEALD processes and should not be construed as limiting, and other ALD tools capable of performing the free radical oxidation and ALD deposition disclosed in this patent document may be used depending on manufacturing requirements and other considerations.

[0052] Reference Figure 3B In one embodiment, the tunnel dielectric sublayer 306a is formed by free radical oxidation in an ALD chamber. This process involves oxidizing the reactant hydrogen (H) without an external ignition event such as forming a plasma. 2 ) and oxygen (O 2 ) flows into the ALD chamber at a ratio of approximately 1:4 or other configurable ratios. 2 and O2 The reaction is performed at a temperature approximately in the range of about 300° C. to about 650° C. and a pressure approximately in the range of about 0.5 Torr to about 10 Torr to form radicals such as OH radicals, HO radicals, etc. at the surface of the substrate 302. 2 The free radicals or O diradicals are formed and eventually directly react with and consume a portion of the exposed surface of the silicon substrate 302. In one embodiment, an example process / operation table for performing free radical oxidation in an ALD chamber is as follows:

[0053] Table 1:

[0054] gas Flow rate (sccm) Time (seconds) <![CDATA[N 2 ]]> 1000 4 <![CDATA[O 2 ]]> 4000 3 <![CDATA[H 2 / THE 2 ]]> 900 / 4000 60 <![CDATA[O 2 ]]> 4000 3 <![CDATA[N 2 ]]> 1000 4

[0055] The thickness, quality and uniformity of the formed tunnel dielectric sublayer 306a may be fine-tuned or customized by modifying or adjusting the process gas sequence, flow rate, order, duration, temperature, gas flow ratio or other process parameters as required by the device being manufactured.

[0056] Reference Figure 3C , the tunnel dielectric sublayer 306b may also be formed using a deposition workflow in the same or similar ALD chamber. In one embodiment, a chlorosilane such as hexachlorodisilane Si 2 Cl 6 (HCD) can be a precursor gas or a silicon source gas. In the absence of an external ignition event such as forming a plasma, hydrogen (H 2 ) and oxygen (O 2 ) flows into the ALD chamber at a ratio of approximately 1:4. H 2 and O 2 The reaction is performed at a temperature approximately in the range of about 300° C. to about 400° C. and a pressure approximately in the range of about 0.5 Torr to about 10 Torr to form free radicals such as OH radicals, HO 2 The free radicals or O diradicals eventually react with HCD to form deposited silicon oxide above the surface of substrate 302. During the same process, the generated free radicals may also react directly with silicon substrate 302 to form silicon oxide, as in the free radical oxidation explained above. In one embodiment, an example process / operation table for performing silicon oxide deposition in an ALD chamber is as follows:

[0057] Table 2:

[0058] gas Flow rate (sccm) Time (seconds) HCD 200 3 <![CDATA[N 2 ]]> 1000 4 <![CDATA[O 2 ]]> 4000 3 <![CDATA[H 2 / THE 2 ]]> 900 / 4000 4 <![CDATA[O 2 ]]> 4000 3 <![CDATA[N 2 ]]> 1000 4

[0059] As with free radical oxidation, the thickness, quality, and uniformity of the formed tunnel dielectric sublayer 306b can be fine-tuned or customized by modifying the process gas sequence, flow rate, duration, temperature, gas flow ratio, or other process parameters as required by the device being manufactured. In one embodiment, the tunnel dielectric layers 306a and 306b produced in the free radical oxidation process or ALD deposition process can be denser and have more than 100 nanometers per cubic centimeter (cm3) than tunnel dielectrics otherwise formed by wet oxidation techniques, even at reduced thickness. 3 ) is composed of substantially fewer hydrogen atoms. The thickness of the tunnel dielectric layer 306, especially the thickness around the STI corner, is uniform, which can reduce the non-uniformity of FN implantation at the corner of the STI 301 of the final SONOS device, thereby making I D or V T The sigma of is reduced.

[0060] In an embodiment, free radical oxidation such as described in Table 1 and ALD oxidation deposition such as described in Table 2 may be repeated individually with or without modification of process parameters, alternately with or without modification of process parameters, in combination of the two, or in any specified order to produce multiple tunnel dielectric sublayers 306a to 306d. Each sublayer may be formed by only one or more free radical oxidation process steps (e.g., as in Table 1 or modified), only one or more ALD oxidation deposition steps (as in Table 2 or modified), or a combination thereof until a predetermined thickness is reached; and each sublayer may be formed down to or less. Figure 3D As best shown in FIG. 3 , the final tunnel dielectric layer 306 is a stack of multiple tunnel dielectric sub-layers 306a to 306d. By controlling and adjusting process parameters such as flow rate, reactants, duration, temperature, etc. in the free radical oxidation process step and the ALD deposition process step, a tunnel dielectric layer 306 with a customizable desired thickness (WTW and WIW), uniformity, oxide-silicon substrate interface conditions, film stoichiometry, etc. can be achieved. It will be understood that Figure 3D The 4-sublayer tunnel dielectric layer 306 shown in FIG. 1 is merely an example for illustrating the proposed ALD oxidation / deposition method and should not be construed as limiting. The tunnel dielectric layer 306 may have one or more sublayers, and each sublayer may have a different thickness, film stoichiometry, density, or other physical and chemical properties by fine-tuning the ALD radical oxidation and deposition process steps. In one embodiment, the tunnel dielectric layer 306 may be formed to a thickness of about to within the range.

[0061] 2, in step 204, multiple layers of silicon nitride or oxynitride (Si x O y N z ) charge trapping layer. In embodiments, the silicon nitride or oxynitride may have different proportions of silicon (x), oxygen (y), and nitrogen (z) in the formed film. The charge trapping layer may be composed of a material and have a thickness suitable for storing charge and thereby changing the threshold voltage of a subsequently formed SONOS device. Figure 4A The charge trapping dielectric sublayer 308a is formed in the same or similar in-situ ALD chamber used for the tunnel dielectric layer 306. In one embodiment, the process involves using precursor gases HCD as a silicon source, ammonia (NH ) as a nitrogen source, and 3 ) and nitrous oxide (N 2 O) flow. In other embodiments, other chlorosilane gases may be used as silicon sources, and other nitrogen source gases or oxygen source gases may be used, according to the practice of one of ordinary skill in the art. In another embodiment, the ammonia or nitrous oxide gas may be plasma enhanced prior to introduction into the ALD chamber to potentially achieve higher silicon nitride deposition rates and better uniformity at low temperatures. In one embodiment, the ALD deposition process of silicon nitride is performed at 650°C, which is lower than most thermal and chemical vapor deposition processes. In one embodiment, a low temperature of up to 100°C may be formed in the ALD chamber. An example process / operation table for performing silicon nitride deposition in an ALD chamber is as follows:

[0062] Table 3:

[0063] gas Flow rate (sccm) Time (seconds) HCD 232 or 200 or 196 3 <![CDATA[N 2 ]]> 1000 4 <![CDATA[NH 3 / N 2 O]]> 18 / 64 or 18 / 100 or 98 / 14 3 <![CDATA[N 2 ]]> 1000 4

[0064] Similar to the silicon oxide ALD process described above, the thickness, uniformity, oxygen, nitrogen and / or silicon ratio in the formed silicon nitride can be tailored to produce a customizable charge trapping dielectric sublayer 308a. In one embodiment, the silicon nitride ALD process can leave the already formed tunnel dielectric layer 306 substantially unaffected. Figure 4B , another charge trapping dielectric sublayer 308b may be formed on the charge trapping dielectric sublayer 308a. In one embodiment, the charge trapping dielectric sublayer 308b may be formed in the same ALD chamber using the process parameters described in Table 3 or any modified process parameters. For example, N may be increased. 2 The flow rate and / or flow time of the O gas may be adjusted or otherwise increased or decreased to produce a silicon-rich nitride layer and a nitrogen-rich nitride layer, respectively. Figure 4C, a further charge trapping dielectric sublayer 308c may be formed on the charge trapping dielectric sublayer 308b using an ALD deposition process similar to that described in Table 3, with or without modifying the process parameters. In one embodiment, the charge trapping dielectric sublayers 308a to 308c may collectively form the charge trapping dielectric layer 308 of the finished SONOS device. It will be appreciated that Figure 4C The three-layer charge trapping dielectric layer 308 shown in the figure is only an example for illustrating the proposed silicon nitride ALD deposition method and should not be construed as limiting. The charge trapping dielectric layer 308 may have one or more sub-layers, and each sub-layer may have different thicknesses, film compositions of Si, O, and N in silicon nitride, or other physical and chemical properties by fine-tuning the ALD deposition process. In one embodiment, the charge trapping dielectric layer 308 may be a multi-layer silicon nitride with an oxygen-rich gradient increasing from top to bottom, wherein the top sub-layer 308c is the silicon nitride sub-layer with the least oxygen content, and the bottom sub-layer 308a is the silicon nitride sub-layer with the most oxygen content.

[0065] As used herein, the terms "oxygen-rich" and "silicon-rich" are relative to the compositions (Si 3 N 4 ) and a refractive index (RI) of about 2.0 for stoichiometric silicon nitride. Therefore, "oxygen-rich" silicon nitride necessarily shifts from stoichiometric silicon nitride, or sometimes referred to as silicon nitride or oxynitride (silicon nitride containing oxygen), to a higher weight % of silicon and oxygen (i.e., reduction of nitrogen). Therefore, the oxygen-rich silicon nitride or oxynitride film is more like silicon dioxide, and the RI decreases toward the 1.45RI of pure silicon dioxide. Similarly, the films described herein as "silicon-rich" necessarily shift from stoichiometric silicon nitride to a higher weight % of silicon with less oxygen than the "oxygen-rich" film. Therefore, the silicon-rich silicon nitride film is more like silicon, and the RI increases toward the 3.5RI of pure silicon. Throughout this document, "silicon nitride" and "silicon oxynitride" will be used interchangeably, and the formed films may or may not have an oxygen content.

[0066] In one embodiment, it may be desirable to produce a charge trapping dielectric film with the majority of the charge traps distributed in the upper portion of the film. This can minimize charge leakage through the underlying tunnel dielectric layer. Figure 4C As an example, the process parameters during the ALD deposition of the charge trapping dielectric sublayer 308a can be configured to produce an oxygen-rich, nitrogen-poor silicon nitride film. Using the same ALD chamber and adjusting the process parameters, the charge trapping dielectric sublayer 308c can be formed as an oxygen-poor, nitrogen-rich silicon nitride film that contains most of the charge traps in the entire multi-layer charge trapping dielectric layer 308.

[0067] In some embodiments, a thin silicon oxide film may be formed within the charge trapping nitride layer and between two nitride layers. Figure 4D , a thin dielectric film 330 may be formed on the lower charge trapping dielectric layer 308'. The lower charge trapping dielectric layer 308' is one or more silicon nitride sublayers formed similarly to the charge trapping dielectric layer 308. The thin dielectric film 330 may be silicon oxide or very oxygen-rich silicon nitride, and may be formed using ALD radical oxidation or ALD oxide deposition similar to the formation of the tunnel dielectric sublayers 306a to 306d described above. The silicon oxide is either deposited directly over the lower charge trapping dielectric layer 308', or the radicals may convert a portion of the silicon nitride in the lower charge trapping dielectric layer 308' into silicon oxide or very oxygen-rich nitride. In an embodiment, the thin dielectric film may be a single layer or have multiple sublayers, and each sublayer is formed in the same ALD chamber using the ALD radical oxidation or oxide deposition process steps described above.

[0068] Reference Figure 4E , then an upper charge trapping dielectric layer 332 is formed over the thin dielectric film 330, so that the finished charge trapping dielectric layer 350 has a total thickness of approximately to 308') (lower) (NON) stack 350. In one embodiment, similar to the lower charge trapping dielectric layer 308', the upper charge trapping dielectric layer 332 includes one or more silicon nitride sublayers (not shown) formed similarly to the charge trapping dielectric sublayers 308a to 308c. The upper charge trapping dielectric layer 332 is also customizable; and by fine-tuning the ALD deposition process, each silicon nitride sublayer therein can have a different thickness, film ratio of Si, O, N in the formed silicon nitride, or other physical and chemical properties. In one embodiment, the thin dielectric film 330 significantly reduces the probability of electron charge accumulated at the boundary of the upper charge trapping layer 332 during programming to tunnel into the lower charge trapping layer 308', thereby achieving lower leakage current than conventional memory devices. In a preferred embodiment, the nitride sublayer in the upper charge trapping dielectric layer 332 can be tailored to be oxygen-poor to contain most of the charge traps, while the nitride sublayer in the lower charge trapping dielectric layer 308' is oxygen-rich.

[0069] 2 , in step 208, a blocking dielectric layer 310 is formed over the charge trapping dielectric layer 308 or the NON charge trapping dielectric layer 350. The process begins by forming a blocking dielectric sublayer 310a over the charge trapping dielectric layer 308 or 350. In one embodiment, the blocking dielectric sublayer 310a is silicon oxide and is formed by free radical oxidation as previously described in Table 1 or ALD oxide deposition as described in Table 2, or modifications, combinations, and variations thereof. Silicon oxide is deposited over the charge trapping dielectric layer 308 or 350, or free radicals may convert a portion of the silicon oxynitride in the charge trapping dielectric layer 308 or 350 into silicon oxide. Referring to FIG. Figure 5B , and then other blocking dielectric sub-layers 310b to 310c may be formed. In one embodiment, the blocking dielectric sub-layers 310b to 310c may be formed by similar free radical oxidation or ALD oxide deposition as a silicon oxide film having a thickness, uniformity, and quality that can be customized by modifying the process performed in the ALD chamber. Thus, the blocking dielectric layer 332 may have a total thickness of approximately to Single or multi-layer silicon oxide within the range. Figure 5C , and then forming an ONO stack layer 320 over at least a portion of the substrate 302, all in the same in-situ ALD tool. Figure 5D In one embodiment, the ONO stack layer 320 may be patterned to form one or more ONO stacks 320' for a SONOS-based transistor. Figure 1 302. The ONO stack 120 of the NVM transistor 100 in FIG. 302 is similar. A mask may be formed on or overlying the ONO stack layer 320, and the ONO stack layer 320 may be etched to form one or more ONO stacks 320' covering the substrate 302. In step 210, the manufacturing process may continue with the remaining processes. Process steps such as source / drain formation, spacer formation, storage gate formation, etc. will be performed according to the practice of those of ordinary skill in the art. It will be understood that the above process steps may be performed before, between, or after the formation of the ONO stack layer 320 (in steps 204 to 208) without departing from the principles of the present disclosure.

[0070] In an alternative embodiment, referring to Figure 5E, instead of being formed as an ONO stack based on a SONOS transistor and directly on the substrate 302, the ONO stack layer 320 can be formed as part of the memory stack layer 540 of the floating gate transistor 550. In one embodiment, the ONO stack layer 320, which acts as a blocking dielectric layer of the floating gate transistor 550 as a whole, is formed on the tunnel oxide layer 502 and the floating gate layer 504. The tunnel oxide layer 502, which is mainly silicon oxide, and the floating gate layer 504, which can be polysilicon, can be formed in the same ALD chamber as the ONO stack layer 320, or formed using other techniques practiced by those of ordinary skill in the art.

[0071] Reference Figure 6 , a portion of a SONOS-based non-volatile memory (NVM) device 600 formed over a single substrate 102 is shown. In one embodiment, the substrate 102 is divided into a memory region where a memory cell 620 is disposed and a logic region where an HV MOS 604, an I / O MOS 606, and a LV MOS 608 are disposed. In one embodiment, only a single device of each type (i.e., memory cell 620, HV MOS 604, I / O MOS 606, and LV MOS 608) is shown for illustration purposes only. Multiple devices of each type and other semiconductor devices may be disposed within the SONOS-based NVM device 600 and may be formed simultaneously or sequentially. As shown in FIG. Figure 6 As best shown in , the NVM transistor 100 may have a polysilicon (poly) or high-K metal gate (HKMG) layer 634 disposed overlying the ONO stack 320 ′, which may serve as a control gate (CG) or a memory gate (MG) of the memory cell 620 .

[0072] like Figure 6 6, in a two-transistor (2T) configuration, the memory cell 620 also includes a pass transistor or select transistor 602 disposed adjacent to the SONOS-based NVM transistor 100 (or referred to as a memory transistor). The pass transistor 602, for example, is a conventional MOSFET that shares a common substrate connection or internal node with the NVM transistor 100. In one embodiment, the pass transistor 102 includes a high-K metal gate (HKMG) or polysilicon select gate (collectively referred to as "SG") 632 disposed overlying an oxide or high-K dielectric gate dielectric layer 612. The SG 632 is appropriately biased to open or close the channel below the pass transistor 602. In another embodiment, the memory cell 620 can be in a single-transistor (1T) configuration and have only the NVM transistor 100.

[0073] Reference Figure 6, in the logic region, the HV MOS transistor 604, the I / O MOS transistor 606, and the LV MOS transistor 608 are field effect transistors (FETs) having a logic gate 632 covering a HKMG gate or a polysilicon gate formed of a HV gate oxide 614, an I / O gate oxide 606, and a LV gate oxide 618, respectively. In one embodiment, the HV gate oxide 614 has the largest thickness, followed by the I / O gate oxide 616, and then the LV gate oxide 618. In one embodiment, the pass transistor 602 in the storage region may have a similar or identical structure and size to one of the HV MOS transistor 604, the I / O MOS transistor 606, and the LVMOS transistor 608.

[0074] Figure 7 is a process flow diagram showing key manufacturing steps for integrating a SONOS or NVM transistor (in the memory area) into a baseline complementary metal oxide semiconductor (CMOS) process flow (in the logic area) according to one embodiment of the present disclosure. Figure 7 The process starts with multiple pre-steps, including forming multiple isolation structures or shallow trench isolation (STI) in step 702, forming liner oxide, forming source / drain, forming wells, pre-cleaning the substrate, etc. The liner oxide 870 can be formed over the substrate 102 in both the memory area and the logic area. In one embodiment, the liner oxide 860 can be a silicon dioxide (SiO2) with a thickness ranging from about 10 nanometers (nm) to about 20 nm. 2 ), and may be formed in an ALD chamber using a radical oxidation or oxide deposition process as previously described, or other oxidation or deposition processes known in the art. It will be appreciated that in some embodiments the pad oxide 870 may not be necessary or may not be formed. Dopants are injected into the substrate 102 through the pad oxide 870 (if present) to form (deep and shallow) wells, sources / drains, or channels for the NVM transistors 100 and the transfer transistors 602 in the storage region, and one or more of the MOS transistors 604, 606, 608 in the logic region. It will be appreciated that one or more pre-steps may be performed later in the manufacturing process without departing from the principles of the present disclosure.

[0075] Next, refer to Figure 7 and Fig. 8A, the surface of the substrate 102 in the storage region is cleaned or pre-cleaned, and a plurality of dielectric layers are formed in steps 704 and 706. Subsequently, in step 706, a mask is formed on or overlying the dielectric layer, and the dielectric layer is etched to form an NV gate stack in the storage region. The pre-cleaning may be a wet or dry process to remove the pad oxide 870 on the substrate 102 (at least in the storage region).

[0076] Reference Figure 7 and Fig. 8A In step 704, the dielectric layer or NV gate stack layer process begins with forming a tunnel dielectric layer 306 in the storage region and can be extended to the logic region where the MOS transistors 604, 606, 608 are to be formed. In one embodiment, the tunnel dielectric layer 306 can be any material and have any thickness suitable for enabling charge carriers to tunnel into the overlying charge trapping layer under an applied gate bias while maintaining an appropriate leakage barrier when the multi-level NVM transistor 926 is not biased. As previously described at least in FIG. 2 and FIG. 3A to FIG. 3D As described in the description thereof, in a preferred embodiment, the tunnel dielectric layer 306 may include one or more layers formed in an ALD chamber such as Figure 2B The silicon oxide sublayer is formed by a free radical oxidation or ALD oxide deposition process step performed in the ALD chamber 90. By controlling and modifying process parameters such as flow rate, reactants, duration, temperature, etc. in the free radical oxidation process and the ALD deposition process, a tunnel dielectric layer 306 with a customizable desired thickness (WTW and WIW), uniformity, oxide-silicon substrate interface condition, and film stoichiometry can be achieved.

[0077] Refer again Fig. 8A In step 704, a charge trapping layer 308 or 350 is formed on or overlying the tunnel dielectric 306. In one embodiment, the charge trapping layer 308 or 350 may be formed by, for example, FIG. 4A to FIG. 4E and the ALD deposition process steps described in their respective descriptions. In one embodiment, as Figure 4E As best shown in FIG. 1 , the charge trapping layer may be a layer having at least one sublayer (e.g., Figure 4C A multi-layer charge trapping layer 308 is best shown as 308a to 308c in FIG. 1 , and by fine-tuning the ALD deposition process steps, each sub-layer can have a different thickness, film ratio of Si, O, N, or other physical and chemical properties.

[0078] In another embodiment, the charge trapping dielectric layer 350 is a NON layer including a plurality of layers, the plurality of layers including: a lower charge trapping layer 308', which is at least physically closer to the tunnel dielectric layer 306; and an upper charge trapping layer 332, which has one or more nitride sublayers and is oxygen-poor relative to the oxygen-rich lower charge trapping layer 308' which also has one or more sublayers, and includes a majority of the charge traps distributed in the multi-layer charge trapping layer 350. Figure 4E As best shown in FIG. 1 , there may be a thin oxide film formed between the upper charge trapping dielectric layer 332 and the lower charge trapping dielectric layer 308' to significantly reduce the probability of electron charges accumulated at the boundary of the upper charge trapping layer 332 tunneling into the lower charge trapping layer 308' during programming, thereby producing lower leakage current than conventional memory devices. In one embodiment, all sub-layers of the charge trapping dielectric layer 308 or 350 may be formed within the same ALD chamber (in-situ) by free radical oxidation, oxide deposition, or nitride deposition process steps.

[0079] Refer again Figure 7 and Fig. 8A In step 706, a capping layer 802 is formed on or overlying the charge trapping layer 308 or 350. In some embodiments, as shown, the capping layer 802 is a multi-layer capping layer including at least a lower capping layer or a first capping layer 802a overlying the charge trapping layer 308 or 350 and a second capping layer 802b overlying the first capping layer 802a.

[0080] In one embodiment, the first capping layer 802a may include a high temperature oxide (HTO) such as silicon oxide (SiO2) deposited using a low pressure chemical vapor deposition (LPCVD) thermal oxidation process with a thickness between 2.0 nm and 4.0 nm. 2 In one embodiment, the second capping layer 802b may include a 2 O / NH 3 and DCS / NH 3 A silicon nitride, silicon-rich silicon nitride, or silicon-rich silicon oxynitride layer having a thickness between 2.0 nm and 4.0 nm is formed by a CVD process using a gas mixture. In another embodiment, the cap layer 802 may also be formed in an ALD chamber using a free radical oxidation or oxide deposition or nitride deposition process step as described in the previous paragraphs, such as Tables 1 to 3 and their corresponding descriptions.

[0081] Still refer to Figure 7 and Fig. 8AIn step 706, a sacrificial oxide layer 806 is formed on or overlying the cap layer 802. In one embodiment, the sacrificial oxide layer 802 may include a high temperature oxide (HTO) layer having a thickness between 2.0 nm and 4.0 nm grown by a thermal oxidation process or free radical oxidation. In another embodiment, the sacrificial oxide layer 806 may be formed in an ALD chamber using free radical oxidation or oxide deposition process steps as described above.

[0082] Next, refer to Figure 7 and Fig. 8A , a patterned mask layer 850 is formed on or covers the sacrificial oxide layer 802, and referring to Figure 8B , the sacrificial oxide layer 806, the cap layer 802 and the charge trapping layer 308 or 350, and the tunnel dielectric layer 306 are etched or patterned to form an NV gate stack 860. In one embodiment, the NV gate stack 860 may be configured to substantially cover the channel of the NVM transistor 100 in the storage area. The etching or patterning process may also remove the individual dielectric layers of the NV gate stack 860 from the logic area (step 706). The patterned mask layer 850 may include a photoresist layer patterned using standard photolithography techniques, and the NV gate stack 860 layer in the logic area may be etched or removed using a dry etching process including one or more separate steps to stop on the surface of the substrate 102 or the unremoved pad oxide 870 (if any). In one embodiment, a well (not shown) may be formed in the logic area. It will be understood that Figure 8B 8 is a representative diagram and one or more NV gate stacks 860 may be formed in the same patterning process step in a storage region or other region on the substrate 102 .

[0083] Reference Figure 7 and Figure 8C In a highly selective cleaning process, the sacrificial oxide layer 806 and the top of the second cap layer 802b in the multi-layer cap layer 802 are partially or substantially completely removed from the NV gate stack 860 (step 708). The cleaning process further removes any oxide remaining in the memory region and logic region outside the NV gate stack 860, such as oxide in the tunnel dielectric layer 306 and / or the pad oxide 870, to prepare the substrate 102 for oxide formation.

[0084] Next, refer to Figure 7 and Fig.8D, a blocking dielectric layer 310 of the NVM transistor 100, a pass transistor gate oxide 612 in the storage region (if present for a 2T configuration), and a LV gate oxide layer 618, an I / O gate oxide layer 616, and a HV gate oxide layer 614 are formed in step 710. In one embodiment, an oxidation process is performed to oxidize the remaining portion of the first capping layer 802a and / or the second capping layer 802b of the multi-layer capping layer 802, and optionally to oxidize a portion of the charge trapping dielectric layer 308 or 350, to form a blocking dielectric layer 310 covering the charge trapping dielectric layer 308 or 350. In one embodiment, the oxidation process is adapted to oxidize or consume the remaining portion of the first cap layer 802a or the second cap layer 802b, or optionally oxidize or consume a portion of the charge trapping dielectric layer 308 or 350, to form the blocking dielectric layer 310 and the gate oxide layer 612 of the transfer transistor 602 (if present) in the storage region, while oxidizing at least a portion of the substrate 102 in which the I / O MOS 606 or the LV MOS 608 or the HV MOS 604 is disposed to form a gate oxide layer in the logic region. In one embodiment, the oxidation process may include an in-situ radical oxidation performed in an ALD chamber, such as the ALD chamber 90. The in-situ radical oxidation process may be performed in accordance with Table 1, FIG. 5A to FIG. 5C and the ALD radical oxidation process steps described in the corresponding description thereof, wherein one or more silicon oxide sub-layers (e.g., as Figure 5B In one embodiment, the silicon oxide in the blocking dielectric layer 310 is formed by a free radical reaction or ultimately conversion of the nitride or oxynitride in the cap layer 802 or possibly the top portion of the charge trapping dielectric layer 308 or 350. In one embodiment, free radicals such as OH radicals, HO radicals, etc. generated during the in-situ ALD free radical oxidation process step are also generated. 2The radicals or O diradicals may also react and consume the silicon substrate 102 to form one or more sublayers in the pass transistor gate oxide 612 in the memory region and the gate oxide layers 612, 614, 616 in the logic region. The process parameters of the in-situ ALD radical oxidation process step (e.g., Table 1) may be modified to produce oxide sublayers having different thicknesses, qualities, uniformities, stoichiometries, or other chemical and physical properties in both the memory region and the logic region. The radical oxidation process steps may also be repeated, alternately repeated, and modified to achieve the desired thickness T1 of the blocking dielectric layer 310, the desired thickness T2 of the gate oxide layer 612 of the pass transistor, and the desired thicknesses T3, T4, T5 of the gate oxide layers 614, 616, 618 of the HV MOS 604, I / O MOS 606, and LV MOS 608, respectively. In one embodiment, T1 may be between 0.1 and 0.2. to In the approximate range of to In the approximate range of to In the approximate range of to The approximate range of T5 can be to in the approximate range of .

[0085] Alternatively or additionally, in the same ALD chamber, in-situ ALD oxide deposition (e.g., Table 2 or modified) may also be performed to generate one or more oxide sublayers in the blocking dielectric layer 310 and at least one of the gate oxides 612, 614, 616, 618. FIG. 5A to FIG. 5CAs previously described in the corresponding description thereof, the radicals generated in the ALD chamber may react with a silicon source gas such as HCD or oxynitride / nitride or a silicon substrate to form one or more silicon oxide sublayers. In an embodiment, the in-situ ALD oxide deposition process steps and the radical oxidation process steps that may be performed in the same ALD chamber may be repeated, modified, alternating, or performed in the above combination until the predetermined thickness T1 to T5 of the corresponding dielectric / oxide layer 310, 612, 614, 616, 618 is achieved. In an alternative embodiment, sometimes the in-situ ALD oxide deposition process step or the radical oxidation process step may not be applied to all areas. A mask (not shown) may be applied to protect one or more areas so that the gate oxide layer therein is not affected by the subsequent radical oxidation or ALD oxide deposition process steps. In one example, the gate oxide layer 618 of the LV MOS 608 in the logic area may be protected with a mask (not shown) after reaching the thickness T5 so that no additional oxide is added for its thickness in the subsequent in-situ ALD process steps (radical oxidation, deposition, or both). In another example, the gate oxide layer 612 of the pass transistor 602 and the gate oxide layer 614 of the HV MOS 604 can be substantially the same and can be formed simultaneously or sequentially in the same process step. One main purpose and advantage of manufacturing the blocking dielectric layer 310 of the NVM transistor and one or more of the gate oxides of the MOS transistors 602, 604, 606, 608 in the same or similar ALD chamber / tool ​​with in-situ ALD process steps (both radical oxidation and oxide deposition) is that the oxide sub-layers and individual layers are formed with a relatively low thermal budget (less than 650° C.) so that the CMOS process flow in the logic area can be unadversely affected. Another purpose and advantage is that the NON stack 320 and the gate oxide layers 612, 614, 616, 618 of the NVM transistor 100 are highly customizable by changing the configuration of the in-situ process steps in the ALD chamber or tool. In one embodiment, the ONO layer of the SONOS transistor and the gate oxide layers 612, 614, 616, 618 of all FETs are formed in-situ within the same ALD chamber or tool.

[0086] In alternative embodiments, at least a portion of gate oxide layers 612, 614, 616, 618 may be formed using RTO, furnace oxidation, free radical oxidation, CVD, in-situ steam generation (ISSG), or a combination thereof. These oxidation process steps may be performed in separate process tools.

[0087] In an embodiment, the LV gate oxide layer 618, the I / O gate oxide layer 616, and the HV gate oxide layer 614 may be formed simultaneously or separately. Fig. 8EAs best shown in FIG. 7 , in step 710, LV gate oxide layer 614, I / O gate oxide layer 616, and HV gate oxide layer 614 are patterned. Although only one of each type of transistor (SONOS NVM transistor, pass transistor, HV MOS transistor, I / O MOS transistor, LV MOS transistor) is shown, it will be understood that each type ( Fig.8D Multiple transistors (not shown) can be manufactured simultaneously or sequentially using the above-mentioned methods and process steps.

[0088] Finally, a standard or baseline CMOS process flow is continued to substantially complete the front-end device fabrication (step 712). The process flow may include forming HKMGs, spacers, channels, source / drain regions, etc. for each type of transistor. In one embodiment, the completed NVM transistor 100 and the HV transistor 604, I / O transistor 606, or LV MOS transistor 608 may be configured to form an embodiment of the NVM cell 620. In an alternative embodiment, the pass transistor 602 may have a different structure than the HV transistor 604, I / O transistor 606, or LV MOS transistor 608, such as a different gate oxide thickness. In another alternative embodiment, the memory cell 620 may include only the NVM transistor 100 in a single transistor configuration.

[0089] Thus, embodiments of SONOS-based non-volatile memory, methods of manufacturing including customizable ONO stacks, and methods of integration into baseline CMOS process flows are described. Although the present disclosure has been described with reference to specific exemplary embodiments, it will be apparent that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the present disclosure. Accordingly, the description and drawings should be regarded as illustrative rather than restrictive.

[0090] The Abstract of the Disclosure is provided to comply with 37 CFR §1.72(b), which requires an abstract that enables the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments require more features than those expressly recited in each claim. Rather, as reflected in the appended claims, the inventive subject matter lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the specific embodiments, with each claim existing independently as a separate embodiment.

[0091] Reference to one embodiment or implementation in the description means that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one implementation of a circuit or method. The appearance of the phrase one embodiment in various places in the specification is not necessarily all referring to the same implementation.

Claims

1. A method for manufacturing a semiconductor device, include: dividing the substrate into a first region and a second region; Forming a customizable oxide-nitride-oxide (ONO) stack in the first region includes: performing at least one of a first radical oxidation process step and a first oxide deposition process step in an atomic layer deposition (ALD) tool to form a tunnel dielectric layer overlying the substrate; A plurality of silicon nitride deposition process steps are performed in the ALD tool to form a multi-layer charge trapping (CT) layer, including: determining process parameters of a first silicon nitride deposition process step among the plurality of silicon nitride deposition process steps to form a first CT sublayer; modifying at least one of the process parameters; performing a second silicon nitride deposition process step to form a second CT sub-layer covering the first CT sub-layer; and At least one of a second radical oxidation process step and a second oxide deposition process step is performed in the ALD tool to form a blocking dielectric layer covering the multi-layer CT layer in the first region.

2. The method according to claim 1, in, The silicon nitride includes silicon oxynitride containing oxygen.

3. The method according to claim 1, in, The customizable ONO stack formation process steps are performed in-situ in the same ALD tool.

4. The method according to claim 1, in, Film compositions of silicon, oxygen, and nitrogen of silicon nitride in the first CT sub-layer and the second CT sub-layer are different.

5. The method according to claim 1, in, The first CT sublayer is oxygen-rich silicon nitride, resulting in the first CT sublayer being substantially free of charge traps, and the second CT sublayer is oxygen-poor silicon nitride, resulting in the second CT sublayer being substantially charge trap-dense.

6. The method according to claim 5, further comprising: include: A plurality of third silicon nitride deposition process steps are performed to form a plurality of third CT sublayers disposed between the first CT sublayer and the second CT sublayer, wherein process parameters of the plurality of third silicon nitride deposition process steps are adjusted so that oxygen richness levels of the plurality of third CT sublayers are between the oxygen richness level of the first CT sublayer and the oxygen richness level of the second CT sublayer.

7. The method according to claim 5, further comprising: include: At least one of a third radical oxidation process step and a third oxide deposition process step is performed in the ALD tool to form a thin oxide film covering the first CT sub-layer and below the second CT sub-layer, wherein the thin oxide film is formed to reduce electron charges accumulated at a boundary of the second CT layer from tunneling into the first CT layer.

8. The method according to claim 1, in, The process parameters of the first free radical oxidation process step and the second free radical oxidation process step include: Including O 2 / H 2 The type of gas reactant gas; the flow rate of the reactant gas into the ALD tool; Reaction time for each reactive gas; the order in which the reactant gases enter the ALD tool; and The number of repetitions and the order of repetitions, wherein the process parameters are configured to control at least one of the thickness, density, and quality of the oxide formed in the tunnel dielectric layer.

9. The method according to claim 1, in, Process parameters of the first oxide deposition process step and the second oxide deposition process step include: Types of silicon source precursor gases including HCD; Including O 2 / H 2 The type of gas reactant; flow rates of the reaction gas and the silicon source precursor gas; Respective reaction times for the reaction gas and the silicon source precursor gas; and The reaction gas and the silicon source precursor gas enter the ALD tool in a sequence, wherein the process parameters are configured to control at least one of a thickness, a density, and a quality of an oxide formed in the blocking dielectric layer.

10. The method according to claim 1, in, The process parameters of the first silicon nitride deposition process step and the second silicon nitride deposition process step include: Types of silicon source precursor gases including HCD; Including NH 3 / N 2 Type of reactive gas for O gas; flow rates of the reaction gas and the silicon source precursor gas; and Respective reaction times for the reaction gas and the silicon source precursor gas; the order in which the reactant gas and the silicon source precursor gas enter the ALD tool; and Number and order of repetitions.

11. The method according to claim 1, in, At least one silicon nitride deposition process step of the plurality of silicon nitride deposition process steps is plasma enhanced.

12. The method according to claim 1, in: Repeating the first radical oxidation process step and the first oxide deposition process step alone, alternately, or in combination thereof to form the tunnel dielectric layer; and The second radical oxidation process step and the second oxide deposition process step are repeated individually, alternately, or in combination thereof to form the blocking dielectric layer, wherein process parameters of the first radical oxidation process step and the second radical oxidation process step and the first oxide deposition process step and the second oxide deposition process step are adjusted during the repeated process steps to customize the tunnel dielectric layer and the blocking dielectric layer.

13. The method according to claim 1, further comprising: include: A high voltage (HV) gate oxide layer, an input / output (I / O) gate oxide layer, and a low voltage (LV) gate oxide layer are formed in the second region of the substrate, wherein the blocking dielectric layer of the customizable ONO layer in the first region and at least one of the HV gate oxide layer, the I / O gate oxide layer, and the LV gate oxide layer are simultaneously formed by at least one of the second radical oxidation process step and the second oxide deposition process step.

14. The method according to claim 1, in, The multi-layer CT layer includes at least three CT sub-layers, and wherein process parameters of the plurality of silicon nitride deposition process steps are modified such that a top CT sub-layer adjacent to the blocking dielectric layer is the most oxygen-poor, and a bottom CT sub-layer adjacent to the tunnel dielectric layer is the most oxygen-rich in the multi-layer CT layer.

15. A method of manufacturing a memory device, include: forming a tunnel oxide layer in a memory region and a logic region of the substrate; forming a customizable charge trapping (CT) layer and a capping layer overlying the tunnel oxide layer, wherein the customizable CT layer comprises a plurality of CT sub-layers, and wherein each of the CT sub-layers is formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber; patterning the tunnel oxide layer, the customizable CT layer, and the cap layer to form a memory stack in the memory region, while removing the tunnel oxide layer, the customizable CT layer, and the cap layer in the logic region; and At least one radical oxidation process step is performed in the ALD chamber to simultaneously convert at least silicon nitride in the cap layer to form a blocking oxide layer covering the customizable CT layer, and convert silicon in the substrate to form a first gate oxide layer in the logic region.

16. The method according to claim 15, further comprising: include: At least one oxide deposition process step is performed in the ALD chamber to simultaneously increase the thickness of the first gate oxide layer and the blocking oxide layer in the logic region.

17. The method according to claim 15, in, The process parameters of the one or more silicon nitride deposition process steps include: Types of silicon source precursor gases including HCD; Including NH 3 / N 2 Type of reactive gas for O gas; flow rates of the reaction gas and the silicon source precursor gas; Respective reaction times for the reaction gas and the silicon source precursor gas; and The order in which the reaction gas and the silicon source precursor gas enter the ALD chamber.

18. The method according to claim 17, in, Process parameters of the one or more silicon nitride deposition process steps are adjusted to produce CT sub-layers having different thicknesses, densities, and at least one of film compositions of Si, O, and N of the silicon nitride in the CT sub-layers.

19. A method of manufacturing a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based memory device, include: A memory cell including a SONOS transistor and a pass transistor is formed in a memory region of a substrate, comprising: forming a tunnel oxide layer in the storage area and the logic area of ​​the substrate; forming a customizable charge trapping (CT) layer and a capping layer overlying the tunnel oxide layer, wherein the customizable CT layer comprises a plurality of CT sub-layers, and wherein each of the CT sub-layers is formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber; patterning the tunnel oxide layer, the customizable CT layer, and the cap layer to form a memory stack in the memory region, while removing the tunnel oxide layer, the customizable CT, and the cap layer in the logic region; and forming a blocking oxide layer covering the customizable CT layer and a first gate oxide of the transfer transistor in the storage region; and A high voltage (HV) gate oxide layer of a high voltage (HV) transistor, an input / output (I / O) gate oxide layer of an I / O transistor, and a low voltage (LV) gate oxide layer of a low voltage (LV) transistor are formed in the logic region, wherein at least one of the HV gate oxide, the I / O gate oxide, and the LV gate oxide is formed at least in part by performing at least one radical oxidation process step in the ALD chamber to simultaneously perform the following operations: in the storage region, at least silicon nitride in the cap layer is converted to form the blocking oxide layer and silicon is converted to form the first gate oxide, and in the logic region, silicon in the substrate is converted to at least partially form at least one of the HV gate oxide, the I / O gate oxide, and the LV gate oxide.

20. The method according to claim 19, further comprising: include: At least one oxide deposition process step is performed in the ALD chamber to simultaneously increase the thickness of the blocking oxide layer and the first gate oxide layer in the storage region.

21. The method according to claim 19, in, The pass transistor and the HV transistor are of the same type, and wherein the first gate oxide and the HV gate oxide are formed simultaneously and have approximately the same thickness.

22. The method according to claim 19, in, The process parameters of the one or more silicon nitride deposition process steps are adjusted to produce the CT sub-layers, wherein the film compositions of Si, O and N of the silicon nitride in the CT sub-layers are different, and wherein, in the customizable CT layer, the top CT sub-layer is the most oxygen-poor and the bottom CT sub-layer is the most oxygen-rich.

23. The method according to claim 20, in, The oxide deposition process step, the radical oxidation process step, and the silicon nitride deposition process step are performed in-situ in the ALD chamber, and the process temperature is controlled to be less than 650°C.

24. The method according to claim 19, further comprising: include: A high-K metal gate (HKMG) is formed covering a blocking oxide layer of the SONOS transistor and a first gate oxide layer of the pass transistor.

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