A method for analyzing reliability test data of integrated circuits

Abstract

This application discloses a method for analyzing reliability test data of integrated circuits. During the data analysis process, a first weight value and a second weight value are used to process the data, which can characterize the risks to a certain extent and thus provide some predictability for the losses caused by the complete failure of the integrated circuit. On the one hand, it enables the application of detailed techniques related to the type or purpose of circuit design in the field of integrated circuit testing; on the other hand, it also demonstrates that there is a broad prospect for further technological development in this field.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital data processing, in particular to the technical field of details of circuit design types or purposes, and more particularly, to an integrated circuit reliability test data analysis method. BACKGROUND

[0002] Quality and reliability testing of integrated circuits (IC) is an important link to ensure stable performance and long-term reliability. In an increasingly complex electronic world, the quality of chips is directly related to the performance and reputation of the final product, so their testing is indispensable.

[0003] The failure process of integrated circuits can generally be divided into three stages: early failure, accidental failure and wear-out failure. They are not completely independent of each other, but there is a certain relationship. Influenced by the design of integrated circuits, specification parameters, etc., the relationship between the aforementioned three stages of different types of integrated circuits is not completely the same. If the existing formula is completely relied on to calculate the reliability of integrated circuits, it will result in a large error. The analysis result of the reliability test data of the integrated circuit is not accurate.

[0004] Therefore, how to provide a unique reliability test data analysis method for different types of integrated circuits based on the differences between integrated circuits has become a problem to be solved.

[0005] For example, the patent application entitled "Integrated Circuit and Test Method of the Integrated Circuit" (Application No. CN98803503.0, main classification number: G06F11 / 22) designs an integrated circuit and a method for testing the same, indicating that in the field of integrated circuit testing, it is feasible to use digital data processing, specifically details of circuit design types or purposes. SUMMARY

[0006] The embodiments of the present application provide an integrated circuit reliability test data analysis method to at least partially solve the above technical problems.

[0007] The embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, the embodiments of the present application provide an integrated circuit reliability test data analysis method, which comprises:

[0009] Based on the preset test means, the reliability of the target integrated circuit is tested, and the collected data is used as the data to be analyzed;

[0010] Based on the data to be analyzed, the failure rate of the target integrated circuit at each time when the reliability test is performed is determined;

[0011] determining a first conversion time point; the first conversion time point is used to represent a time node of conversion from early failure to accidental failure;

[0012] determining a second conversion time point; the second conversion time point is after the first conversion time point, and is a starting time point of a specified time length in which a slope of the failure rate curve is positive;

[0013] regarding a time period between a starting time point of performing the reliability test and the first conversion time point as early failure, regarding a time period between the first conversion time point and the second conversion time point as accidental failure, and regarding a time period between the second conversion time point and an ending time point of performing the reliability test as wear-out failure;

[0014] determining a first weight value; the first weight value is used to represent an influence of defects of the target integrated circuit on the accidental failure;

[0015] determining a second weight value; the second weight value is used to represent an influence of the defects of the target integrated circuit on a use cycle of the target integrated circuit; in a case where a length of the use cycle is greater than a preset use cycle threshold, the second weight value is negatively related to a failure rate at the first conversion time point;

[0016] in a case where an average failure rate of the accidental failure is less than a preset failure rate threshold, if the length of the use cycle is greater than the use cycle threshold, the failure rate is weighted by the first weight value and the second weight value to obtain a target failure rate;

[0017] obtaining a data analysis result of the target integrated circuit based on the target failure rate.

[0018] In an optional embodiment of the present specification, weighting the failure rate by the first weight value and the second weight value to obtain a target failure rate comprises:

[0019] weighting a failure rate of the early failure by the first weight value, weighting failure rates of the accidental failure and the wear-out failure by the second weight value, and obtaining the target failure rate.

[0020] In an optional embodiment of the present specification, the method further comprises:

[0021] In a case where the average failure rate of the accidental failure is not less than the failure rate threshold, if the length of the use period is greater than the use period threshold, it is determined whether the maximum failure rate of the early failure is greater than a preset maximum failure rate threshold; if yes, it is determined that the data analysis result of the target integrated circuit is defective; and / or,

[0022] The first conversion time point is a time point between a time node at which the curve of the failure rate appears a slope less than a preset first slope threshold for the first time and a time node at which the curve of the failure rate appears a slope greater than a preset second slope threshold for the first time after the time node; the first slope threshold and the second slope threshold are both less than zero, and the first slope threshold is less than the second slope threshold.

[0023] In an optional embodiment of the present specification, the method further comprises:

[0024] If the maximum failure rate of the early failure is not greater than the maximum failure rate threshold, it is determined that the data analysis result of the target integrated circuit is defective design.

[0025] In an optional embodiment of the present specification, the method further comprises:

[0026] In a case where the average failure rate of the accidental failure is not less than the failure rate threshold, if the length of the use period is not greater than the use period threshold, it is determined that the data analysis result of the target integrated circuit is unqualified product.

[0027] In an optional embodiment of the present specification, the method further comprises:

[0028] In a case where the average failure rate of the accidental failure is less than the failure rate threshold, if the length of the use period is not greater than the use period threshold, it is determined that the data analysis result of the target integrated circuit is defective design.

[0029] In an optional embodiment of the present specification, the method further comprises:

[0030] The test means is a high-pressure cooking test.

[0031] In an optional embodiment of the present specification, the method further comprises:

[0032] the first weight value is positively related to a ratio of the length of the early failure to a length of performing the reliability test, and is negatively related to a ratio of the chance failure to the length of performing the reliability test; and the first weight value in a case where the ratio of the length of the early failure to the length of performing the reliability test is greater than a preset ratio threshold is greater than the first weight value in a case where the ratio of the length of the early failure to the length of performing the reliability test is not greater than the ratio threshold.

[0033] In an optional embodiment of the present specification, the method further comprises:

[0034] The ratio threshold is negatively related to an average failure rate of the early failure.

[0035] In a second aspect, the embodiments of the present application further provide an integrated circuit reliability test data analysis device, configured to implement the method steps in the first aspect.

[0036] In a third aspect, the embodiments of the present application further provide an electronic device, comprising:

[0037] a processor; and

[0038] a memory arranged to store computer executable instructions that, when executed, cause the processor to perform the method steps of the first aspect.

[0039] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium storing one or more programs, which, when executed by an electronic device comprising a plurality of applications, cause the electronic device to perform the method steps of the first aspect.

[0040] The above at least one technical solution adopted by the embodiments of the present application can achieve the following beneficial effects:

[0041] The technical solutions in the specification divide several stages of the use cycle of the target integrated circuit according to the failure rate, can effectively quantify the defects and design problems of the integrated circuit by the use performance of the integrated circuit, and can reflect the individual characteristics of the integrated circuit. Further, the first weight value and the second weight value are used to process the data in the process of test data analysis. The first weight value is used to represent the influence of the defects of the target integrated circuit on the accidental failure. The defects are mainly caused by material defects and design problems. Such problems not only break out in the early failure, but also affect the subsequent accidental failure. The accidental failure is also the stage that can best reflect the use value of the integrated circuit. The method in the specification can more specifically represent the actual risk of the integrated circuit in use. The second weight value is used to represent the influence of the defects of the target integrated circuit on the use cycle of the target integrated circuit. Even if it is in the wear-out failure, the integrated circuit should not be damaged by the serious and rapid failure. The technical means in the specification can represent the risk to a certain extent, and can predict the loss caused by the complete failure of the integrated circuit. On the one hand, it can realize electric digital data processing, specifically, the use of details of the type or purpose of circuit design in the field of integrated circuit testing; on the other hand, it can also explain that the technical mining in this field also has a relatively wide expansion prospect. BRIEF DESCRIPTION OF DRAWINGS

[0042] The drawings described herein are used to provide further understanding of the present application, and form a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute improper limitations on the present application. In the drawings:

[0043] Figure 1 A process schematic diagram of an integrated circuit reliability test data analysis method provided by the embodiment of the specification;

[0044] Figure 2 A structure schematic diagram of an electronic device in the embodiment of the specification. DETAILED DESCRIPTION

[0045] The application will be described in further detail below with specific reference to the drawings. Like elements are marked with like numerals throughout the various figures. In the following description, numerous specific details are described to provide a thorough understanding of the application. However, it will be apparent to one skilled in the art that the application can be practiced without some or all of these details. In other instances, well known process operations have not been described in detail in order to avoid unnecessarily obscuring the application. As used in this application, the term "comprising" or grammatical variants thereof is intended to mean that the applications contain the recited features, but not excluding others. The use of the term "comprising" is not intended to exclude any feature, structure, operation, and the like that can be added to the compositions or methods described herein. Further, the use of the term "comprising" is intended to cover the terms "consisting of" and "consisting essentially of" where appropriate.

[0046] In addition, features, operations, or steps described in the specification can be combined in any suitable manner without departing from the scope of the applications. Various steps or actions in a method can also be performed in an order other than the order in which the steps or actions are described. Accordingly, unless otherwise specified, the various embodiments can be implemented in any combination of hardware and software in one or more systems or apparatuses that interact and / or are in electrical communication with one another.

[0047] The terms "first", "second", and the like, as used in this specification, can be used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. Unless the context clearly indicates otherwise, the terms "comprise", "comprising", "consist of" and "consisting of" as used herein are used in their inclusive sense and not in an exclusive sense.

[0048] The technical solutions provided by the embodiments of the application are described in detail below with reference to the drawings.

[0049] As shown in FIG. 1, the integrated circuit reliability test data analysis method in the specification includes the following steps: Figure 1

[0050] S100: Based on the preset test means, the reliability of the target integrated circuit is tested, and the collected data is used as the data to be analyzed.

[0051] The reliability test in the specification is mainly qualitative and quantitative in terms of failure rate. When the failure rate of the integrated circuit is too high, the integrated circuit shows irreversible loss of use performance, and the integrated circuit is completely failed, the test can be ended. The integrated circuit is IC, and the integrated circuit in the related art can be used as the target integrated circuit in the specification under the condition of permission.

[0052] ​In an alternative embodiment of the present disclosure, the test method can be the pressure cooker test (PCT). The researchers have found that the subsequent weighting method of the present disclosure can achieve more excellent results in the pressure cooker test. Other existing test methods are also applicable to the present disclosure if the conditions permit.

[0053] S102: Based on the data to be analyzed, determine the failure rate of the target integrated circuit at each time when the reliability test is performed.

[0054] The failure rate refers to the probability of failure at a certain time. In related technologies, the technical means that can be used to calculate the failure rate are applicable to the present disclosure if the conditions permit.

[0055] S104: Determine the first conversion time.

[0056] The first conversion time in the present disclosure refers to the time node of the conversion from early failure to accidental failure. In early failure, the failure rate of the integrated circuit shows a rapid downward trend. In accidental failure, the failure rate of the integrated circuit remains relatively stable, and the failure reason is affected by factors such as defects in the integrated circuit on the one hand and environmental influences on the other hand.

[0057] In an alternative embodiment of the present disclosure, the first conversion time is the time between the time node when the curve of the failure rate first appears with a slope less than a preset first slope threshold and the time node when the curve of the failure rate first appears with a slope greater than a preset second slope threshold. The first slope threshold and the second slope threshold are empirical values related to the situation of the integrated circuit and the test conditions. Both the first slope threshold and the second slope threshold are less than zero, and the first slope threshold is less than the second slope threshold.

[0058] S106: Determine the second conversion time.

[0059] The second conversion time in the present disclosure is the time node of the conversion from accidental failure to wear-out failure. Ideally, the integrated circuit should be in accidental failure for a long time, and the duration of wear-out failure should not be too short. In wear-out failure, the integrated circuit will show a rapid upward trend in failure rate, which is mainly caused by aging. However, in reality, the aging of the integrated circuit is not only related to the use conditions, but also related to various defects in the integrated circuit. The failure impact caused by such defects has actually been reflected in early failure.

[0060] The second transition time is the starting point of the specified time period after the first transition time, provided that the slope of the failure rate curve becomes positive within a preset specified time period. In practical applications, both the first and second transition times can be inflection points. The specified time period can be an empirical value.

[0061] S108: The time period between the start time of the reliability test and the first transition time is designated as an early failure; the time period between the first transition time and the second transition time is designated as an accidental failure; and the time period between the second transition time and the end time of the reliability test is designated as a loss failure.

[0062] Under normal circumstances, the lifecycle of an integrated circuit includes the three stages mentioned above. However, there are also extreme cases, such as when an integrated circuit fails completely in its early stages. In such cases, the integrated circuit product can be directly deemed unqualified.

[0063] S110: Determine the first weight value.

[0064] The first weight value in this specification is used to characterize the impact of defects in the target integrated circuit on the accidental failure. Both the first weight value and the second weight value (mentioned later) are values ​​greater than 1; the larger the value, the more negative the impact of the integrated circuit defect. In other words, the weighted average of the first and second weight values ​​reflects the degree of risk.

[0065] In an optional embodiment of this specification, the first weight value may be an empirical value that satisfies the following conditions: the first weight value is positively correlated with the ratio of the duration of the early failure to the duration of the reliability test (indicating that the instability of the integrated circuit exhibited by the early failure is more obvious and has stronger persistence), and negatively correlated with the ratio of the random failure to the duration of the reliability test (in the case of random failure, the integrated circuit is in a relatively stable state, and if the duration of the random failure is longer, the negative impact can be diluted); and the first weight value is greater than the ratio of the duration of the early failure to the duration of the reliability test when it is greater than a preset ratio threshold, and greater than the ratio of the duration of the early failure to the duration of the reliability test when it is not greater than the preset ratio threshold (the proportion of early failure is too large, indicating that the negative impact is more profound, and this negative impact is mainly caused by defects, which can be overcome and has improvement value).

[0066] In an optional embodiment of this specification, the ratio threshold is an empirical value.

[0067] In another optional embodiment of this specification, the ratio threshold is negatively correlated with the average failure rate of early failures to amplify the effect of the data and highlight the risk expressed in the data.

[0068] S112: Determine the second weight value.

[0069] The second weight value is used to characterize the impact of the defects of the target integrated circuit on the service life (including the three stages mentioned above) of the target integrated circuit. When the duration of the service life exceeds a preset service life threshold (characterized by the lifespan of the target integrated circuit design under ideal conditions), the second weight value is negatively correlated with the failure rate at the first transition time (indicating that although the failure rate is high, the overall system is stable and will not have an overly negative impact on the use of the integrated circuit; that is, the integrated circuit is robust and stable, and even if it enters a period of wear and tear, it will not experience a rapid failure, thus avoiding sudden failure without warning. This stability may contribute more to the signal processing performance of the integrated circuit than to its actual use).

[0070] S114: If the average failure rate of the accidental failure is less than the preset failure rate threshold, and if the duration of the usage period is greater than the usage period threshold, then the failure rate is weighted using the first weight value and the second weight value to obtain the target failure rate.

[0071] The weighted target failure rate reflects both the impact of defects on random failures, which are a crucial stage for integrated circuits to maintain stable performance, and the quantification and characterization of potential risks, which allows for a more comprehensive understanding of the target integrated circuit's online performance. Furthermore, it quantifies the impact of defects on the robustness of the target integrated circuit throughout its entire lifecycle, resulting in a more comprehensive analysis.

[0072] In an optional embodiment of this specification, the weighting method may be to use the first weight value to weight the failure rate of the early failure, in order to amplify the impact of the defects exhibited by the early failure on the accidental failure, and more importantly, to amplify the mismatch effect between material selection and structural design; the second weight value may be used to weight the failure rates of the accidental failure and the wear failure, the second weight value being used to characterize the impact on the entire service life of the integrated circuit. This impact mainly focuses on the impact of accidental failure on the stable performance of the integrated circuit, and also examines whether the integrated circuit may suddenly and completely fail due to wear failure, without giving the user time to deal with the risk event.

[0073] In another optional embodiment of this specification, a second weight value can be used to weight the failure rates of the three stages. This embodiment can be used when the average failure rate over the entire usage period is too high (e.g., greater than the corresponding preset threshold) in order to further amplify the impact of the defect.

[0074] The second weight value is determined when the usage period is longer than a preset usage period threshold. If the usage period is shorter than the usage period threshold, no second weight value is needed; in this case, the relationship between the average failure rate of random failures and the preset failure rate threshold is mainly examined. In this embodiment, if the average failure rate of random failures is not less than the failure rate threshold (indicating a high failure rate), and the usage period is not greater than the usage period threshold (indicating the target integrated circuit cannot reach its expected lifespan), then the data analysis result for the target integrated circuit is determined to be a product defective. If the average failure rate of random failures is less than the preset failure rate threshold, and the usage period is not greater than the usage period threshold, then the data analysis result for the target integrated circuit is determined to be a design flaw.

[0075] Furthermore, in a further optional embodiment of this specification, if the average failure rate of the accidental failure is not less than the failure rate threshold (indicating a high failure rate), and if the duration of the service life is greater than the service life threshold (indicating that the target integrated circuit can still be used for a long time and has a certain degree of robustness), then it is determined whether the maximum failure rate of the early failure is greater than a preset maximum failure rate threshold (which can be an empirical value, usually used to characterize the maximum allowable failure rate of the target integrated circuit while achieving preset performance indicators (e.g., electrical signal processing efficiency)); if so, then the data analysis result of the target integrated circuit is determined to be defective (mismatch between material selection and structural design, or even problems with both). If the maximum failure rate of the early failure is not greater than the maximum failure rate threshold, then the data analysis result of the target integrated circuit is determined to be poorly designed.

[0076] S116: Based on the target failure rate, obtain the data analysis results of the target integrated circuit.

[0077] In related technologies, any technical means that enables analysis of integrated circuits based on test data can be applied to this specification, provided that conditions permit.

[0078] The data analysis results obtained through the technical means described in this specification can be used to guide improvements to details related to the type or purpose of the circuit design. For example, if the data analysis indicates that the target integrated circuit has defects (both in material selection and structural layout), the designer can improve the materials and structure of the target integrated circuit to improve its performance. If the data analysis indicates that the target integrated circuit only has design defects, the designer can improve the structural layout. If the data analysis indicates that the target integrated circuit has no defects, it can be put into production. If the data analysis indicates that the target integrated circuit is unqualified, then the integrated circuit can be considered to have little room for improvement, and the development of a new product can begin.

[0079] Of course, there may also be problems with poor material selection in target integrated circuits. However, the defects caused by material selection are often related to structural design. Such problems are more often due to the mismatch between material selection and structural design, and the two usually manifest at the same time.

[0080] The technical solution in this specification divides the lifecycle of the target integrated circuit into several stages based on failure rate, effectively quantifying potential defects and design problems through the performance of the integrated circuit, and reflecting the unique characteristics of the integrated circuit. Furthermore, a first weighting value and a second weighting value are used to process the test data during analysis. The first weighting value characterizes the impact of defects in the target integrated circuit on accidental failures. These defects are mainly caused by material defects and design problems. These problems not only erupt in the early stages of failure but also affect subsequent accidental failures. Accidental failures are the stage that best reflects the value of the integrated circuit. The method in this specification can effectively characterize the actual risks of using the integrated circuit in a production line. The second weighting value characterizes the impact of defects in the target integrated circuit on its lifecycle. Even at the point of wear and tear failure, the integrated circuit should not suffer destructive consequences due to severe and rapid failure. The technical means in this specification can characterize this risk to a certain extent, thus providing some predictability for the losses caused by complete failure of the integrated circuit. On the one hand, it can realize the processing of electronic digital data, specifically the use of detailed techniques related to the type or purpose of circuit design in the field of integrated circuit testing; on the other hand, it can also illustrate that the technological exploration in this field has a relatively broad prospect for expansion.

[0081] Figure 2This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Please refer to it. Figure 2 At the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and memory. The memory may include main memory, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk drive. Of course, the electronic device may also include other hardware required for other business operations.

[0082] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 2 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0083] Memory is used to store programs. Specifically, programs may include program code, which includes computer operation instructions. Memory may include main memory and non-volatile memory, and provides instructions and data to the processor.

[0084] The processor reads the corresponding computer program from non-volatile memory into main memory and then runs it, forming an integrated circuit reliability test data analysis device at the logical level. The processor executes the program stored in memory and specifically performs any of the aforementioned integrated circuit reliability test data analysis methods.

[0085] The above is as stated in this application. Figure 1The integrated circuit reliability test data analysis method disclosed in the illustrated embodiment can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0086] The electronic device can also perform Figure 1 A method for analyzing reliability test data of integrated circuits is proposed and implemented. Figure 1 The functions of the embodiments shown are not described in detail here.

[0087] This application also proposes a computer-readable storage medium that stores one or more programs, the programs including instructions that, when executed by an electronic device including multiple applications, perform any of the aforementioned integrated circuit reliability test data analysis methods.

[0088] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0089] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0090] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0091] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0092] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0093] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0094] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0095] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0096] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0097] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An integrated circuit reliability test data analysis method, characterized by, The method comprises: performing reliability testing on a target integrated circuit based on a preset testing method, and collecting data as to-be-analyzed data; determining failure rates of the target integrated circuit at various time points during the reliability testing based on the to-be-analyzed data; determining a first conversion time point, which represents a time node at which early failure is converted to accidental failure; determining a second conversion time point, which is a starting time point of a specified time length after the first conversion time point, and in which the failure rate curve appears to have a positive slope within the specified time length; regarding a time period between a starting time point of the reliability testing and the first conversion time point as early failure, regarding a time period between the first conversion time point and the second conversion time point as accidental failure, and regarding a time period between the second conversion time point and an ending time point of the reliability testing as wear-out failure; determining a first weight value, which represents an influence of defects of the target integrated circuit on the accidental failure; determining a second weight value, which represents an influence of the defects of the target integrated circuit on a use cycle of the target integrated circuit, and which is negatively correlated with a failure rate at the first conversion time point when a length of the use cycle is greater than a preset use cycle threshold; when an average failure rate of the accidental failure is less than a preset failure rate threshold, if the length of the use cycle is greater than the use cycle threshold, weighting the failure rate by using the first weight value and the second weight value to obtain a target failure rate; obtaining a data analysis result of the target integrated circuit based on the target failure rate.

2. The method of claim 1, wherein, The weighting of the failure rate by using the first weight value and the second weight value to obtain a target failure rate comprises: weighting a failure rate of the early failure by using the first weight value, and weighting failure rates of the accidental failure and the wear-out failure by using the second weight value to obtain the target failure rate.

3. The method of claim 1, wherein, The method further comprises: when the average failure rate of the accidental failure is not less than the failure rate threshold, if the length of the use cycle is greater than the use cycle threshold, determining whether a maximum failure rate of the early failure is greater than a preset maximum failure rate threshold, and if yes, determining that the data analysis result of the target integrated circuit is a defect defect; and / or the first conversion time point is a time point between a time node at which the failure rate curve appears to have a slope less than a preset first slope threshold for the first time and a time node at which the failure rate curve appears to have a slope greater than a preset second slope threshold for the first time after the time node; the first slope threshold and the second slope threshold are both less than zero, and the first slope threshold is less than the second slope threshold.

4. The method of claim 3, wherein, The method further comprises: if the maximum failure rate of the early failure is not greater than the maximum failure rate threshold, determining that the data analysis result of the target integrated circuit is a design defect.

5. The method of claim 1, wherein, The method further comprises: In a case where the average failure rate of the accidental failures is not less than the failure rate threshold, if the length of the use period is not greater than the use period threshold, it is determined that the data analysis result of the target integrated circuit is product unqualified.

6. The method of claim 1, wherein, The method further comprises: In a case where the average failure rate of the accidental failures is less than the failure rate threshold, if the length of the use period is not greater than the use period threshold, it is determined that the data analysis result of the target integrated circuit is design unqualified.

7. The method of claim 1, wherein, The method further comprises: The test means is high-pressure cooking test.

8. The method of claim 1, wherein, The method further comprises: The first weight value is positively related to the ratio of the length of the early failures to the length of the reliability test, and is negatively related to the ratio of the accidental failures to the length of the reliability test; and the first weight value in a case where the ratio of the length of the early failures to the length of the reliability test is greater than a preset ratio threshold is greater than the first weight value in a case where the ratio of the length of the early failures to the length of the reliability test is not greater than the ratio threshold.

9. The method of claim 8, wherein, The method further comprises: The ratio threshold is negatively related to the average failure rate of the early failures. 10.A computer readable storage medium storing one or more programs, which when executed by an electronic device comprising a plurality of applications, cause the electronic device to perform any of the methods of claims 1-9.

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