Chip performance test method and system based on automation equipment

Abstract

The invention provides a chip performance test method and system based on automation equipment, and the method comprises the steps: connecting a to-be-tested chip to a test channel through a probe card, sampling a plurality of voltage sensor nodes in a power distribution layer of the probe card, and obtaining the voltage distribution data of a power rail; calculating power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; performing compensation control on the multi-stage parallel capacitor array on the test board according to the prediction data, and executing chip test under the control to obtain a test result and compensation control data; and correcting the test result by using the compensation control data and the voltage distribution data to obtain corrected chip performance parameters. According to the invention, accurate monitoring, prediction, active compensation and correction of the transient voltage drop of the power supply rail are realized, and the accuracy and consistency of chip performance testing are obviously improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly to a method and system for testing chip performance based on an automated device. Background Art

[0002] In the field of integrated circuit testing, chip performance testing is a key link to ensure the functions and performance of chips. Existing methods for testing chip performance based on automated devices usually use fixed test vector sequences to verify the functions and performance of chips. However, during the testing process of high-performance integrated circuits, especially in transient response testing, high-speed switching testing, or analog mixed-signal circuit testing, the power consumption of chips will show characteristics of drastic fluctuations. Such power consumption fluctuations cause transient voltage drops in the power rails of the testing equipment, affecting the stability of the testing voltage. Especially when the chip has sudden high current demands, obvious transient voltage drops will occur in the power rails of the testing equipment, resulting in voltage fluctuations in the maintained voltage. Since existing testing systems usually only perform single-point voltage monitoring at the power supply end and cannot capture voltage changes at different positions in the power distribution network, and at the same time use a single large-capacity decoupling capacitor for power supply stabilization, it is difficult to cope with distributed and high-frequency voltage fluctuations. Therefore, the accuracy and reliability of the testing results are severely affected, especially for the testing of timing-sensitive circuits and chips in low-voltage operating regions. Summary of the Invention

[0003] The main objective of the present invention is to solve the technical problem of deviation in testing results caused by transient voltage drops in the power rails during the existing chip performance testing process; In a first aspect of the present invention, a method for testing chip performance based on an automated device is provided. The automated device includes a test board, a probe card, and test channels. The method for testing chip performance based on the automated device includes: Placing a chip under test on the test board, connecting it to the test channels through the probe card, and performing sampling control on a plurality of voltage sensor nodes arranged in the power distribution layer of the probe card to obtain power rail voltage distribution data; Obtaining a test vector sequence of the chip under test, and calculating power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; According to the power rail voltage drop prediction data, performing compensation control on a multi-stage parallel capacitor array on the test board, and performing chip testing corresponding to the test vector sequence under the compensation control to obtain a chip testing result and power rail compensation control data; According to the power rail compensation control data and the power rail voltage distribution data, performing calibration processing on the chip testing result to obtain calibrated chip performance parameters.

[0004] Optionally, in the first implementation manner of the first aspect of the present invention, the steps of placing the chip under test on the test board, connecting it to the test channel through the probe card, and sampling and controlling a plurality of voltage sensor nodes provided in the power distribution layer of the probe card to obtain power rail voltage distribution data include: Place the chip under test on the test board, connect it to the test channel through the probe card, perform current density analysis on the power distribution layer of the probe card, and determine the key monitoring positions of voltage fluctuations; Divide the power distribution layer of the probe card into multiple sampling regions according to the key monitoring positions, and set voltage sensor nodes in each sampling region; Perform initial sampling on the voltage sensor nodes in each sampling region, obtain the main frequency component and harmonic component of voltage fluctuations, and calculate the bandwidth range of power consumption changes through Fourier transform according to the main frequency component and harmonic component; Configure sampling timing control parameters for the voltage sensor nodes in each sampling region according to the bandwidth range, and transmit the sampling data to the sensor control unit through a low-latency data bus to obtain the power rail voltage distribution data.

[0005] Optionally, in the second implementation manner of the first aspect of the present invention, the steps of obtaining the test vector sequence of the chip under test and calculating the power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model include: Obtain the test vector sequence of the chip under test, and call the corresponding pre-trained neural network model according to the identification code of the chip under test; Segment the test vector sequence according to the execution timing, calculate the signal flip data of each segment of test vectors, and construct a test vector feature matrix; Perform time-domain decomposition on the power rail voltage distribution data, extract the amplitude, frequency, and phase characteristics of voltage fluctuations, and generate a voltage feature matrix; Input the test vector feature matrix and the voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate time-series correlation features; Perform voltage change prediction according to the time-series correlation features through the decoder of the pre-trained neural network model to obtain the power rail voltage drop prediction data.

[0006] Optionally, in the third implementation manner of the first aspect of the present invention, the step of inputting the test vector feature matrix and the voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate time-series correlation features includes: Perform two-way segmentation on the test vector feature matrix, input the forward time-series features of the test vector feature matrix into the forward channel of the bidirectional encoder, and input the reverse time-series features of the test vector feature matrix into the reverse channel of the bidirectional encoder to obtain the bidirectional hidden layer features of the test vector; Perform two-way segmentation on the voltage feature matrix, input the forward time-series features of the voltage feature matrix into the forward channel of the bidirectional encoder, and input the reverse time-series features of the voltage feature matrix into the reverse channel of the bidirectional encoder to obtain the bidirectional hidden layer features of the voltage feature; Calculate the bidirectional cross-attention weights based on the bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage feature, and generate a weight matrix for the forward and reverse features; Perform weighted combination on the bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage feature according to the weight matrix to obtain the time-series correlation features.

[0007] Optionally, in the fourth implementation manner of the first aspect of the present invention, the compensating and controlling the multi-stage parallel capacitor array on the test board according to the power supply rail voltage drop prediction data, and performing the chip test corresponding to the test vector sequence under the compensating control to obtain the chip test result and the power supply rail compensation control data includes: Perform response speed analysis on the power supply rail voltage drop prediction data, and calculate the voltage drop compensation requirements at different time scales; According to the voltage drop compensation requirements at different time scales, calculate the compensation current magnitudes and injection timings of the capacitor units at all levels in the multi-stage parallel capacitor array; Control the charging and discharging of the capacitor units in the multi-stage parallel capacitor array through a multi-channel PWM controller to obtain the power supply rail compensation control data, and perform the test vector sequence under the charging and discharging control to obtain the chip test result.

[0008] Optionally, in the fifth implementation manner of the first aspect of the present invention, the calculating the compensation current magnitudes and injection timings of the capacitor units at all levels in the multi-stage parallel capacitor array according to the voltage drop compensation requirements at different time scales includes: Perform wavelet transform decomposition on the voltage drop compensation requirements at different time scales, decompose the compensation signal into different frequency sub-bands, and calculate the energy distribution characteristics and phase characteristics of each frequency sub-band; Construct a dynamic impedance model according to the parasitic parameters and temperature characteristics of each capacitor unit in the multi-stage parallel capacitor array, and calculate the compensation capabilities of each capacitor unit at different frequencies through the state equation; Optimize the distribution of the compensation tasks for each frequency sub-band based on the genetic algorithm, establish an objective function for the compensation efficiency and compensation timing of the capacitor units, and generate a candidate set of compensation strategies; Iteratively optimize the candidate set of the compensation strategy through the particle swarm optimization algorithm, and calculate the compensation current magnitude and injection timing of each capacitor unit.

[0009] Optionally, in the sixth implementation manner of the first aspect of the present invention, the correcting the chip test result according to the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters includes: Align the power rail compensation control data and the power rail voltage distribution data in a time series to obtain the actual working voltage data; Calculate the working voltage deviation curve of each functional module of the chip under test according to the difference between the nominal working voltage of the chip under test and the actual working voltage data; Associate the performance parameters in the chip test result with the working voltage deviation curve according to the test timing to obtain parameter-voltage relationship data; Perform non-linear correction calculation on the chip test result according to the parameter-voltage relationship data to obtain the corrected chip performance parameters.

[0010] The second aspect of the present invention provides a chip performance test system based on an automated device. The automated device includes a test board, a probe card, and test channels. The chip performance test system based on the automated device includes: A voltage acquisition module, configured to place the chip under test on the test board, connect it to the test channels through the probe card, and sample and control a plurality of voltage sensor nodes provided in the power distribution layer of the probe card to obtain power rail voltage distribution data; A voltage drop prediction module, configured to obtain the test vector sequence of the chip under test, and calculate the power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; A dynamic compensation module, configured to perform compensation control on the multi-stage parallel capacitor array on the test board according to the power rail voltage drop prediction data, and perform the chip test corresponding to the test vector sequence under the compensation control to obtain the chip test result and the power rail compensation control data; A result correction module, configured to correct the chip test result according to the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters.

[0011] The above chip performance testing method and system based on automated equipment connect a chip under test to a test channel through a probe card, sample multiple voltage sensor nodes in the power distribution layer of the probe card to obtain power rail voltage distribution data; calculate power rail voltage drop prediction data according to the power rail voltage distribution data and a test vector sequence through a preset neural network model; perform compensation control on a multi-stage parallel capacitor array on a test board according to the prediction data, and perform chip testing under this control to obtain test results and compensation control data; use the compensation control data and voltage distribution data to correct the test results to obtain corrected chip performance parameters. The present invention realizes precise monitoring, prediction, active compensation and correction of power rail transient voltage drops, and significantly improves the accuracy and consistency of chip performance testing.

[0012] Other features and advantages of the present invention will be described in the following specification, and in part will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention are realized and obtained by the structures specifically pointed out in the specification, claims and drawings.

[0013] To make the above objectives, features and advantages of the present invention more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, the detailed description is as follows. Description of the Drawings

[0014] Figure 1 Schematic diagram of the first embodiment of the chip performance testing method based on automated equipment in the embodiments of the present invention; Figure 2 Schematic diagram of an embodiment of the chip performance testing system based on automated equipment in the embodiments of the present invention. Detailed Embodiments

[0015] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0016] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes other unlisted steps or units, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0017] For the convenience of understanding this embodiment, first, a chip performance testing method based on an automated device disclosed in the embodiments of the present invention will be introduced in detail. The automated device includes a test board, a probe card, and a test channel. As Figure 1 shown, this method includes the following steps: 101. Place the chip to be tested on the test board, connect it to the test channel through the probe card, and perform sampling control on multiple voltage sensor nodes set in the power distribution layer of the probe card to obtain power rail voltage distribution data; In an embodiment of the present invention, the step of placing the chip to be tested on the test board, connecting it to the test channel through the probe card, and performing sampling control on multiple voltage sensor nodes set in the power distribution layer of the probe card to obtain power rail voltage distribution data includes: placing the chip to be tested on the test board, connecting it to the test channel through the probe card, performing current density analysis on the power distribution layer of the probe card to determine the key monitoring positions of voltage fluctuations; dividing the power distribution layer of the probe card into multiple sampling regions according to the key monitoring positions, and setting voltage sensor nodes in each sampling region; initializing the sampling of the voltage sensor nodes in each sampling region, obtaining the main frequency component and harmonic component of voltage fluctuations, and calculating the bandwidth range of power consumption changes through Fourier transform according to the main frequency component and harmonic component; configuring sampling timing control parameters for the voltage sensor nodes in each sampling region according to the bandwidth range, and transmitting the sampling data to the sensor control unit through a low-latency data bus to obtain the power rail voltage distribution data.

[0018] Specifically, in this embodiment, first place the chip under test on the test board and connect it to the test channels through the probe card, thereby establishing an electrical connection from the test equipment to each functional unit of the chip. During the specific operation process, use a vacuum chuck to accurately position the chip under test in the chip fixing area of the test board, and ensure the precise alignment of the chip pins and the test board contacts through the positioning pins and the optical alignment system, with the alignment error controlled within ±5μm. Then start the automatic pressing system and apply a uniform pressure (usually 0.5 - 0.8 kg / cm²) to establish stable contact between the micro-elastic probes on the probe card and the test pads on the chip surface. The system then performs a contact impedance test, measuring the contact impedance of each probe through the four-wire measurement method to ensure that the resistance values of all contact points are less than 100 mΩ and the dispersion does not exceed ±10%. Next, perform a current density analysis on the power distribution layer of the probe card, and use a dedicated power integrity analysis tool (such as Cadence Sigrity or Ansys PowerSI) to build an accurate electrical model of the probe card. The analysis tool combines the SPICE model of the chip with the probe card power network model, and performs transient power analysis for the key state transition points in the test vectors. The system calculates the current density heat map of each node in the power network under different test states, and identifies the areas where the current density exceeds 50 A / cm² or the voltage fluctuation amplitude exceeds 5% of the nominal value as the key monitoring positions.

[0019] Specifically, according to the determined key monitoring positions, the system implements a partition monitoring strategy. First, use the K-means clustering algorithm to perform spatial clustering on these key positions, grouping the points with similar electrical characteristics and close physical positions into one group to initially form the monitoring areas. Subsequently, apply the Voronoi diagram algorithm to optimize the area boundaries to ensure that the monitoring areas consider both spatial distribution and electrical connectivity. Usually, the entire probe card is divided into 10 - 12 areas, and the area of each area is between 5 mm² - 15 mm². After determining the areas, the system uses precise positioning technology to install voltage sensor nodes in each area. These sensor nodes are designed with a dedicated ASIC, with a size of 120μm × 85μm, integrating a 12-bit ADC, a precision reference source, and a digital interface circuit. During the installation process, use a micro-welding device to directly weld the sensor nodes to specific positions on the probe card power layer, with the solder joint spacing controlled at 75μm to ensure the reliability of the electrical connection while minimizing the interference to the original power network as much as possible. The system configures the registers of each sensor node, setting the sampling accuracy, trigger threshold, and working mode to ensure that the sensor nodes can effectively capture voltage fluctuation information in the target areas.

[0020] Specifically, after the sensor layout is completed, the system performs sensor node calibration and initialization sampling processes. During the calibration phase, a high-precision power supply (stability ±0.01%) is used to provide 2-3 standard voltage points (such as 0.9V, 1.0V, 1.1V), the output values of each sensor are recorded, and the gain and bias correction coefficients of the sensors are calculated. Before the initialization sampling starts, the system first places the chip in a typical working state and runs specially designed power supply transient test vectors (including workloads such as high-speed switching, block memory access, and multi-core parallel computing). All sensors start synchronously, the sampling frequency is set to 12.8 GS / s, each sensor continuously collects voltage data for 250 μs, and the sampling depth reaches 3,200,000 points. After the sampling data is processed by a pre-filter (bandwidth upper limit is 4 GHz), the system segments the time-domain data of each sensor into data blocks with a length of 8,192 points, and performs a 512-point overlapping FFT operation on each data block, with a resolution of 1.56 MHz. The system implements a specific spectrum analysis algorithm: First, find the frequency point with the most concentrated energy as the main frequency component by amplitude sorting, and calculate the percentage of its power in the total power; then scan point by point along the frequency axis, and when the energy of a certain frequency point exceeds 10% of the energy of the main frequency component, mark it as a harmonic component, and record its frequency and phase information; perform a refined analysis on each harmonic component, calculate its multiple relationship and phase difference with the main frequency, and distinguish the real harmonics generated by nonlinear loads from the pseudo-harmonics caused by system noise; finally, sort all harmonics according to the energy contribution size, and retain the first 5 harmonics as the characteristic harmonic components.

[0021] Specifically, based on the obtained main frequency and harmonic data, the system executes a bandwidth determination algorithm. First, a spectral energy cumulative distribution function is established. Starting from the low frequency, the energy cumulative percentage is calculated, and the frequency upper limit containing 98% of the signal energy is determined as the actual bandwidth boundary. Typically, the bandwidth range of the chip power supply fluctuation is between 100 MHz and 2.5 GHz. The system customizes sampling parameters for each sampling area according to the determined bandwidth data. For example, for the digital core area with a high power switching frequency, the sampling rate is set to 5 GS / s; while for the analog peripheral area with slower fluctuations, the sampling rate is set to 1.2 GS / s. At the same time, the system configures an adaptive trigger threshold for the sensor nodes according to the characteristic frequencies of each area, and generally sets the trigger sensitivity to ±1.5% of the nominal voltage. The sampling timing control adopts a time-division multiplexing strategy, dividing all sensors into 3 - 4 groups. The sensors within each group sample at staggered peaks, and the sampling time between groups is staggered by 10 - 15 ns to prevent power interference caused by simultaneous sampling. The system uses a customized low-latency data bus to collect sampling data. This bus is designed based on a high-speed serial interface, with a bandwidth of 3.2 Gbps for each channel, and a 7-bit check code and a 16-bit timestamp mark are attached to the data of each sampling point. The data is transmitted through the bus to the central sensor control unit, and the control unit performs real-time data verification and recombination, reconstructing the data from different areas into a complete power rail voltage distribution data set in chronological order. This data set is stored in a three-dimensional data structure, including three dimensions: spatial coordinates, time coordinates, and voltage values, and a test vector execution status mark is attached to form a complete dynamic mapping of the power rail voltage distribution.

[0022] 102. Obtain the test vector sequence of the chip under test, and calculate the power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; In an embodiment of the present invention, the obtaining the test vector sequence of the chip under test and calculating the power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model includes: obtaining the test vector sequence of the chip under test, and calling the corresponding pre-trained neural network model according to the identification code of the chip under test; segmenting the test vector sequence according to the execution timing, calculating the signal flip data of each segment of the test vector, and constructing a test vector feature matrix; performing time-domain decomposition on the power rail voltage distribution data, extracting the amplitude, frequency, and phase characteristics of the voltage fluctuation, and generating a voltage feature matrix; inputting the test vector feature matrix and the voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate a time-series correlation feature; and performing voltage change prediction according to the time-series correlation feature through the decoder of the pre-trained neural network model to obtain the power rail voltage drop prediction data.

[0023] Specifically, in this embodiment, first, the test vector sequence of the chip under test is obtained from the test plan library of the test system. The test vector sequence is usually stored in the standard test vector format (STIL or WGL format), and includes input excitation signals, expected output responses, and timing control information. The system identifies the specific model and version information of the chip by reading the electronic identification code on the chip package or wafer (usually a 64-bit binary code, including the manufacturer information, chip series model, process version, etc.). The identification code is obtained using a dedicated read instruction, and during the read process, a 3.3V TTL level signal is used to complete the serial data communication. After obtaining the identification code, the system queries the model library index table, which contains the mapping relationship between different chip models and the corresponding pre-trained neural network models. For a specific chip under test, such as an ARM Cortex-A78 architecture processor using a 14nm process, the system will call the pre-trained model specifically trained for this chip series. These models are stored in the model library of the system and saved in the standard HDF5 format, including network weights, neuron bias values, model hyperparameters, and normalization parameters. The model call process is implemented through a cache loading mechanism, loading the model parameters into the GPU or dedicated TPU computing unit, initializing the running environment, and preparing to start the prediction calculation.

[0024] Specifically, after obtaining the test vector sequence, the system performs segmentation processing on it in the time dimension. First, according to the test clock signal, the test vector sequence is divided into paragraphs of fixed length according to the execution timing. Each paragraph usually contains 1000 - 2000 consecutive test vectors. The segmentation length is determined according to the clock frequency of the chip and the discharge time constant of the power supply network to ensure the continuous correlation of the power state within each paragraph. For each paragraph of test vectors, the system calculates the signal flip data, including the state change of each signal line. In the specific calculation process, the system first represents each test vector as a binary signal state vector, and then calculates the Hamming distance (i.e., the number of bits with state flips) between adjacent test vectors. For a chip with 256 input pins, the system constructs a 256-dimensional flip vector, and each dimension represents the number of flips of the corresponding pin during adjacent test cycles. Further, the system also calculates the weighted flip data, considering the difference in load capacitance of different pins. For example, pins connected to a large-area bus have a larger load capacitance, and the current consumption caused by their flips is more, so they are given a higher weight. The system assigns a weight factor (usually in the range of 0.5 - 2.5) to each pin according to the load parameters in the chip design file, and multiplies it by the original flip data to obtain the weighted flip data. Finally, the system integrates the weighted flip data of each paragraph of test vectors into a test vector feature matrix, and the matrix dimension is the number of paragraphs × feature dimension, where the feature dimension includes multi-dimensional features such as the total number of flips, the maximum continuous number of flips, and the flip mode of the pin group.

[0025] Specifically, at the same time, the system performs time-domain decomposition and feature extraction on the acquired power rail voltage distribution data. First, the empirical mode decomposition (EMD) algorithm is applied to decompose the voltage waveform into multiple intrinsic mode functions (IMFs), and each IMF represents a characteristic oscillation mode in voltage fluctuations. Typically, the system extracts 5 - 7 IMF components, covering the complete spectrum from high-frequency transient responses to low-frequency voltage drifts. For each IMF component, the system calculates the instantaneous amplitude and instantaneous phase through the Hilbert transform to obtain the dynamic characteristics of voltage fluctuations at different time scales. During the feature extraction process, the system calculates the main characteristic parameters of each IMF, including the mean amplitude, maximum amplitude, amplitude standard deviation, dominant frequency component, phase change rate, etc. In addition, the system also extracts the statistical features of the voltage waveform, such as skewness, kurtosis, average crossing rate, etc., to capture the non-Gaussian characteristics of the voltage distribution. For the spatially distributed voltage data, the system uses the principal component analysis (PCA) method for dimensionality reduction, retaining the principal components that explain 95% of the variance and reducing data redundancy. Finally, the system combines these time-domain features, frequency-domain features, and statistical features into a voltage feature matrix, which has two dimensions: the number of time windows × the feature dimension. The feature dimension is usually 30 - 50, containing multi-angle descriptions of voltage fluctuations.

[0026] Specifically, after completing the construction of the test vector feature matrix and the voltage feature matrix, the system inputs them into the bidirectional encoder of the pre-trained neural network model for processing. The bidirectional encoder is designed with a BiLSTM (bidirectional long short-term memory network) structure, including a forward recursive unit and a backward recursive unit. The forward recursive unit starts from the starting point of the time series and processes data in chronological order; the backward recursive unit starts from the end of the sequence and processes data in the reverse time direction. The input layer of the network receives the concatenated vector of the test vector feature matrix and the voltage feature matrix, and is converted into a unified feature representation through an embedding layer with 128 units. The BiLSTM layer contains 64 LSTM units in each of the forward and backward directions. Each LSTM unit contains an input gate, a forget gate, an output gate, and a memory unit, and determines the flow of information by controlling the on / off states of these gates. The forward LSTM captures the causal relationship between the test vector and voltage fluctuations, while the backward LSTM captures the global constraint conditions of the voltage distribution. Together, they establish a complete temporal dependence model. After the BiLSTM layer is the attention mechanism layer, which calculates the importance weights at each time step, enabling the model to focus on the time points that are most critical for voltage prediction. Finally, the bidirectional encoder generates temporal correlation features containing rich context information, which encode the potential laws of voltage fluctuations during the execution of the test vector.

[0027] Specifically, after the temporal correlation features are generated, they are passed to the decoder part of the pre-trained neural network model for voltage change prediction. The decoder adopts a multi-layer Transformer structure, including 4 decoder blocks, and each block contains a multi-head self-attention layer and a feed-forward neural network layer. The self-attention mechanism allows the model to associate each position in the input sequence with all other positions, effectively modeling long-range dependencies. In the specific implementation, 8 attention heads are used, and the dimension of each attention head is 64, allowing the model to simultaneously focus on different aspects of the input sequence. The decoding process is carried out in an autoregressive manner, that is, the model first predicts the voltage change at the next time step, and then uses the prediction result as the new input to continue predicting further time steps. To improve the prediction accuracy, the system adopts a beam search algorithm, maintains multiple candidate prediction paths, and selects the optimal path according to the cumulative probability as the final prediction result. The output of the decoder is converted into the expected voltage change value through a fully connected layer, covering the voltage fluctuations within 100 - 500 test vector execution cycles in the future. Finally, the system combines the predicted voltage change with the nominal voltage value to construct the complete power rail voltage drop prediction data, which contains three dimensions: time, spatial position, and predicted voltage value, forming an accurate prediction map of the future state of the power network.

[0028] Further, the generating the temporal correlation features by inputting the test vector feature matrix and the voltage feature matrix into the bidirectional encoder of the pre-trained neural network model includes: performing bidirectional segmentation on the test vector feature matrix, inputting the forward temporal features of the test vector feature matrix into the forward channel of the bidirectional encoder, inputting the reverse temporal features of the test vector feature matrix into the reverse channel of the bidirectional encoder, and obtaining the bidirectional hidden layer features of the test vector; performing bidirectional segmentation on the voltage feature matrix, inputting the forward temporal features of the voltage feature matrix into the forward channel of the bidirectional encoder, inputting the reverse temporal features of the voltage feature matrix into the reverse channel of the bidirectional encoder, and obtaining the bidirectional hidden layer features of the voltage feature; calculating the bidirectional cross-attention weights according to the bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage feature to generate a weight matrix of positive and reverse features; and performing weighted combination on the bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage feature according to the weight matrix to obtain the temporal correlation features.

[0029] Specifically, first, the test vector feature matrix is processed by bidirectional segmentation to make full use of the bidirectional information of the test vector in the time series. In specific implementation, the system first divides the original test vector feature matrix (with dimensions N×F, where N is the time step and F is the feature dimension) along the time axis into multiple overlapping windows of length L, and the overlapping rate of adjacent windows is set to 50%. For the data of each window, the system constructs two representations: forward temporal features and backward temporal features. The forward temporal features maintain the original time order, that is, from t0 to tL-1; the backward temporal features reverse the time order, from tL-1 to t0. This bidirectional segmentation strategy enables the model to consider both causal relationships (forward propagation) and constraints (backward propagation) simultaneously. Subsequently, the system inputs the forward temporal features into the forward channel of the bidirectional encoder, which consists of three stacked GRUs (gated recurrent units), with each layer containing 128 neurons. The forward channel starts processing from the beginning of the sequence and gradually updates the hidden state in chronological order. At the same time, the system inputs the backward temporal features into the backward channel of the bidirectional encoder, which also consists of three stacked GRUs, but the processing direction is opposite to that of the forward channel. The backward channel starts from the end of the sequence and updates the hidden state in reverse chronological order. After the two channels process the data independently, the system extracts all the time step outputs of the last layer GRU of each channel and combines them to form the bidirectional hidden layer features of the test vector, represented as a tensor Ht with dimensions N×(2×128), where the first 128 dimensions represent the forward channel features and the last 128 dimensions represent the backward channel features.

[0030] Specifically, the same processing flow is also applied to the voltage feature matrix to capture the bidirectional temporal characteristics of voltage changes. The voltage feature matrix (with dimensions N×E, where E is the voltage feature dimension) first constructs forward and backward temporal representations through the same window slicing method. The voltage feature is processed using a bidirectional encoder with the same architecture as the test vector feature, but with independent weight parameters to optimize specifically for the temporal pattern of voltage features. In specific implementation, the forward channel adopts a residual connection structure, adding skip connections after each layer of GRU to alleviate the problem of gradient vanishing; the backward channel adopts layer normalization technology to improve the training stability. The forward channel processes the forward temporal data of voltage features to capture the progressive trend of voltage changes; the backward channel processes the backward temporal data to identify the mutation points and rebound patterns of voltage fluctuations. After processing, the system also extracts all the time step outputs of the last layer GRU of the two channels to form the bidirectional hidden layer features of voltage features, Hv, a tensor with dimensions N×(2×128). The bidirectional processing enables the model to understand the behavior patterns of voltage fluctuations at different time scales, including fast transient responses and slow accumulation effects, greatly improving the modeling ability for complex voltage changes.

[0031] Specifically, after obtaining the bidirectional hidden layer features of the test vector and voltage features, the system calculates the bidirectional cross-attention weights to establish the correlation between the two types of features. First, the system maps the bidirectional hidden layer features Ht of the test vector to a query matrix Q (with a dimension of N×64) through a linear transformation; the bidirectional hidden layer features Hv of the voltage features are respectively mapped to a key matrix K (with a dimension of N×64) and a value matrix V (with a dimension of N×64) through different linear transformations. The linear transformation adopts a weight sharing mechanism to reduce the number of parameters while maintaining the model's expressive ability. Then, the system calculates the dot product of the query matrix and the key matrix, divides it by the scaling factor 8 (i.e., the square root of the feature dimension), and then applies the softmax function for normalization to obtain the attention weight matrix A with a dimension of N×N. Each element Aij of the attention weight matrix represents the degree of attention of the test vector feature at the i-th time step to the voltage feature at the j-th time step. To enhance the model's ability to model long-term dependencies, the system also implements a multi-head attention mechanism, which projects the hidden layer features in parallel into 8 subspaces, calculates the attention weights respectively, and then combines the results. In addition, the system introduces relative position encoding, considering the relative distance between the test vector and voltage features in the time dimension, enabling the model to capture local and global dependencies in the time series. The finally generated weight matrix contains the weights of four cross relationships: positive feature and positive feature, positive feature and negative feature, negative feature and positive feature, and negative feature and negative feature.

[0032] Specifically, based on the calculated weight matrix, the system performs a weighted combination of the bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage features to generate the temporal correlation features. First, the system multiplies the weight matrix by the value matrix to obtain the weighted voltage feature representation. Then, the weighted voltage feature is combined with the original test vector hidden layer features through a gated fusion mechanism. In the specific implementation, the system uses a two-layer feed-forward neural network to calculate the fusion gate value, and the gate value ranges from 0 to 1, controlling the fusion ratio of the original feature and the weighted feature. The calculation of the fusion gate takes into account the local context information of the features and assigns different weights to the noise features and strongly correlated features. The fused features go through layer normalization and residual connection to form the preliminary correlation features. Then, the system further transforms the features using a two-layer position-aware feed-forward network to extract more abstract representations. The hidden layer dimension of the feed-forward network is 512, and it uses the GELU activation function, which has good non-linear modeling ability. Finally, the system applies a feature enhancement module to extract global statistical features through global average pooling and max pooling operations and combines them with the local features to form the final temporal correlation features. The obtained temporal correlation features are a tensor with a dimension of N×256, and each row represents the comprehensive feature representation at a time step, containing the in-depth interaction information between the test vector and voltage features in the time series, and can effectively express the influence pattern of the test vector on voltage changes and the feedback effect of the voltage state on subsequent test executions.

[0033] 103. According to the predicted data of the power supply rail voltage drop, perform compensation control on the multi-stage parallel capacitor array on the test board, and perform chip testing corresponding to the test vector sequence under the compensation control to obtain the chip test result and the power supply rail compensation control data; In an embodiment of the present invention, the performing compensation control on the multi-stage parallel capacitor array on the test board according to the predicted data of the power supply rail voltage drop and performing chip testing corresponding to the test vector sequence under the compensation control to obtain the chip test result and the power supply rail compensation control data includes: performing response speed analysis on the predicted data of the power supply rail voltage drop, and calculating the voltage drop compensation requirements at different time scales; according to the voltage drop compensation requirements at different time scales, calculating the compensation current magnitudes and injection timings of the capacitor units at all levels in the multi-stage parallel capacitor array; controlling the charging and discharging of the capacitor units in the multi-stage parallel capacitor array through a multi-channel PWM controller to obtain the power supply rail compensation control data, and performing the test vector sequence under the charging and discharging control to obtain the chip test result.

[0034] Specifically, first perform response speed analysis on the predicted data of the power supply rail voltage drop to determine the voltage drop compensation requirements at different time scales. The system uses the multi-resolution wavelet analysis method to perform time-frequency domain decomposition on the predicted data of the power supply rail voltage drop, and performs 5-level decomposition using the db4 wavelet basis function to decompose the original predicted data into components in different frequency bands. The decomposed data includes high-frequency detail component D1 (corresponding frequency range 1 - 2 GHz), medium-high frequency detail component D2 (500 MHz - 1 GHz), medium-frequency detail component D3 (250 - 500 MHz), medium-low frequency detail component D4 (125 - 250 MHz), low-frequency detail component D5 (62.5 - 125 MHz), and low-frequency approximation component A5 (0 - 62.5 MHz). For the components in each frequency band, the system calculates their energy distribution and time response characteristics, including parameters such as peak amplitude, energy ratio, rising edge rate, and duration. High-frequency components usually reflect the spike voltage drops caused by events such as rapid switching of the chip core and clock edge triggering; medium-frequency components reflect the fluctuations caused by operations such as data bus transmission and memory access; while low-frequency components represent the temperature effects and cumulative voltage drops caused by long-term operation. The system combines these analysis results to construct a three-dimensional time-frequency-amplitude feature map and maps it into a voltage drop compensation requirement matrix at different time scales. Each element in the matrix contains information in three dimensions: time point, frequency segment, and required compensation current value.

[0035] Specifically, based on the voltage drop compensation requirements at different time scales, the system calculates the compensation current magnitudes and injection timings of each capacitor cell in the multi-stage parallel capacitor array. The multi-stage parallel capacitor array on the test board consists of three types of capacitor cells: large-capacity electrolytic capacitors (330 μF - 470 μF, ESR about 10 - 15 mΩ), medium-capacity ceramic capacitors (4.7 μF - 10 μF, ESR about 5 - 8 mΩ), and small-capacity thin-film capacitors (0.01 μF - 0.1 μF, ESR about 2 - 3 mΩ). The system first establishes an accurate equivalent circuit model of the capacitor array, including the capacitance value, equivalent series resistance, equivalent series inductance of each capacitor cell, and the interconnection impedance between cells. Then, the system uses the state space method to solve the optimal charge and discharge control strategy. In the specific implementation, the system constructs an objective function, taking the mean square error between the predicted voltage and the desired voltage as the main optimization objective, while considering switching losses and stability constraints. The optimization process adopts a model predictive control framework to gradually solve the optimal control sequence within a sliding time window. For high-frequency voltage drop compensation requirements, the system mainly calls small-capacity thin-film capacitor cells and sets their charge and discharge cycles within the range of 5 - 20 ns; for medium-frequency voltage drops, it calls medium-capacity ceramic capacitor cells with charge and discharge cycles set within the range of 50 - 200 ns; for low-frequency voltage drops, it calls large-capacity electrolytic capacitor cells with charge and discharge cycles in the range of 500 ns - 2 μs. The system also considers the position distribution of the capacitor cells and preferentially calls the capacitor cells closer to the voltage drop hotspots to reduce transmission delays. Finally, the system generates a complete control strategy for the capacitor cells, including the activation time, conduction duration, and compensation current magnitude of each capacitor cell.

[0036] Specifically, after the calculation of the control strategy is completed, the system performs precise charge and discharge control on the capacitor units in the multi-level parallel capacitor array through a multi-channel PWM controller. The multi-channel PWM controller is implemented using a dedicated FPGA, has 128 independent control channels, each channel is equipped with a high-speed MOSFET drive circuit, the drive ability reaches 2A, and the rise time is less than 3ns. The clock frequency of the controller is set to 500MHz, the PWM resolution is 10 bits, and the minimum pulse width modulation accuracy of 1ns can be achieved. The system converts the control strategy of the capacitor unit calculated in the previous step into specific PWM parameters, including PWM frequency, duty cycle, and phase. For high-frequency compensation that requires precise control, the system adopts a multi-phase interleaved PWM technology to superimpose multiple PWM signals with staggered phases to achieve an equivalent resolution improvement. The controller also integrates an adaptive dead-time control function to dynamically adjust the dead time (usually 2 - 5ns) according to the switching characteristics of the MOSFET to prevent through-current. The PWM signal controls the on and off of the MOSFET switch through an isolation buffer and a drive amplifier, thereby realizing the charge and discharge process of the capacitor unit. The actual compensation current of each capacitor unit is monitored in real time through an integrated current sensor to form a closed-loop control system. The system records all control parameters and monitoring data as power rail compensation control data, including the PWM parameters, switch states, compensation current values, and actual power supply voltage values of each capacitor unit at each time point, for subsequent test result correction.

[0037] Specifically, after establishing a complete compensation control system, the system performs chip testing corresponding to the test vector sequence under dynamic compensation conditions. The test execution process adopts a synchronous control strategy, and the test vector generator and the PWM controller maintain consistent timing through an accurate clock synchronization mechanism, with the deviation controlled within 100ps. The system first enters a warm-up phase and runs a set of standard test vectors (lasting about 100μs) to make the capacitor array reach a stable operating state. Then the system starts the formal test process. The test vector generator applies input excitation to the chip according to the predetermined timing, and at the same time, the PWM controller adjusts the compensation state of the capacitor array in real time according to the pre-calculated control strategy. During the test process, the system continuously monitors the output response and power supply voltage state of the chip to form a closed-loop adjustment mechanism. If the actual voltage deviates from the predicted value by more than the preset threshold (usually ±3% of the nominal voltage), the system will trigger an emergency compensation adjustment logic to temporarily increase the compensation intensity. The test data acquisition system records all output signals and power supply state information of the chip, with the sampling rate set to 5GS / s and the accuracy of 12 bits. After the test is completed, the system performs preliminary processing on the collected raw data, including digitization, denoising, and time alignment, to generate a structured chip test result data set. This data set contains information such as test vector ID, timestamp, input state, output response, expected output, and power supply voltage value.

[0038] Further, calculating the compensation current magnitudes and injection timings of the capacitor units at all levels in the multi-stage parallel capacitor array according to the voltage drop compensation requirements at different time scales includes: performing wavelet transform decomposition on the voltage drop compensation requirements at different time scales, decomposing the compensation signal into different frequency sub-bands, and calculating the energy distribution characteristics and phase characteristics of each frequency sub-band; constructing a dynamic impedance model according to the parasitic parameters and temperature characteristics of the capacitor units in the multi-stage parallel capacitor array, and calculating the compensation capabilities of the capacitor units at different frequencies through the state equation; optimizing the distribution of the compensation tasks for each frequency sub-band based on the genetic algorithm, establishing an objective function for the compensation efficiency and compensation timing of the capacitor units, and generating a candidate set of compensation strategies; and iteratively optimizing the candidate set of compensation strategies through the particle swarm optimization algorithm to calculate the compensation current magnitudes and injection timings of the capacitor units.

[0039] Specifically, first, wavelet transform decomposition is performed on the voltage drop compensation requirements at different time scales to accurately distinguish the compensation characteristics of different frequency components. The system uses the dual-tree complex wavelet transform (DWPT) technique and selects the Daubechies 8 (db8) wavelet basis function for decomposition. This function has good time-frequency localization characteristics and smoothness, and is suitable for processing the spike and oscillation components in the power supply waveform. During the decomposition process, the system decomposes the original compensation requirement signal into 7 levels according to the binary tree structure, generating a total of 128 frequency sub-bands, covering the complete frequency spectrum range from 5 MHz to 2.5 GHz. For each frequency sub-band, the system calculates four groups of key characteristic parameters: energy density (energy distribution per unit time), peak factor (ratio of the maximum amplitude to the root mean square), in-band frequency center (energy-weighted average frequency), and phase continuity (phase change rate between adjacent time windows). These parameters reflect the distribution characteristics of different frequency components in the time and amplitude dimensions. Especially for high-frequency transient voltage drops, the system additionally calculates the rise time and duration to accurately characterize their time-domain characteristics. After processing, the system organizes these characteristics into a structured spectral map, including four dimensions of time-frequency-energy-phase, describing the complete characteristics of the voltage drop compensation requirements on different frequency sub-bands, and providing a data basis for subsequent compensation resource allocation.

[0040] Specifically, the system constructs an accurate dynamic impedance model based on the parasitic parameters and temperature characteristics of each capacitor unit in the multi-level parallel capacitor array. The capacitor array on the test board includes three types of capacitor units: large-capacity electrolytic capacitors (330 μF, ESR = 12 mΩ, ESL = 15 nH), medium-capacity ceramic capacitors (10 μF, ESR = 6 mΩ, ESL = 5 nH), and small-capacity thin-film capacitors (0.1 μF, ESR = 3 mΩ, ESL = 1 nH), corresponding to low-frequency, medium-frequency, and high-frequency compensation requirements respectively. First, the system measures the impedance characteristics of each type of capacitor unit at different frequencies (from 100 kHz to 3 GHz) using a vector network analyzer, generating impedance curves at 25 frequency points. Then, the system represents each capacitor unit using the Foster equivalent circuit model, which includes an RLC parallel branch and a series impedance, and determines the model parameters through a curve fitting algorithm. To consider the influence of temperature, the system establishes parameter models at three key temperature points (25 °C, 55 °C, and 85 °C) respectively, and uses piecewise linear interpolation to calculate the parameter values at intermediate temperatures. The position effect of the capacitor units is also incorporated into the model, and by establishing a planar electromagnetic field distribution map based on measured data, the electrical coupling coefficient of capacitor units at different positions is calculated. Finally, the system integrates all parameters into the state-space equation, which uses differential-algebraic equations (DAE) to describe the dynamic characteristics of the system, and solves the transient responses of each capacitor unit under different operating states through numerical integration to obtain a complete compensation ability evaluation index, including response delay, peak compensation current, energy efficiency, and stable operating region.

[0041] Specifically, based on the spectral features and the dynamic model of the capacitor units obtained in the first two steps, the system applies a genetic algorithm to optimize the allocation of compensation tasks for each frequency sub-band. The genetic algorithm uses 128-bit binary encoding to represent a compensation strategy, where each gene bit represents whether a frequency sub-band is allocated to a specific type of capacitor unit. The initial population contains 500 randomly generated strategies to ensure sufficient coverage of the solution space. The fitness function design comprehensively considers three factors: compensation accuracy (the mean square error between the predicted voltage and the target voltage), energy efficiency (the energy consumption during the compensation process), and switching losses (the number of switchings of the capacitor units). The fitness calculation uses a weighted summation method to comprehensively evaluate the performance under different test scenarios. The genetic operations include elitist selection, single-point crossover, and uniform mutation, with the crossover probability set to 0.85 and the mutation probability set to 0.05. To accelerate convergence, the algorithm adopts adaptive genetic parameters and dynamically adjusts the operation probabilities according to the population diversity. After 200 generations of iteration, the algorithm generates a set of Pareto non-dominated solution sets, representing the optimal trade-offs between different compensation strategies. For each candidate strategy, the system calculates in detail the allocation scheme of 128 frequency sub-bands among the three types of capacitor units, as well as the preliminary compensation timing of each capacitor unit. From these non-dominated solutions, the system selects 50 representative solutions to form a compensation strategy candidate set as the initial point for the next optimization.

[0042] Specifically, the system finely iteratively optimizes the compensation strategy candidate set through a particle swarm optimization algorithm, and calculates the exact compensation current magnitude and injection timing of each capacitor unit. The particle swarm algorithm uses 50 particles corresponding to the 50 candidate strategies generated by the genetic algorithm. Each particle contains three groups of parameters: the capacitor unit activation time series, the current amplitude modulation coefficient, and the phase adjustment factor. The position of the particle represents a specific compensation control scheme, and the velocity represents the search direction and step size. The objective function design uses a weighted synthesis method to combine the three objectives of minimizing voltage error, minimizing power consumption, and minimizing response time into a single score. The inertia weight is set to a linearly decreasing strategy, from 0.9 to 0.4, so that the algorithm has strong global search ability in the early stage and fine local optimization ability in the later stage. The individual best position and the global best position respectively record the historical best solutions of each particle and the entire population, guiding the movement direction of the particles. To improve the search efficiency, the algorithm introduces a dynamic topology structure and adaptively adjusts the information sharing range according to the Euclidean distance between particles. After 150 iterations, the algorithm converges to a stable solution and generates a complete compensation control strategy. The final output result includes the exact compensation parameters of each capacitor unit (a total of 56): the activation time point (with an accuracy of 1 ns), the current amplitude modulation curve (represented by 10-point piecewise linearity), the action duration, and the cooling time. These parameters constitute a complete control scheme for the multi-stage parallel capacitor array, ensuring precise power supply rail voltage drop compensation on different frequency sub-bands.

[0043] 104. Correct the chip test results according to the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters.

[0044] In an embodiment of the present invention, the correcting the chip test results according to the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters includes: aligning the power rail compensation control data and the power rail voltage distribution data in time series to obtain the actual working voltage data; calculating the working voltage deviation curves of each functional module of the chip under test according to the difference between the nominal working voltage of the chip under test and the actual working voltage data; associating the performance parameters in the chip test results with the working voltage deviation curves according to the test timing to obtain parameter-voltage relationship data; and performing non-linear correction calculation on the chip test results according to the parameter-voltage relationship data to obtain the corrected chip performance parameters.

[0045] Specifically, first perform time series alignment processing on the power rail compensation control data and the power rail voltage distribution data to obtain complete actual working voltage data. The system adopts a multi-source data synchronization algorithm based on timestamps to process two sets of time series data: the power rail compensation control data (including PWM control parameters, switch states, and compensation current values) and the power rail voltage distribution data (including voltage measurement values at each sampling point). The alignment process first constructs a unified time reference line, with the test vector clock as the main reference and a time resolution of 100 ps. Then the system maps the two sets of data to the reference time axis according to their respective timestamps. For regions with inconsistent sampling points, the cubic spline interpolation method is used to calculate the values at intermediate times. During the alignment process, the system also handles the sampling delay problems of different data sources, calculates the relative delay between each data stream through cross-correlation analysis, with typical delay values of 3 - 15 ns, and performs time offset compensation accordingly. After data alignment, the system combines the compensation current in the compensation control data with the voltage distribution data and uses a distributed circuit model to calculate the actual working voltage of each functional area of the chip. The impedance characteristics of the power distribution network, the spatial distribution effect of the compensation current, and the voltage drop difference between the voltage measurement points and the actual chip power supply points are considered in the calculation. The finally generated actual working voltage data is a three-dimensional data structure, including three coordinate axes: the time dimension (test cycle), the spatial dimension (chip functional area), and the voltage value, which completely records the actual power supply status of each area of the chip during the test.

[0046] Based on the acquired actual operating voltage data, the system calculates the operating voltage deviation curves of each functional module of the chip under test. First, the system extracts the nominal operating voltage data from the chip design database, which includes the designed voltage values and allowable fluctuation ranges of different functional modules of the chip (such as core logic, I / O interface, analog circuit, memory cell, etc.). During the nominal voltage extraction process, the system considers the configuration information of different power domains. For example, the nominal voltage of the core logic area is 0.9V, the I / O area is 1.8V, and the analog circuit area is 2.5V, etc. Then the system compares the actual operating voltage data with the nominal voltage to calculate the voltage deviation value ΔV = V_actual - V_nominal. To accurately characterize the voltage state of each functional module, the system divides the planar layout of the chip into regions. According to the layout data, the chip is divided into 16 main functional blocks, and corresponding voltage monitoring points are assigned to each block. For areas with insufficient voltage monitoring points, the system constructs a voltage distribution interpolation model based on the power network topology and equipotential surface characteristics to estimate the voltage values of the areas not directly monitored. The temperature effect is also considered during the calculation of the operating voltage deviation. Through the readings of the temperature sensors integrated on the chip and combined with the voltage-temperature sensitivity coefficient (usually -1.5mV / °C to -2.2mV / °C), the voltage offset caused by temperature fluctuations is corrected. The finally generated operating voltage deviation curve contains two dimensions: the time dimension (the execution process of the test vector sequence) and the space dimension (the 16 functional blocks of the chip), recording the dynamic changes of the voltage deviation during the entire test process.

[0047] Next, the system performs a correlation analysis on the performance parameters and the working voltage deviation curve in the chip test results to establish parameter-voltage relationship data. First, the system extracts key performance parameters from the original test results, including digital circuit parameters (such as logic gate delay, flip-flop setup time, clock skew, etc.), analog circuit parameters (such as amplifier gain, bandwidth, signal-to-noise ratio, etc.), and mixed-signal parameters (such as ADC / DAC linearity, effective number of bits, etc.). The parameter extraction process is based on a specific test vector sequence and the corresponding output response. For example, the logic gate delay is calculated by measuring the time interval between the input change and the output change; the amplifier gain is determined by the ratio of the input and output voltages. Then the system establishes a mapping relationship between the performance parameters and the test timing, determining the exact measurement time points of each parameter in the test vector sequence. This mapping is obtained through the test program flowchart and vector annotation information, and each performance parameter is assigned one or more timestamps indicating the moment when the measurement occurs. Subsequently, the system aligns these time points with the previously calculated working voltage deviation curve to find the actual working voltage value corresponding to each parameter measurement moment. For parameters whose measurement process spans multiple test cycles, the system calculates the voltage statistical characteristics within this time window, including the average value, maximum deviation, standard deviation, etc. The finally generated parameter-voltage relationship data is an association table, where each row contains a performance parameter, its measured value, normal range, measurement time period, and the corresponding voltage deviation characteristics, comprehensively describing the impact of voltage changes on the test results.

[0048] Based on the established parameter-voltage relationship data, the system performs non-linear correction calculations on the chip test results to obtain the corrected chip performance parameters. The correction process first extracts the sensitivity coefficients of each parameter to voltage changes from a pre-constructed parameter sensitivity library. These sensitivity coefficients are obtained through off-line characterization experiments, during which parameter measurements are performed on standard chip samples under different voltage conditions to establish parameter-voltage response curves. For example, the logic gate delay parameter usually shows a relationship proportional to the reciprocal of voltage, and its sensitivity curve is described by a piecewise polynomial model; while analog parameters such as the gain of an operational amplifier often exhibit non-linear response characteristics and are represented by high-order polynomials or look-up tables. For each measured parameter, the system extracts the corresponding correction model from the sensitivity library and calculates the parameter correction value based on the actual voltage deviation. The calculation process uses an adaptive correction algorithm, applying different correction strategies for different degrees of voltage deviation: linear correction for small deviations (<3%), second-order polynomial correction for medium deviations (3%-8%), and look-up table interpolation method for large deviations (>8%). The correction calculation also takes into account the mutual influence between parameters, describing the multi-parameter coupling effect through a sensitivity matrix. Especially for related parameters sharing the same power supply domain, a joint correction strategy is adopted to improve accuracy. Finally, the system generates a complete set of corrected chip performance parameters, and each parameter contains four parts of information: the original measured value, the correction value, the correction confidence level, and the reference range. The corrected performance parameters reflect the true performance characteristics of the chip under standard voltage conditions, eliminating the measurement bias introduced by power supply rail voltage drops, and providing an accurate and reliable basis for chip performance evaluation and grading.

[0049] In this embodiment, the chip under test is connected to the test channel through a probe card, and multiple voltage sensor nodes in the power distribution layer of the probe card are sampled to obtain power supply rail voltage distribution data; a preset neural network model calculates power supply rail voltage drop prediction data based on the power supply rail voltage distribution data and the test vector sequence; the multi-stage parallel capacitor array on the test board is compensated and controlled according to the prediction data, and the chip test is performed under this control to obtain the test results and compensation control data; the test results are corrected using the compensation control data and the voltage distribution data to obtain the corrected chip performance parameters. The present invention realizes the precise monitoring, prediction, active compensation, and correction of power supply rail transient voltage drops, significantly improving the accuracy and consistency of chip performance testing.

[0050] The method for testing chip performance based on an automated device in the embodiments of the present invention has been described above. Next, the system for testing chip performance based on an automated device in the embodiments of the present invention will be described. Please refer to Figure 2 , an embodiment of the system for testing chip performance based on an automated device in the embodiments of the present invention includes: The voltage acquisition module 201 is configured to place the chip under test on the test board, connect it to the test channel through the probe card, and perform sampling control on multiple voltage sensor nodes arranged in the power distribution layer of the probe card to obtain power rail voltage distribution data; The voltage drop prediction module 202 is configured to obtain the test vector sequence of the chip under test, and calculate the power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; The dynamic compensation module 203 is configured to perform compensation control on the multi-stage parallel capacitor array on the test board according to the power rail voltage drop prediction data, and perform the chip test corresponding to the test vector sequence under the compensation control to obtain the chip test result and the power rail compensation control data; The result correction module 204 is configured to perform correction processing on the chip test result according to the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters.

[0051] In the embodiment of the present invention, the chip performance test system based on the automation device runs the above-mentioned chip performance test method based on the automation device. The chip performance test system based on the automation device connects the chip under test to the test channel through the probe card, samples multiple voltage sensor nodes in the power distribution layer of the probe card, and obtains the power rail voltage distribution data; calculates the power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; performs compensation control on the multi-stage parallel capacitor array on the test board according to the prediction data, and performs the chip test under this control to obtain the test result and the compensation control data; corrects the test result by using the compensation control data and the voltage distribution data to obtain the corrected chip performance parameters. The present invention realizes the accurate monitoring, prediction, active compensation and correction of the power rail transient voltage drop, and significantly improves the accuracy and consistency of the chip performance test.

[0052] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described system or device and unit can refer to the corresponding processes in the foregoing method embodiments, and will not be described herein again.

[0053] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0054] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A chip performance testing method based on automated equipment, characterized in that: The automation equipment includes a test board, a probe card and a test channel, and the chip performance test method based on the automation equipment includes: Placing the chip to be tested on the test board, connecting it to the test channel through the probe card, and performing sampling control on a plurality of voltage sensor nodes arranged in the power distribution layer of the probe card to obtain power rail voltage distribution data; Acquire a test vector sequence of the chip to be tested, and calculate power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; According to the power rail voltage drop prediction data, compensation control is performed on the multi-stage parallel capacitor array on the test board, and chip test corresponding to the test vector sequence is performed under the compensation control to obtain chip test results and power rail compensation control data; The chip test result is corrected according to the power rail compensation control data and the power rail voltage distribution data to obtain corrected chip performance parameters.

2. The chip performance testing method based on automated equipment according to claim 1, characterized in that: Placing the chip to be tested on the test board, connecting the probe card to the test channel, and sampling and controlling a plurality of voltage sensor nodes provided in the power distribution layer of the probe card to obtain power rail voltage distribution data include: Placing the chip to be tested on the test board, connecting it to the test channel through the probe card, performing current density analysis on the power distribution layer of the probe card, and determining the key monitoring position of voltage fluctuation; Dividing the power distribution layer of the probe card into a plurality of sampling areas according to the key monitoring positions, and setting a voltage sensor node in each sampling area; Initialize sampling of the voltage sensor nodes in each sampling area to obtain the main frequency component and harmonic component of the voltage fluctuation, and calculate the bandwidth range of the power consumption change through Fourier transform according to the main frequency component and harmonic component; The sampling timing control parameters are configured for the voltage sensor nodes in each sampling area according to the bandwidth range, and the sampling data is transmitted to the sensor control unit through a low-latency data bus to obtain the power rail voltage distribution data.

3. The chip performance testing method based on automated equipment according to claim 1, characterized in that: The step of acquiring the test vector sequence of the chip to be tested, and calculating the power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model includes: Acquire a test vector sequence of the chip to be tested, and call a corresponding pre-trained neural network model according to the identification code of the chip to be tested; Segmenting the test vector sequence according to the execution timing, calculating the signal flip data of each test vector segment, and constructing a test vector feature matrix; Decomposing the power rail voltage distribution data in the time domain, extracting the amplitude, frequency and phase characteristics of the voltage fluctuation, and generating a voltage feature matrix; Inputting the test vector feature matrix and the voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate timing correlation features; The voltage change prediction is performed according to the timing correlation characteristics by using the decoder of the pre-trained neural network model to obtain the power rail voltage drop prediction data.

4. The chip performance testing method based on automated equipment according to claim 3, characterized in that: The step of inputting the test vector feature matrix and the voltage feature matrix into the bidirectional encoder of the pre-trained neural network model to generate the timing correlation features comprises: Bidirectionally segmenting the test vector feature matrix, inputting the forward time series features of the test vector feature matrix into the forward channel of the bidirectional encoder, and inputting the reverse time series features of the test vector feature matrix into the reverse channel of the bidirectional encoder to obtain the bidirectional hidden layer features of the test vector; The voltage feature matrix is ​​bidirectionally segmented, the forward time series features of the voltage feature matrix are input into the forward channel of the bidirectional encoder, and the reverse time series features of the voltage feature matrix are input into the reverse channel of the bidirectional encoder to obtain the bidirectional hidden layer features of the voltage feature; Calculate bidirectional cross attention weights according to the bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage features to generate a weight matrix of forward and reverse features; The bidirectional hidden layer features of the test vector and the bidirectional hidden layer features of the voltage features are weightedly combined according to the weight matrix to obtain the time series correlation features.

5. The chip performance testing method based on automated equipment according to claim 1, characterized in that: The method of performing compensation control on the multi-stage parallel capacitor array on the test board according to the power rail voltage drop prediction data, and performing chip testing corresponding to the test vector sequence under the compensation control to obtain chip test results and power rail compensation control data includes: Performing response speed analysis on the power rail voltage drop prediction data to calculate voltage drop compensation requirements at different time scales; According to the voltage drop compensation requirements of different time scales, the compensation current magnitude and injection timing of each capacitor unit in the multi-stage parallel capacitor array are calculated; The capacitor units in the multi-stage parallel capacitor array are charged and discharged by a multi-channel PWM controller to obtain power rail compensation control data, and the test vector sequence is executed under the charge and discharge control to obtain the chip test result.

6. The chip performance testing method based on automated equipment according to claim 5, characterized in that: The calculating of the compensation current magnitude and injection timing of each capacitor unit in the multi-stage parallel capacitor array according to the voltage drop compensation requirements of different time scales includes: Performing wavelet transform decomposition on the voltage drop compensation requirements according to the different time scales, decomposing the compensation signal into different frequency sub-bands, and calculating the energy distribution characteristics and phase characteristics of each frequency sub-band; According to the parasitic parameters and temperature characteristics of each capacitor unit in the multi-stage parallel capacitor array, a dynamic impedance model is constructed, and the compensation capability of each capacitor unit at different frequencies is calculated by a state equation; Based on the genetic algorithm, the compensation tasks of each frequency sub-band are optimally allocated, the objective function of the compensation efficiency and compensation timing of the capacitor unit is established, and the candidate set of compensation strategies is generated; The compensation strategy candidate set is iteratively optimized by a particle swarm optimization algorithm to calculate the compensation current size and injection timing of each capacitor unit.

7. The chip performance testing method based on automated equipment according to claim 1, characterized in that: The correcting the chip test result according to the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters includes: Aligning the power rail compensation control data and the power rail voltage distribution data in time series to obtain actual operating voltage data; Calculating the operating voltage deviation curve of each functional module of the chip to be tested according to the difference between the nominal operating voltage of the chip to be tested and the actual operating voltage data; Correlating the performance parameters in the chip test results with the operating voltage deviation curve according to the test sequence to obtain parameter-voltage relationship data; A nonlinear correction calculation is performed on the chip test result according to the parameter-voltage relationship data to obtain a corrected chip performance parameter.

8. A chip performance testing system based on automated equipment, characterized in that: The automation equipment includes a test board, a probe card and a test channel, and the chip performance test system based on the automation equipment includes: A voltage acquisition module is used to place the chip to be tested on the test board, connect it to the test channel through the probe card, and perform sampling control on multiple voltage sensor nodes arranged in the power distribution layer of the probe card to obtain power rail voltage distribution data; A voltage drop prediction module, used to obtain a test vector sequence of the chip to be tested, and calculate power rail voltage drop prediction data according to the power rail voltage distribution data and the test vector sequence through a preset neural network model; A dynamic compensation module, used to perform compensation control on the multi-stage parallel capacitor array on the test board according to the power rail voltage drop prediction data, and execute the chip test corresponding to the test vector sequence under the compensation control to obtain the chip test result and the power rail compensation control data; The result correction module is used to correct the chip test result according to the power rail compensation control data and the power rail voltage distribution data to obtain the corrected chip performance parameters.

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