Extensible test network for high-speed interconnection interface between core grains

Abstract

The invention provides an extensible test network oriented to a high-speed interconnection interface between core particles, and efficient test of the high-speed interface in the core particles is realized through an optimized TAP controller and an SIB structure. The network is compatible with the IEEE 1687 standard, and supports the built-in self-test of a storage unit, the boundary scan test of IO and inter-chip interconnection, and the Loopback function test of SERDES data receiving and transmitting. And through flexible configuration of testmode and bscanmode control signals, inter-chip interconnection interface serial boundary scanning testing of a sending end, a receiving end and a middle core particle is realized. Besides, the loopback test controller configured through lbmode control signals supports inner loopback and far-end loopback tests, physical link function testing and fault diagnosis of a high-speed interface are achieved, and inter-chip data receiving and transmitting testing of the core particle system is completed, so that the testing efficiency and flexibility of the core particle system are remarkably improved, and the testing cost is reduced. And the expansion test requirements of the high-speed interconnected core particle system are met.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and particularly to a scalable test network for high-speed inter-chip interconnect interfaces of chiplets. Background Art

[0002] With the development of integrated circuit technology, the chiplet technology has been widely used due to its high integration and flexibility, and the chiplet system has gradually become an important part of high-performance computing and complex system design. The chiplet system realizes high-performance computing through the interconnection of multiple chiplets, and the testing of high-speed inter-chip interconnect interfaces (such as SERDES interfaces) between these chiplets has become a key step to ensure the reliability of the system.

[0003] However, the testing of high-speed inter-chip interconnect interfaces in the chiplet system faces many challenges, such as a large number of high-speed interfaces, high interface complexity, large test data volume, low test efficiency, etc. In addition, considering different interconnection methods and heterogeneous integration of the chiplet system, traditional testing methods have problems such as inconsistent test scheduling, low efficiency, high cost, and difficulty in comprehensive coverage.

[0004] Therefore, the existing technology is difficult to meet the testing requirements of high-speed inter-chip interconnect interfaces in the chiplet system, and there is an urgent need for an efficient and flexible test scheduling control circuit. Summary of the Invention

[0005] This application provides a scalable test network for high-speed inter-chip interconnect interfaces of chiplets, which can be used to solve the technical problems of inconsistent scheduling and low efficiency of traditional methods.

[0006] This application provides a scalable test network for high-speed inter-chip interconnect interfaces of chiplets, and the test network includes:

[0007] n chiplets are interconnected through SERDES; the test network is connected end to end through the JTAG interface, and the SIB controls whether each IP in the chiplet is connected to the current test scan chain;

[0008] In the test network, each chiplet accesses the test circuit through five ports of JTAG, namely TDI, TRST, TMS, TCK, and TDO. Test data is input into the test network through TDI, and the input configuration vector is decoded in the TAP controller, and control signals such as select, shift, update, and capture are output to the SIB network;

[0009] The test network includes two layers of SIB networks: in the first layer of SIB network, each SIB is divided into SIB0 to SIBn; the first layer of SIB network is connected to the TAP controller of each die, SIB0 to SIBn are connected in series, and the following are each IP under test inside the die. The TAP controller outputs test vectors to SIB0, SIB1... SIBn, and the SIB switch configures whether each IP under test connected below is accessed to the current scan chain;

[0010] When the IP under test is SERDES, the second layer of SIB network is adopted to configure the test mode of SERDES. Each SIB in the second layer of SIB network is SIB0_1, SIB0_2... SIB0n respectively; it includes a serial boundary scan mode and a parallel loopback test mode. SIB0_1 controls the enabling of the boundary scan test, serially inputs the test vector to the inter-die interconnect pins to test whether the connectivity is normal, and SIB0_2 controls the enabling of the loopback test to configure the registers related to the loopback test in the current SERDES IP to implement the functional test of the high-speed interface.

[0011] Compared with the prior art, the beneficial effects of the present invention are:

[0012] (1) By using the SIB structure to be compatible with the IEEE 1687 standard, it can flexibly configure whether each IP (such as memory, IO, SERDES, etc.) inside the die is accessed to the current test scan chain, can test multiple dies or IPs in parallel, adapt to different die architectures and test requirements, and significantly improve the test efficiency;

[0013] (2) Through the test mode register, the unified scheduling and efficient configuration of various test modes in the die system are realized; the transmitter (TX) and receiver (RX) of the die can be flexibly configured according to the data transmission direction, support the inter-die interconnect packet test in different transmission directions, reduce the test complexity; support the test after extended interconnection, can cover complex inter-die interconnect scenarios, and quickly locate and diagnose faults. Description of the Drawings

[0014] Figure 1 It is a block diagram of an extensible test network architecture for the high-speed inter-die interconnect interface provided by the embodiment of the present application;

[0015] Figure 2 It is a test mode decoding structure diagram of the TAP controller for die interconnect testing provided by the embodiment of the present application;

[0016] Figure 3 It is a structure diagram of the die interconnect boundary scan controller provided by the embodiment of the present application;

[0017] Figure 4 It is a structure diagram of the die high-speed interface loopback test controller provided by the embodiment of the present application;

[0018] Figure 5 This is the MBIST test path diagram in the die system test network provided by the embodiments of the present application;

[0019] Figure 6 This is the inter-die interface boundary scan test path diagram in the die system provided by the embodiments of the present application; wherein, (a) is the inter-die interface boundary scan test path with die 0 as the sender; (b) is the inter-die interface boundary scan test path with die 0 as the receiver;

[0020] Figure 7 This is the high-speed interconnection loopback test path diagram of the inter-die interface in the die system provided by the embodiments of the present application; (a) is the parallel test path of the high-speed loopback internal loop in the die system interface; (b) is the remote loopback test path of the high-speed loopback in the die system interface. Detailed implementation manners

[0021] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0022] The following first introduces the embodiments of the present application with reference to the accompanying drawings.

[0023] As Figure 1 shown, assuming that there are n dies in the die system interconnected through SERDES, considering the test compatibility of SERDES IP and other IPs in the die and the connectivity test between dies after die system integration, the test network proposed by the present invention is connected end to end through the JTAG interface, and the SIB (Segment Insertion Bit) is used to control whether each IP in the die is connected to the current test scan chain. A test mode selection register and a corresponding output strobe MUX are added to the TAP controller, which can flexibly configure the tests of the IO, inter-die interconnection interface, high-speed interface physical layer (PHY), and the built-in self-test of the internal storage IP in the die connected to the scan chain.

[0024] In the test network, each die accesses the test circuit through the five ports of TDI, TRST, TMS, TCK, and TDO of JTAG. The test data is input into the test network through TDI, and the input configuration vector is decoded in the TAP controller, and the control signals of select, shift, update, and capture are output to the SIB network;

[0025] The test network includes two layers of SIB networks: In the first - layer SIB network, each SIB is divided into SIB0 to SIBn; the first - layer SIB network is connected to the TAP controller of each die. SIB0 to SIBn are connected in series and are connected to each IP under test inside the die. The TAP controller outputs test vectors to SIB0, SIB1... SIBn, and the SIB switch configures each IP under test connected below to determine whether to access the current scan chain.

[0026] When the IP under test is SERDES, the second - layer SIB network is adopted to configure the test mode of SERDES. Each SIB in the second - layer SIB network is SIB0_1, SIB0_2... SIB0n respectively; it includes a serial boundary - scan mode and a parallel loop - back test mode. SIB0_1 controls the enabling of the boundary - scan test, serially inputs the test vector to the inter - die interconnect pins to test whether the connectivity is normal, and SIB0_2 controls the enabling of the loop - back test, configures the registers related to the loop - back test in the current SERDES IP, and realizes the functional test of the high - speed interface.

[0027] When there are multiple groups of SERDES in the die, each group of SERDES is controlled for testing through the two - layer SIB network, and then output to the TDO of the TAP controller through the SIB scan chain to compare the test results.

[0028] After the multi - die extended interconnection, for the test network of each die, the TDO and TDI are connected end - to - end to connect the test networks of each die, and the unified scheduling of the die system test is realized without increasing the test ports.

[0029] The high - speed interface interconnection test process includes the following steps:

[0030] Step 1, the storage unit performs memory built - in self - test (MBIST): The die system test network is compatible with the original IEEE 1687 standard network structure, and the built - in self - test of the storage units in each die is controlled through JTAG and the SIB switch.

[0031] Step 2, the IO and inter - die interconnect perform boundary - scan test (DCJTAG / ACJTAG): Due to different transmission directions, the test network configures the inter - die pins to be serially connected to the scan chain according to the transmission direction; in the inter - die interconnect test, the party acting as the transmitter TX loads the EXTEST / EXTEST_TRAIN / EXTEST_PULSE instruction, while the party acting as the receiver RX loads the SAMPLE instruction; the boundary - scan chains between the dies are serially connected through JTAG, and finally the test results of the inter - die interconnect connectivity are output through TDO.

[0032] Step 3, Loopback test for SERDES data transceiver: The test network accesses the high-speed interface IPs in each die through SIB, accesses the high-speed interface IP test configuration register through the control signal decoded by the test mode register, configures the high-speed interface IP in the die for internal loopback test. The test network supports parallel testing to improve test efficiency. After the internal loopback test ends, the internal loopback test results of each IP are output by TDO; the high-speed interface IPs at both ends of the interconnected dies in the test network are enabled for remote loopback test through SIB. One end is configured as the master device for the loopback test, and the corresponding die at the interconnected opposite end becomes the slave device for the loopback test, realizing the functional test and fault diagnosis of the high-speed interface physical link.

[0033] The TAP controller structure optimized for high-speed inter-die interconnection is as Figure 2 shown. A test mode register is added to the TAP controller, and a 5-bit control signal test_mode[4:0] for inter-die interconnection function is configured through the test mode register; the default value of test_mode is defined as 5’b00000. According to the JTAG test convention, the LSB (least significant bit) is used as the bit closest to the output port and is explained as follows:

[0034] test_mode[0] represents the SERDES test enable. When it is 1’b1, it represents that the test mode of the current die is enabled; test_mode[1] is the boundary scan control enable. When it is 1’b1, it represents that the boundary scan controller is enabled; test_mode[2] represents the position of the current die. When it is 1’b0, it represents that the current die is used as the transmitter, and when it is 1’b1, it represents that the current die is used as the receiver; test_mode[3] represents the loopback internal loopback test enable, and test_mode[4] represents the loopback remote loopback test enable.

[0035] In the die system test, according to the different architectures of the dies in the system, the SIB switch is flexibly configured through the test_mode signal to complete the tests of each IP within the die and the inter-die interconnection; when test_mode is at the default value, the select signal of the TAP controller does not select the SERDES IP, that is, the SIB controlling the SERDES test is bypassed, and only the MBIST-related tests are enabled; when performing the boundary scan test, test_mode[1] is set to 1, the bs_en output by the TAP controller is valid, and the die position test_mode[2] is configured according to the data transmission direction of the die system. The signal is decoded into config_tx / config_rx and output to the boundary scan controller, and the interconnection port accessing the current test scan chain is controlled through bs_en, config_tx, and config_rx; when performing the internal loopback test, test_mode[3] is set to 1, the lb_int signal output by the TAP controller is valid, and the signal is output to the loopback test controller to configure the SERDES IP into the internal loopback test mode; when performing the remote loopback test, test_mode[4] is set to 1, the lb_rem signal output by the TAP controller is valid, and the die position test_mode[2] is configured according to the data transmission direction of the die system. The signal is decoded into config_tx / config_rx and output to the loopback test controller to configure the SERDES IP into the remote loopback test mode and configure the master / slave device for the remote test.

[0036] The reconstructed boundary scan controller structure is as Figure 3 shown. When test_mode[1] is valid, the boundary scan chain is enabled, and the die system is controlled by the boundary scan controller to perform the inter-die connectivity test; in the die system with multi-die interconnection, the boundary scan units are divided into a transmitter group TX_GROUP and a receiver group RX_GROUP according to the inter-die transmission direction. A MUX is added before and after the scan data input and output respectively, so that the transmitter group and the receiver group can be separately connected to the scan chain. The connection method is configured by the scan register bscan_mode[1:0], and the default value is 2'b00; using the LSB (least significant bit) as the bit closest to the output port, the control signal description is as follows:

[0037] Setting bscan_mode[0] to 1 means that the current die only has the transmitter group interface connected to the scan chain, and the receiver interface is bypassed, that is, it acts as an input die for the die system test network; setting bscan_mode[1] to 1 means that the current die only has the receiver group interface connected to the scan chain, and the transmitter port is bypassed, that is, it acts as an output die for the die system test network; if bscan_mode[1:0] = 2'b00, it means that the inter-die interface of the current die is bypassed, and the data shifted into TDI is directly output to the next die or the outside through TDO.

[0038] During the multi-die system test, the connectivity test of the interconnection interfaces of the dies in different positions is flexibly configured according to the die system architecture, and the test after extended interconnection is also supported. Taking the first die as an example, the test process after its interconnection includes the following steps:

[0039] S21: Test the first die as the transmitting side. Configure the die interconnected with the first die as the receiving side. Only connect the transmitter group of the first die and the receiver groups of other dies interconnected with the first die to the scan chain, and bypass other dies. Load the EXTEST / SAMPLE instructions into the dies acting as the transmitter and the receiver respectively, and then shift the signals received by the receiver interconnection interface out through TDO.

[0040] S22: Test the first die as the receiving side. Only connect the receiver group of the first die and the transmitter groups of other dies interconnected with it to the scan chain, and bypass other dies. Load the EXTEST / SAMPLE instructions into the dies acting as the transmitter and the receiver respectively, and then shift the signals received by the receiver interconnection interface out through TDO.

[0041] Repeating the above steps for each group of interconnection interfaces in the scenario of multi-die extended interconnection can complete the inter-die interconnection test without increasing the overhead of additional test vectors compared with the single-die boundary scan test.

[0042] The loopback test controller structure is as Figure 4 shown. The loopback test of the high-speed interface is divided into internal loopback test and remote loopback test. The test mode is configured by the loopback test register lb_mode[3:0], and the default value is 4'b0000; taking the LSB (least significant bit) as the bit closest to the output port, the control signals are described as follows:

[0043] lb_mode[0] represents the instruction configuration. Setting it to 0 means that the data shifted in by TDI is written to the configuration register, and setting it to 1 means it is invalid data for shifting only. lb_mode[1] set to 1 represents address access, that is, the subsequent configuration is the current accessed register address; lb_mode[2] set to 1 represents writing data, that is, writing the configuration value to the current address; lb_mode[3] set to 1 represents reading data, that is, reading the result of the destination register for comparison.

[0044] Assume that the register address and data bit width are 16-bit, then the steps of the internal loopback test are as follows:

[0045] S31: The TAP controller decodes that lb_int is valid and enables the high-speed interface IP through SIB;

[0046] S32: Configure lb_mode = 4'b0011 through TDI shifting, that is, the next 16-bit writes the register address to the address controller;

[0047] S33: Configure lb_mode = 4'b0101 through TDI shifting, that is, the next 16-bit writes the register address to the address controller;

[0048] S34: According to different SERDES register definition situations, repeat S2 and S3 to configure its initialization, loopback test enable, rate, Pattern generation mode (such as PRBS sequence), etc.;

[0049] S35: Wait for the internal loopback test to complete, configure lb_mode = 4'b0101 through TDI shifting, and write the error indication register address to the address controller;

[0050] S36: Configure lb_mode = 4'b1000 through TDI shifting, continue to shift 16-bit test vectors into this data link, and output the test results through TDO.

[0051] The steps of the remote loopback test are as follows:

[0052] S41: The TAP controller decodes that lb_rem is valid and enables the SERDES test of the inter-chiplet transmitter and receiver through SIB;

[0053] S42: Configure lb_mode = 4'b0011 through TDI shifting, that is, the next 16-bit writes the register address to the address controller;

[0054] S43: Configure lb_mode = 4'b0101 through TDI shifting, that is, the next 16-bit writes the register address to the address controller;

[0055] S44: According to different SERDES register definition situations, repeat S2 and S3 to configure its initialization, link training, rate, test data generation mode, etc.;

[0056] S45: Wait for the internal loopback test to complete, configure lb_mode = 4'b0101 through TDI shift, and write the error indication register address to the address controller;

[0057] S46: Configure lb_mode = 4'b1000 through TDI shift, continue to shift 16-bit test vectors into this data link, and output the test results through TDO.

[0058] As Figure 5 shown, in the MBSIT test of the chiplet system, the test_mode is decoded by the optimized TAP controller. When test_mode[0] is valid, it represents the start of the chiplet test mode, and the SIB switch of the MBIST controller is gated for testing, enabling parallel testing of the Memories of each chiplet to shorten the test time; after the MBIST test is completed, the test results of each chiplet are output from TDO in the chiplet order.

[0059] As Figure 6 shown, in the chiplet inter-chip connectivity test, when test_mode[0] is valid, it represents the start of the chiplet test mode, and when test_mode[1] is valid, it represents the access of the boundary scan controller. In the chiplet system, the circuits responsible for the boundary scan are divided into two parts: external IO and inter-chip interconnection; in this test network, according to the data transmission direction, by reasonably configuring the test_mode signal and using the SIB switch, the test task can be efficiently completed, avoiding the scan shift cycle overhead caused by simultaneous access of all inter-chip pins.

[0060] In one implementation, first, the case where die 0 is the transmitter is tested. Then, test_mode[2] is set to 0. The transmitter of the inter-die interface in die 0 is connected to the boundary scan chain. At the same time, test_mode[1] and test_mode[2] of other dies interconnected with die 0 are both set to 1, indicating that the receivers of the inter-die interfaces are connected to the boundary scan chain. As shown in the figure, through the SIB switches of the corresponding inter-die interfaces involved in the interconnection and by configuring the instruction register in the TAP controller, the transmitter die is configured as EXTEST, and the receiver die is configured as SAMPLE. At the same time, since the number of inter-die interconnect pins is different for each die, the die pairs that have completed the connectivity test are configured for the instruction register such that after all inter-die interfaces have been tested, the test results are sequentially output by TDO. Conversely, when testing die 0 as the receiver, test_mode[2] is set to 1. At this time, the receiver of the inter-die interface in die 0 is connected to the boundary scan chain. At the same time, test_mode[1] of other dies interconnected with die 0 is set to 1, and test_mode[2] is set to 0, indicating that the transmitters of the inter-die interfaces are connected to the boundary scan chain. The connectivity test of all inter-die interfaces is completed using the same method as described above.

[0061] As Figure 7 shown, in the functional test of the high-speed inter-die interface of the die, test_mode[0] is valid, indicating the start of the test mode for this die, and the loopback test circuit built into the high-speed interface IP is accessed using the SIB network. In the internal loopback test, test_mode[3] is valid, and the high-speed interface IPs can be tested in parallel through the SIB network. For each IP enabled by SIB, its loopback mode is configured as the internal loopback mode through the Loopback controller, that is, the relevant addresses, write enable, and write data are configured. In the external loopback test, test_mode[4] is valid, and the dies at both ends of the interconnection in the die system are respectively configured as the loopback test host and slave, that is, test_mode[2] is configured accordingly. When test_mode[4] is valid and test_mode[2] is 0, this side is the master device for the remote loopback test; when test_mode[4] is valid and test_mode[2] is 1, this side is the slave device for the remote loopback test. The host is controlled by the Loopback controller to complete configurations and assignments such as link training, write enable, and write data, access and compare the transmitted and received data, and after the test is completed, control the read enable to read out the test results and output them through TDO, thereby verifying the signal transmission function and data link integrity of the high-speed inter-die interface of the die.

[0062] Finally, it should be noted that the above are only preferred examples of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0063] The embodiments of the present application described above do not constitute a limitation to the protection scope of the present application.

Claims

1. A scalable test network for high-speed interconnect interfaces between chips, characterized in that: The test network includes: n chiplets are interconnected through SERDES; the test network is connected end to end through the JTAG interface, and the SIB is used to control whether each IP in the chiplet is connected to the current test scan chain; In the test network, each chip accesses the test circuit through the five ports of JTAG: TDI, TRST, TMS, TCK, and TDO. The test data is input to the test network through TDI. The input configuration vector is decoded in the TAP controller, and the select, shift, update, and capture control signals are output to the SIB network. The test network includes two layers of SIB networks: each SIB in the first layer of SIB network is divided into SIB0 to SIBn; the first layer of SIB network is connected to the TAP controller of each chiplet, SIB0 to SIBn are connected in series, and each IP to be tested inside the chiplet is connected. The TAP controller outputs test vectors to SIB0, SIB1...SIBn, and each IP to be tested is configured through the SIB switch to determine whether to access the current scan chain; When the IP to be tested is SERDES, the second-layer SIB network is used to configure the SERDES test mode. The SIBs in the second-layer SIB network are SIB0_1, SIB0_2...SIB0n respectively; it includes a serial boundary scan mode and a parallel loopback test mode. SIB0_1 controls the boundary scan test enable, and the test vector is serially input to the inter-chip interconnection pins to test whether the connectivity is normal. SIB0_2 controls the loopback test enable, configures the registers related to the loopback test in the current SERDES IP, and implements the functional test of the high-speed interface.

2. The test network according to claim 1, characterized in that: When there are multiple groups of SERDES in the chip, each group of SERDES is tested through two layers of SIB network, and then output to TDO of TAP controller through SIB scan chain to compare the test results; After the multi-chip expansion interconnection, the test network of each chip is connected in the form of TDO and TDI connected end to end.

3. The test network according to claim 2, characterized in that: The high-speed interface interconnection test process includes the following steps: Step 1, the memory cell performs a memory built-in self-test (MBIST): the chip system test network is compatible with the original IEEE1687 standard network structure, and the memory cell in each chip is controlled to perform a built-in self-test through JTAG and SIB switches; Step 2, perform boundary scan test on IO and inter-chip interconnection: Due to different transmission directions, the test network configures the inter-chip pins to be connected in series to the scan chain according to the transmission direction; in the inter-chip interconnection test, the TX side as the transmitter loads the EXTEST / EXTEST_TRAIN / EXTEST_PULSE instruction, and the RX side as the receiver loads the SAMPLE instruction; the boundary scan chains between the chiplets are connected in series through JTAG, and finally the test results of the inter-chip interconnection connectivity are output through TDO; Step 3, loopback test (Loopback) of SERDES data reception and transmission: the test network uses SIB to access the high-speed interface IP in each chip, accesses the high-speed interface IP test configuration register through the control signal decoded by the test mode register, and configures the high-speed interface IP in the chip to perform internal loopback test. The test network supports parallel testing to improve test efficiency. After the internal loopback test is completed, TDO outputs the internal loopback test results of each IP; the high-speed interface IPs at both ends of the interconnected chip in the test network are turned on through SIB to perform remote loopback test, one end of which is configured as the master device for loopback test, and the interconnected opposite chip becomes the slave device for loopback test accordingly, so as to realize functional test and fault diagnosis of high-speed interface physical link.

4. The test network according to claim 2, characterized in that: Add a test mode register in the TAP controller, and configure the 5-bit control signal test_mode[4:0] for the inter-chip interconnection function through the test mode register; define the default value of test_mode as 5'b00000, with LSB as the nearest bit to the output port as follows: test_mode[0] represents the SERDES test enable, 1'b1 represents the current chip test mode enable; test_mode[1] represents the boundary scan control enable, 1'b1 represents the boundary scan controller is turned on; test_mode[2] represents the current chip position, 1'b0 represents the current chip as the transmitter, 1'b1 represents the current chip as the receiver; test_mode[3] represents the loopback internal loopback test enable, test_mode[4] represents the loopback remote loopback test enable. In the chip system test, according to the different architectures of the chip in the system, the SIB switch is configured through the test_mode signal to complete the test of each IP in the chip and the interconnection between the chip slices; when the test_mode is at the default value, the TAP controller select signal does not select the SERDES IP, that is, the SIB that controls the SERDES test is bypassed and only the MBIST related test is enabled; when performing boundary scan test, test_mode[1] is set to 1, the TAP controller outputs bs_en valid, and configures the chip position test_mode[2] according to the data transmission direction of the chip system, and the signal is decoded as config_tx / config_rx and output to the boundary scan controller, and the interconnection port connected to the current test scan chain is controlled through bs_en, config_tx, and config_rx; when performing internal loopback test, test_mode[3] is set to 1, the TAP controller outputs lb_int signal valid, and the signal is output to the loopback test controller to configure the SERDES The IP is in internal loopback test mode. When performing a remote loopback test, test_mode[4] is set to 1, the TAP controller outputs a valid lb_rem signal, and configures the chip position test_mode[2] according to the chip system data transmission direction. The signal is decoded as config_tx / config_rx and output to the loopback test controller. The SERDES IP is configured in remote loopback test mode, and the master / slave device of the remote test is configured.

5. The test network according to claim 4, characterized in that: When test_mode[1] is valid, the boundary scan chain is enabled, and the boundary scan controller controls the chiplet system to perform inter-chip connectivity testing. In a chiplet system with multiple chiplets interconnected, the boundary scan unit is divided into a transmitter group TX_GROUP and a receiver group RX_GROUP according to the transmission direction between the chiplets. A MUX is added before and after the scan data input, respectively, so that the transmitter group and the receiver group can be separately connected to the scan chain. The access mode is configured by the scan register bscan_mode[1:0], and the default value is 2'b00. LSB is the bit closest to the output port. The control signal is described as follows: bscan_mode[0] is set to 1, which means that only the transmitting end group interface of the current chip is connected to the scan chain, and the receiving end interface is bypassed, that is, it serves as the input chip of the chip system test network; bscan_mode[1] is set to 1, which means that only the receiving end group interface of the current chip is connected to the scan chain, and the transmitting port is bypassed, that is, it serves as the output chip of the chip system test network; if bscan_mode[1:0]=2'b00, it means that the inter-chip interface of the current chip is bypassed, and the data shifted into TDI is directly output to the next chip or to the outside through TDO.

6. The test network according to claim 4, characterized in that: When testing a multi-chiplet system, the connectivity test of the chiplet interconnection interfaces at different locations is configured according to the chiplet system architecture, and the test after the extended interconnection is supported; the test process after the first chiplet is interconnected includes the following steps: S21: Test the first chip as the transmitting side, configure the chip interconnected with the first chip as the receiving side, only connect the transmitting end group of the first chip and the receiving end group of other chip interconnected with the first chip to the scan chain, bypass other chip, load EXTEST / SAMPLE instructions in the chip as the transmitting end and the receiving end respectively, and then shift and output the signal received by the receiving end interconnection interface through TDO; S22: Test the first chip as the receiving side, only connect the receiving end group of the first chip and the transmitting end group of other chip interconnected with it to the scan chain, bypass other chip, load EXTEST / SAMPLE instructions in the chip as the transmitting end and the receiving end respectively, and then shift the signal received by the receiving end interconnection interface through TDO output.

7. The test network according to claim 4, characterized in that: The loopback test of the high-speed interface is divided into internal loopback test and remote loopback test; the test mode is configured by the loopback test register lb_mode[3:0], and the default value is 4'b0000; the LSB (least significant bit) is used as the bit closest to the output port, and the control signal is described as follows: lb_mode[0] represents instruction configuration. Setting it to 0 means that the data shifted in by TDI is written into the configuration register. Setting it to 1 means that it is only used as invalid data for shifting. Setting lb_mode[1] to 1 represents address access, that is, the subsequent configuration is the current access register address. Setting lb_mode[2] to 1 represents writing data, that is, writing the configuration value to the current address. Setting lb_mode[3] to 1 represents reading data, that is, reading the result of the destination register for comparison.

8. The test network according to claim 7, characterized in that: Assuming the register address and data bit width are 16-bit, the steps of the inner loop test are as follows: S31: TAP controller decodes lb_int to be valid and enables the high-speed interface IP through SIB; S32: Shift the TDI bit to configure lb_mode = 4'b0011, that is, the next 16 bits are written to the register address controller; S33: configure lb_mode=4'b0101 through TDI shift, that is, write the register address to the address controller in the next 16 bits; S34: According to the definition of different SERDES registers, repeat S32 and S33 to configure its initialization, loopback test enable, rate, pattern generation mode, etc.; S35: Wait for the inner loop test to be completed, configure lb_mode=4'b0101 through TDI shift, and write the error indication register address to the address controller; S36: Shift configuration lb_mode=4'b1000 through TDI, continue to shift 16-bit test vectors into the data link, and output the test results through TDO; The steps for the remote loopback test are as follows: S41: TAP controller decodes lb_rem to be valid, and enables SERDES testing of the transmitter and receiver of the interconnected chip through SIB; S42: lb_mode = 4'b0011 is configured by TDI shift, that is, the next 16-bit register address is written to the address controller; S43: lb_mode = 4'b0101 is configured by TDI shift, that is, the next 16-bit register address is written to the address controller; S44: according to the definition of different SERDES registers, repeat S42 and S43 to configure its initialization, link training, rate, and test data generation mode; S45: Wait for the inner loop test to be completed, configure lb_mode=4'b0101 by TDI shift, and write the error indication register address to the address controller; S46: Shift configuration lb_mode=4'b1000 through TDI, continue to shift 16-bit test vectors into the data link, and output the test results through TDO.

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